Testing Method for Semiconductor Device and Testing Apparatus for Semiconductor Device

Abstract

The present disclosure provides a test method and a test device for a semiconductor device. The test method includes: forming a plurality of test values according to a first retention time range and a first step size, and sequentially testing a plurality of memory cells in the semiconductor device according to the plurality of test values from small to large; determining the memory cells in the test whose retention time is less than the test value corresponding to each test value, and recording the positions of the memory cells and the corresponding test values to form first test data; forming a plurality of test values according to a second retention time range and a second step size, and sequentially testing a plurality of memory cells in the semiconductor device according to the plurality of test values from large to small; determining the memory cells in the test whose retention time is less than the test value corresponding to each test value, and recording the positions of the memory cells and the corresponding test values to form second test data; determining the positions of the memory cells that fail the retention time test and the corresponding test values according to the first test data and the second test data.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technologies, and more particularly, to a method for testing a semiconductor device and a testing apparatus for a semiconductor device. Background Art

[0002] A dynamic random access memory (DRAM) includes a plurality of memory cells for storing data. Each memory cell may include a transistor and a capacitor. The transistor serves as a gate for the flow of data into and out of the memory cell, and the capacitor is used to store data in the form of electric charges. However, the initial charges stored in the capacitors of each memory cell may gradually disappear due to leakage current occurring in the typical PN junctions of MOS transistors, resulting in data loss. These memory cells are referred to as variable retention time (VRT) memory cells.

[0003] Generally, memory devices have different process variables and different characteristics during the packaging process. For example, during the packaging process, different memory devices or different memory regions of a memory may be exposed to high temperatures, while other memory devices may be exposed to low temperatures. Such variables have a great impact on the likelihood of VRT errors occurring in the memory device, and VRT errors may occur at different rates in the memory device.

[0004] Therefore, it is necessary to accurately identify the VRT memory cells in the memory device through testing.

[0005] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0006] The purpose of the embodiments of the present disclosure is to provide a method for testing a semiconductor device and a testing apparatus for a semiconductor device, which improve the efficiency and accuracy of testing the retention time.

[0007] According to one aspect of the embodiments of the present disclosure, there is provided a method for testing a semiconductor device, the testing method including:

[0008] Presetting a first retention time range and a first step size;

[0009] Form a plurality of test values according to the first retention time range and the first step size, and sequentially test a plurality of memory cells in the semiconductor device according to the plurality of test values from smallest to largest; determine the memory cells with a retention time less than the test value in each test corresponding to the test value, and record the positions of the memory cells with a retention time less than the test value and the corresponding test values to form first test data;

[0010] Preset a second retention time range and a second step size;

[0011] Form a plurality of test values according to the second retention time range and the second step size, and sequentially test a plurality of memory cells in the semiconductor device according to the plurality of test values from largest to smallest; determine the memory cells with a retention time less than the test value in each test corresponding to the test value, and record the positions of the memory cells with a retention time less than the test value and the corresponding test values to form second test data;

[0012] Determine the positions and corresponding test values of the memory cells that fail the retention time test according to the first test data and the second test data.

[0013] In an exemplary embodiment of the present disclosure, the presetting of the first retention time range and the first step size includes:

[0014] Preset a retention time, a step size, and a plurality of test ambient temperatures;

[0015] Under a plurality of test ambient temperatures, respectively test a plurality of memory cells in the semiconductor device that adopt the retention time and the step size according to the retention time and the step size to obtain test data;

[0016] According to the test data, the retention time, and the step size, preset the first retention time range and the first step size.

[0017] In an exemplary embodiment of the present disclosure, the presetting of the second retention time range and the second step size includes:

[0018] Preset a retention time, a step size, and a plurality of test ambient temperatures;

[0019] Under a plurality of test ambient temperatures, respectively test a plurality of memory cells in the semiconductor device that adopt the retention time and the step size according to the retention time and the step size to obtain test data;

[0020] According to the test data, the retention time, and the step size, preset the second retention time range and the second step size.

[0021] In an exemplary embodiment of the present disclosure, the first retention time range is the same as the second retention time range, and the first step size is the same as the second step size.

[0022] In an exemplary embodiment of the present disclosure, a plurality of test values are formed according to the first retention time range and the first step size, and a plurality of memory cells in the semiconductor device are sequentially tested according to the plurality of test values from smallest to largest; determine the memory cells in which the retention time during the test corresponding to each test value is less than the test value, and record the positions of the memory cells in which the retention time is less than the test value and the corresponding test values, to form first test data, including:

[0023] Form a plurality of test values according to the first retention time range and the first step size;

[0024] Select the test values in sequence according to the order of the plurality of test values from smallest to largest, and test a plurality of memory cells in the semiconductor device with the selected test values;

[0025] Determine whether the retention time of the plurality of memory cells in the semiconductor device during the test corresponding to each test value is greater than or equal to the test value;

[0026] If it is greater than or equal to the test value, determine whether the test value is less than the maximum value of the first retention time range;

[0027] If it is less than the test value, output the test value and position information of the memory cell;

[0028] If the test value is less than the maximum value of the first retention time range, sequentially select the next test value, and continue to test the plurality of memory cells in the semiconductor device with the selected next test value;

[0029] Form first test data according to the test values and position information of the memory cells output during the test corresponding to each test value.

[0030] In an exemplary embodiment of the present disclosure, a plurality of test values are formed according to the second retention time range and the second step size, and a plurality of memory cells in the semiconductor device are sequentially tested according to the plurality of test values from largest to smallest; determine the memory cells in which the retention time during the test corresponding to each test value is less than the test value, and record the positions of the memory cells in which the retention time is less than the test value and the corresponding test values, to form second test data, including:

[0031] Form a plurality of test values according to the second retention time range and the second step size;

[0032] Select the test values in sequence according to the order of the plurality of test values from largest to smallest, and test a plurality of memory cells in the semiconductor device with the selected test values;

[0033] Determine whether the retention time of the plurality of memory cells in the semiconductor device during the test corresponding to each test value is greater than or equal to the test value;

[0034] If it is greater than or equal to the test value, determine whether the test value is less than or equal to the minimum value of the second retention time range;

[0035] If it is less than the test value, output the test value and location information of the storage unit;

[0036] If the test value is greater than the minimum value of the second retention time range, sequentially select the next test value, and continue to test multiple storage units in the semiconductor device according to the selected next test value;

[0037] Form second test data according to the test values and location information of the storage units output during the test corresponding to each of the test values.

[0038] In an exemplary embodiment of the present disclosure, the test method further includes:

[0039] If the test value is greater than or equal to the maximum value of the first retention time range, determine whether the test value is less than the minimum value of the second retention time range;

[0040] If the test value is greater than the minimum value of the second retention time range, sequentially select the test values according to the order of the multiple test values from large to small, and test multiple storage units in the semiconductor device in sequence.

[0041] In an exemplary embodiment of the present disclosure, the test method further includes:

[0042] Determine the number of tests;

[0043] Before testing multiple storage units in the semiconductor device in sequence according to the multiple test values from small to large and testing multiple storage units in the semiconductor device in sequence according to the multiple test values from large to small, determine whether the number of tests has reached the maximum value;

[0044] If the maximum value of the number of tests is not reached, continue the test;

[0045] If the maximum value of the number of tests is reached, stop the test.

[0046] In an exemplary embodiment of the present disclosure, preset the first step length and the second step length according to the number of tests.

[0047] In an exemplary embodiment of the present disclosure, determining the locations and corresponding test values of the storage units that fail the retention time test according to the first test data and the second test data includes:

[0048] Determine the positions of the memory cells that fail the retention time test and the corresponding test values according to the first test data;

[0049] Determine the positions of the memory cells that fail the retention time test and the corresponding test values according to the second test data;

[0050] Perform a union statistic on the memory cells that fail the retention time test determined by the first test data and the second test data as the test result.

[0051] According to another aspect of the embodiments of the present disclosure, a test device for a semiconductor device is provided. The test device includes:

[0052] A parameter presetting module configured to preset a first retention time range and a first step size, and preset a second retention time range and a second step size;

[0053] A first test module connected to the parameter presetting module. The first test module is configured to form a plurality of test values according to the first retention time range and the first step size, and sequentially test a plurality of memory cells in the semiconductor device according to the plurality of test values from small to large; determine the memory cells whose retention time is less than the test value in each test corresponding to the test values, and record the positions of the memory cells whose retention time is less than the test value and the corresponding test values to form first test data;

[0054] A second test module connected to the parameter presetting module and the first test module. The second test module is configured to form a plurality of test values according to the second retention time range and the second step size, and sequentially test a plurality of memory cells in the semiconductor device according to the plurality of test values from large to small; determine the memory cells whose retention time is less than the test value in each test corresponding to the test values, and record the positions of the memory cells whose retention time is less than the test value and the corresponding test values to form second test data;

[0055] An output module connected to the first test module and the second test module. The output module is configured to determine the positions of the memory cells that fail the retention time test and the corresponding test values according to the first test data and the second test data.

[0056] The test method for a semiconductor device provided by the present disclosure forms multiple test values according to a first retention time range and a first step size, and sequentially tests multiple memory cells in the semiconductor device according to the multiple test values from smallest to largest; determines the memory cells whose retention time during the test is less than the test value corresponding to each test value, and records the positions of these memory cells and the corresponding test values to form first test data; forms multiple test values according to a second retention time range and a second step size, and sequentially tests multiple memory cells in the semiconductor device according to the multiple test values from largest to smallest; determines the memory cells whose retention time during the test is less than the test value corresponding to each test value, and records the positions of these memory cells and the corresponding test values to form second test data; determines the positions and corresponding test values of the memory cells that fail the retention time test according to the first test data and the second test data, realizing the effective integration of testing the test values from low to high, from high to low and the VRT cycle together, can efficiently and accurately test the minimum retention time of the memory cells, and effectively record the position information of the failed memory cells without damaging the test memory; solves the problems of the efficiency and accuracy of testing the retention time; and minimizes the memory usage by dumping the most useful position information, and can be used in the wafer test and aging test phases.

[0057] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings according to these drawings without creative efforts. In the drawings:

[0059] Figure 1 is a flowchart of a test method for a semiconductor device provided by an embodiment of the present disclosure;

[0060] Figure 2 is a flowchart of a test method for a semiconductor device provided by another embodiment of the present disclosure;

[0061] Figure 3 is a schematic diagram of a test device for a semiconductor device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0062] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.

[0063] In addition, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of the embodiments of the present disclosure. However, those skilled in the art will realize that the technical solutions of the present disclosure can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be employed. In other cases, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the present disclosure.

[0064] The block diagrams shown in the drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0065] The flowcharts shown in the drawings are merely illustrative and do not necessarily include all the contents and operations / steps, nor are they necessarily executed in the order described. For example, some operations / steps can be decomposed, while some operations / steps can be combined or partially combined, so the actual execution order may change according to the actual situation.

[0066] The inventors have found that there are currently three main methods for testing the retention time and screening memory cells with short retention times as follows:

[0067] First, measure whether the retention time of a certain memory cell passes at a certain set retention time. For example, if the set retention time is 64 ms, the retention time during testing is greater than 64 ms, then it passes; if it is less than 64 ms, then it fails. The disadvantage of this testing method is that during subsequent other tests, the test results are different, the correlation is poor, and the test results are inaccurate; because the VRT phenomenon itself is changing, it is impossible to obtain a definite result with a single measurement;

[0068] Second, measure multiple times whether the retention time of a certain memory cell passes a certain set value at a certain set retention time. As long as it fails once, it is considered that this memory cell fails this set value. The disadvantage of this measurement is that it is very time-consuming, and the useful information that can be obtained is very little;

[0069] Third, measurements are performed in ascending or descending retention time order. For example, measure in sequence whether it passes when the retention times are 16 ms, 24 ms, 32 ms, and 40 ms. If it stays at a certain retention time, it is considered to pass at that retention time. For example, if it passes at 24 ms but fails at 32 ms, it is considered that the retention time at which this memory cell passes is 24 ms. One drawback of this method is that it is time-consuming. On the other hand, due to the existence of test noise and the VRT phenomenon, the minimum retention time cannot be determined.

[0070] In addition, another drawback of the above-mentioned prior art is that it is difficult to collect the location information of failed memory cells. Because the test data volume of different memory cells is different. For example, methods two and three will test a lot of data or the obtained retention time data is variable (i.e., inaccurate), so the location information of failed memory cells cannot be accurately collected.

[0071] Due to the existence of the VRT phenomenon, the test noise increases and the temperature requirement is also very high. Therefore, how to accurately test and screen out failed memory cells is crucial. In view of the above technical problems, embodiments of the present disclosure first provide a test method for semiconductor devices, as Figure 1 shown, the test method includes:

[0072] Step S100: Preset a first retention time range and a first step size;

[0073] Step S200: Form a plurality of test values according to the first retention time range and the first step size, and sequentially test a plurality of memory cells in the semiconductor device according to the plurality of test values from small to large; determine the memory cells in the test whose retention time is less than the test value, and record the locations of the memory cells whose retention time is less than the test value and the corresponding test values to form first test data;

[0074] Step S300: Preset a second retention time range and a second step size;

[0075] Step S400: Form a plurality of test values according to the second retention time range and the second step size, and sequentially test a plurality of memory cells in the semiconductor device according to the plurality of test values from large to small; determine the memory cells in the test whose retention time is less than the test value, and record the locations of the memory cells whose retention time is less than the test value and the corresponding test values to form second test data;

[0076] Step S500: Determine the locations and corresponding test values of the memory cells that fail the retention time test according to the first test data and the second test data.

[0077] The test method for a semiconductor device provided by the present disclosure forms multiple test values according to a first retention time range and a first step size, and sequentially tests multiple memory cells in the semiconductor device according to the multiple test values from smallest to largest; determines the memory cells in the test whose retention time is less than the test value corresponding to each test value, and records the position of the memory cell and the corresponding test value to form first test data; forms multiple test values according to a second retention time range and a second step size, and sequentially tests multiple memory cells in the semiconductor device according to the multiple test values from largest to smallest; determines the memory cells in the test whose retention time is less than the test value corresponding to each test value, and records the position of the memory cell and the corresponding test value to form second test data; determines the positions and corresponding test values of the memory cells that fail the retention time test according to the first test data and the second test data, realizes the effective integration of testing the test values from low to high, from high to low and the VRT cycle together, can efficiently and accurately test the minimum retention time of the memory cells, and effectively records the position information of the failed memory cells without damaging the test memory; solves the problems of the efficiency and accuracy of testing the retention time; and minimizes the memory usage by dumping the most useful position information, and can be used in the wafer test and the aging test stage (aging test of the RDBI segment after packaging).

[0078] Next, each step in the test method for a semiconductor device provided by the present disclosure will be described in detail.

[0079] In step S100, a first retention time range and a first step size are preset.

[0080] Specifically, the retention time of the memory cell is affected by factors such as temperature, manufacturing process, test method or other unknown reasons. Since the test temperature range is large and the retention time is different at different test temperatures, and the tester itself also has limitations on the number of test steps, a range and a step size are roughly estimated first.

[0081] Among them, due to the limitation of the number of tests on the machine, such as 32 test values are limited for aging tests; 64 test values are limited for wafer tests; if the number of test values is too small, the retention time will not be accurate enough, and if the number of test values is too large, it may exceed the number limit of the machine; therefore, through optimization, a retention time range and a step size can be given that can be close to the number limit of the machine, that is, the test accuracy is relatively high, and can cover the entire range of the retention time.

[0082] Therefore, a retention time range and a step size can be roughly estimated first, and then tests are carried out at multiple test environmental temperatures. Multiple memory cells using the retention time and the step size in the semiconductor device are respectively tested according to the roughly estimated retention time range and the step size to obtain test data, and the roughly estimated retention time range and the step size are optimized according to the test data to form an optimized preset first retention time range and a first step size.

[0083] In step S200, a plurality of test values are formed according to the first retention time range and the first step size, and a plurality of memory cells in the semiconductor device are sequentially tested according to the plurality of test values from small to large; the memory cells with a retention time less than the test value during the test corresponding to each test value are determined, and the positions of the memory cells with a retention time less than the test value and the corresponding test values are recorded to form first test data.

[0084] Specifically, a plurality of test values are formed according to the first retention time range and the first step size; then, according to the order of the plurality of test values from small to large, the test values are sequentially selected to test a plurality of memory cells in the semiconductor device;

[0085] It is judged whether the retention time of the plurality of memory cells in the semiconductor device during the test corresponding to each test value is greater than or equal to the test value;

[0086] If the retention time of the memory cell is greater than or equal to the test value, it is judged whether the test value is less than the maximum value of the first retention time range;

[0087] If the retention time of the memory cell is less than the test value, the failed test value of the memory cell and its position information are output;

[0088] If the test value is less than the maximum value of the first retention time range, the next test value is sequentially selected according to the order of the test values from small to large, and the test of whether the retention time of the plurality of memory cells in the semiconductor device passes is continued according to the selected next test value;

[0089] The first test data is formed according to the test values and position information of the memory cells output during the test corresponding to each test value, that is, the test values and their position information corresponding to the memory cells that fail the test are recorded. The first test data only records the memory cells that fail the test, and the use of memory is minimized by dumping these most useful position information.

[0090] In step S300, a preset second retention time range and a second step size are set.

[0091] Specifically, a retention time range and a step size can be roughly estimated first, and then tests are carried out at multiple test environmental temperatures. Multiple memory cells in the semiconductor device that adopt the retention time and the step size are respectively tested according to the roughly estimated retention time range and the step size to obtain test data. The roughly estimated retention time range and the step size are optimized according to the test data to form an optimized preset second retention time range and a second step size.

[0092] Among them, the first retention time range can be the same as the second retention time range, and the first step size can be the same as the second step size, that is, the first retention time range and the first step size can be directly used as the second retention time range and the second step size.

[0093] In step S400, multiple test values are formed according to the second retention time range and the second step size. Multiple memory cells in the semiconductor device are sequentially tested according to the multiple test values from largest to smallest; the memory cells whose retention time is less than the test value during the test corresponding to each test value are determined, and the positions of the memory cells whose retention time is less than the test value and the corresponding test values are recorded to form second test data.

[0094] Specifically, multiple test values are formed according to the second retention time range and the second step size; then, according to the order of the multiple test values from largest to smallest, the test values are sequentially selected to test multiple memory cells in the semiconductor device;

[0095] It is judged whether the retention time of multiple memory cells in the semiconductor device during the test corresponding to each test value is greater than or equal to the test value;

[0096] If the retention time of the memory cell is greater than or equal to the test value, it is judged whether the test value is less than or equal to the minimum value of the second retention time range;

[0097] If the retention time of the memory cell is less than the test value, the unqualified test value of the memory cell and its position information are output;

[0098] If the test value is greater than the minimum value of the second retention time range, the next test value is sequentially selected according to the order of the test values from largest to smallest, and the test of whether the retention time of multiple memory cells in the semiconductor device passes is continued according to the selected next test value;

[0099] If the test value is less than or equal to the minimum value of the second retention time range, the test can be stopped.

[0100] The second test data is formed based on the test values and location information of the storage units output during the test corresponding to each test value, that is, the test values corresponding to the storage units that fail the test and their location information are recorded. The second test data only records the storage units that fail the test, and by dumping these most useful location information, the memory usage is minimized.

[0101] In one embodiment of the present disclosure, as Figure 2 shown, after the detection process of step S200 is completed, the above step S400 can be performed, that is, first, multiple storage units in the semiconductor device are sequentially tested according to multiple test values from small to large, and then sequentially tested according to multiple test values from large to small, which increases the process of cross-verification.

[0102] Specifically, if the test value is greater than or equal to the maximum value of the first retention time range, it is determined whether the test value is less than or equal to the minimum value of the second retention time range.

[0103] If the test value is greater than the minimum value of the second retention time range, step S400 is performed, that is, according to the order of multiple test values from large to small, test values are sequentially selected to test multiple storage units in the semiconductor device.

[0104] In another embodiment of the present disclosure, after the detection process of step S400 is completed, the above step S200 can be performed, that is, first, multiple storage units in the semiconductor device are sequentially tested according to multiple test values from large to small, and then sequentially tested according to multiple test values from small to large, which increases the process of cross-verification.

[0105] Specifically, if the test value is less than or equal to the minimum value of the second retention time range, it is determined whether the test value is greater than or equal to the maximum value of the first retention time range.

[0106] If the test value is less than the maximum value of the first retention time range, step S200 is performed, that is, according to the order of multiple test values from small to large, test values are sequentially selected to test multiple storage units in the semiconductor device.

[0107] In step S500, the locations and corresponding test values of the storage units that fail the retention time test are determined according to the first test data and the second test data.

[0108] Specifically, the locations and corresponding test values of the storage units that fail the retention time test can be determined according to the first test data, and the locations and corresponding test values of the storage units that fail the retention time test can be determined according to the second test data; the union statistics of the storage units that fail the retention time test determined by the first test data and the second test data are used as the test result.

[0109] In another embodiment of the present disclosure, the testing method further includes:

[0110] Determine the number of tests. Each time a test is performed based on a test value, it is recorded as one test completed;

[0111] Before testing multiple memory cells in the semiconductor device in sequence according to multiple test values from small to large and testing multiple memory cells in the semiconductor device in sequence according to multiple test values from large to small, determine whether the number of tests has reached the maximum value; due to the limitation of the number of tests of the machine tool, determine whether the number of tests has reached the limit number of tests of the machine tool;

[0112] If the maximum value of the number of tests is not reached, continue the test;

[0113] If the maximum value of the number of tests is reached, stop the test.

[0114] Among them, according to the number of tests, a first step length and a second step length are preset. If the number of test values is too small, the retention time is not accurate enough; if the number of test values is too large, it may exceed the number limit of the machine tool; therefore, according to the number of tests of the machine tool, through optimization, the first step length and the second step length can be given to be close to the number limit of the machine tool, that is, the test accuracy is relatively high, and at the same time, the entire range of the retention time can be covered.

[0115] The following introduces the device embodiments of the present disclosure, which can be used to execute the above-mentioned testing method of the semiconductor device of the present disclosure.

[0116] An embodiment of the present disclosure further provides a testing device for a semiconductor device, as Figure 3 shown. The testing device 900 includes:

[0117] A parameter presetting module 910, configured to preset a first retention time range and a first step length, and preset a second retention time range and a second step length;

[0118] A first testing module 920, connected to the parameter presetting module 910. The first testing module 920 is configured to form multiple test values according to the first retention time range and the first step length, and test multiple memory cells in the semiconductor device in sequence according to the multiple test values from small to large; determine the memory cells in the test whose retention time is less than the test value, and record the positions of the memory cells whose retention time is less than the test value and the corresponding test values to form first test data;

[0119] The second test module 930, connected to the parameter presetting module 910 and the first test module 920, is configured to form a plurality of test values according to the second retention time range and the second step length, and sequentially test a plurality of memory cells in the semiconductor device according to the plurality of test values from largest to smallest; determine the memory cells whose retention time during the test corresponding to each test value is less than the test value, and record the positions of the memory cells whose retention time is less than the test value and the corresponding test values, thereby forming second test data;

[0120] The output module 940, connected to the first test module 920 and the second test module 930, is configured to determine the positions of the memory cells that fail the retention time test and the corresponding test values according to the first test data and the second test data.

[0121] For the test device of the semiconductor device provided by the present disclosure, the parameter presetting module presets the first retention time range and the first step length, and presets the second retention time range and the second step length. The first test module forms a plurality of test values according to the first retention time range and the first step length, and sequentially tests a plurality of memory cells in the semiconductor device according to the plurality of test values from smallest to largest; determines the memory cells whose retention time during the test corresponding to each test value is less than the test value, and records the positions of the memory cells and the corresponding test values, thereby forming first test data; the second test module forms a plurality of test values according to the second retention time range and the second step length, and sequentially tests a plurality of memory cells in the semiconductor device according to the plurality of test values from largest to smallest; determines the memory cells whose retention time during the test corresponding to each test value is less than the test value, and records the positions of the memory cells and the corresponding test values, thereby forming second test data; the output module determines the positions of the memory cells that fail the retention time test and the corresponding test values according to the first test data and the second test data, integrating the test of the test values from low to high and from high to low and the VRT cycle effectively together, which can test the minimum retention time of the memory cells efficiently and accurately, and effectively record the position information of the failed memory cells without damaging the test memory; solves the problems of the efficiency and accuracy of testing the retention time; and minimizes the memory usage by dumping the most useful position information, and can be used in the wafer test and the aging test phase.

[0122] Since each functional module of the test device of the semiconductor device in the exemplary embodiment of the present disclosure corresponds to the steps in the exemplary embodiment of the above-mentioned test method of the semiconductor device, for the details not disclosed in the embodiment of the present disclosure device, please refer to the embodiment of the above-mentioned test method of the semiconductor device of the present disclosure.

[0123] It should be noted that although several modules or units of a device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more of the above-described modules or units can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0124] Through the description of the above embodiments, those skilled in the art can easily understand that the exemplary embodiments described herein can be implemented by software or by a combination of software and necessary hardware. Therefore, the technical solutions according to the embodiments of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium or on a network, including several instructions to enable a computing device (which can be a personal computer, a server, a touch terminal, or a network device, etc.) to execute the method according to the embodiments of the present disclosure.

[0125] After considering the specification and practicing the invention disclosed herein, those skilled in the art will readily conceive of other embodiments of the present disclosure. This application is intended to cover any variations, uses, or adaptations of the present disclosure, which follow the general principles of the present disclosure and include well-known common general knowledge or conventional technical means in the technical field not disclosed by the present disclosure. The specification and examples are only regarded as exemplary, and the true scope and spirit of the present disclosure are pointed out by the following claims.

[0126] It should be understood that the present disclosure is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present disclosure is only limited by the appended claims.

Claims

1. A test method for a semiconductor device, characterized in that, it includes: Presetting a first retention time range and a first step size; Forming a plurality of test values according to the first retention time range and the first step size, and sequentially testing a plurality of memory cells in the semiconductor device according to the plurality of test values from small to large; determining the memory cells in the test whose retention time is less than the test value corresponding to each test value, and recording the positions of the memory cells whose retention time is less than the test value and the corresponding test values to form first test data; Presetting a second retention time range and a second step size; Forming a plurality of test values according to the second retention time range and the second step size, and sequentially testing a plurality of memory cells in the semiconductor device according to the plurality of test values from large to small; determining the memory cells in the test whose retention time is less than the test value corresponding to each test value, and recording the positions of the memory cells whose retention time is less than the test value and the corresponding test values to form second test data; Determining the positions and corresponding test values of the memory cells that fail the retention time test according to the first test data and the second test data.

2. The test method according to claim 1, characterized in that, The presetting of the first retention time range and the first step size includes: Presetting a retention time, a step size, and a plurality of test ambient temperatures; Testing a plurality of memory cells in the semiconductor device that adopt the retention time and the step size according to the retention time and the step size respectively at a plurality of test ambient temperatures to obtain test data; Presetting the first retention time range and the first step size according to the test data, the retention time, and the step size.

3. The test method according to claim 1, characterized in that, The presetting of the second retention time range and the second step size includes: Presetting a retention time, a step size, and a plurality of test ambient temperatures; Testing a plurality of memory cells in the semiconductor device that adopt the retention time and the step size according to the retention time and the step size respectively at a plurality of test ambient temperatures to obtain test data; Presetting the second retention time range and the second step size according to the test data, the retention time, and the step size.

4. The test method according to claim 1, characterized in that, The first retention time range is the same as the second retention time range, and the first step size is the same as the second step size.

5. The test method according to claim 1, characterized in that, Forming a plurality of test values according to the first retention time range and the first step size, and sequentially testing a plurality of memory cells in the semiconductor device according to the plurality of test values from small to large; determining the memory cells in the test whose retention time is less than the test value corresponding to each test value, and recording the positions of the memory cells whose retention time is less than the test value and the corresponding test values to form first test data, including: Forming a plurality of test values according to the first retention time range and the first step size; Sequentially selecting the test values to test a plurality of memory cells in the semiconductor device according to the ascending order of the plurality of test values; Judging whether the retention time of the plurality of memory cells in the semiconductor device during the test corresponding to each test value is greater than or equal to the test value; If it is greater than or equal to the test value, determine whether the test value is less than the maximum value of the first retention time range; If it is less than the test value, output the test value and location information of the storage unit; If the test value is less than the maximum value of the first retention time range, sequentially select the next test value, and continue to test multiple storage units in the semiconductor device according to the selected next test value; Form first test data based on the test values and location information of the storage units output during the test corresponding to each test value.

6. The test method according to claim 5, wherein, Form multiple test values according to the second retention time range and the second step length, and sequentially test multiple storage units in the semiconductor device according to the multiple test values from largest to smallest; determine the storage units in which the retention time is less than the test value during the test corresponding to each test value, and record the locations and corresponding test values of the storage units whose retention time is less than the test value to form second test data, including: Form multiple test values according to the second retention time range and the second step length; According to the order of the multiple test values from largest to smallest, sequentially select the test values to test multiple storage units in the semiconductor device; Judge whether the retention time of multiple storage units in the semiconductor device during the test corresponding to each test value is greater than or equal to the test value; If it is greater than or equal to the test value, determine whether the test value is less than or equal to the minimum value of the second retention time range; If it is less than the test value, output the test value and location information of the storage unit; If the test value is greater than the minimum value of the second retention time range, sequentially select the next test value, and continue to test multiple storage units in the semiconductor device according to the selected next test value; Form second test data based on the test values and location information of the storage units output during the test corresponding to each test value.

7. The test method according to claim 6, wherein, The test method further includes: If the test value is greater than or equal to the maximum value of the first retention time range, determine whether the test value is less than the minimum value of the second retention time range; If the test value is greater than the minimum value of the second retention time range, according to the order of the multiple test values from largest to smallest, sequentially select the test values to test multiple storage units in the semiconductor device.

8. The test method according to claim 1, wherein, The test method further includes: Determine the number of tests; Before sequentially testing multiple storage units in the semiconductor device according to the multiple test values from smallest to largest and sequentially testing multiple storage units in the semiconductor device according to the multiple test values from largest to smallest, judge whether the number of tests reaches the maximum value; If the maximum value of the number of tests is not reached, continue the test; If the maximum value of the number of tests is reached, stop the test.

9. The test method according to claim 8, wherein, Preset the first step length and the second step length according to the number of tests.

10. The testing method according to claim 1, wherein, determining the positions and corresponding test values of the memory cells that fail the retention time test according to the first test data and the second test data includes: determining the positions and corresponding test values of the memory cells that fail the retention time test according to the first test data; determining the positions and corresponding test values of the memory cells that fail the retention time test according to the second test data; performing union statistics on the memory cells that fail the retention time test determined by the first test data and the second test data as the test result.

11. A testing device for a semiconductor device, wherein, comprising: a parameter presetting module configured to preset a first retention time range and a first step size, and preset a second retention time range and a second step size; a first testing module connected to the parameter presetting module, the first testing module being configured to form a plurality of test values according to the first retention time range and the first step size, and sequentially test a plurality of memory cells in the semiconductor device according to the plurality of test values from small to large; determining the memory cells with a retention time less than the test value in each test corresponding to the test values, and recording the positions and corresponding test values of the memory cells with a retention time less than the test value to form first test data; a second testing module connected to the parameter presetting module and the first testing module, the second testing module being configured to form a plurality of test values according to the second retention time range and the second step size, and sequentially test a plurality of memory cells in the semiconductor device according to the plurality of test values from large to small; determining the memory cells with a retention time less than the test value in each test corresponding to the test values, and recording the positions and corresponding test values of the memory cells with a retention time less than the test value to form second test data; an output module connected to the first testing module and the second testing module, the output module being configured to determine the positions and corresponding test values of the memory cells that fail the retention time test according to the first test data and the second test data.

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