Auxiliary wafer and method of forming the same, semiconductor process

Abstract

The embodiment of the present application provides a kind of auxiliary wafer and its forming method, semiconductor process, auxiliary wafer includes: wafer, at least two test structures are in the wafer, the feature of each test structure is identical with the feature of corresponding product wafer, at least one feature of different test structure is different, the feature includes test feature and non-test feature, the test feature of at least two test structures is different;Each test structure includes sequentially arranged multiple test grooves, and the test feature includes the structure density of multiple test grooves, and the structure density includes opening width and vertical depth;Each product wafer includes sequentially arranged multiple process grooves, and the structure density of multiple test grooves in the test structure is equal to the structure density of multiple process grooves in corresponding product wafer.The embodiment of the present application is conducive to reducing wafer rejection rate and improving test efficiency.

Description

Technical Field

[0001] The embodiments of the present invention relate to the semiconductor field, and in particular to an auxiliary wafer and a method for forming the same, and a semiconductor manufacturing process. Background Technology

[0002] As the semiconductor industry continues to develop, companies are constantly shrinking the critical dimensions of semiconductor devices in pursuit of maximum profit and performance. However, as the critical dimensions of semiconductor devices continue to shrink, the negative impact of tiny defects that were originally present in semiconductor devices may be amplified, thus significantly affecting the performance of the miniaturized semiconductor devices.

[0003] Minor defects can originate from inherent flaws in the manufacturing process or from mismatches between the process and the structure. The presence of these minor defects can cause semiconductor devices to fail to meet pre-defined performance requirements, increasing wafer scrap rates and consequently raising the manufacturing cost of semiconductor devices. Summary of the Invention

[0004] This invention provides an auxiliary wafer and its formation method, as well as a semiconductor manufacturing process, which helps to reduce wafer scrap rate and improve testing efficiency.

[0005] To address the aforementioned problems, embodiments of the present invention provide an auxiliary wafer, comprising: a wafer having at least two test structures, each test structure having features identical to those of a corresponding product wafer, and at least one feature differing between different test structures, the features including test features and non-test features, and at least two test structures having different test features; each test structure comprising a plurality of test grooves arranged sequentially, the test features including the structural density of the plurality of test grooves, the structural density including opening width and vertical depth; each product wafer comprising a plurality of process grooves arranged sequentially, the structural density of the plurality of test grooves in the test structure being equal to the structural density of the plurality of process grooves in the corresponding product wafer.

[0006] Optionally, the test features may further include at least one of the extension direction, arrangement density, or sidewall morphology of the test groove.

[0007] Optionally, at least one of the test structures further includes at least one auxiliary groove, wherein the auxiliary groove is located on at least one side of the plurality of test grooves in the arrangement direction of the test grooves; the test feature further includes at least one of the number, position or opening width of the auxiliary grooves.

[0008] Optionally, the test structure includes two auxiliary arrays, each auxiliary array consisting of a plurality of auxiliary grooves arranged sequentially, with the plurality of test grooves located between the two auxiliary arrays; the test feature also includes at least one of the adjacent spacing of the auxiliary grooves or the number of auxiliary grooves included in each auxiliary array.

[0009] Optionally, the test structure includes a protective layer and a plurality of initial grooves arranged in sequence. The protective layer covers the bottom surface and sidewalls of the initial grooves and the top surface of the wafer. The protective layer located within the initial grooves forms the test grooves.

[0010] Optionally, the initial groove of the product wafer corresponding to the test structure is used to form a functional groove corresponding to a functional component, the thickness of the protective layer is equal to the opening width of the functional groove, and the functional component includes at least one of an active region, a bit line, or a capacitor contact hole.

[0011] Optionally, the wafer includes a silicon substrate and a buffer layer covering the surface of the silicon substrate, the buffer layer having a harder hardness than the silicon substrate, and the initial groove penetrating the buffer layer and located within the silicon substrate.

[0012] Accordingly, embodiments of the present invention also provide a method for forming an auxiliary wafer, comprising: providing an initial wafer; processing the initial wafer to form a wafer having at least two test structures, wherein the features of each test structure are the same as the features of the corresponding product wafer, at least one feature of different test structures is different, the features include test features and non-test features, and the test features of at least two test structures are different; each test structure includes a plurality of test grooves arranged in sequence, the test features include the structural density of the plurality of test grooves, the structural density including the opening width and vertical depth; each product wafer includes a plurality of process grooves arranged in sequence, the structural density of the plurality of test grooves in the test structure is equal to the structural density of the plurality of process grooves in the corresponding product wafer.

[0013] Optionally, the process step of forming at least two test structures includes: providing a silicon substrate; forming a buffer layer covering the surface of the silicon substrate, the buffer layer having a harderness than the silicon substrate, the buffer layer and the silicon substrate forming the initial wafer; etching the buffer layer and the silicon substrate to form a first test structure and a second test structure, the first test structure including a plurality of first test grooves arranged in sequence, the second test structure including a plurality of second test grooves arranged in sequence, the first test grooves and the second test grooves penetrating the buffer layer and located within the silicon substrate, the structural density of the plurality of first test grooves being different from the structural density of the plurality of second test grooves.

[0014] Optionally, the process steps for forming the first test groove and the second test groove include: etching the buffer layer and the silicon substrate to form a first initial groove and a second initial groove; forming a protective layer that covers the bottom surface and sidewalls of the first initial groove and the bottom surface and sidewalls of the second initial groove, wherein the protective layer located in the first initial groove forms the first test groove, and the protective layer located in the second initial groove forms the second test groove.

[0015] Accordingly, embodiments of the present invention also provide a semiconductor manufacturing process, comprising: providing an auxiliary wafer and a product wafer as described in any of the preceding claims, the auxiliary wafer having a first test structure having a plurality of first test grooves arranged sequentially, and the product wafer having a plurality of first process grooves; performing a first deposition process to form a first filling layer, the first filling layer filling the first test grooves of the first test structure and covering the top surface of the wafer; detecting the height difference between different positions of the first filling layer above the first test structure, and if the height difference is less than a preset value, performing the first deposition process on the plurality of first process grooves of the product wafer.

[0016] Optionally, the semiconductor process further includes: removing the first filler layer; performing a second deposition process to form a second filler layer, the second filler layer filling the first test groove of the first test structure and covering the top surface of the wafer, the material of the second filler layer being different from the material of the first filler layer; detecting the height difference between different positions of the second filler layer above the first test structure, if the height difference is less than the preset value, then performing the second deposition process on the plurality of first process grooves of the product wafer; and removing the second filler layer.

[0017] Optionally, the auxiliary wafer has a second test structure, the second test structure having a plurality of second test grooves; the semiconductor process further includes: performing the first deposition process to form a third filling layer, the third filling layer filling the second test grooves of the second test structure and covering the top surface of the wafer; detecting the height difference between different positions of the third filling layer above the second test structure, and if the height difference is less than the preset value, then performing the first deposition process on the plurality of second process grooves of another product wafer.

[0018] Optionally, the preset value is 30nm to 50nm.

[0019] Optionally, the first filler layer is made of SOC material, and the first filler layer is removed by an ashing process.

[0020] Accordingly, embodiments of the present invention also provide a semiconductor manufacturing process, comprising: providing an auxiliary wafer and a product wafer as described in any of the preceding claims, the auxiliary wafer having a first test structure having a plurality of first test grooves arranged sequentially, and the product wafer having a plurality of first process grooves; performing a first deposition process to form a first filling layer, the first filling layer filling the first test grooves of the first test structure and covering the top surface of the wafer; detecting the surface morphology between different positions of the first filling layer above the first test structure, and if the surface morphology meets preset requirements, performing the first deposition process on the plurality of first process grooves of the product wafer.

[0021] In the above technical solution, an auxiliary wafer with test structures is provided. Since the characteristics of each test structure are the same as those of the corresponding product wafer, the processing technology and the product wafer can be tested through the corresponding test structures in the auxiliary wafer before the product wafer is processed, so as to ensure that the product wafer and the corresponding processing technology meet the preset performance requirements and reduce the wafer scrap rate. At the same time, the auxiliary wafer has at least two test structures. During the testing process, different test structures can be tested simultaneously using the same processing technology, which is beneficial to improving testing efficiency.

[0022] In addition, auxiliary wafers can also be used to test the impact of auxiliary grooves on product wafers and processing technology. That is, to test whether the setting of auxiliary grooves can partially offset some of the inherent defects of the product wafer or partially offset the inherent defects of the processing technology. Based on the test results, the product wafer and processing technology can be optimized and improved, which is conducive to improving the yield of semiconductor devices formed based on product wafers. Attached Figure Description

[0023] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0024] Figure 1 This is a schematic diagram of the structure corresponding to each step of a semiconductor manufacturing process.

[0025] Figures 2 to 4 This is a schematic diagram of the structure of the auxiliary wafer provided in an embodiment of the present invention;

[0026] Figures 5 to 7 This is a schematic diagram of the structure corresponding to each step of the auxiliary wafer formation method provided in the embodiments of the present invention;

[0027] Figure 8 This is a schematic diagram of the structure corresponding to the semiconductor manufacturing process provided in an embodiment of the present invention. Detailed Implementation

[0028] Before forming functional recesses to fill functional components, a corresponding mask layer is often formed first. The pattern openings of the mask layer are then set according to the characteristics of the functional recess. However, as the feature size of semiconductor devices shrinks, to achieve etching of functional recesses with smaller opening widths, it is generally chosen to first form process recesses with larger opening widths, and then use self-aligned double patterning (SADP) to form corresponding pattern openings with smaller opening widths. Finally, the functional recesses are formed by etching using these pattern openings. The specific process steps are as follows:

[0029] refer to Figure 1 The present invention provides a product wafer 200 having a plurality of initial grooves 210 arranged in sequence; a sacrificial layer 220 is formed, the sacrificial layer 220 covering the sidewalls and bottom surface of each initial groove 210, and covering the top surface of the product wafer 200; and a fill layer 230 is formed, the fill layer 230 filling each initial groove 210.

[0030] The filler layer 230 is generally formed using a maskless deposition process. During this process, the deposition rate and time are the same in different regions, meaning that the total amount of material deposited in the filler layer 230 per unit area is the same. Since the initial groove 210 accommodates some of the filler layer 230 material, the top surface of the filler layer 230 in the first region 200a containing the initial groove 210 is often lower than the top surface of the filler layer 230 in the adjacent second region 200b. The top surface profile of the filler layer 230 is related to the characteristic parameters of the initial groove 210 and the fluidity of the filler layer 230 material. The better the fluidity of the filler layer 230 material, the smoother the top surface profile. However, regardless of how smooth it is, the top surface of the filler layer 230 always gradually increases in the direction from the first region 200a to the second region 200b.

[0031] The first region 200a includes a middle region 201 and an edge region 202. It is understood that if the filling layer 230 of the middle region 201 just exposes the surface of the underlying sacrificial layer 220, then the filling layer 230 of the edge region 202 will still cover the surface of the underlying sacrificial layer 220. Furthermore, during the process of etching the sacrificial layer 220 covering the sidewalls of the initial groove 210 using a maskless dry etching process to form a pattern opening, since the top surface of the sacrificial layer 220 in the edge region 202 is still covered by the filling layer 230, until the sacrificial layer 220 covering the sidewalls of the initial groove 210 in the middle region 201 is etched away, a significant amount of the sacrificial layer 220 covering the sidewalls of the initial groove 210 in the edge region 202 may remain, or even remain unetched.

[0032] In other words, in the small linewidth etching process, the pattern structure density varies in different regions. In particular, the middle region 201 has a large number of small linewidth patterns, resulting in a high structure density. However, the pattern formation density is lower in the edge region 202, especially the edge region facing the second region 200b. As a result, when performing the same process, such as filling the filler material at the same time, height differences occur between different regions. This height difference leads to abnormalities in the boundary processes of different regions. For example, only the middle region 201 forms an effective pattern opening, while the edge region 202 does not form an effective pattern opening, which will affect subsequent processes.

[0033] To address the aforementioned issues, embodiments of the present invention provide an auxiliary wafer and its formation method, as well as a semiconductor manufacturing process. The auxiliary wafer includes test structures. Since the characteristics of each test structure are identical to those of the corresponding product wafer, the processing technology and the product wafer can be tested using the corresponding test structures in the auxiliary wafer before processing the product wafer. This monitors the stability of the process, ensuring that the product wafer and the corresponding processing technology meet preset performance requirements and reducing wafer scrap rates. Furthermore, the auxiliary wafer contains at least two test structures, allowing for simultaneous testing of different test structures using the same processing technology during the testing process, which improves testing efficiency.

[0034] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the various embodiments of the present invention to enable the reader to better understand this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0035] refer to Figure 2 The auxiliary wafer includes: a wafer 100, which has at least two test structures 101. Each test structure 101 has the same features as the corresponding product wafer. At least one feature of the different test structures 101 is different. The features include test features and non-test features. The test features of at least two test structures 101 are different. Each test structure 101 includes a plurality of test grooves arranged in sequence. The test features include the structural density of the plurality of test grooves. The structural density includes the opening width and vertical depth. Each product wafer includes a plurality of process grooves arranged in sequence. The structural density of the plurality of test grooves in the test structure 101 corresponds to the structural density of the plurality of process grooves in the product wafer.

[0036] Auxiliary wafers, with varying structural densities and angles, can simulate the conditions on product wafers. This allows for characterization of the center and edge morphology of the auxiliary wafers, as well as the structures at different structural densities. This not only enables monitoring of the product wafer's manufacturing process and stability but also allows for the design of next-generation product wafers based on the structural density effect, making them more rational and shortening the development cycle. In this paper, the groove formed by the sacrificial layer within the initial groove is designated as the test groove. The test groove is used to fill the filler layer. Multiple functional grooves arranged sequentially have corresponding test grooves. By monitoring the top surface contour of the filler layer after filling the test grooves, the fabrication feasibility of the sequentially arranged functional grooves can be analyzed. The fabrication feasibility of the functional grooves is mainly reflected in whether, under existing processing technology, a sufficient number of effective pattern openings can be formed within a preset etching time. If formation is not possible, the functional groove is deemed unfeasible.

[0037] The opening width of the test groove is limited by the spacing between adjacent functional grooves and the opening width of the functional groove. The larger the opening width, the more filling layer material the test groove can accommodate, and the greater the top surface range of the filling layer in the first region. The vertical depth of the test groove is limited by the vertical depth of the functional groove. During the process of etching the functional groove using the pattern opening of the mask layer, the etchant will also etch the mask layer. To ensure selective etching of the functional groove, the mask layer needs a certain thickness, that is, the pattern opening and the test groove have a minimum vertical depth.

[0038] The test features and non-test features of the test groove are determined and selected by technicians as needed. The features of the test groove correspond to the features of the functional groove. Based on the changes in the features of the functional groove, individual changes in each feature corresponding to the test groove may result in the inability to form an effective pattern opening that meets the quantity requirements within the preset etching time. Therefore, in the process of testing the test grooves corresponding to existing product wafers, it is necessary to first prioritize multiple features and then compare and test them one by one according to the ranking results to determine the impact of individual changes in each feature on the formation of the pattern opening. At the same time, due to the limited energy of technicians, only a limited number of features can be selected as test features, while other features are designated as non-test features.

[0039] In actual testing, by identifying test features and non-test features, and then testing only the test features while ignoring or selectively testing the non-test features, it is beneficial to shorten the testing time. Correspondingly, since the testing time is part of the semiconductor device manufacturing time, shortening the testing time is equivalent to shortening the semiconductor device manufacturing time. Therefore, shortening the testing time helps to reduce the manufacturing cost of semiconductor devices and provide timing leeway for other manufacturing processes.

[0040] In this embodiment, technicians prioritize multiple features based on their variations across different scenarios. For example, the structural density of functional grooves varies considerably across different process scenarios. This application can verify the fabrication feasibility of functional grooves with multiple structural densities through a single test. Since the number of structural density test samples is large, technicians can accurately analyze the impact trend of structural density on fabrication feasibility based on the test results. Furthermore, based on the analysis results, the structural density of multiple functional components can be optimized to ensure the effectiveness of a large number of functional components. In other words, using frequently changing features as test features helps obtain accurate analysis results, thereby maximizing the improvement of functional structure characteristics and the electrical performance of the corresponding semiconductor devices.

[0041] Specifically, when forming the active region, bit line, and capacitor contact hole of a semiconductor device, the structural density of the functional grooves corresponding to different functional components is different. Corresponding functional grooves and test grooves need to be formed. To avoid the impact on the electrical performance of the semiconductor device due to the structural features of the active region, bit line, and capacitor contact hole not meeting preset requirements, a corresponding test structure 101 can be set to test the fabrication feasibility of the corresponding functional groove. If the fabrication feasibility of the functional groove meets the requirements, an initial groove and etching process can be used to form a pattern opening, and the pattern opening can be used to etch and form the functional groove, and the functional groove can be filled to form at least one of the active region, bit line, or capacitor contact hole. If the fabrication feasibility of a certain functional groove does not meet the requirements, the structural density of that functional groove can be adjusted according to the test results to ensure the effectiveness of the corresponding functional structure.

[0042] Furthermore, the prioritization of features also depends on the improvements made to the target product wafer. During wafer improvement, engineers often directly adjust the features of the functional recesses, which in turn leads to corresponding adjustments to the features of the test recesses. For example, compared to a high-performance existing product wafer, the target product wafer may have adjusted the structural density of multiple functional recesses. In this case, the structural density of the test recesses corresponding to the functional recesses should be prioritized as a test feature to verify the performance of the target product wafer and avoid a high scrap rate in its fabrication. In other words, if engineers want to improve one or more features on an existing product wafer, the corresponding test recess features should be used as test features to verify the feasibility of the improvement, while features that have not been improved can be considered non-test features.

[0043] It should be noted that one functional groove may correspond to multiple test grooves. Technicians need to test whether each test groove can be used to form a functional groove, and which test groove produces the best quality functional groove, and / or which test groove takes the shortest time to form a functional groove.

[0044] In this embodiment, the test features also include at least one of the extension direction, arrangement density, or sidewall morphology of the test groove. The extension direction of the test groove is defined by the extension direction of the functional groove; the sidewall morphology of the test groove may affect the sidewall morphology of the functional groove.

[0045] For example, wafer 100 includes a first test structure 102, a second test structure 103, a third test structure 104, and a fourth test structure 105. The distinguishing feature between the first test structure 102 and the second test structure 103 is their vertical depth; the distinguishing feature between the first test structure 102 and the third test structure 104 is their extension direction; and the distinguishing feature between the first test structure 102 and the fourth test structure is their arrangement density. That is, at least one feature of each test structure 101 is different, and at least two test structures 101 have different test features. It should be noted that at least two test structures 101 having different test features means that the opening width or vertical depth of the test grooves of at least two test structures 101 are different; furthermore, if the first test structure 102 and the second test structure 103 are the same, then the test structures 101 on wafer 100 only satisfy the condition that "at least two test structures 101 have different test features".

[0046] Of course, the test features of the first test structure 102, the second test structure 103, the third test structure 104, and the fourth test structure 105 can be completely different. For example, they can correspond to the test grooves etched in various process nodes in semiconductor manufacturing, such as active region structures, word line structures, capacitor contact structures, and metal contact layer structures. The test features of these test grooves in these processes, such as extension angle and direction, are different, so that the stability of the corresponding process can be monitored in different test structures.

[0047] In this embodiment, reference Figure 3At least one test structure further includes at least one auxiliary groove 111, which is located on at least one side of the plurality of test grooves 110 in the arrangement direction of the test grooves 110; the test features also include one of the number, position or opening width of the auxiliary grooves 111. To reduce the top surface gradient of the filling layer in the first region 100a, so that more of the wafer 100 top surface is exposed after the maskless dry etching process, the feature parameters of the test grooves 110 can be adjusted to reduce the filling layer material contained in the test grooves 110; or the fluidity of the filling layer material can be increased to make the top surface of the filling layer in the first region 100a tend to be flat; auxiliary grooves 111 can also be provided in the second region 100b to contain part of the filling layer material and reduce the top surface of the filling layer at the edge of the first region 100a.

[0048] It is known that the more auxiliary grooves 111 there are, the closer the auxiliary grooves 111 are to the first region 100a, the larger the opening width of the auxiliary grooves 111, and the lower the top surface height of the edge region 102a of the first region 100a. Furthermore, the auxiliary grooves 111 can be functional grooves within the second region 100b used to fill other functional components. By setting the auxiliary grooves 111, the required size and number of auxiliary grooves 111, as well as the spacing between them, can be accurately determined when forming a stable process, i.e., within a preset height difference range.

[0049] Furthermore, the test structure 101 includes two auxiliary arrays, each consisting of a plurality of auxiliary grooves arranged sequentially, with the multiple test grooves located between the two auxiliary arrays. The test features also include at least one of the adjacent spacing of the auxiliary grooves or the number of auxiliary grooves contained in each auxiliary array. With other parameters remaining constant, a larger adjacent spacing of the auxiliary grooves, a greater number of auxiliary grooves in each auxiliary array, and a larger space occupied by the auxiliary arrays are beneficial. By setting the test features of the auxiliary arrays and performing corresponding tests, it is advantageous to ensure that the auxiliary arrays have a better effect on reducing the top surface height of the edge region 102a, thereby reducing the height difference between the top surfaces of the middle region 101a and the edge region 102a. It also helps to prevent the auxiliary arrays from occupying the positions of adjacent functional components.

[0050] In this embodiment, reference Figure 4 The test structure 101 includes a protective layer 120 and a plurality of initial grooves 140 arranged in sequence. The protective layer 120 covers the bottom surface and sidewalls of the initial grooves 140 and the top surface of the wafer 100. The protective layer 120 located within the initial grooves 140 forms a test groove 110. This helps to avoid the deposition and removal of subsequent filling layers from affecting the structural morphology of the test groove 110, ensuring that the test structure 101 can be used multiple times.

[0051] In this design, the initial groove 140 of the product wafer corresponding to the test structure 101 is used to form the functional groove corresponding to the functional component. The thickness of the protective layer 120 is equal to the opening width of the functional groove. The functional component includes at least one of an active region, a bit line, or a capacitor contact hole. The specific process for forming the functional groove based on the initial groove 140 and the etching process can be referred to the aforementioned method steps and will not be repeated here. The wafer 100 may include a silicon substrate (not shown) and a buffer layer (not shown) covering the surface of the silicon substrate. The hardness of the buffer layer is greater than the hardness of the silicon substrate. The initial groove 140 penetrates the buffer layer and is located within the silicon substrate. The buffer layer helps to avoid damage to the silicon substrate in other areas by the processing process and also helps to improve the positional accuracy of the initial groove 140.

[0052] The protective layer 120 can be an oxide film. The oxide film is prepared by the following methods: furnace tube atmospheric pressure thermal oxidation, which involves high-temperature oxidation at 700℃~1300℃ under atmospheric pressure by introducing O2 or a mixture of O2 and H2; furnace tube low-pressure oxidation, which involves high-temperature oxidation at a low pressure of 0.2 to 10 torr within a temperature range of 700℃-1100℃; and chamber rapid oxidation, which involves rapid thermal oxidation under rapid heating conditions by introducing a mixture of O2 and H2 at 700℃~1300℃.

[0053] In this embodiment, an auxiliary wafer with test structures is provided. Since the characteristics of each test structure are the same as those of the corresponding product wafer, the processing technology and the product wafer can be tested through the corresponding test structures in the auxiliary wafer before the product wafer is processed, so as to ensure that the product wafer and the corresponding processing technology meet the preset performance requirements and reduce the wafer scrap rate. At the same time, the auxiliary wafer has at least two test structures. During the testing process, different test structures can be tested simultaneously using the same processing technology, which is beneficial to improving testing efficiency.

[0054] Accordingly, embodiments of the present invention also provide a method for forming an auxiliary wafer, used to fabricate the aforementioned auxiliary wafer. The method for forming an auxiliary wafer includes: providing an initial wafer; processing the initial wafer to form a wafer having at least two test structures, each test structure having features identical to those of a corresponding product wafer, and at least one feature differing between the different test structures, the features including test features and non-test features, and the test features of at least two test structures being different; each test structure including a plurality of test grooves arranged sequentially, the test features including the structural density of the plurality of test grooves, the structural density including the opening width and vertical depth; each product wafer including a plurality of process grooves arranged sequentially, the structural density of the plurality of test grooves in the test structure being equal to the structural density of the plurality of process grooves in the corresponding product wafer.

[0055] Figures 5 to 8The diagram shows the structural schematics corresponding to each step of the auxiliary wafer formation method provided in the embodiments of the present invention.

[0056] refer to Figure 5 A silicon substrate 10b is provided and a buffer layer 10c is formed thereon. The buffer layer 10c covers the surface of the silicon substrate 10b. The hardness of the buffer layer 10c is greater than that of the silicon substrate 10b. The buffer layer 10c and the silicon substrate 10b together form an initial wafer 10a. (Reference) Figure 6 The buffer layer 10c and the silicon substrate 10b are etched to form an initial groove 140 located within the wafer 100. The initial groove 140 penetrates the buffer layer and is located within the silicon substrate. Figure 7 A protective layer 120 is formed, which covers the bottom and sidewalls of the initial groove 140 and the top surface of the wafer 100. The protective layer 120 located in the initial groove 140 forms a test groove 110.

[0057] For example, the initial groove 140 includes a first initial groove and a second initial groove. The protective layer 120 covers the bottom surface and sidewalls of the first initial groove and the bottom surface and sidewalls of the second initial groove. The protective layer 120 located in the first initial groove forms a first test groove, and the protective layer 120 located in the second initial groove forms a second test groove. Further, the first test structure includes a plurality of first test grooves arranged in sequence, and the second test structure includes a plurality of second test grooves arranged in sequence. The structural density of the plurality of first test grooves is different from the structural density of the plurality of second test grooves.

[0058] In this embodiment, an auxiliary wafer with test structures is provided. Since the characteristics of each test structure are the same as those of the corresponding product wafer, the processing technology and the product wafer can be tested through the corresponding test structures in the auxiliary wafer before the product wafer is processed, so as to ensure that the product wafer and the corresponding processing technology meet the preset performance requirements and reduce the wafer scrap rate. At the same time, the auxiliary wafer has at least two test structures. During the testing process, different test structures can be tested simultaneously using the same processing technology, which is beneficial to improving testing efficiency.

[0059] Accordingly, embodiments of the present invention also provide a semiconductor manufacturing process.

[0060] refer to Figure 8The semiconductor manufacturing process includes: providing an auxiliary wafer and a product wafer as described above, the auxiliary wafer having a first test structure having a plurality of first test grooves 110 arranged in sequence, and the product wafer having a plurality of first process grooves; performing a deposition process to form a first fill layer 130, the first fill layer 130 filling the first test grooves 110 of the first test structure and covering the top surface of the wafer 100; detecting the height difference of the first fill layer 130 above the first test structure (i.e., the difference between the first thickness d1 and the second thickness d2), if the height difference is less than a preset value, it indicates that the product wafer corresponding to the first test structure is valid, and a first deposition process can be performed on the plurality of first process grooves of the product wafer to form a corresponding fill layer, and using the fill layer as a mask etching sacrificial layer to form a preset number of valid pattern openings within a preset time.

[0061] After the height difference is detected, the first filling layer 130 can be removed. If the filling and removal of the first filling layer 130 does not change the structural morphology of the first test groove, the first test structure can be reused. In addition, the size of the preset value can be set according to the test features in the first test structure, such as the size of the opening width. For example, when the opening width, i.e. the line width, is 17nm, the preset value can be 30nm to 50nm, such as 35nm, 40nm or 45nm. The material of the first filling layer 130 can be SOC material, and the first filling layer 130 can be removed by an ashing process.

[0062] In this embodiment, after the first deposition process, the first filler layer 130 is removed and a second deposition process is performed to form a second filler layer. The second filler layer fills the first test groove 110 of the first test structure and covers the top surface of the wafer 100. The material of the second filler layer is different from that of the first filler layer. The height difference between different positions of the second filler layer above the first test structure is detected. If the height difference is less than a preset value, the second deposition process is performed on multiple first process grooves of the product wafer. The second filler layer is then removed. In this way, the effectiveness of the same product wafer under different deposition processes can be tested using the same test structure, reducing the number of test structures required, reducing the area and manufacturing cost of the auxiliary wafer, and monitoring the stability of the process.

[0063] It is important to emphasize that different deposition processes result in different characteristics of the filler layer. Specifically, these differences include variations in the height difference between different locations within the filler layer and variations in its surface morphology. For example, the lower the hardness and the smaller the molecular size of the deposited material, the better its fluidity. This leads to a smaller height difference in the filler layer and a smoother top surface profile. Furthermore, a faster deposition rate results in less fluid time for the deposited material, poorer step coverage, and a worse surface morphology. This poor morphology is primarily characterized by a larger height difference between theoretically flush or nearly flush locations. Additionally, the formation method of the deposited material also affects the surface morphology. If the deposition process employs in-situ reactive synthesis, some precursors may not participate in the reaction and may deposit on the test structure surface, resulting in a poorer surface morphology for the filler layer.

[0064] Whether the height difference between different locations in the filler layer is insufficient or the surface morphology of the filler layer is unsatisfactory, it may result in the inability to form the predetermined number of effective pattern openings within the preset time. Specifically, assuming the protective layer 120 is located as sacrificial material, if the height difference between different locations in the filler layer is large, after removing the sacrificial material to be removed in the middle area, a large amount of sacrificial material to be removed will remain in the edge area. This residual sacrificial material will prevent the edge area from forming effective pattern openings. If the surface morphology of the filler layer is poor, the height difference between the top surfaces of adjacent locations in the same area may be large. After the maskless dry etching process, only some areas in the middle area, which should all form effective pattern openings, may form effective pattern openings, or even none at all. That is, each pattern opening contains a large amount of residual sacrificial material.

[0065] Therefore, when changing the deposition process to form a new filler layer, adaptive quantitative improvements are needed based on the height range and surface morphology of the filler layer formed by the previous deposition process. It should be noted that the presence of sacrificial material remaining within the pattern opening does not necessarily mean the pattern opening is invalid. A small amount of residual sacrificial layer can be effectively removed by briefly extending the etching time of the maskless dry etching process, or it can be removed simultaneously using other processes. These other processes include cleaning processes for the pattern opening, etching processes for the material exposed by the pattern opening, and maskless dry etching processes for adjacent areas.

[0066] In this embodiment, technicians can adjust parameters such as deposition method, deposition rate, and deposition materials according to the height difference and surface morphology of the fill layer under different deposition processes, ultimately finding a deposition process that meets the requirements and applying it to the product wafer corresponding to the test structure to ensure the effective formation of pattern openings and functional components. The surface morphology can be obtained using an atomic force microscope (AFM), but is not limited to this; any other characterization method capable of detecting height differences and surface morphology should be included within the scope of protection claimed in this invention.

[0067] In this embodiment, technicians not only utilize test structures to find the optimal deposition process, but also insert test structures during the wafer fabrication process to monitor the wafer's processing stability. Specifically, compared to macroscopic height differences, microscopic surface morphology is more susceptible to external factors, such as contamination of the reaction chamber. However, if AFM is used to directly probe the surface morphology of the filler layer on the wafer, it may damage the filler layer. Therefore, test structures can be inserted during wafer fabrication to monitor whether the surface morphology of the filler layer meets the requirements and to monitor its stability, thereby ensuring effective wafer fabrication.

[0068] In this embodiment, the auxiliary wafer has a second test structure with multiple second test grooves. The semiconductor process further includes: performing a first deposition process to form a third filling layer, which fills the second test grooves of the second test structure and covers the top surface of the wafer; detecting the height difference between different positions of the third filling layer above the second test structure; if the height difference is less than a preset value, performing the first deposition process on the multiple second process grooves of another product wafer; and removing the third filling layer. Thus, the effectiveness of different test structures for testing different product wafers under the same deposition process can be detected.

[0069] Accordingly, embodiments of the present invention also provide another semiconductor manufacturing process.

[0070] The semiconductor manufacturing process includes: providing an auxiliary wafer and a product wafer as described above, the auxiliary wafer having a first test structure having a plurality of first test grooves arranged in sequence, and the product wafer having a plurality of first process grooves; performing a deposition process to form a first fill layer, the first fill layer filling the first test grooves of the first test structure and covering the top surface of the wafer; detecting the surface morphology of the first fill layer above the first test structure, if the surface morphology meets the preset requirements, it indicates that the product wafer corresponding to the first test structure is valid, then the first deposition process can be performed on the plurality of first process grooves of the product wafer to form the corresponding fill layer, and using the fill layer as a mask etching sacrificial layer to form a preset number of pattern openings within a preset time.

[0071] In this embodiment, an auxiliary wafer with test structures is provided. Since the characteristics of each test structure are the same as those of the corresponding product wafer, the processing technology and the product wafer can be tested through the corresponding test structures in the auxiliary wafer before the product wafer is processed, so as to ensure that the product wafer and the corresponding processing technology meet the preset performance requirements and reduce the wafer scrap rate. At the same time, the auxiliary wafer has at least two test structures. During the testing process, different test structures can be tested simultaneously using the same processing technology, which is beneficial to improving testing efficiency.

[0072] Those skilled in the art will understand that the above embodiments are specific examples of implementing the present invention, and in practical applications, various changes in form and detail can be made without departing from the spirit and scope of the present invention. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A support wafer, characterized by, Comprising: a wafer having at least two test structures, each of the test structures having the same characteristics as a corresponding product wafer, at least one of the characteristics being different for different test structures, the characteristics including test characteristics and non-test characteristics, the test characteristics being different for at least two of the test structures; each of the test structures including a plurality of test trenches arranged in sequence, the test characteristics including a structure density of the plurality of test trenches, the structure density including an opening width and a vertical depth; each of the product wafers including a plurality of process trenches arranged in sequence, the structure density of the plurality of test trenches in the test structure being equal to the structure density of the plurality of process trenches in the corresponding product wafer.

2. The assist wafer of claim 1, wherein The test characteristics further include at least one of an extension direction, an arrangement density, or a sidewall profile of the test trenches.

3. The assist wafer of claim 1, wherein At least one of the test structures further includes at least one auxiliary trench, the auxiliary trench being located at least on one side of the plurality of test trenches in the arrangement direction of the test trenches; the test characteristics further include at least one of a number, a position, or an opening width of the auxiliary trench.

4. The support wafer of claim 3, wherein The test structure includes two auxiliary arrays, the auxiliary arrays being composed of a plurality of auxiliary trenches arranged in sequence, the plurality of test trenches being located between the two auxiliary arrays; the test characteristics further include at least one of a neighboring pitch of the auxiliary trenches or a number of the auxiliary trenches included in each of the auxiliary arrays.

5. The assist wafer of claim 1, wherein The test structure includes a protective layer and a plurality of initial trenches arranged in sequence, the protective layer covering the bottom surface and sidewalls of the initial trenches and covering the top surface of the wafer, the protective layer located in the initial trenches forming the test trenches.

6. The aid wafer according to claim 5, wherein The initial trenches of the product wafer corresponding to the test structure are used to form functional trenches corresponding to functional components, a thickness of the protective layer being equal to an opening width of the functional trenches, the functional components including at least one of an active region, a bit line, or a capacitor contact hole.

7. The assist wafer of claim 5, wherein The wafer includes a silicon substrate and a buffer layer covering a surface of the silicon substrate, a hardness of the buffer layer being greater than a hardness of the silicon substrate, the initial trenches penetrating through the buffer layer and being located in the silicon substrate.

8. A method of assisting formation of a wafer, characterized by, Comprising: providing an initial wafer; processing the initial wafer to form a wafer having at least two test structures, each of the test structures having the same characteristics as a corresponding product wafer, at least one of the characteristics being different for different test structures, the characteristics including test characteristics and non-test characteristics, the test characteristics being different for at least two of the test structures; each of the test structures including a plurality of test trenches arranged in sequence, the test characteristics including a structure density of the plurality of test trenches, the structure density including an opening width and a vertical depth; each of the product wafers including a plurality of process trenches arranged in sequence, the structure density of the plurality of test trenches in the test structure being equal to the structure density of the plurality of process trenches in the corresponding product wafer.

9. The method of claim 8, wherein The process steps of forming the at least two test structures include: providing a silicon substrate; forming a buffer layer covering the surface of the silicon substrate, the buffer layer having a hardness greater than that of the silicon substrate, the buffer layer and the silicon substrate constituting the initial wafer; etching the buffer layer and the silicon substrate to form a first test structure and a second test structure, the first test structure comprising a plurality of first test grooves arranged in sequence, the second test structure comprising a plurality of second test grooves arranged in sequence, the first test grooves and the second test grooves penetrating through the buffer layer and being located in the silicon substrate, the plurality of first test grooves having a different structure density from that of the plurality of second test grooves.

10. The method of claim 9, wherein The process steps of forming the first test grooves and the second test grooves comprise: etching the buffer layer and the silicon substrate to form a first initial groove and a second initial groove; forming a protective layer covering the bottom surface and the sidewall of the first initial groove and covering the bottom surface and the sidewall of the second initial groove, the protective layer located in the first initial groove enclosing the first test groove, and the protective layer located in the second initial groove enclosing the second test groove.

11. A semiconductor process, characterized by, comprising: providing an auxiliary wafer and a product wafer, the auxiliary wafer having a first test structure with a plurality of first test grooves arranged in sequence, the product wafer having a plurality of first process grooves; performing a first deposition process to form a first filling layer, the first filling layer filling the first test grooves of the first test structure and covering the top surface of the wafer; detecting the height range between different positions of the first filling layer above the first test structure, if the height range is less than a preset value, performing the first deposition process on the plurality of first process grooves of the product wafer.

12. The semiconductor process of claim 11, wherein, further comprising: removing the first filling layer; performing a second deposition process to form a second filling layer, the second filling layer filling the first test grooves of the first test structure and covering the top surface of the wafer, the material of the second filling layer being different from that of the first filling layer; detecting the height range between different positions of the second filling layer above the first test structure, if the height range is less than the preset value, performing the second deposition process on the plurality of first process grooves of the product wafer; removing the second filling layer.

13. The semiconductor process of claim 11, wherein, the auxiliary wafer has a second test structure with a plurality of second test grooves; further comprising: performing the first deposition process to form a third filling layer, the third filling layer filling the second test grooves of the second test structure and covering the top surface of the wafer; detecting the height range between different positions of the third filling layer above the second test structure, if the height range is less than the preset value, performing the first deposition process on a plurality of second process grooves of another product wafer.

14. The semiconductor process of claim 11, wherein, The preset value is 30nm-50nm.

15. The semiconductor process of claim 11, wherein, The material of the first filling layer is an SOC material, and the first filling layer is removed by an ashing process.

16. A semiconductor process, comprising: comprising: The application provides an auxiliary wafer and a product wafer, the auxiliary wafer has a first test structure, the first test structure has a plurality of first test grooves arranged in sequence, and the product wafer has a plurality of first process grooves. A first deposition process is performed to form a first filling layer, the first filling layer fills the first test grooves of the first test structure and covers a wafer top surface; The surface topography of the first filling layer above the first test structure is detected, and if the surface topography meets preset requirements, the first deposition process is performed on the plurality of first process grooves of the product wafer.

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