A two-bus communication repeater

Abstract

This invention relates to the field of two-bus communication technology, specifically disclosing a two-bus communication repeater, including a power supply circuit, a front-end communication circuit, a CPU control circuit, an uplink signal transmitting circuit, an uplink signal receiving circuit, a downlink signal transmitting circuit, and a downlink signal receiving circuit. The downlink signal transmitting circuit is electrically connected to the downlink signal receiving circuit, the uplink signal transmitting circuit, and the uplink signal receiving circuit, respectively. The power supply circuit, the front-end communication circuit, the uplink signal transmitting circuit, the uplink signal receiving circuit, and the downlink signal transmitting circuit are all electrically connected to the CPU control circuit. This invention enhances and amplifies the existing two-bus voltage and signal by setting up the uplink signal transmitting circuit, the uplink signal receiving circuit, the downlink signal transmitting circuit, and the downlink signal receiving circuit, thereby extending the two-bus communication distance, increasing the number of slave devices that can be connected, and increasing the stability of the two-bus communication.

Description

Technical Field

[0001] This invention relates to the field of two-bus communication technology, and in particular to a two-bus communication repeater. Background Technology

[0002] Two-wire communication is a technology that combines power and signal lines into one, compared to a four-wire system (two power lines and two communication lines), allowing both signals and power to share a single bus. Two-wire systems save on construction and cabling costs, greatly simplifying on-site installation and subsequent maintenance. They are widely used in fire protection, instrumentation, sensors, and industrial control. Typical two-wire technologies include M-BUS and fire protection bus.

[0003] Two-bus communication allows for flexible cabling, supporting star, tree, and bus topologies. However, due to the variety of wiring methods and the significant radiation interference and long distances in some scenarios, these factors combined can lead to interference signals in the communication signal, causing communication abnormalities. Furthermore, under heavy loads and long distances, line loss occurs in the connection lines, creating a significant voltage difference between the top and bottom ends. When the voltage drops below the minimum voltage of the connected device, it will affect the device's normal operation. Existing repeaters require an external power supply to solve the line loss problem, and the communication voltage is not adjustable, severely limiting their use to certain two-bus communication applications. Further modifications and custom-made repeaters are needed for other applications, resulting in long delivery times.

[0004] Two-wire communication is commonly used in complex environments, such as subways, hospitals, and large commercial complexes. The wiring of two-wire communication is therefore quite complex, differing from the usage of other everyday electronic products, making it difficult to add an external power supply to the repeater. However, line loss is unavoidable, so it is necessary to increase the supply voltage before outputting without adding an external power supply.

[0005] Furthermore, due to differences in industry standards and product usage across various industries, the power supply and communication voltages on the two-wire bus will vary. To enable the use of the same repeater, both the power supply and communication voltages must be adjustable. Additionally, different manufacturers may have different protocols, meaning the repeater cannot have excessive delays when processing communication signals. As the communication distance on the two-wire bus increases and the number of slave devices grows (increasing power), the line loss on the two-wire bus will increase, causing the communication signal to attenuate continuously, potentially leading to unstable communication or even complete unusability. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a two-bus communication repeater in view of the above-mentioned defects of the prior art. By setting up an uplink signal transmitting circuit, an uplink signal receiving circuit, a downlink signal transmitting circuit, and a downlink signal receiving circuit, the existing two-bus voltage and signal are enhanced and amplified respectively, so as to extend the two-bus communication distance, increase the number of slave devices that can be connected, and increase the stability of the two-bus communication.

[0007] To solve the above-mentioned technical problems, the technical solution of the present invention is as follows:

[0008] A two-bus communication repeater includes a power supply circuit, a front-end communication circuit, a CPU control circuit, an uplink signal transmitting circuit, an uplink signal receiving circuit, a downlink signal transmitting circuit, and a downlink signal receiving circuit. The downlink signal transmitting circuit is electrically connected to the downlink signal receiving circuit, the uplink signal transmitting circuit, and the uplink signal receiving circuit, respectively. The power supply circuit, the front-end communication circuit, the uplink signal transmitting circuit, the uplink signal receiving circuit, and the downlink signal transmitting circuit are all electrically connected to the CPU control circuit.

[0009] Preferably, the CPU control circuit includes a main control CPU chip U7, a serial port J3, and peripheral circuits, all of which are connected to the main control CPU chip U7.

[0010] Preferably, the downlink signal transmission circuit includes a transistor VT7, a transistor VS1, a Zener diode TVS1, resistors R10, R22, and R35, and an EBUS output interface J1. The transistor VS1 is connected to the resistors R19, R22, TVS1, and EBUS output interface J1, respectively. The transistor VT7 is connected to the main control CPU chip U7, resistors R19, R22, and R35, respectively.

[0011] Preferably, the front-end communication circuit includes an EBUS input interface J2, a fuse FU1, a Zener diode VD5, a Zener diode ESD1, diodes D1, D2, D3, and D6, resistors R26, R28, R29, R33, R34, and R44, and a transistor Q1. The fuse FU1 is connected to the EBUS input interface J2, the Zener diode VD5, the Zener diode ESD1, and the diode D6. The resistor R44 is connected to the Zener diode VD5, the resistor R26, the diode D1, and the transistor Q1. The resistor R28 is connected to the second pin of the main control CPU chip U7, diodes D1 and D2, and resistor R31. The diode D3 is connected to the ninth pin of the main control CPU chip U7, diode D2, resistor R31, and resistor R29. The transistor Q1 is connected to resistors R29 and R34.

[0012] Preferably, the power supply circuit includes a power management chip U1, a voltage regulator chip U4, an external power interface J5, resistors R3, R6, R7, and R11, capacitors C6, C7, and EC1, an inductor LS1, a Zener diode VD2, resistors R13, C10, and C11, and a diode D7. The diode D7 is connected to the external power interface J5 and the first pin of the power management chip U1. Resistors R3, R6, R7, and R11, capacitors C6, C7, and EC1, inductor LS1, and Zener diode VD2 are all connected to the power management chip U1. Resistors R13, C10, and C11 are all connected to the voltage regulator chip U4.

[0013] Preferably, the downlink signal receiving circuit includes a power management chip U6, an inductor L1, a diode D4, capacitors C12, C13, C14, C15, C16, C21, and C22, resistors R15, R16, R17, and R18, a transistor Q2, a diode D3, and an adjustable resistor R14. The inductor L1, diode D4, capacitors C12, C13, C14, C15, C16, C21, C22, resistors R15, R16, R17, and R18, transistor Q2, diode D3, and adjustable resistor R14 are all connected to the power management chip U6, and diode D3 is connected to the transistor VS1.

[0014] Preferably, the uplink signal transmission circuit includes a power management chip U2, resistors R1, R8, and R9, capacitors C1, C2, C4, C5, and C8, an adjustable resistor R2, and a transistor VT1. Resistors R1, R8, C1, C2, C4, C5, C8, the adjustable resistor R2, and the transistor VT1 are all connected to the power management chip U2. Resistor R1 is connected to the transistor VS1, and resistor R9 is connected to both the transistor VT1 and the main control CPU chip U7.

[0015] Preferably, the uplink signal receiving circuit includes an operational amplifier U3B, capacitors C3 and C9, resistors R10 and R12, and a Zener diode VD4. The operational amplifier U3B is connected to the main control CPU chip U7, capacitors C3 and C9, resistors R10 and R12, and the Zener diode VD4 is connected to resistor R10 and transistor VS1.

[0016] By adopting the above technical solution, the present invention provides a two-bus communication repeater with the following beneficial effects: The downlink signal transmitting circuit in the two-bus communication repeater is electrically connected to the downlink signal receiving circuit, the uplink signal transmitting circuit, and the uplink signal receiving circuit, respectively. The power supply circuit, the front-end communication circuit, the uplink signal transmitting circuit, the uplink signal receiving circuit, and the downlink signal transmitting circuit are all electrically connected to the CPU control circuit. When downlink data is on the bus, the front-end communication circuit receives a voltage signal and sends the communication signal to the CPU control circuit. The CPU control circuit controls the downlink signal transmitting circuit to transmit the communication signal transparently, making the input and output of the communication signal on the bus consistent. When uplink data is on the bus, the front-end communication circuit... After receiving the current signal from the master device, the system synchronously sends a current signal to the slave device through the uplink signal transmission circuit. After receiving the communication signal fed back from the slave device, it sends it to the CPU control circuit. The CPU control circuit controls the front-end communication circuit to feed back the communication signal from the slave device to the master device. The power supply circuit boosts the voltage for powering the two-wire bus, and the CPU control circuit filters out interference signals from the communication signal, shaping the distorted communication wave back to the standard waveform. It can absorb external interference such as electromagnetic induction from the external environment, thereby protecting the stability of the two-wire bus communication. Furthermore, it can enhance and amplify the existing two-wire bus voltage and signal, extending the two-wire bus communication distance, increasing the number of slave devices that can be connected, and increasing the stability of the two-wire bus communication. Attached Figure Description

[0017] Figure 1 This is a structural block diagram of the present invention;

[0018] Figure 2 This is a circuit diagram of the CPU control circuit in this invention;

[0019] Figure 3 This is a circuit diagram of the front-end communication circuit in this invention;

[0020] Figure 4 This is a circuit diagram of the power supply circuit in this invention;

[0021] Figure 5 This is a circuit diagram of the uplink signal transmitting circuit, uplink signal receiving circuit, downlink signal transmitting circuit, and downlink signal receiving circuit in this invention.

[0022] Figure 6 This is a schematic diagram illustrating an application embodiment of the present invention;

[0023] Figure 7 This is a schematic diagram of the communication signals of the present invention;

[0024] Figure 8 This is a flowchart of the process of the present invention;

[0025] In the diagram, 1-power supply circuit, 2-front-end communication circuit, 3-CPU control circuit, 4-uplink signal transmitting circuit, 5-uplink signal receiving circuit, 6-downlink signal transmitting circuit, and 7-downlink signal receiving circuit. Detailed Implementation

[0026] The specific embodiments of the present invention will be further described below with reference to the accompanying drawings. It should be noted that these descriptions are for the purpose of aiding understanding the present invention, but do not constitute a limitation thereof. Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0027] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0028] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0029] like Figure 1 As shown in the structural block diagram of this invention, the two-bus communication repeater includes a power supply circuit 1, a front-end communication circuit 2, a CPU control circuit 3, an uplink signal transmitting circuit 4, an uplink signal receiving circuit 5, a downlink signal transmitting circuit 6, and a downlink signal receiving circuit 7. The downlink signal transmitting circuit 6 is electrically connected to the downlink signal receiving circuit 7, the uplink signal transmitting circuit 4, and the uplink signal receiving circuit 5, respectively. The power supply circuit 1, the front-end communication circuit 2, the uplink signal transmitting circuit 4, the uplink signal receiving circuit 5, and the downlink signal transmitting circuit 6 are all electrically connected to the CPU control circuit 3. It can be understood that in practical applications, the power supply circuit 1, the front-end communication circuit 2, the CPU control circuit 3, the uplink signal transmitting circuit 4, the uplink signal receiving circuit 5, the downlink signal transmitting circuit 6, and the downlink signal receiving circuit 7 can be integrated onto a single PCB board and then connected to a two-bus interface for use.

[0030] Specifically, Figure 2 This is a circuit diagram of the CPU control circuit in this invention, combined with... Figures 1-5It can be seen that the CPU control circuit 3 includes a main control CPU chip U7, a serial port J3, and peripheral circuits, all of which are connected to the main control CPU chip U7; the downlink signal transmission circuit 6 includes a transistor VT7, a transistor VS1, a Zener diode TVS1, resistors R10, R22, and R35, and an EBUS output interface J1. The transistor VS1 is connected to resistors R19, R22, TVS1, and EBUS output interface J1, and the transistor VT7 is connected to the main control CPU chip U7, resistors R19, R22, and R35; the front-end communication circuit 2 includes an EBUS input interface J2, a fuse FU1, a Zener diode VD5, and a Zener diode... ESD1, diodes D1, D2, D3, and D6, resistors R26, R28, R29, R33, R34, and R44, and transistor Q1. Fuse FU1 is connected to the EBUS input interface J2, Zener diode VD5, Zener diode ESD1, and diode D6. Resistor R44 is connected to Zener diode VD5, resistor R26, diode D1, and transistor Q1. Resistor R28 is connected to the second pin of the main control CPU chip U7, diodes D1 and D2, and resistor R31. Diode D3 is connected to the ninth pin of the main control CPU chip U7, diode D2, resistor R31, and resistor R29. Transistor Q1... The resistors R29 and R34 are connected to each other respectively. The power supply circuit 1 includes a power management chip U1, a voltage regulator chip U4, an external power interface J5, resistors R3, R6, R7, and R11, capacitors C6, C7, and EC1, an inductor LS1, a Zener diode VD2, resistors R13, C10, and C11, and a diode D7. Diode D7 is connected to both the external power interface J5 and the first pin of the power management chip U1. Resistors R3, R6, R7, and R11, capacitors C6, C7, and EC1, inductor LS1, and Zener diode VD2 are all connected to the power management chip U1. Resistors R13, C10, and C11 are all connected to the voltage regulator chip U4. 4. Connections: The downlink signal receiving circuit 7 includes a power management chip U6, an inductor L1, a diode D4, capacitors C12, C13, C14, C15, C16, C21, C22, resistors R15, R16, R17, R18, a transistor Q2, a diode D3, and an adjustable resistor R14. The inductor L1, diode D4, capacitors C12, C13, C14, C15, C16, C21, C22, resistors R15, R16, R17, R18, transistor Q2, diode D3, and adjustable resistor R14 are all connected to the power management chip U6. The diode D3 is connected to the transistor VS1.The uplink signal transmitting circuit 4 includes a power management chip U2, resistors R1, R8, and R9, capacitors C1, C2, C4, C5, and C8, an adjustable resistor R2, and a transistor VT1. Resistors R1, R8, C1, C2, C4, C5, C8, the adjustable resistor R2, and transistor VT1 are all connected to the power management chip U2. Resistor R1 is connected to transistor VS1. Resistor R9 is connected to transistor VT1 and the main control CPU chip U7. The uplink signal receiving circuit 5 includes an operational amplifier U3B, capacitors C3 and C9, resistors R10 and R12, and a Zener diode VD4. Operational amplifier U3B is connected to the main control CPU chip U7, capacitors C3 and C9, resistors R10 and R12, and the Zener diode VD4 is connected to resistor R10 and transistor VS1. Understandably, this power supply circuit is used to connect to an external power source and provide power to the aforementioned circuits, including 12V, 3.3V, and 36V power supplies; the front-end communication circuit is used for sending and receiving communication signals; the uplink signal transmitting circuit is used to send uplink signals, the uplink signal receiving line 5 is used to receive uplink signals, the downlink signal transmitting circuit 6 is used to send downlink signals, and the downlink signal receiving line 7 is used to receive downlink signals; the CPU control circuit 3, as the main controller of the entire two-bus communication circuit, is responsible for signal processing and outputting control signals to control the operating status of the aforementioned circuits.

[0031] Understandably, the power management chip U1 can be an MC34063 chip, the power management chip U2 can be a 7805 chip, the voltage regulator chip U4 can be an RS3005 chip, and the power management chip U6 can be an FB5138 chip. The Vin pin is the power input, the FB pin is the output voltage signal feedback, the SCP pin is for protection / soft start, the SW pin is for switch control, the COMP pin is for signal compensation, the OSC pin is for oscillation, the OUT pin is for signal output, and the VSS / GND pins are both grounded. The main control CPU chip U7 can be an STM32 or 80C51 microcontroller chip, etc. The seventh pin is for communication status detection, and the tenth pin is for EBUS current detection.

[0032] It is understood that only the main circuit components and their connections are listed above. The remaining circuit components and their specific connections are shown in the attached figures, and will not be described in detail here.

[0033] Understandable. Figure 6 This is a schematic diagram illustrating an application embodiment of the present invention, in conjunction with... Figures 6-8This two-bus communication repeater acts as an intermediate device, connected to the two-bus network. Because it can autonomously send and receive data, it is a terminal relative to network segment one and a host relative to network segment two. Communication signals are interspersed between power supply interruptions (see attached diagram). Figure 7 Downlink data uses voltage signals. The master device sends communication signals to the slave device by changing the voltage value on the bus. Uplink data uses current signals. After the master device sends a current signal, it feeds back information by judging the current consumption of the slave device. In the figure, "CPU" corresponds to the CPU control circuit, "repeater" corresponds to the two-bus communication repeater, and "master" corresponds to the master device.

[0034] Working principle: First, the power supply section is powered by the power supply circuit 1, which boosts the input voltage from 5-40V to 43V (adjustable, maximum 60V). The voltage difference generated by the transmission of electrical energy on the two buses through the transmission line will be boosted back up due to the voltage difference reduced by line loss.

[0035] When downlink data is on the bus, the front-end communication circuit 2 receives the voltage signal and sends the communication signal to the CPU control circuit 3. The CPU control circuit 3 controls the downlink signal transmission circuit 6 to transmit the communication signal through, so that the input and output of the communication signal on the bus are consistent.

[0036] When there is uplink data on the bus, the front-end communication circuit 2 receives the current signal sent by the master device and synchronously sends the current signal to the slave device through the uplink signal sending circuit 4. After receiving the communication signal fed back by the slave device, it sends it to the CPU control circuit 3. The CPU control circuit 3 controls the front-end communication circuit to feed back the communication signal fed back by the slave device to the master device.

[0037] In summary, this two-bus communication repeater boosts the power supply on the two buses, filters out interference signals from the communication signals, and can reshape distorted communication waves back to standard waveforms.

[0038] Understandably, this invention is reasonably designed and uniquely constructed, and can enhance and amplify the existing two-bus voltage and signal, thereby extending the two-bus communication distance and increasing the number of slave devices that can be connected.

[0039] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to the described embodiments. For those skilled in the art, various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention, and these variations still fall within the protection scope of the present invention.

Claims

1. A two-bus communication repeater, characterized in that: It includes a power supply circuit, a front-end communication circuit, a CPU control circuit, an uplink signal transmitting circuit, an uplink signal receiving circuit, a downlink signal transmitting circuit, and a downlink signal receiving circuit. The downlink signal transmitting circuit is electrically connected to the downlink signal receiving circuit, the uplink signal transmitting circuit, and the uplink signal receiving circuit, respectively. The power supply circuit, the front-end communication circuit, the uplink signal transmitting circuit, the uplink signal receiving circuit, and the downlink signal transmitting circuit are all electrically connected to the CPU control circuit. The uplink signal transmitting circuit, uplink signal receiving circuit, downlink signal transmitting circuit, and downlink signal receiving circuit respectively enhance and amplify the existing two-bus voltage and signal. When downlink data is on the bus, the front-end communication circuit receives the voltage signal and sends the communication signal to the CPU control circuit. The CPU control circuit controls the downlink signal transmitting circuit to pass through the communication signal, so that the input and output of the communication signal on the bus are consistent. When uplink data is on the bus, after receiving the current signal sent by the master device, the front-end communication circuit synchronously sends the current signal to the slave device through the uplink signal transmitting circuit. After receiving the communication signal fed back by the slave device, it sends it to the CPU control circuit. The CPU control circuit controls the front-end communication circuit to feed back the communication signal fed back by the slave device to the master device. The power supply circuit plays a role in boosting the power supply on the two-bus, and the CPU control circuit plays a role in filtering out interference signals and shaping the distorted communication wave back to the standard waveform.

2. The dual-bus communication repeater according to claim 1, characterized in that: The CPU control circuit includes a main control CPU chip U7, a serial port J3, and peripheral circuits, all of which are connected to the main control CPU chip U7.

3. The dual-bus communication repeater according to claim 2, characterized in that: The downlink signal transmission circuit includes a transistor VT7, a transistor VS1, a Zener diode TVS1, resistors R10, R22, and R35, and an EBUS output interface J1. The transistor VS1 is connected to the resistors R19, R22, TVS1, and EBUS output interface J1, respectively. The transistor VT7 is connected to the main control CPU chip U7, resistors R19, R22, and R35, respectively.

4. The two-bus communication repeater according to claim 2, characterized in that: The front-end communication circuit includes an EBUS input interface J2, a fuse FU1, a Zener diode VD5, a Zener diode ESD1, diodes D1, D2, D3, and D6, resistors R26, R28, R29, R33, R34, and R44, and a transistor Q1. The fuse FU1 is connected to the EBUS input interface J2, Zener diode VD5, Zener diode ESD1, and diode D6. Resistor R44 is connected to Zener diode VD5, resistor R26, diode D1, and transistor Q1. Resistor R28 is connected to the second pin of the main control CPU chip U7, diodes D1 and D2, and resistor R31. Diode D3 is connected to the ninth pin of the main control CPU chip U7, diode D2, resistor R31, and resistor R29. Transistor Q1 is connected to resistor R29. And connect with resistor R34.

5. The dual-bus communication repeater according to claim 2, characterized in that: The power supply circuit includes a power management chip U1, a voltage regulator chip U4, an external power interface J5, resistors R3, R6, R7, and R11, capacitors C6, C7, and EC1, an inductor LS1, a Zener diode VD2, resistors R13, C10, and C11, and a diode D7. The diode D7 is connected to both the external power interface J5 and the first pin of the power management chip U1. Resistors R3, R6, R7, and R11, capacitors C6, C7, and EC1, inductor LS1, and Zener diode VD2 are all connected to the power management chip U1. Resistors R13, C10, and C11 are all connected to the voltage regulator chip U4.

6. The two-bus communication repeater according to claim 3, characterized in that: The downlink signal receiving circuit includes a power management chip U6, an inductor L1, a diode D4, capacitors C12, C13, C14, C15, and C16. Capacitors C21 and C22, resistors R15, R16, R17, and R18, transistor Q2, diode D3, and adjustable resistor R14, along with inductor L1, diode D4, capacitors C12, C13, C14, C15, C16, C21, C22, R15, R16, R17, R18, transistor Q2, diode D3, and adjustable resistor R14, are all connected to the power management chip U6. Diode D3 is connected to transistor VS1.

7. The two-bus communication repeater according to claim 3, characterized in that: The uplink signal transmission circuit includes a power management chip U2, resistors R1, R8, and R9, capacitors C1, C2, C4, C5, and C8, an adjustable resistor R2, and a transistor VT1. Resistors R1, R8, C1, C2, C4, C5, C8, the adjustable resistor R2, and transistor VT1 are all connected to the power management chip U2. Resistor R1 is connected to transistor VS1, and resistor R9 is connected to both transistor VT1 and the main control CPU chip U7.

8. The two-bus communication repeater according to claim 3, characterized in that: The uplink signal receiving circuit includes an operational amplifier U3B, capacitors C3 and C9, resistors R10 and R12, and a Zener diode VD4. The operational amplifier U3B is connected to the main control CPU chip U7, capacitors C3 and C9, resistors R10 and R12, and the Zener diode VD4 is connected to resistor R10 and transistor VS1.

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