Component carrier and method for manufacturing component carrier

Abstract

A method for manufacturing a component carrier (100) is provided, the method comprising: providing a stack comprising at least one electrically conductive layer structure (102) and at least one electrically insulating layer structure (104); forming a patterned thin film mask (110) on the at least one electrically insulating layer structure (104); and forming a hole (120) in the at least one electrically insulating layer structure (104) by means of a recess (112) through a patterned thin film mask (110) by plasma etching. Additionally, a component carrier (100) is provided.

Description

Technical Field

[0001] This invention relates to a method for manufacturing component carriers and to component carriers. Background Technology

[0002] With the increasing functionality of products that incorporate one or more components, the growing miniaturization of these components, and the increasing number of components to be mounted on component carriers, such as printed circuit boards (PCBs), increasingly powerful arrays of components or packages with multiple contacts or connections are being used. These arrays or packages have increasingly smaller spacing between these contacts. The PCB industry, in particular, faces the task of adjusting the size of already manufactured PCBs to meet miniaturization requirements. This may especially involve creating small vias in the dielectric layers of the PCB. Laser drilling is disadvantageous for this purpose because it typically results in tapered holes with a truncated cone shape, and the bottom dimension of laser-drilled holes is too small for tiny vias, posing a high risk to interconnect reliability. Conversely, plasma etching is very popular in PCB manufacturing for creating small vias.

[0003] Conventionally, during plasma etching used to form vias, copper foil or a thick dry film is typically used as a protective layer to create a conformal mask. However, due to the large thickness of the copper foil and the fragility of the dry film, as well as the potential for contamination when using the dry film to create a conformal mask, it is difficult to fabricate small conformal masks. Summary of the Invention

[0004] It may be necessary to manufacture a component carrier that allows for the creation of small vias, such as those with a diameter of less than 12 μm, with high reliability and no contamination issues.

[0005] According to an exemplary embodiment of the present invention, a method for manufacturing a component carrier is provided, wherein the method includes: providing a stack comprising at least one electrically conductive layer structure and at least one electrically insulating layer structure; forming a patterned thin film mask on the at least one electrically insulating layer structure; and forming a hole in the at least one electrically insulating layer structure by means of a recess in the patterned thin film mask through plasma etching.

[0006] According to another exemplary embodiment of the present invention, a component carrier is provided, the component carrier comprising: a stack comprising at least one electrically conductive layer structure and at least one electrically insulating layer structure; and a hole located in the at least one electrically insulating layer structure, the hole being defined by generally vertical sidewalls and having a diameter (particularly an average diameter) in the range of 1 μm to 12 μm.

[0007] In the context of this application, the term "component carrier" may specifically refer to any support structure capable of accommodating one or more components on and / or within the component carrier to provide mechanical support and / or electrical connection. In other words, a component carrier can be configured as a mechanical and / or electronic carrier for components. Specifically, a component carrier can be one of a printed circuit board, an organic interposer, and an IC (integrated circuit) substrate. A component carrier can also be a hybrid board combining different types of component carriers of the types mentioned above.

[0008] In the context of this application, the term "patterned thin film mask" may specifically refer to a patterned or structured (more specifically, provided with recesses) thin film (particularly having a thickness of less than 3 μm, for example, in the range of 50 nm to 2 μm) that can be used as a mask (or template) for forming holes in an electrical insulating or dielectric layer on the underside by means of, in particular, plasma etching.

[0009] In the context of this application, the term "plasma etching" may specifically refer to a dry etching technique that combines physical etching and chemical reactions and may include reactive ion etching (RIE), which may be particularly advantageous in terms of etching anisotropy. In particular, according to exemplary embodiments of the invention, small holes defined by generally vertical sidewalls can be formed in an electrically insulating (or dielectric) layer structure by plasma etching.

[0010] In the context of this application, the term "generally vertical sidewall" may specifically mean: (e.g., the deviation of the sidewall of a hole) from the vertical direction is no more than 10%, preferably no more than 5%, and / or the difference between the bottom diameter and the top diameter of the hole is less than 15%, preferably less than 5%. A hole defined by a generally vertical sidewall may specifically represent a hole having a generally cylindrical shape.

[0011] According to an exemplary embodiment of the present invention, a method for manufacturing a component carrier is provided, wherein a thin film, such as an electrodeposited or laminated copper thin film, is used as a protective layer to create a conformal mask for forming vias. Due to the small thickness of the conformal mask, this thin film can be patterned (more specifically, provided with recesses) by means of, for example, a UV laser or an optimized CO2 laser (rather than by means of, for example, photolithography processes), such that recesses with small diameters are formed in the thin film in a very precise and reliable manner. The resulting patterned thin film mask allows for the formation of small vias with high reliability and without contamination issues by plasma etching. Therefore, component carriers comprising small vias (e.g., having an average diameter of 12 μm or less) with generally vertical sidewalls can be obtained.

[0012] Detailed description of exemplary embodiments

[0013] The following description will illustrate a method for manufacturing a component carrier and other exemplary embodiments of the component carrier. However, the invention is not limited to the following detailed description of the exemplary embodiments, but is for illustrative purposes only.

[0014] It should be noted that features described in conjunction with one exemplary implementation or aspect can be combined with any other exemplary implementation or aspect. In particular, unless otherwise specifically stated, features described in conjunction with any exemplary implementation of the method of manufacturing a component carrier can be combined with any other exemplary implementation of the method of manufacturing a component carrier and exemplary implementations of the component carrier, and vice versa.

[0015] Unless otherwise specified, when referring to a singular term, the use of an indefinite or definite article, such as “a,” “a,” or “the,” also includes the plural form of the term, and vice versa. As used herein, the term “one” or the number “1” generally refers to “only one” or “exact one.”

[0016] It should be noted that the term "comprising" does not exclude other elements or steps, and as used herein, the term "comprising" includes not only the meaning of "including," "containing," or "comprises," but may also include "consistently composed of" and "comprises of."

[0017] Unless otherwise specified, as used herein, the expressions “at least partially,” “at least partially,” “at least a portion of,” or “at least a part of” may refer to at least 1%, particularly at least 5%, particularly at least 10%, particularly at least 15%, particularly at least 20%, particularly at least 25%, particularly at least 30%, particularly at least 35%, particularly at least 40%, particularly at least 45%, particularly at least 50%, particularly at least 55%, particularly at least 60%, particularly at least 65%, particularly at least 70%, particularly at least 75%, particularly at least 80%, particularly at least 85%, particularly at least 90%, particularly at least 95%, particularly at least 98%, and may also include 100%.

[0018] In this embodiment, the patterned thin-film mask is metallic. Specifically, the patterned thin-film mask may include or be composed of copper. However, other suitable metals or alloys may also be used for the patterned thin-film mask.

[0019] In this implementation, the patterned thin film mask is formed by electroless deposition. By taking this approach, very thin films (e.g., as low as 50 μm in thickness) can be generated, which can then be patterned using, in particular, a UV laser or an optimized CO2 laser.

[0020] In implementation, electroless deposition includes physical deposition processes, particularly sputtering or physical vapor deposition (PVD).

[0021] In alternative embodiments, electroless deposition includes chemical deposition processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or electroless plating. For example, electroless deposition may include forming a seed layer (e.g., comprising or composed of palladium) and then chemically growing a metal (particularly copper) on the seed layer.

[0022] In implementation, the patterned thin film mask has a thickness ranging from 20 nm to 700 nm, particularly from 50 nm to 500 nm, such as from 100 nm to 300 nm. Such very thin films, which are particularly suitable for patterning by means of, in particular, UV lasers or optimized CO2 lasers, can be achieved specifically by electrodeposition.

[0023] In an alternative embodiment of electrodeposition, a patterned thin-film mask is formed by lamination, and the patterned thin-film mask has a thickness, for example, ranging from 1 μm to 2 μm. By taking this approach, an electrically insulating or dielectric layer (e.g., an Ajinomoto Build-up Film (ABF) layer or a photoimageable dielectric (PID) layer) and a thin film of metal (which may be a patterned film or a continuous film to be patterned subsequently) can be applied simultaneously or at least in one process step onto the core or stack.

[0024] In an embodiment, the method (more specifically, the step of forming a patterned thin film mask on the at least one electrically insulating layer structure) includes: forming a continuous thin film on the electrically insulating layer structure (preferably by electroless deposition or lamination), and patterning the thin film by laser processing or by photolithography (using a dry film added to a conformal mask). Thus, recesses are formed in the thin film, which can then be used to form holes in the underlying (below) electrically insulating or dielectric layer by means of plasma etching.

[0025] In this embodiment, laser processing includes patterning the thin film using at least one of a UV laser, a CO2 laser (with optimized wavelength, particularly short wavelength and / or large amplitude, such as optimized power and / or short pulse width, for example, with a power of 0.11 mJ and a pulse width of 16 μs), or an excimer laser. Among the aforementioned lasers, a UV laser is preferred due to its high performance. Furthermore, since the thin film is very thin, it can be patterned using a UV laser even without first blackening the surface of the film (e.g., by roughening the surface to produce a "black oxide"). Therefore, the thin film can be patterned in a very reliable and efficient manner (in particular, small recesses can be formed in the thin film).

[0026] In an embodiment, the electrically insulating (or dielectric) layer structure (a continuous thin film (if present) and a patterned thin film mask are formed on the electrically insulating (or dielectric) layer structure, and a hole is formed in the electrically insulating (or dielectric) layer structure by a recess in the patterned thin film mask through plasma etching) has a thickness in the range of 5 μm to 100 μm, particularly in the range of 10 μm to 70 μm, particularly in the range of 20 μm to 60 μm, such as in the range of 30 μm to 50 μm.

[0027] In one implementation, the method further includes removing the patterned thin-film mask, for example by rapid etching, after the aperture has been formed.

[0028] In some embodiments, the method further includes filling the holes. Specifically, the method may include at least partially filling the holes with an electrically conductive material (e.g., copper) by means of electrodeposition and / or galvanically plating. This allows the creation of small vias (or small through-holes) penetrating the electrically insulating (or dielectric) layer structure. In particular, component carriers comprising small vias with generally vertical sidewalls can be obtained.

[0029] In this embodiment, the deviation of the sidewall from the vertical direction does not exceed 10%, and preferably does not exceed 5%.

[0030] In an embodiment, the difference between the bottom diameter of the hole (i.e., the diameter adjacent to or near the bottom of the hole) and the top diameter of the hole (i.e., the diameter adjacent to or near the top of the hole or the opening) is less than 15%, particularly less than 10%, or even less than 5%. As an example, if the bottom diameter is 10 μm, the top diameter is preferably in the range of 8.5 μm to 11.5 μm, and vice versa.

[0031] In this embodiment, the overhang of the hole is less than 2 μm. A small overhang can be formed (or retained) specifically at or near the top of the hole. In particular, a (concave) notch or recess below the top surface can be formed during a plasma etching step. However, it is advantageous if the overhang is as small as possible, preferably less than 1 μm or even less than 0.1 μm.

[0032] In an embodiment, the pore has a diameter (particularly the average diameter) in the range of 3 μm to 10 μm, for example, in the range of 4 μm to 8 μm.

[0033] In an embodiment, the at least one electrical insulating layer structure includes at least one of the following: resin, epoxy-based dielectric, prepreg, and photosensitive dielectric.

[0034] In this embodiment, the at least one electrical insulating layer structure lacks a reinforcing structure or agent, such as a glass sphere or glass fiber. This approach facilitates the etching of the electrical insulating layer structure.

[0035] In one embodiment, the bottom of the hole is closed (bounded) by the at least one electrically conductive layer structure. When the hole is filled, particularly with an electrically conductive material, an electrical connection to the at least one electrically conductive layer structure can be obtained via a small via (or a small through-hole) thus formed through the electrically insulating (or dielectric) layer structure.

[0036] In this embodiment, the holes are at least partially filled with an electrically conductive material, such as copper. Therefore, small vias (or small through-connections) can be obtained that penetrate the electrically insulating (or dielectric) layer structure. In particular, component carriers comprising small vias with generally vertical sidewalls can be obtained.

[0037] In embodiments, the component carrier comprises a stack of at least one electrically insulating layer structure and at least one electrically conductive layer structure. For example, the component carrier may be a stack of the aforementioned electrically insulating and electrically conductive layer structures, particularly a stack of electrically insulating and electrically conductive layer structures formed by applying mechanical pressure and / or heat. The aforementioned stack can provide a plate-like component carrier capable of providing a large mounting surface for other components while remaining very thin and compact. The term "layer structure" may specifically refer to a continuous layer, a patterned layer, or multiple discontinuous island sections in a common plane.

[0038] In this implementation, the component carrier is formed as a plate. This contributes to a compact design, whereby the component carrier still provides a large base for the mounting components on it. Furthermore, in particular, a bare die, as an example of an embedded electronic component, can be easily embedded into a thin plate, such as a printed circuit board, due to its small thickness.

[0039] In one embodiment, the component carrier is constructed as one of a printed circuit board, a substrate (especially an IC substrate), and an interposer.

[0040] In the context of this application, the term "printed circuit board" (PCB) can specifically refer to a sheet-like component carrier formed by laminating multiple electrically conductive layer structures with multiple electrically insulating layer structures, for example by applying pressure and / or by supplying heat. As preferred materials for PCB technology, the electrically conductive layer structures are made of copper, while the electrically insulating layer structures may include resin and / or glass fiber, so-called prepreg, or FR4 material. The individual electrically conductive layer structures can be connected to each other in a desired manner by forming through-holes through the laminate, for example by laser drilling or mechanical drilling, and by filling these through-holes with an electrically conductive material (particularly copper) to form vias serving as through-hole connections. In addition to one or more components that can be embedded in the PCB, the PCB is generally configured to accommodate one or more components on one surface or opposite surfaces of the sheet-like PCB. The one or more components can be soldered to the respective main surfaces. The dielectric portion of the PCB can be made of resin with reinforcing fibers (e.g., glass fiber).

[0041] In the context of this application, the term "substrate" can specifically refer to a small component carrier. A substrate can be a relatively small component carrier relative to a PCB, on which one or more components can be mounted and which can serve as a connection medium between one or more chips and another PCB. For example, a substrate can have approximately the same size as the components (particularly electronic components) to be mounted on it (e.g., in the case of chip-scale packages (CSP)). More specifically, a substrate can be understood as a component carrier that serves as a carrier for electrical connections or electrical networks and as a connector with a relatively high density of lateral and / or vertical arrangements, comparable to a printed circuit board (PCB). Lateral connectors are, for example, conductive channels, while vertical connectors can be, for example, drilled holes. These lateral and / or vertical connectors are arranged within the substrate and can be used to provide electrical, thermal, and / or mechanical connections between mounted or unmounted components (e.g., bare wafers), particularly IC chips, and printed circuit boards or intermediate printed circuit boards. Therefore, the term "substrate" also includes "IC substrate." The dielectric portion of the substrate can be made of resin with reinforcing particles (e.g., reinforcing spheres, especially glass spheres).

[0042] The substrate or interlayer may include or consist of at least one of the following: glass; silicon (Si); photosensitive or dry-etchable organic material, such as epoxy-based laminated material (e.g., epoxy-based laminated film); or polymer compound, such as polyimide, polybenzoxazole, or benzocyclobutene-functionalized polymer.

[0043] In an embodiment, the at least one electrically insulating layer structure comprises at least one of the following: resin (e.g., reinforced or unreinforced resin, such as epoxy resin or bismaleimide-triazine resin), cyanate ester resin, polyphenylene derivative, glass (especially glass fiber, multilayer glass, glassy material), prepreg (e.g., FR-4 or FR-5), polyimide, polyamide, liquid crystal polymer (LCP), epoxy-based laminated film, polytetrafluoroethylene (PTFE, Teflon). Materials can include ceramics and metal oxides. Reinforcing structures, such as meshes, fibers, or spheres, made of glass (multilayer glass) can also be used. While prepregs, particularly FR4, are generally preferred for rigid PCBs, other materials, particularly epoxy-based laminates or photosensitive dielectrics, can also be used. For high-frequency applications, high-frequency materials, such as polytetrafluoroethylene (PTFE), liquid crystal polymers and / or cyanate ester resins, low-temperature co-fired ceramics (LTCC), or other low, very low, or ultra-low DK materials, can be implemented as electrically insulating layers in component carriers.

[0044] In an embodiment, the at least one electrically conductive layer structure comprises at least one of the following: copper, aluminum, nickel, silver, gold, palladium, and tungsten. Although copper is generally preferred, other materials or coating variations thereof, particularly those coated with superconducting materials such as graphene, are also possible.

[0045] At least one component may be selected from: non-electrically conductive inlays, electrically conductive inlays (e.g., metallic inlays, preferably including copper or aluminum), heat transfer units (e.g., heat pipes), light guiding elements (e.g., optical waveguides or optical conductor connectors), optical elements (e.g., lenses), electronic components, or combinations thereof. For example, the component may be an active electronic component, a passive electronic component, an electronic chip, a storage device (e.g., DRAM or other data memory), a filter, an integrated circuit, a signal processing component, a power management component, an optoelectronic interface element, a light-emitting diode, an optocoupler, a voltage converter (e.g., a DC / DC converter or an AC / DC converter), a cryptographic component, a transmitter and / or receiver, an electromechanical transducer, a sensor, an actuator, a microelectromechanical system (MEMS), a microprocessor, a capacitor, a resistor, an inductor, a battery, a switch, a camera, an antenna, a logic chip, and an energy harvesting unit. However, other components may also be embedded in a component carrier. For example, a magnetic element may be used as a component. Such magnetic elements can be permanent magnetic elements (e.g., ferromagnetic, antiferromagnetic, multiferroic, or ferrimagnetic elements, such as ferrite cores) or paramagnetic elements. However, the component can also be, for example, a substrate, interlayer, or other component carrier in a plate-in-plate configuration. The component can be surface-mounted on the component carrier and / or embedded within the component carrier. Furthermore, other components, particularly those that generate and emit electromagnetic radiation and / or are sensitive to electromagnetic radiation propagating from the environment, can also be used as components.

[0046] In one embodiment, the component carrier is a laminated component carrier. In this embodiment, the component carrier is a multilayer composite structure that is stacked and connected together by applying pressure and / or heat.

[0047] After the internal layer structure of the component carrier is fabricated, one or more additional electrically insulating and / or electrically conductive layer structures (particularly by lamination) can be used to symmetrically or asymmetrically cover one main surface or two opposite main surfaces of the fabricated layer structure. In other words, stacking can continue until the desired number of layers is achieved.

[0048] After the stacked structure of the electrical insulation layer and the electrical conductivity layer is formed, the surface of the obtained layer structure or component carrier can be treated.

[0049] Specifically, in terms of surface treatment, an electrically insulating solder resist can be applied to one or both opposing main surfaces of the laminate or component carrier. For example, a solder resist can be formed over the entire main surface and then the solder resist layer can be patterned to expose one or more electrically conductive surface portions, which will be used to electrically couple the component carrier to electronic peripherals. The solder resist-covered surface portions of the component carrier, particularly those containing copper, can be effectively protected from oxidation or corrosion.

[0050] In terms of surface treatment, surface trimming can be selectively applied to the exposed electrically conductive surface portions of a component carrier. This surface trimming can be an electrically conductive covering material on the exposed electrically conductive layer structure (e.g., pads, conductive traces, etc., particularly including or composed of copper) on the surface of the component carrier. If this exposed electrically conductive layer structure is not protected, the exposed electrically conductive component carrier material (particularly copper) will oxidize, resulting in lower reliability of the component carrier. The surface trimming can then be formed, for example, as a joint between a surface-mount component and the component carrier. The surface trimming functions to protect the exposed electrically conductive layer structure (particularly copper circuitry), and the surface trimming can be joined to one or more components, for example, by soldering. Examples of suitable materials for surface trimming are organic solderable corrosion inhibitors (OSP), electroless nickel immersion gold (ENIG), gold (particularly hard gold), electroless tin, nickel-gold, nickel-palladium, ENIPIG (electroless nickel-palladium immersion gold), etc.

[0051] The above-defined aspects and other aspects of the present invention will become apparent from the exemplary embodiments described below and will be illustrated with reference to these exemplary embodiments. Attached Figure Description

[0052] Figure 1 An exemplary embodiment of a method for manufacturing a component carrier according to the present invention is shown.

[0053] Figure 2 An enlarged view of a hole in a component carrier according to an exemplary embodiment of the present invention is shown.

[0054] Figure 3 A scanning electron microscope (SEM) image of a recess formed by UV laser processing of a sputtered copper (Cu) thin film according to an exemplary embodiment of the present invention is shown.

[0055] Figure 4 A scanning electron microscope (SEM) image of a hole (plasma-etched via) formed by plasma etching according to an exemplary embodiment of the present invention is shown. Detailed Implementation

[0056] The illustrations in the accompanying drawings are schematic. Similar or identical parts are given the same reference numerals in different drawings.

[0057] Before describing exemplary embodiments in more detail with reference to the accompanying drawings, some basic considerations will be summarized, based on which exemplary embodiments of the present invention have been developed.

[0058] According to an exemplary embodiment of the present invention, a component carrier is provided with holes (unfilled or filled, such as vias) with a diameter of up to 12 μm, defined by generally vertical sidewalls. Plasma etching is very popular in PCB manufacturing for fabricating small vias because the bottom size of UV laser drilling is too small for tiny vias, and the reliability risk of interconnects is high. The basic idea of ​​the present invention introduces the use of thin electroless copper (Cu) instead of copper foil or heavy dry film to fabricate smaller conformal masks. Based on this, CO2 lasers (beam shape optimized) and UV lasers can be used instead of photolithography processes to directly open the conformal mask to fabricate smaller conformal masks. Conventionally, during plasma etching for forming vias, copper foil and thick dry film are typically used as protective layers to fabricate conformal masks; however, it is difficult to fabricate small conformal masks because of the large thickness of copper foil and the fragility and contamination introduced when using dry film to fabricate conformal masks. In contrast, this invention proposes using electroless copper (Cu) instead of copper foil and thick dry film as a protective layer to fabricate smaller conformal masks. Based on electroless copper (Cu) as a protective layer, conformal masks can be directly opened using a beam-shape optimized CO2 laser or UV laser instead of photolithography, and this concept can be applied to cavity formation via plasma etching.

[0059] In summary, according to an exemplary embodiment of the present invention, a method for manufacturing a component carrier is provided, wherein a thin film, such as an electrodeposited or laminated copper thin film, is used as a protective layer to create a conformal mask for forming vias. Due to the small thickness of the conformal mask, this thin film can be patterned (more specifically, provided with recesses) by means of, for example, a UV laser or an optimized CO2 laser (rather than, for example, photolithography), such that recesses with small diameters are formed in the thin film in a very precise and reliable manner. The resulting patterned thin film mask allows for the formation of small vias with high reliability and without contamination issues by plasma etching. Therefore, component carriers comprising small vias (e.g., having an average diameter of 12 μm or less) with generally vertical sidewalls can be obtained.

[0060] Figure 1 An exemplary embodiment of a method for manufacturing a component carrier according to the present invention is shown.

[0061] First, a stacked layer having a core 106 and one or more electrically conductive layer structures 102 is provided.

[0062] Next, an electrically insulating layer structure 104 or a dielectric layer (e.g., an Ajinomoto stacked film (ABF) layer or a photosensitive dielectric (PID) layer) is applied to the stacked layer, such that at least a portion of the electrically conductive layer structure 102 is covered by the electrically insulating layer structure 104 (the electrically insulating layer structure 104 preferably does not contain any reinforcing agents, such as glass fibers or glass spheres). Subsequently, a continuous thin film 108 (e.g., made of copper and having a thickness in the range of 50 nm to 500 nm) is formed on the electrically insulating layer structure 104 or the dielectric layer by electroless deposition, particularly by physical deposition or chemical deposition processes, such as by sputtering or by forming a seed layer (not shown) followed by chemical growth of a metal (especially copper) on the seed layer.

[0063] Alternatively, the continuous thin film 108 or the already patterned thin film mask 110 can be applied by lamination, for example, the continuous thin film 108 or the already patterned thin film mask 110 having a thickness in the range of 1 μm to 2 μm. In particular, a composite of an electrically insulating layer or dielectric layer 104 (e.g., an Ajinomoto stacked film (ABF) layer or a photosensitive dielectric (PID) layer) and a thin film of metal (which may be already patterned or may be the continuous thin film 108 to be patterned subsequently) can be laminated onto the stacked layer in a single process step.

[0064] With the continuous thin film 108 already applied, recesses 112 are formed in the continuous thin film 108 by means of laser processing. In particular, UV lasers, as well as optimized CO2 lasers or excimer lasers, can be used to form the recesses 112 in the continuous thin film 108. The inventors have discovered that it is not necessary to perform surface roughening to blacken the surface (“black oxide”) beforehand because the (copper) film to be patterned is very thin. Therefore, the continuous thin film 108 accommodates structures or patterns, thereby producing a patterned thin film mask 110.

[0065] Next, the obtained intermediate product undergoes plasma etching, such that: holes 120 are formed in the electrically insulating layer 104 at locations where the electrically insulating layer 104 is exposed by recesses 112 in a patterned thin film mask 110, while at other locations, the electrically insulating layer 104 is protected from plasma etching by the patterned thin film mask 110. Thus, holes 120 with small diameters (e.g., in the range of 1 μm to 12 μm) can be obtained, bounded by generally vertical sidewalls (which may have minute overhangs (not shown) due to the plasma etching step).

[0066] Subsequently, the patterned thin film mask 110 is removed, for example by rapid etching, thereby exposing the remaining portion of the electrical insulating layer 104 that has not yet been plasma etched.

[0067] Although not in Figure 1 As shown, the aperture 120 can be at least partially filled with an electrically conductive material, such as copper, by means of electrodeposition and / or electroplating. Thus, small vias (or small through-holes) can be formed through the electrically insulating (or dielectric) layer structure 104, thereby providing electrical connection to the at least one electrically conductive layer 102.

[0068] Figure 2 An enlarged view of a hole in a component carrier 100 according to an exemplary embodiment of the present invention is shown.

[0069] The component carrier 100 includes: a core 106; and a stack comprising at least one electrically conductive layer structure 102 and at least one electrically insulating layer structure 104. The electrically insulating layer structure 104 includes a hole 120 defined by a generally vertical sidewall 122 and having a diameter d (particularly the average diameter) in the range of 1 μm to 12 μm. In the depicted embodiment, the bottom 124 of the hole 120 is defined by the electrically conductive layer structure 102, such that when the hole 120 is filled with an electrically conductive material (not shown), an electrical connection to the electrically conductive layer structure 102 can be obtained via a small via or through-connection (not shown) thus formed through the electrically insulating (or dielectric) layer structure 104.

[0070] The sidewall 122 deviates by no more than 10% from the vertical direction (i.e., the direction perpendicular to the main surface of the electrically conductive layer structure 102 or the electrically insulating layer structure 104). Additionally or alternatively, the bottom diameter d of the hole 120... b With top diameter d t The difference between them is less than 15%. An overhang 126 is shown on the left sidewall 122 of the hole 120. Such a small overhang 126, for example, less than 2 μm, can be specifically formed or retained at the top of the hole 126 (e.g., a concave notch or recess below the top surface can be formed in a plasma etching step), but it is advantageous to keep the overhang 126 as small as possible.

[0071] Figure 3 A scanning electron microscope (SEM) image of a recess formed by UV laser processing of a sputtered copper (Cu) film with a thickness of 300 nm according to an exemplary embodiment of the present invention is shown. The depicted recess has a diameter of 8 μm, and due to the extremely small crystal structure of copper obtained by sputtering, the depicted recess exhibits very good roundness and high uniformity.

[0072] Figure 4 A scanning electron microscope (SEM) image of a hole (i.e., a plasma-etched via) formed by plasma etching according to an exemplary embodiment of the present invention is shown. As can be clearly seen from the image, a hole bounded by generally vertical sidewalls, particularly a hole having a generally cylindrical shape, can be obtained.

[0073] It should be noted that the reference numerals in the claims should not be construed as limiting the scope of the claims.

[0074] The embodiments of the present invention are not limited to the preferred embodiments shown in the accompanying drawings and described above. Rather, various variations using the illustrated solutions and the principles of the invention are possible, even in fundamentally different implementations.

[0075] Figure Labels

[0076] 100 component carriers

[0077] 102 Electrically Conductive Layer Structure

[0078] 104 Electrical insulation layer structure

[0079] 106 cores

[0080] 108 Continuous Thin Film

[0081] 110 Patterned thin film mask

[0082] 112 concavity

[0083] 120 holes

[0084] 122 Sidewall

[0085] 124 Bottom

[0086] 126 Overhang

Claims

1. A method for manufacturing a component carrier (100), wherein, The method includes: A stack comprising at least one electrically conductive layer structure (102) and at least one electrically insulating layer structure (104) is provided; A continuous thin film (108) is formed on the at least one electrically insulating layer structure (104), and the continuous thin film (108) is patterned by laser processing, thereby forming a patterned thin film mask (110) on the at least one electrically insulating layer structure (104); and Holes (120) are formed in at least one electrically insulating layer structure (104) by plasma etching through recesses (112) in the patterned thin film mask (110). The patterned thin film mask (110) has a thickness ranging from 20 nm to 700 nm.

2. The method for manufacturing a component carrier (100) according to claim 1, wherein, The patterned thin film mask (110) is metallic.

3. The method for manufacturing a component carrier (100) according to claim 1 or 2, wherein, The patterned thin film mask (110) is formed by electroless deposition.

4. The method for manufacturing a component carrier (100) according to claim 3, wherein, The electroless deposition includes physical deposition processes.

5. The method for manufacturing a component carrier (100) according to claim 3, wherein, The electroless deposition includes chemical deposition processes.

6. The method for manufacturing a component carrier (100) according to claim 1 or 2, wherein, The patterned thin film mask (110) is formed by lamination.

7. The method for manufacturing a component carrier (100) according to claim 1, wherein, The laser processing includes patterning the continuous thin film (108) using at least one of a UV laser, a CO2 laser, or an excimer laser.

8. The method for manufacturing a component carrier (100) according to claim 1 or 2, wherein, The at least one electrically insulating layer structure (104) has a thickness in the range of 5 μm to 100 μm.

9. The method for manufacturing a component carrier (100) according to claim 1 or 2, wherein, The method also includes removing the patterned thin film mask (110).

10. The method for manufacturing a component carrier (100) according to claim 1 or 2, wherein, The method also includes filling the hole (120).

11. A component carrier (100) manufactured according to the method of claim 1, wherein, The component carrier (100) includes: The stack includes at least one electrically conductive layer structure (102) and at least one electrically insulating layer structure (104). A hole (120) is located in the at least one electrical insulating layer structure (104), the hole (120) being bounded by generally vertical sidewalls and having a diameter (d) in the range of 1 μm to 12 μm.

12. The component carrier (100) according to claim 11, wherein, The deviation of the sidewall (122) from the vertical direction is no more than 10%.

13. The component carrier (100) according to claim 11 or 12, wherein, The bottom diameter (d) of the hole (120) b ) and the top diameter (d) of the hole (120) t The difference between them is less than 15%.

14. The component carrier (100) according to claim 11 or 12, wherein, The overhang (126) of the hole (120) is less than 2 μm.

15. The component carrier (100) according to claim 11 or 12, wherein, The hole (120) has a diameter (d) in the range of 3 μm to 10 μm.

16. The component carrier (100) according to claim 11 or 12, wherein, The at least one electrical insulating layer structure (104) includes at least one of the following: resin, prepreg, and photosensitive dielectric.

17. The component carrier (100) according to claim 11 or 12, wherein, The at least one electrically insulating layer structure (104) includes an epoxy-based dielectric.

18. The component carrier (100) according to claim 11 or 12, wherein, The at least one electrically insulating layer structure (104) has no reinforcing structure.

19. The component carrier (100) according to claim 18, wherein, The reinforcing structure is a glass sphere or glass fiber.

20. The component carrier (100) according to claim 11 or 12, wherein, The bottom (124) of the hole (120) is closed by the at least one electrically conductive layer structure (102).

21. The component carrier (100) according to claim 11 or 12, wherein, The hole (120) is at least partially filled with an electrically conductive material.

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