Memory array with multiplexed select lines

By employing a multiplexed selection line design in the memory array, the problems of noise interference and power consumption between digital lines are solved, achieving higher memory density and energy efficiency.

CN115605956BActive Publication Date: 2026-06-09MICRON TECHNOLOGY INC
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
MICRON TECHNOLOGY INC
Filing Date
2021-03-18
Publication Date
2026-06-09

AI Technical Summary

Technical Problem

In existing memory arrays, as the distance between digital lines decreases, noise interference increases, leading to interference between selected and unselected digital lines during access operations. Furthermore, shunt transistors and shunt lines increase the area and power consumption of the memory array.

Method used

The design employs a multiplexed selection line, which reduces the number of shunt transistors and shunt lines by coupling the selection line group with the sensing component. It utilizes a single selection line to simultaneously couple selected and unselected digital lines with the sensing component, thereby reducing noise interference and lowering power consumption.

Benefits of technology

It effectively mitigates interference between selected and unselected digital lines, reduces the die area and total power consumption of the memory array, and improves memory density and energy efficiency.

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Abstract

This application relates to a memory array with multiplexed select lines. In some cases, a memory cell of a memory device can include a storage component, a first transistor coupled with a word line, and a second transistor coupled with a first select line to selectively couple the memory cell with a first digit line. A third transistor can be coupled with the first digit line and a sensing component common to a set of digit lines and a set of select lines. A second select line can be coupled with the third transistor and configured to couple the sensing component with the first digit line and to couple the sensing component with a second digit line. The sensing component can determine a logic state stored by the memory cell based on a signal from the first digit line and a signal from the second digit line.
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