A display substrate, its manufacturing method, and a display device.

Abstract

A display substrate, a method for manufacturing the same, and a display device are disclosed. The display substrate includes: in a plane parallel to the display substrate, the display substrate includes multiple gate lines, multiple data lines, multiple power lines, and multiple sub-pixels disposed on a substrate, at least one sub-pixel including a light-emitting device and a driving circuit configured to drive the light-emitting device to emit light, the driving circuit including multiple transistors and a storage capacitor; in a plane perpendicular to the display substrate, the display substrate includes a substrate and multiple functional layers; the multiple functional layers include a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed sequentially; a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer are respectively disposed between the multiple functional layers; in the direction of the gate lines extending, the power lines are interconnected through at least one functional layer.

Description

Technical Field

[0001] This article relates to the field of display technology, specifically to a display substrate and its manufacturing method, and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) display substrates are different from traditional liquid crystal display (LCD) substrates. They possess advantages such as active light emission, good temperature characteristics, low power consumption, fast response, flexibility, ultra-thinness, and low cost. Therefore, they have become one of the important developments in next-generation display devices and have received increasing attention.

[0003] To achieve high-frequency driving of OLED display substrates, a dual-data-line OLED display substrate has been proposed in related technologies, where pixels in the same column are connected to two data lines. However, while these OLED display substrates can achieve high-frequency driving, their resolution is generally low, failing to meet market demands for high-resolution display devices. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] A display substrate includes, in a plane parallel to the display substrate, a plurality of gate lines, a plurality of data lines, a plurality of power lines, and a plurality of sub-pixels disposed on a substrate. At least one sub-pixel includes a light-emitting device and a driving circuit configured to drive the light-emitting device to emit light. The driving circuit includes a plurality of transistors and a storage capacitor. In a plane perpendicular to the display substrate, the display substrate includes a substrate and a plurality of functional layers disposed on the substrate. The plurality of functional layers include a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed sequentially. A first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer are respectively disposed between the plurality of functional layers. In the direction of the gate lines extending, the power lines are interconnected through at least one functional layer.

[0006] In an exemplary embodiment, in the direction of data line extension, the power line includes a plurality of sub-power lines connected in sequence, and at least one sub-power line is disposed in a sub-pixel; the sub-power line of at least one sub-pixel includes a plurality of power parts connected in sequence, and there is an angle greater than 90 degrees and less than 180 degrees between at least one power part and the power part connected to the power part.

[0007] In an exemplary embodiment, of the at least one power supply unit and the power supply unit connected to the power supply unit, one of the power supply units is arranged parallel to the data line.

[0008] In an exemplary embodiment, the sub-power line includes a first power section, a second power section, and a third power section; the second power section is configured to connect the first power section and the third power section, the first power section and the third power section are arranged parallel to the data line, the angle between the second power section and the first power section is greater than 90 degrees and less than 180 degrees, and the angle between the second power section and the third power section is greater than 90 degrees and less than 180 degrees.

[0009] In an exemplary embodiment, the first power supply unit is connected to a third power supply unit located in the previous row of sub-pixels in the same column, and the third power supply unit is connected to the first power supply unit located in the next row of sub-pixels in the same column.

[0010] In an exemplary embodiment, the length of the first power supply unit extending along the data line extension direction is greater than the average width of the first power supply unit, the length of the second power supply unit extending along the inclined direction is greater than the average width of the second power supply unit, and the length of the third power supply unit extending along the data line extension direction is greater than the average width of the third power supply unit; the inclined direction is the direction in which the second power supply unit and the first power supply unit have the included angle.

[0011] In an exemplary embodiment, the average width of the third power supply section is smaller than the average width of the first power supply section.

[0012] In an exemplary embodiment, the distance between the edge of the first power supply unit near the side extending in the gate line direction of the third power supply unit and the edge of the third power supply unit near the side extending in the gate line direction of the first power supply unit is equivalent to the average width of the third power supply unit.

[0013] In an exemplary embodiment, the display substrate further includes a first connection portion, wherein the second electrode of the storage capacitor in at least one sub-pixel is connected to the second electrode of the storage capacitor in a sub-pixel adjacent to the gate line extension direction through the first connection portion; in at least one sub-pixel, the orthographic projection of the second power supply portion on the substrate overlaps with the orthographic projection of the second electrode of the storage capacitor on the substrate, or the orthographic projection of the second power supply portion on the substrate overlaps with the orthographic projection of the first connection portion on the substrate.

[0014] In an exemplary embodiment, the orthographic projection of the second power supply unit on the substrate overlaps with the orthographic projection of the first electrode of the storage capacitor on the substrate.

[0015] In an exemplary embodiment, the orthographic projection of the second power supply unit on the substrate overlaps with the orthographic projection of the gate line on the substrate.

[0016] In an exemplary embodiment, the plurality of transistors includes a second transistor, and the orthographic projection of the first power supply portion on the substrate overlaps with the orthographic projection of the second transistor on the substrate.

[0017] In an exemplary embodiment, the display substrate further includes a fifth insulating layer disposed on the fourth conductive layer and a fifth conductive layer disposed on the fifth insulating layer. A fifth via is disposed on the fifth insulating layer, and the fifth via is configured to connect the fifth conductive layer to the fourth conductive layer. The orthographic projection of the fifth via on the substrate does not overlap with the orthographic projection of the sub-power line on the substrate.

[0018] In an exemplary embodiment, in at least one sub-pixel, the orthographic projection of the fifth via on the substrate overlaps with the orthographic projection of the virtual extension line of the first power part in the sub-power line in the data line extension direction on the substrate.

[0019] In an exemplary embodiment, an eighth via is provided on the first insulating layer, the second insulating layer, and the third insulating layer. The eighth via is configured to allow the data line to write data signals to the semiconductor layer. The orthographic projection of the eighth via on the substrate does not overlap with the orthographic projections of the first power supply portion and the second power supply portion in the sub-power line on the substrate.

[0020] In an exemplary embodiment, in at least one sub-pixel, the orthographic projection of the eighth via on the substrate overlaps with the orthographic projection of the virtual extension line of the third power part in the sub-power line in the data line extension direction on the substrate.

[0021] In an exemplary embodiment, the power line is disposed on the third conductive layer or on the fourth conductive layer, and the power line is disposed on the same layer as the data line.

[0022] In an exemplary embodiment, the power line is disposed on the third conductive layer and the data line is disposed on the fourth conductive layer, or the data line is disposed on the third conductive layer and the power line is disposed on the fourth conductive layer.

[0023] In an exemplary embodiment, the display substrate further includes a first connection portion, wherein the second electrode of the storage capacitor in at least one sub-pixel is connected to the second electrode of the storage capacitor in a sub-pixel adjacent to the gate line extension direction through the first connection portion.

[0024] In an exemplary embodiment, there is at least one region comprising 2*4 sub-pixels. The second electrodes of the storage capacitors in the first sub-pixel and the second electrodes of the storage capacitors in the second sub-pixel of a row are interconnected through the first connecting portion. The second electrodes of the storage capacitors in the second sub-pixel and the second electrodes of the storage capacitors in the third sub-pixel are directly connected. The second electrodes of the storage capacitors in the third sub-pixel and the second electrodes of the storage capacitors in the fourth sub-pixel are interconnected through the first connecting portion. In another row, the second electrodes of the storage capacitors in the first sub-pixel and the second electrodes of the storage capacitors in the second sub-pixel are directly connected. The second electrodes of the storage capacitors in the second sub-pixel and the second electrodes of the storage capacitors in the third sub-pixel and the second electrodes of the storage capacitors in the fourth sub-pixel are interconnected through the first connecting portion.

[0025] In an exemplary embodiment, the semiconductor layers in the first sub-pixel and the second sub-pixel are spaced apart, the semiconductor layers in the second sub-pixel and the third sub-pixel are spaced apart, and the semiconductor layers in the third sub-pixel and the fourth sub-pixel are spaced apart.

[0026] In an exemplary embodiment, the third conductive layer includes a first electrode of a fifth transistor; the first electrode of the fifth transistor in the first sub-pixel is spaced apart from the first electrode of the fifth transistor in the second sub-pixel, the first electrode of the fifth transistor in the second sub-pixel is spaced apart from the first electrode of the fifth transistor in the third sub-pixel, and the first electrode of the fifth transistor in the third sub-pixel is spaced apart from the first electrode of the fifth transistor in the fourth sub-pixel.

[0027] In an exemplary embodiment, at least one region comprising 2*4 sub-pixels exists, where the second electrodes of the capacitors stored in the first sub-pixel and the second electrodes of the capacitors stored in the second sub-pixel of a row are interconnected via the first connecting portion, the second electrodes of the capacitors stored in the second sub-pixel and the second electrodes of the capacitors stored in the third sub-pixel are disconnected, and the second electrodes of the capacitors stored in the third sub-pixel and the second electrodes of the capacitors stored in the fourth sub-pixel are interconnected via the first connecting portion; in another row, the second electrodes of the capacitors stored in the first sub-pixel and the second electrodes of the capacitors stored in the second sub-pixel are disconnected, the second electrodes of the capacitors stored in the second sub-pixel and the second electrodes of the capacitors stored in the third sub-pixel are interconnected via the first connecting portion, and the second electrodes of the capacitors stored in the third sub-pixel and the second electrodes of the capacitors stored in the fourth sub-pixel are disconnected.

[0028] In an exemplary embodiment, the third conductive layer includes a first electrode and a second connection portion of a fifth transistor; the first electrode of the fifth transistor in the first sub-pixel of a row is disconnected from the first electrode of the fifth transistor in the second sub-pixel, the first electrode of the fifth transistor in the second sub-pixel is connected to the first electrode of the fifth transistor in the third sub-pixel through the second connection portion, and the first electrode of the fifth transistor in the third sub-pixel is disconnected from the first electrode of the fifth transistor in the fourth sub-pixel; in another row, the first electrode of the fifth transistor in the first sub-pixel is connected to the first electrode of the fifth transistor in the second sub-pixel through the second connection portion, the first electrode of the fifth transistor in the second sub-pixel is disconnected from the first electrode of the fifth transistor in the third sub-pixel, and the first electrode of the fifth transistor in the third sub-pixel is connected to the first electrode of the fifth transistor in the fourth sub-pixel through the second connection portion.

[0029] In an exemplary embodiment, the power line is interconnected with the second electrode of the storage capacitor and the first electrode of the fifth transistor in the direction of gate line extension.

[0030] In an exemplary embodiment, a first via is provided on the fourth insulating layer to expose the first electrode of the fifth transistor, and a second via is provided on the third insulating layer to expose the second electrode of the storage capacitor. The power line is connected to the first electrode of the fifth transistor through the first via, and the first electrode of the fifth transistor is connected to the second electrode of the storage capacitor through the second via.

[0031] In an exemplary embodiment, in at least one sub-pixel, the number of the first via is one, and the number of the second via is multiple, with the multiple second vias arranged along the extension direction of the data line; the orthographic projection of the power line on the substrate includes the orthographic projection of the first via on the substrate, and the orthographic projection of the first electrode of the fifth transistor on the substrate includes the orthographic projection of the second via on the substrate.

[0032] In an exemplary embodiment, the semiconductor layer includes a third connection portion; the semiconductor layer in the first sub-pixel of one row is disconnected from the semiconductor layer in the second sub-pixel, the semiconductor layer in the second sub-pixel is connected to the semiconductor layer in the third sub-pixel through the third connection portion, and the semiconductor layer in the third sub-pixel is disconnected from the semiconductor layer in the fourth sub-pixel; the semiconductor layer in the first sub-pixel of another row is connected to the semiconductor layer in the second sub-pixel through the third connection portion, the semiconductor layer in the second sub-pixel is disconnected from the semiconductor layer in the third sub-pixel, and the semiconductor layer in the third sub-pixel is connected to the semiconductor layer in the fourth sub-pixel through the third connection portion.

[0033] In an exemplary embodiment, in the gate line extension direction, the power line is interconnected with the second electrode of the storage capacitor via the third connection portion of the semiconductor layer.

[0034] In an exemplary embodiment, an eleventh via is provided on the third insulating layer to expose the second electrode of the storage capacitor, and a twelfth via is provided on the first, second, and third insulating layers to expose the third connection portion of the semiconductor layer. The power line is connected to the second electrode of the storage capacitor through the eleventh via, and the power line is connected to the third connection portion of the semiconductor layer through the twelfth via.

[0035] In an exemplary embodiment, in at least one sub-pixel, the number of the eleventh via is one, and the number of the twelfth via is multiple, with the multiple twelfth vias arranged along the extension direction of the data line; the orthogonal projection of the power line on the substrate includes the orthogonal projections of the eleventh via and the twelfth via on the substrate.

[0036] In an exemplary embodiment, the plurality of transistors includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; in at least one sub-pixel, the semiconductor layer includes at least a first active region at the location of the first transistor, a second active region at the location of the second transistor, a third active region at the location of the third transistor, a fourth active region at the location of the fourth transistor, a fifth active region at the location of the fifth transistor, a sixth active region at the location of the sixth transistor, and a seventh active region at the location of the seventh transistor, wherein the first active region, the second active region, the third active region, the fourth active region, the fifth active region, the sixth active region, and the seventh active region are an integral structure.

[0037] In an exemplary embodiment, the distance between the second active region and the first active region in the direction of the extension of the gate line is less than the distance between the second active region and the seventh active region in the direction of the extension of the gate line.

[0038] In an exemplary embodiment, the seventh active region and the first active region are arranged sequentially along the direction from the data line to the power line of the data signal being written.

[0039] In an exemplary embodiment, at least one sub-pixel includes a first region, a second region, and a third region arranged sequentially along the data line extension direction; the first active region and the seventh active region are disposed on the side of the first region away from the second region, the second active region and the fourth active region are disposed on the side of the first region close to the second region; the third active region is disposed in the second region; and the fifth active region and the sixth active region are disposed in the third region.

[0040] In an exemplary embodiment, the first terminal of the first transistor is connected to the initial signal line, the second terminal of the first transistor T1 is connected to the first electrode of the storage capacitor, the first terminal of the second transistor is connected to the first electrode of the storage capacitor, the second terminal of the second transistor is connected to the second terminal of the sixth transistor, the first terminal of the third transistor is connected to the second terminal of the fourth transistor, the second terminal of the third transistor is connected to the second terminal of the sixth transistor, the first terminal of the fourth transistor is connected to the data line, the first terminal of the fifth transistor is connected to the power line, the second terminal of the fifth transistor is connected to the first terminal of the third transistor, the second terminal of the sixth transistor is connected to the anode of the light-emitting device, the first terminal of the seventh transistor is connected to the initial signal line, and the second terminal of the seventh transistor is connected to the anode of the light-emitting device; the first active region is connected to the second active region and the seventh active region respectively, the second active region is connected to the third active region and the sixth active region respectively, and the fourth active region is connected to the third active region and the fifth active region respectively.

[0041] In an exemplary embodiment, the semiconductor layers of adjacent sub-pixels are symmetrical in the direction of gate line extension.

[0042] In an exemplary embodiment, there is at least one region comprising 2*2 sub-pixels, wherein the semiconductor layer shape in the first sub-pixel of one row is the same as the semiconductor layer shape in the second sub-pixel of another row, and the semiconductor layer shape in the second sub-pixel of one row is the same as the semiconductor layer shape in the first sub-pixel of another row.

[0043] In an exemplary embodiment, the semiconductor layer includes a third connection portion, and the semiconductor layer in at least one sub-pixel is connected to the semiconductor layer in an adjacent sub-pixel in the gate line extension direction through the third connection portion.

[0044] In an exemplary embodiment, the third connection portion is connected to the active region of the fifth transistor.

[0045] In an exemplary embodiment, the orthographic projection of the third connection portion on the substrate overlaps with the orthographic projection of the power line on the substrate.

[0046] In an exemplary embodiment, a twelfth via is provided on the first insulating layer, the second insulating layer, and the third insulating layer to expose the third connection portion, and the power line is connected to the third connection portion through the twelfth via.

[0047] In an exemplary embodiment, there is at least one region comprising 2*4 sub-pixels, wherein the semiconductor layer in the first sub-pixel of one row is disconnected from the semiconductor layer in the second sub-pixel, the semiconductor layer in the second sub-pixel is connected to the semiconductor layer in the third sub-pixel through the third connecting portion, and the semiconductor layer in the third sub-pixel is disconnected from the semiconductor layer in the fourth sub-pixel; in another row, the semiconductor layer in the first sub-pixel is connected to the semiconductor layer in the second sub-pixel through the third connecting portion, the semiconductor layer in the second sub-pixel is disconnected from the semiconductor layer in the third sub-pixel, and the semiconductor layer in the third sub-pixel is connected to the semiconductor layer in the fourth sub-pixel through the third connecting portion.

[0048] In an exemplary embodiment, there is at least one pixel column, and in the data line extension direction, the data line includes a plurality of sequentially connected sub-data lines; there is at least one sub-pixel, and two sub-data lines are disposed between the sub-pixel and the adjacent sub-pixel in the gate line extension direction.

[0049] In an exemplary embodiment, the two sub-data lines are parallel to each other.

[0050] In an exemplary embodiment, within at least one sub-pixel, an eighth via is provided on the first insulating layer, the second insulating layer, and the third insulating layer to expose the semiconductor layer, and a third via is provided on the fourth insulating layer to expose the first electrode of the fourth transistor. The data line is connected to the first electrode of the fourth transistor through the third via, and the first electrode of the fourth transistor is connected to the semiconductor layer through the eighth via.

[0051] In an exemplary embodiment, the eighth vias of adjacent sub-pixels are symmetrical in the direction of the gate line extension.

[0052] In an exemplary embodiment, the data line is provided with the third conductive layer, and the power line is provided with the third conductive layer.

[0053] In an exemplary embodiment, the data line is disposed on the fourth conductive layer, and the power line is disposed on the third or fourth conductive layer.

[0054] In an exemplary embodiment, in at least one column of sub-pixels, the data line includes a first sub-data line and a second sub-data line, the first sub-data line and the second sub-data line being located on both sides of the column of sub-pixels, respectively.

[0055] In an exemplary embodiment, the power line is located between the first sub-data line and the second sub-data line.

[0056] In an exemplary embodiment, the pixel structures of adjacent sub-pixels are symmetrical in the direction of the gate line extension.

[0057] In an exemplary embodiment, there is at least one region comprising 2*2 sub-pixels, wherein the pixel structure of the first sub-pixel in one row is the same as the pixel structure of the second sub-pixel in another row, and the pixel structure of the second sub-pixel in one row is the same as the pixel structure of the first sub-pixel in another row.

[0058] In an exemplary embodiment, the display substrate further includes a reset signal line, a light emission control line, and an initial signal line; the semiconductor layer includes at least the active regions of a plurality of transistors, the first conductive layer includes at least a gate line, a light emission control line, a reset signal line, a first electrode of a storage capacitor, and a gate electrode of a plurality of transistors, the second conductive layer includes at least an initial signal line and a second electrode of a storage capacitor; the third conductive layer includes at least the source and drain electrodes of a plurality of transistors, and the fourth conductive layer includes at least a data line and a power line.

[0059] In an exemplary embodiment, at least one sub-pixel includes a first region, a second region, and a third region arranged sequentially along the data line extension direction; the gate line, the initial signal line, and the reset signal line are located in the first region, the first electrode and the second electrode of the storage capacitor are located in the second region, and the light emission control line is located in the third region.

[0060] In an exemplary embodiment, the second conductive layer further includes a shielding electrode, wherein in at least one sub-pixel, the orthographic projection of the shielding electrode on the substrate overlaps with the orthographic projection of the power line on the substrate.

[0061] In an exemplary embodiment, the power line is connected to the shielding electrode via a via.

[0062] In an exemplary embodiment, the shielding electrode is disposed between the gate line and the reset signal line in the data line extension direction.

[0063] In an exemplary embodiment, the shielding electrode includes a first portion extending along the grid line extension direction and a second portion extending along the data line extension direction, wherein one end of the first portion near the second portion is connected to one end of the second portion near the first portion.

[0064] In an exemplary embodiment, the first conductive layer further includes a gate block extending along the data line extension direction, the gate block being connected to the gate line; in the data line extension direction, the gate block and the second part of the shielding electrode have a directly opposite region.

[0065] In an exemplary embodiment, the source and drain electrodes of the plurality of transistors include the first electrode of the second transistor. A seventh via is provided on the second and third insulating layers to expose the first electrode of the storage capacitor. A ninth via is provided on the first, second, and third insulating layers to expose the active region of the second transistor. One end of the first electrode of the second transistor is connected to the first electrode of the storage capacitor through the seventh via, and the other end is connected to the active region of the second transistor through the ninth via.

[0066] In an exemplary embodiment, the orthographic projection of the first electrode of the second transistor on the substrate overlaps with the orthographic projection of the gate line on the substrate, but the orthographic projection of the first electrode of the second transistor on the substrate does not overlap with the orthographic projections of the light emission control line, the reset signal line, and the initial signal line on the substrate.

[0067] In an exemplary embodiment, the source and drain electrodes of the plurality of transistors include the first electrode of the first transistor, a sixth via is provided on the third insulating layer to expose the initial signal line, and a tenth via is provided on the first, second and third insulating layers to expose the active region of the first transistor. One end of the first electrode of the first transistor is connected to the initial signal line through the sixth via, and the other end is connected to the active region of the first transistor through the tenth via.

[0068] In an exemplary embodiment, the orthographic projection of the first electrode of the first transistor on the substrate overlaps with the orthographic projection of the reset signal line on the substrate, but the orthographic projection of the first electrode of the first transistor on the substrate does not overlap with the orthographic projections of the gate line and the light emission control line on the substrate.

[0069] In an exemplary embodiment, the display substrate further includes a fifth insulating layer disposed on the fourth conductive layer and a fifth conductive layer disposed on the fifth insulating layer; the fourth conductive layer further includes a connection electrode, and the source and drain electrodes of the plurality of transistors include the second electrode of the sixth transistor; the fourth insulating layer is provided with a fourth via exposing the second electrode of the sixth transistor, the fifth insulating layer is provided with a fifth via exposing the connection electrode, the connection electrode is connected to the second electrode of the sixth transistor through the fourth via, and the fifth conductive layer is connected to the connection electrode through the fifth via.

[0070] In an exemplary embodiment, the orthographic projection of the connection electrode on the substrate overlaps with the orthographic projection of the first electrode of the second transistor on the substrate.

[0071] In an exemplary embodiment, at least one sub-pixel includes at least: a first via exposing a first electrode of a fifth transistor, the first via being configured to connect the first electrode of the fifth transistor to the power line; a second via exposing a second electrode of a storage capacitor, the second via being configured to connect the second electrode to the first electrode of the fifth transistor; a third via exposing a first electrode of a fourth transistor, the third via being configured to connect the first electrode of the fourth transistor to the data line; a fourth via exposing a second electrode of a sixth transistor, the fourth via being configured to connect the second electrode of the sixth transistor to a connection electrode; and a fifth via exposing a connection electrode, the fifth via being configured to connect the connection electrode to the anode of a fifth conductive layer. The following are connections: a sixth via exposing an initial signal line, the sixth via configured to connect the initial signal line to the first electrode of a first transistor; a seventh via exposing the first electrode of a storage capacitor, the seventh via configured to connect the first electrode to the first electrode of a second transistor; an eighth via exposing the active region of a fourth transistor, the eighth via configured to connect the active region of the fourth transistor to the first electrode of the fourth transistor; a ninth via exposing the active region of a second transistor, the ninth via configured to connect the active region of the second transistor to the first electrode of the second transistor; and a tenth via exposing the active region of a first transistor, the tenth via configured to connect the active region of the first transistor to the first electrode of the first transistor.

[0072] In an exemplary embodiment, at least one sub-pixel includes at least: an eleventh via exposing a second electrode of a storage capacitor, the eleventh via being configured to connect the second electrode to a power line; and a twelfth via exposing a third connection portion, the twelfth via being configured to connect the third connection portion to a power line.

[0073] The display device includes the aforementioned display substrate.

[0074] A method for manufacturing a display substrate, configured to manufacture a display substrate as described in this disclosure, wherein the display substrate includes gate lines, data lines, power lines and a plurality of sub-pixels disposed on a substrate in a plane parallel to the display substrate, at least one sub-pixel including a light-emitting device and a driving circuit configured to drive the light-emitting device to emit light, the driving circuit including a plurality of transistors and a storage capacitor; the manufacturing method includes:

[0075] Provide a base;

[0076] Multiple functional layers are formed on the substrate; the multiple functional layers include a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer arranged sequentially; a first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer are respectively disposed between the multiple functional layers; in the gate line extension direction, the power lines are interconnected through at least one functional layer.

[0077] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0078] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0079] Figure 1 This is a schematic diagram of the structure of the display substrate provided in this disclosure;

[0080] Figure 2 A side view of a sub-pixel in a display substrate provided in this disclosure;

[0081] Figure 3 This is a top view of a sub-pixel in a display substrate provided in this disclosure;

[0082] Figure 4A The equivalent circuit diagram of the driving circuit provided in this disclosure;

[0083] Figure 4B The timing diagram of the driving circuit provided in this disclosure;

[0084] Figure 5 This is a top view of a display substrate containing multiple sub-pixels, as provided in this disclosure;

[0085] Figure 6A This is a top view of a sub-pixel corresponding to Implementation Method 1;

[0086] Figure 6B This is another top view of the sub-pixel corresponding to Implementation Method 1;

[0087] Figure 7A This is a top view of the second metal layer corresponding to Embodiment 1;

[0088] Figure 7B This is a top view of the third metal layer corresponding to Embodiment 1;

[0089] Figure 8A This is a top view of a sub-pixel corresponding to Implementation Method 2;

[0090] Figure 8B This is another top view of the sub-pixel corresponding to Implementation Method 2;

[0091] Figure 9A This is a top view of the second metal layer corresponding to Embodiment 2;

[0092] Figure 9B This is a top view of the third metal layer corresponding to Embodiment 2;

[0093] Figure 10 This is another top view of a plurality of sub-pixels in a display substrate provided in this disclosure;

[0094] Figure 11 A flowchart illustrating a method for manufacturing a display substrate provided in this disclosure;

[0095] Figure 12 This is a first schematic diagram of the fabrication of a display substrate provided in this disclosure;

[0096] Figure 13 This is a second schematic diagram of the fabrication of a display substrate provided in this disclosure;

[0097] Figure 14A This is a third manufacturing schematic diagram of a display substrate provided in this disclosure;

[0098] Figure 14B This is another third schematic diagram of the fabrication of a display substrate provided in this disclosure;

[0099] Figure 15A This is a fourth manufacturing schematic diagram of a display substrate provided in this disclosure;

[0100] Figure 15B This is another fourth schematic diagram of the fabrication of a display substrate provided in this disclosure;

[0101] Figure 16A This is a fifth manufacturing schematic diagram of a display substrate provided in this disclosure;

[0102] Figure 16B This is another fifth schematic diagram of the fabrication of a display substrate provided in this disclosure;

[0103] Figure 17 A top view of a plurality of sub-pixels in another display substrate provided in this disclosure;

[0104] Figure 18 A cross-sectional view of a plurality of sub-pixels in another display substrate provided in this disclosure;

[0105] Figure 19 A top view of a sub-pixel in another display substrate provided in this disclosure;

[0106] Figure 20 A top view of another portion of a sub-pixel in another display substrate provided in this disclosure;

[0107] Figure 21 This is a top view of another portion of the sub-pixels in another display substrate provided in this disclosure;

[0108] Figure 22 A flowchart illustrating another method for manufacturing a display substrate provided in this disclosure;

[0109] Figure 23 A schematic diagram illustrating the fabrication of the active region of another display substrate provided in this disclosure;

[0110] Figure 24 A schematic diagram illustrating the fabrication of a first insulating layer and a first metal layer for another display substrate provided in this disclosure;

[0111] Figure 25 A schematic diagram illustrating the fabrication of a second insulating layer and a second metal layer for another display substrate provided in this disclosure;

[0112] Figure 26 This is a schematic diagram illustrating the fabrication of the third insulating layer of another display substrate provided in this disclosure. Detailed Implementation

[0113] This disclosure describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0114] This disclosure includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this disclosure may also be combined with any conventional features or elements to form a unique inventive scheme as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive schemes to form another unique inventive scheme as defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this disclosure may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

[0115] Furthermore, in describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that the method or process does not depend on the specific order of steps described herein. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims relating to the method and / or process should not be limited to the steps performed in the order written, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of this disclosure.

[0116] Unless otherwise defined, the technical or scientific terms used in the embodiments of this invention shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in the embodiments of this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0117] In this article, "approximately" refers to a value that is not strictly defined and is within the allowable range of process and measurement errors. "Equivalently" refers to a ratio of one dimension to another that is between 0.8 and 1.2.

[0118] This disclosure provides a display substrate in several embodiments. In a plane parallel to the display substrate, the display substrate includes gate lines, data lines, power lines, and a plurality of sub-pixels disposed on a substrate. At least one sub-pixel includes a light-emitting device and a driving circuit configured to drive the light-emitting device to emit light. The driving circuit includes a plurality of transistors and a storage capacitor. In a plane perpendicular to the display substrate, the display substrate includes a substrate and a plurality of functional layers disposed on the substrate. The plurality of functional layers include a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed sequentially. A first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer are respectively disposed between the plurality of functional layers. In the direction of gate line extension, the power lines are interconnected through at least one functional layer. In an exemplary embodiment, the display substrate further includes a fifth insulating layer disposed on the fourth conductive layer and a fifth conductive layer disposed on the fifth insulating layer.

[0119] Figure 1 This is a schematic diagram of the structure of the display substrate provided in this disclosure. Figure 2 This is a side view of a sub-pixel in a display substrate provided in this disclosure. Figure 3 This is a top view of a sub-pixel in a display substrate provided in this disclosure, such as... Figures 1-3 As shown, in a plane parallel to the display substrate, the display substrate provided in this disclosure includes a gate line G, a data line D, a power line VDD, a reset signal line Reset, a light emission control line EM, an initial signal line Vinit, and multiple sub-pixels P. Each sub-pixel includes a light-emitting device and a driving circuit configured to drive the light-emitting device to emit light. The driving circuit includes multiple transistors and a storage capacitor. In a plane perpendicular to the display substrate, the display substrate includes a substrate 10 and semiconductor layers 20, a first metal layer 30, a second metal layer 40, a third metal layer 50, a fourth metal layer 60, and a fifth metal layer 70 disposed on the substrate 10 and insulated from each other. The first metal layer 30 serves as a first conductive layer, the second metal layer 40 serves as a second conductive layer, the third metal layer 50 serves as a third conductive layer, the fourth metal layer 60 serves as a fourth conductive layer, and the fifth metal layer 70 serves as a fifth conductive layer. In an exemplary embodiment, the display substrate includes a display area (AA) and a border area located around the display area. The display area includes a plurality of display sub-pixels, and the border area includes a plurality of dummy sub-pixels. The sub-pixels referred to herein are the display sub-pixels of the display area.

[0120] In an exemplary embodiment, the semiconductor layer 20 may include the active regions of a plurality of transistors; the first metal layer 30 may include a gate line G, a light-emitting control line EM, a reset signal line Reset, a first electrode C1 of a storage capacitor, and the gate electrodes of the plurality of transistors; the second metal layer 40 may include an initial signal line Vinit and a second electrode C2 of a storage capacitor; the third metal layer 50 may include the first and second electrodes of the plurality of transistors; the fourth metal layer 60 may include a data line D and a power line VDD; and the fifth metal layer 70 may include the anode of a light-emitting device.

[0121] In an exemplary embodiment, the data line may include multiple sequentially connected sub-data lines along its extension direction, with each sub-data line corresponding to a multiple sub-pixels. At least one sub-pixel has two sub-data lines disposed between it and an adjacent sub-pixel in the gate line extension direction. In an exemplary embodiment, the two sub-data lines are parallel to each other.

[0122] like Figure 1As shown, in an exemplary embodiment, the display substrate may be provided with M rows * N columns of sub-pixels, N columns of data lines D1~DN, N columns of power lines VDD1~VDDN, M rows of gate lines G1~GM, M-1 rows of light emission control lines EM1~EMM-1, a reset signal line Reset, and an initial signal line Vinit. The display substrate may also include: a data driver configured to provide data signals to the data lines, a scan driver configured to provide scan signals to the gate lines, a light emission driver configured to provide light emission control signals to the light emission control lines, and a timing controller configured to provide drive signals to the data driver, the scan driver, and the light emission driver.

[0123] In some possible implementations, such as Figure 1 As shown, the driving circuit in the i-th column of sub-pixels is connected to the i-th column of data lines. Each column of data lines includes a first sub-data line DO and a second sub-data line DE. The first sub-data line DOi and the second sub-data line DEi in the i-th column of data lines are located on both sides of the i-th column of sub-pixels, respectively. i N, where N is the total number of columns of sub-pixels.

[0124] In some possible implementations, two sub-data lines are set between two adjacent columns of sub-pixels. That is, a first sub-data line DO of the sub-pixel in the current column and a second sub-data line DE of the sub-pixel in the adjacent column are set between two adjacent columns of sub-pixels. Alternatively, a second sub-data line DE of the sub-pixel in the current column and a first sub-data line DO of the sub-pixel in the adjacent column are set between two adjacent columns of sub-pixels.

[0125] For example, the first sub-data line Doi of the i-th column data line is located on the side of the i-th column sub-pixel closest to the i+1-th column sub-pixel, and the first sub-data line DOi+1 of the i+1-th column data line is located on the side of the i+1-th column sub-pixel closest to the i-th column sub-pixel; or, the second sub-data line DEi of the i-th column data line is located on the side of the i-th column sub-pixel closest to the i+1-th column sub-pixel, and the second sub-data line DEi+1 of the i+1-th column data line is located on the side of the i+1-th column sub-pixel closest to the i-th column sub-pixel.

[0126] In some possible implementations, the substrate 10 can be a rigid substrate or a flexible substrate. The rigid substrate can be one or more of glass and metal sheets, but is not limited to; the flexible substrate can be one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers, but is not limited to.

[0127] In some possible implementations, the semiconductor layer 20 may be made of polycrystalline silicon or metal oxide, and this disclosure does not limit it in any way.

[0128] In some possible implementations, the first metal layer can be made of a metal such as silver, aluminum, or copper, and this disclosure does not limit this to any particular material.

[0129] In some possible implementations, the second metal layer can be made of metals such as silver, aluminum or copper, and this disclosure does not limit this to any particular material.

[0130] In some possible implementations, the third metal layer can be made of metals such as silver, aluminum or copper, and this disclosure does not limit it in any way;

[0131] In some possible implementations, the fourth metal layer can be made of metals such as silver, aluminum or copper, and this disclosure does not limit this to any particular material.

[0132] In some possible implementations, the fifth metal layer can be made of metals such as silver, aluminum or copper, and this disclosure does not limit this to any particular material.

[0133] Figure 4A The equivalent circuit diagram of the drive circuit provided in this disclosure is shown below. Figure 4B The timing diagram of the driving circuit provided in this disclosure is as follows: Figure 4A and Figure 4B As shown, Figure 4A The following description uses the driving circuit included in the i-th column sub-pixel and the (i+1)-th column sub-pixel as an example. The driving circuit provided in this disclosure can be a 7T1C structure. The driving circuit can include: a first transistor T1 to a seventh transistor T7 and a storage capacitor C, wherein the storage capacitor C includes a first electrode C1 and a second electrode C2.

[0134] In an exemplary embodiment, specifically, the gate electrode of the first transistor T1 is connected to the reset signal line Reset, the first terminal of the first transistor T1 is connected to the initial signal line Vinit, the second terminal of the first transistor T1 is connected to the first electrode C1 of the storage capacitor C, the gate electrode of the second transistor T2 is connected to the gate line G, the first terminal of the second transistor T2 is connected to the first electrode C1 of the storage capacitor C, the second terminal of the second transistor T2 is connected to the second terminal of the sixth transistor T6, the gate electrode of the third transistor T3 is connected to the first electrode C1 of the storage capacitor C, the first terminal of the third transistor T3 is connected to the second terminal of the fourth transistor T4, the second terminal of the third transistor T3 is connected to the second terminal of the sixth transistor T6, and the gate electrode of the fourth transistor T4 is connected to the gate line G. The circuit is connected as follows: line G is connected; the first electrode of the fourth transistor T4 is connected to the data line D; the gate electrode of the fifth transistor T5 is connected to the light-emitting control line EM; the first electrode of the fifth transistor T5 is connected to the power line VDD; the second electrode of the fifth transistor T5 is connected to the first electrode of the third transistor T3; the gate electrode of the sixth transistor T6 is connected to the light-emitting control line EM; the second electrode of the sixth transistor T6 is connected to the anode of the light-emitting device; the gate electrode of the seventh transistor T7 is connected to the reset signal line Reset; the first electrode of the seventh transistor T7 is connected to the initial signal line Vinit; the second electrode of the seventh transistor T7 is connected to the anode of the light-emitting device; the second electrode C2 of the storage capacitor is connected to the power line VDD; and the cathode of the light-emitting device OLED is connected to the low-level power supply terminal VSS.

[0135] In an exemplary embodiment, the third transistor T3 is a driving transistor, and all other transistors except the third transistor T3 are switching transistors. The first transistor T1 to the seventh transistor T7 can all be P-type transistors or N-type transistors, and this disclosure does not limit them in any way.

[0136] Taking the first transistor T1 to the seventh transistor T7 as examples, all of which are P-type transistors, the operation of the driving circuit can include:

[0137] In the first stage, P1, the reset stage, the reset signal line Reset provides an effective level, the first transistor T1 and the seventh transistor T7 are turned on, and the initial signal provided by the initial signal line Vinit initializes the signal at the second electrode of the sixth transistor T6 and the signal at the first electrode C1.

[0138] In the second stage P2, the write stage, the gate line G provides an effective level, the second transistor T2 and the fourth transistor T4 are turned on, and the data signal provided by the data line D is written to the first electrode of the third transistor T3, so that the potential of the signal at the gate electrode and the second electrode of the second transistor T2 is the same, so that the third transistor T3 is turned on.

[0139] In the third stage, P3, the light-emitting stage, the light-emitting control line EM provides an effective level, the fifth transistor T5 and the sixth transistor T6 are turned on, and the power line VDD provides driving current to the light-emitting device OLED to drive the light-emitting device to emit light.

[0140] In some possible implementations, such as Figure 4A As shown, the light-emitting device in this disclosure can be an OLED.

[0141] The display substrate provided in this disclosure includes gate lines, data lines, power lines, reset signal lines, light-emitting control lines, initial signal lines, and multiple sub-pixels. Each sub-pixel includes a light-emitting device and a driving circuit configured to drive the light-emitting device to emit light. The driving circuit may include multiple transistors and a storage capacitor. The display substrate may include a substrate and a semiconductor layer, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and a fifth metal layer, which are sequentially disposed on the substrate and insulated from each other. The semiconductor layer includes the active regions of multiple transistors. The first metal layer includes the gate lines, light-emitting control lines, reset signal lines, the first electrode of the storage capacitor, and the gate electrode of the multiple transistors. The second metal layer includes the initial signal line and the second electrode of the storage capacitor. The third metal layer includes the source and drain electrodes of the multiple transistors. The fourth metal layer includes the data lines and power lines. The fifth metal layer includes the anode of the light-emitting device. The i-th column of sub-pixels is connected to the i-th column of data lines. Each column of data lines includes a first sub-data line and a second sub-data line. The first and second sub-data lines in the i-th column of data lines are located on both sides of the i-th column of sub-pixels, respectively. i N, where N is the total number of columns of sub-pixels.

[0142] This disclosure features five metal layers. By distributing the data lines and power lines to the source and drain electrodes of multiple transistors in different layers, the volume occupied by the data lines connecting the sub-pixels can be reduced, thereby improving the resolution of the high-frequency driven OLED display substrate.

[0143] In some possible implementations, such as Figure 3 As shown, each sub-pixel in the display substrate provided in this disclosure can be divided into a first region R1, a second region R2, and a third region R3 arranged sequentially along the data line extension direction.

[0144] The storage capacitor is located in the second region R2. The first region R1 and the third region R3 are located on both sides of the second region R2, respectively. The initial signal line Vinit, the gate line G and the reset signal line Reset connected to the sub-pixel driving circuit are located in the first region R1. The light emission control line EM connected to the sub-pixel driving circuit is located in the third region R3.

[0145] The driving circuits of adjacent sub-pixels located in the same column are connected to different sub-data lines. That is, if the sub-pixel in the i-th row and j-th column is connected to the first sub-data line DOj in the j-th column, then the sub-pixel in the (i+1)-th row and j-th column is connected to the second sub-data line Dej in the j-th column; if the sub-pixel in the i-th row and j-th column is connected to the second sub-data line DEj in the j-th column, then the sub-pixel in the (i+1)-th row and j-th column is connected to the first sub-data line DOj in the j-th column.

[0146] In some possible implementations, such as Figure 1 and Figure 3 It can be seen that the driving circuit of the i-th column sub-pixel is also connected to the i-th column power line, 1 i N. The power line VDDi in column i is located between the first sub-data line DOi and the second sub-data line DEi in column i.

[0147] Figure 5 This is a top view of a display substrate containing multiple sub-pixels, as provided in this disclosure. Figure 5 As shown, the pixel structures of adjacent sub-pixels in the same row are mirror images of each other about the center line CL of the two sub-data lines between the adjacent sub-pixels. The pixel structure of the sub-pixel located in row i, column j is the same as that of the sub-pixel located in row i, column j+2; the pixel structure of the sub-pixel located in row i, column j+1 is the same as that of the sub-pixel located in row i, column j+3; the pixel structure of the sub-pixel located in row i, column j is the same as that of the sub-pixel located in row i+1, column j+1; and the pixel structure of the sub-pixel located in row i, column j is the same as that of the sub-pixel located in row i+1, column j. In this paper, identical pixel structures include, but are not limited to, identical overall shapes, identical connection relationships between parts, and identical signal flow trends.

[0148] like Figure 5 As shown, the power lines of two adjacent columns are mirror-symmetric about the center line between them, meaning that the power lines of adjacent sub-pixels are symmetrical to each other. The center line CL of the two sub-data lines located between the sub-pixel in row i and column j and the sub-pixel in row i and (j+1)th column can be the same center line as the center line between the power line in column j and the power line in column (j+1).

[0149] In some possible implementations, such as Figure 5 As shown, taking a region of 8 sub-pixels in two rows and four columns (including a region of 2*4 sub-pixels) as an example, the power lines in the i-th column include: multiple interconnected sub-power lines, namely S1 to SN. The multiple sub-power lines correspond one-to-one with all the sub-pixels in each column, and the multiple sub-power lines are respectively set in the multiple sub-pixels in the column.

[0150] In an exemplary embodiment, the shape of the sub-power line corresponding to the sub-pixel in row i and column j, after being mirrored along the center line of the first and second sub-data lines located in column j, is the same as the shape of the sub-power line corresponding to the sub-pixel in row i+1 and column j. In this document, the same power line shape includes, but is not limited to, the same overall shape, the same connection relationship between the various parts, and the same signal flow direction.

[0151] In an exemplary embodiment, each sub-power line may include a first power section SS1, a second power section SS2, and a third power section SS3 arranged sequentially along a second direction. The second power section SS2 is configured to connect the first power section SS1 and the third power section SS3. The first power section SS1 and the third power section SS3 may be arranged parallel to the data line. The angle between the second power section SS2 and the first power section SS1 is greater than 90 degrees and less than 180 degrees, forming a zigzag-shaped sub-power line. The second direction is the extension direction of the data line.

[0152] In this document, "parallel" refers to a state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes states where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to a state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes states where the angle is greater than or equal to 85° and less than 95°. In this document, "parallel to the data line" means that the main body of the first power supply unit is parallel to the main body of the data line, not that the edges of the first power supply unit and the data line are necessarily parallel. The edges of the first power supply unit and the data line are allowed to be slightly uneven due to manufacturing errors. Within the connection area where the first power supply unit and the second power supply unit connect, this connection area may belong to either the first power supply unit or the second power supply unit.

[0153] In an exemplary embodiment, the first power supply unit SS1, the second power supply unit SS2, and the third power supply unit SS3 may be an integral structure.

[0154] like Figure 5As shown, the length of the first power supply section SS1 extending along the second direction is greater than the average width of the first power supply section SS1; the length of the second power supply section SS2 extending along the inclined direction is greater than the average width of the second power supply section SS2; and the length of the third power supply section SS3 extending along the second direction is greater than the average width of the third power supply section SS3. The inclined direction is the direction in which the second power supply section and the first power supply section have the aforementioned angle. The average width of the third power supply section SS3 is smaller than the average width of the first power supply section SS1. This is partly for the layout of the pixel structure, and partly because the third power supply section SS3 is closer to the data lines, the smaller average width of the third power supply section SS3 can reduce parasitic capacitance. In this disclosure, the width of the first power supply section SS1 and the third power supply section SS3 refers to the dimension of the first power supply section SS1 and the third power supply section SS3 in the first direction; the width of the second power supply section SS2 refers to the dimension perpendicular to the inclined direction; the average width refers to the average of the widths at multiple positions; and the first direction is the gate line extension direction.

[0155] In an exemplary embodiment, in the first direction, the distance between the center line of the first power supply section SS1 and the center line of the third power supply section SS3 is equivalent to the average width of the third power supply section SS3.

[0156] In an exemplary embodiment, the first power supply section SS1 in the sub-power line corresponding to the sub-pixel in the i-th row and j-th column is connected to the third power supply section SS3 in the sub-power line corresponding to the sub-pixel in the (i-1)-th row and j-th column, and the third power supply section SS3 in the sub-power line corresponding to the sub-pixel in the i-th row and j-th column is connected to the first power supply section SS1 in the sub-power line corresponding to the sub-pixel in the (i+1)-th row and j-th column. The interconnected power supply sections are arranged sequentially along the second direction (the data line extension direction).

[0157] like Figure 5 As shown, the power cord in this disclosure can be a zigzag shape.

[0158] In an exemplary embodiment, combined with Figure 5 The working process of each sub-pixel includes: in the reset phase, the reset signal line Reset located in the first metal layer and the initial signal line Vinit located in the second metal layer provide signals to initialize the driving circuit; in the write phase, the gate line G located in the first metal layer and the data line D located in the fourth metal layer provide signals to write the data signal provided by the data line D into the driving circuit; in the light emission phase, the light emission control line EM located in the first metal layer provides signals and the power line VDD provides power signals, so that the driving circuit provides driving current to the light emission device OLED to drive the light emission device to emit light.

[0159] In this configuration, pixels in the same row are displayed simultaneously, while pixels in adjacent rows are displayed sequentially.

[0160] In some possible implementations, such as Figure 2 As shown, the display substrate provided in this disclosure may further include: a first insulating layer 11, a second insulating layer 12, a third insulating layer 13, and a fourth insulating layer 14.

[0161] The first insulating layer 11 is disposed between the semiconductor layer 20 and the first metal layer 30, the second insulating layer 12 is disposed between the first metal layer 30 and the second metal layer 40, the third insulating layer 13 is disposed between the second metal layer 40 and the third metal layer 50, and the fourth insulating layer 14 is disposed between the third metal layer 50 and the fourth metal layer 60.

[0162] In some possible implementations, the materials of the first insulating layer 11, the second insulating layer 12, the third insulating layer 13 and the fourth insulating layer 14 may be silicon oxide, silicon nitride or a composite of silicon oxide and silicon nitride, and this disclosure does not limit them in any way.

[0163] In an exemplary embodiment, such as Figure 4A As shown, the multiple transistors for each sub-pixel may include: a first transistor to a seventh transistor, wherein the first electrode of the fifth transistor is connected to the power line VDD and the second electrode C2 of the storage capacitor, respectively.

[0164] In this disclosure, for each sub-pixel, the power line in each sub-pixel is connected to the second electrode of the storage capacitor through the first electrode of the fifth transistor.

[0165] The second electrode of the storage capacitor of the adjacent sub-pixel located in the second metal layer can be reused as a power signal line. This configuration ensures that the power signals provided by the power lines of the adjacent sub-pixels are the same, thereby avoiding display defects on the display substrate and ensuring the display effect of the display substrate.

[0166] In an exemplary embodiment, every four consecutive sub-pixels constitute a pixel. In the j-th pixel, the four consecutive sub-pixels along the first direction are the i-th sub-pixel, the (i+1)-th sub-pixel, the (i+2)-th sub-pixel, and the (i+3)-th sub-pixel, where i can take values ​​of 4j-3, and j is a positive integer.

[0167] In an exemplary embodiment, there are various ways to connect the second electrode of the storage capacitor of the multiple sub-pixels to the power supply line. One such embodiment is... Figure 6A This is a top view of a sub-pixel corresponding to Implementation Method 1. Figure 6B This is another top view of the sub-pixel corresponding to Implementation Method 1, wherein, as Figure 6A As shown, the fourth insulating layer has a first via V1 that exposes a portion of the first electrode 51 of the fifth transistor, and the power line is connected to the first electrode 51 of the fifth transistor through the first via V1. Figure 6BAs shown, the third insulating layer has a second via V2 that exposes a portion of the second electrode C2 of the storage capacitor. The first electrode 51 of the fifth transistor is connected to the second electrode C2 of the storage capacitor through the second via V2. It should be noted that... Figure 3 and Figure 5 The following explanation uses Implementation Method 1 as an example.

[0168] Specifically, the orthographic projection of the power line connected to the sub-pixel on the substrate includes the orthographic projection of the first via V1 on the substrate 10, and the orthographic projection of the second electrode of the storage capacitor on the substrate includes the orthographic projection of the second via on the substrate. In this paper, "the orthographic projection of A includes the orthographic projection of B" or "the orthographic projection of B is within the orthographic projection range of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0169] In some possible implementations, the number of first vias V1 can be one.

[0170] In some possible implementations, the number of second vias V2 can be at least one. Since the width of the first electrode of the fifth transistor is relatively narrow, when there are multiple second vias V2, the multiple second vias are arranged along the data line extension direction. The more vias there are, the better the conductivity of the components connected through the vias. Figure 6A It is a first via V1, Figure 6B This explanation uses two second vias V2 as an example, and this disclosure does not impose any limitations on them.

[0171] In an exemplary embodiment, such as Figure 6A As shown, the fourth insulating layer also includes a third via V3 that exposes the first electrode of the fourth transistor T4. The data line is connected to the first electrode of the fourth transistor T4 through the third via V3. The fourth insulating layer also includes a fourth via V4 that exposes the second electrode of the sixth transistor T6.

[0172] In an exemplary embodiment, such as Figure 6B As shown, the first insulating layer, the second insulating layer, and the third insulating layer further include vias that expose a portion of the active region, such that the source and drain electrodes of the transistor are connected to the active region through these vias, and the source and drain electrodes of the transistor include the first electrode and the second electrode of the transistor.

[0173] In an exemplary embodiment, the first electrode of the fifth transistor is also connected to the active region through vias on the first insulating layer, the second insulating layer, and the third insulating layer.

[0174] In an exemplary embodiment, each pixel may include four sub-pixels. Figure 7AThis is a top view of the second metal layer corresponding to Embodiment 1. Figure 7B This is a top view of the third metal layer corresponding to Embodiment 1. To more clearly illustrate the structure of the display substrate, Figure 7A and Figure 7B This explanation uses two pixels arranged along a column as an example.

[0175] like Figure 7A As shown, the second electrodes of the storage capacitors in adjacent sub-pixels located in the same row are directly connected, as... Figure 7B As shown, the first poles 51 of the fifth transistors of adjacent sub-pixels located in the same row are spaced apart.

[0176] In the first embodiment, by connecting the second electrodes of the storage capacitors disposed on the second metal layer by multiple sub-pixels, the power supply signals provided by the power lines of adjacent sub-pixels are the same, thereby avoiding display defects of the display substrate and ensuring the display effect of the display substrate.

[0177] In an exemplary embodiment, through a reasonable layout design, the interconnection of the conductive layers of multiple sub-pixels can be achieved solely through a semiconductor layer, or solely through a first metal layer, or solely through a second metal layer, or solely through a third metal layer. This enables the power lines of sub-pixels located in the same row to be interconnected via functional layers in the gate line extension direction, which will not be elaborated further here.

[0178] like Figure 7A As shown, at least one sub-pixel also includes a first connecting portion C3, which is disposed on one side of the second electrode C2 in the first direction.

[0179] In an exemplary embodiment, in two adjacent rows of pixels, the second electrode C2 of the i-th sub-pixel and the second electrode C2 of the (i+1)-th sub-pixel in one row are connected by a first connecting portion C3, the second electrode C2 of the (i+1)-th sub-pixel and the second electrode C2 of the (i+2)-th sub-pixel are directly connected, and the second electrode C2 of the (i+2)-th sub-pixel and the second electrode C2 of the (i+3)-th sub-pixel are connected by the first connecting portion C3. Similarly, in the other row of pixels, the second electrode C2 of the i-th sub-pixel and the second electrode C2 of the (i+1)-th sub-pixel are directly connected, the second electrode C2 of the (i+1)-th sub-pixel and the second electrode C2 of the (i+2)-th sub-pixel are connected by the first connecting portion C3, and the second electrode C2 of the (i+2)-th sub-pixel and the second electrode C2 of the (i+3)-th sub-pixel are directly connected.

[0180] As another implementation method Figure 8A This is a top view of the sub-pixel corresponding to Implementation Method 2. Figure 8BThis is another top view of the sub-pixel corresponding to Implementation Method 2. For example... Figure 8A As shown, the fourth insulating layer has a first via V1 that exposes a portion of the first electrode 51 of the fifth transistor T5, and the power line is connected to the first electrode 51 of the fifth transistor T5 through the first via V1. Figure 8B As shown, the third insulating layer is provided with a second via V2 that exposes part of the second electrode C2 of the storage capacitor, and the first electrode 51 of the fifth transistor T5 is connected to the second electrode C2 of the storage capacitor through the second via V2.

[0181] like Figure 8A and Figure 8B As shown, compared with Embodiment 1, Embodiment 2 has a different area occupied by the second electrode of the storage capacitor of each sub-pixel and a different shape of the first electrode 51 of the fifth transistor T5 of each sub-pixel.

[0182] In an exemplary embodiment, such as Figure 8A As shown, the fourth insulating layer also includes a third via V3 that exposes the first electrode of the fourth transistor T4. The data line is connected to the first electrode of the fourth transistor T4 through the third via V3. The fourth insulating layer also includes a fourth via V4 that exposes the second electrode of the sixth transistor T6.

[0183] like Figure 3 and 8B As shown, the first, second, and third insulating layers may further include vias exposing portions of the active region, such that the source and drain electrodes of the transistor are connected to the active region through these vias. The first electrode of the fifth transistor may also be connected to the active region through vias in the first, second, and third insulating layers.

[0184] The orthographic projection of the power line in the sub-pixel onto the substrate includes the orthographic projection of the first via V1 onto the substrate 10, and the orthographic projection of the second electrode of the storage capacitor onto the substrate includes the orthographic projection of the second via onto the substrate.

[0185] In some possible implementations, the number of first vias V1 can be one.

[0186] In some possible implementations, the number of second vias V2 is at least one. Since the width of the first electrode of the fifth transistor is relatively narrow, multiple second vias can be arranged along the data line extension direction to ensure a sufficient number of vias. The more vias there are, the better the conductivity of the components connected through the vias. Figure 8A It is a first via V1, Figure 8B This explanation uses two second vias V2 as an example, and this disclosure does not impose any limitations on them.

[0187] Figure 9AThis is a top view of the second metal layer corresponding to Embodiment 2. Figure 9B This is a top view of the third metal layer corresponding to Embodiment 2. Figure 10 This is another top view of a plurality of sub-pixels in a display substrate provided in this disclosure. To more clearly illustrate the structure of the display substrate, Figure 9A and Figure 9B This explanation uses two pixels arranged along a column as an example. Figure 10 Including other film layers besides the anode of the light-emitting device, Figure 10 The multiple sub-pixels included are the sub-pixels corresponding to Implementation Method 2.

[0188] like Figure 9A and Figure 9B As shown, in each pixel of one row of two adjacent rows of pixels, the second electrode of the storage capacitor of the i-th sub-pixel is connected to the second electrode of the storage capacitor of the (i+1)-th sub-pixel through the first connecting part C3, the second electrodes of the storage capacitor of the (i+1)-th sub-pixel and the second electrodes of the storage capacitor of the (i+2)-th sub-pixel are spaced apart, and the second electrodes of the storage capacitor of the (i+2)-th sub-pixel and the second electrodes of the storage capacitor of the (i+3)-th sub-pixel are connected through the first connecting part C3; in each pixel of the other row of two adjacent rows of pixels, the second electrode of the storage capacitor of the i-th sub-pixel is spaced apart, the second electrodes of the storage capacitor of the (i+1)-th sub-pixel and the second electrodes of the storage capacitor of the (i+2)-th sub-pixel are connected through the first connecting part C3, and the second electrodes of the storage capacitor of the (i+2)-th sub-pixel and the second electrodes of the storage capacitor of the (i+3)-th sub-pixel are spaced apart.

[0189] like Figure 8A As shown, the second electrode C2 storing the capacitor in at least one sub-pixel can be rectangular, and the first connecting part C3 can be strip-shaped. The first connecting part C3 is disposed on one side of the second electrode C2 in the first direction.

[0190] In an exemplary embodiment, in two adjacent rows of pixels, the second electrode C2 of the i-th sub-pixel and the second electrode C2 of the (i+1)-th sub-pixel in one row are interconnected via a first connecting portion C3, the second electrode C2 of the (i+1)-th sub-pixel and the second electrode C2 of the (i+2)-th sub-pixel are spaced apart, and the second electrode C2 of the (i+2)-th sub-pixel and the second electrode C2 of the (i+3)-th sub-pixel are interconnected via the first connecting portion C3. Similarly, in another row of pixels, the second electrode C2 of the i-th sub-pixel and the second electrode C2 of the (i+1)-th sub-pixel are spaced apart, the second electrode C2 of the (i+1)-th sub-pixel and the second electrode C2 of the (i+2)-th sub-pixel are interconnected via the first connecting portion C3, and the second electrode C2 of the (i+2)-th sub-pixel and the second electrode C2 of the (i+3)-th sub-pixel are spaced apart.

[0191] It should be noted that, Figure 9A The following example illustrates how the second electrode of the storage capacitor of the i-th sub-pixel in the first row of pixels is directly connected to the second electrode of the storage capacitor of the (i+1)-th sub-pixel through the first connecting part C3, and the second electrode of the storage capacitor of the (i+2)-th sub-pixel in the second row of pixels is directly connected to the second electrode of the storage capacitor of the (i+3)-th sub-pixel through the first connecting part C3.

[0192] In some possible implementations, such as Figure 10 As shown, for each sub-pixel, there is an overlap between the orthographic projection of the first pole of the fifth transistor on the substrate and the orthographic projection of the connected data line on the substrate.

[0193] In an exemplary embodiment, combined with Figure 9A , Figure 9B and Figure 10 For the j-th pixel, a second connection portion 56 may be included. When the second electrode C2 of the storage capacitor in the i-th sub-pixel is connected to the second electrode C2 of the storage capacitor in the (i+1)-th sub-pixel, the first electrode 51 of the fifth transistor T5 in the (i+1)-th sub-pixel is connected to the first electrode 51 of the fifth transistor T5 in the (i+2)-th sub-pixel via the second connection portion 56. The second electrode C2 of the storage capacitor in the i-th sub-pixel located in the second metal layer is connected to the second electrode C2 of the storage capacitor in the (i+3)-th sub-pixel located in the second metal layer via the first electrode 51 of the fifth transistor T5 in the (i+1)-th sub-pixel located in the third metal layer, the second connection portion 56, and the first electrode 51 of the fifth transistor T5 in the (i+2)-th sub-pixel.

[0194] In an exemplary embodiment, for the j-th pixel, when the second electrode C2 of the storage capacitor of the (i+1)-th sub-pixel is connected to the second electrode C2 of the storage capacitor of the (i+2)-th sub-pixel, the first electrode 51 of the fifth transistor T5 in the i-th sub-pixel is connected to the first electrode 51 of the fifth transistor T5 in the (i+1)-th sub-pixel through the second connection portion 56, and the first electrode 51 of the fifth transistor T5 in the (i+2)-th sub-pixel is connected to the first electrode 51 of the fifth transistor T5 in the (i+3)-th sub-pixel through the second connection portion 56. Specifically, the second electrode C2 of the storage capacitor of the i-th sub-pixel located in the second metal layer is connected to the second electrode C2 of the storage capacitor of the i+1 sub-pixel located in the second metal layer through the first electrode 51, the second connection portion 56 of the fifth transistor T5 in the i-th sub-pixel located in the third metal layer, and the first electrode 51 of the fifth transistor T5 in the (i+1)-th sub-pixel located in the (i+2)-th sub-pixel located in the second metal layer. The second electrode C2 of the storage capacitor of the i+2 sub-pixel located in the second metal layer is connected to the second electrode C2 of the storage capacitor of the i+3 sub-pixel located in the second metal layer through the first electrode 51, the second connection portion 56 of the fifth transistor T5 in the (i+2)-th sub-pixel located in the third metal layer, and the first electrode 51 of the fifth transistor T5 in the (i+3)-th sub-pixel located in the second metal layer.

[0195] In the second embodiment, the present disclosure uses the second metal layer and the third metal layer to complete the lateral (first direction) bridging, realizing the function of the power connection line, so that the power signal provided to each sub-pixel is the same, thus ensuring the display effect of the display substrate.

[0196] It should be noted that, since the resistivity of the third metal layer is less than that of the second metal layer, the display substrate provided in Embodiment 2 can further reduce dynamic crosstalk compared with the display substrate provided in Embodiment 1.

[0197] In some possible implementations, such as Figure 2 As shown, the display substrate provided in this disclosure may further include: a fifth insulating layer 15 and a planarization layer 16 disposed between the fourth metal layer 60 and the fifth metal layer 70, and an organic light-emitting layer and a cathode (not shown) of a light-emitting device disposed on the side of the fifth metal layer 70 away from the substrate 10. The fifth insulating layer 15 is disposed on the side of the planarization layer 16 close to the substrate 10; the cathode is disposed on the side of the organic light-emitting layer away from the substrate 10.

[0198] like Figure 3As shown, the fourth metal layer provided in this disclosure may further include a connection electrode 61, wherein the connection electrode 61 is connected to the fifth metal layer and the second electrode of the sixth transistor, respectively. The fifth insulating layer and the planarization layer are provided with a fifth via V5 exposing the connection electrode. The fifth metal layer is connected to the connection electrode 61 through the fifth via V5 exposing the connection electrode 61. The fourth insulating layer is provided with a fourth via V4 exposing the second electrode of the sixth transistor. The connection electrode 61 is connected to the second electrode of the sixth transistor through the fourth via V4 exposing the second electrode of the sixth transistor.

[0199] The exemplary embodiments of this disclosure reduce the area occupied by the data lines and power lines to the first and second electrodes of the plurality of transistors by displacing them in layers, thereby improving the resolution of the high-frequency driven OLED display substrate.

[0200] Based on the same inventive concept, this disclosure also provides a method for manufacturing a display substrate to produce the display substrate provided in the above embodiments. In an exemplary embodiment, in a plane parallel to the display substrate, the display substrate includes gate lines, data lines, power lines, and a plurality of sub-pixels disposed on a substrate. At least one sub-pixel includes a light-emitting device and a driving circuit configured to drive the light-emitting device to emit light. The driving circuit includes a plurality of transistors and a storage capacitor. The manufacturing method may include:

[0201] Provide a base;

[0202] Multiple functional layers are formed on the substrate; the multiple functional layers include a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer arranged sequentially; a first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer are respectively disposed between the multiple functional layers; in the gate line extension direction, the power lines are interconnected through at least one functional layer.

[0203] Figure 11 A flowchart of a method for manufacturing a display substrate provided in this disclosure is shown below. Figure 11 As shown, the method for manufacturing a display substrate provided in this disclosure may include the following steps:

[0204] Step B1: Provide a substrate.

[0205] Step B2: Sequentially form a semiconductor layer, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and a fifth metal layer that are mutually insulated from each other on the substrate.

[0206] In an exemplary embodiment, the semiconductor layer may include: active regions of multiple transistors; the first metal layer may include: gate lines, light-emitting control lines, reset signal lines, a first electrode of a storage capacitor, and gate electrodes of multiple transistors; the second metal layer may include: an initial signal line and a second electrode of the storage capacitor; the third metal layer may include: source and drain electrodes of multiple transistors; the fourth metal layer may include: data lines and power lines; and the fifth metal layer may include: the anode of a light-emitting device. The driving circuit of the i-th column of sub-pixels is connected to the i-th column of data lines. Each column of data lines includes: a first sub-data line and a second sub-data line; the first and second sub-data lines in the i-th column of data lines are located on both sides of the i-th column of sub-pixels, and all sub-data lines between two adjacent columns of sub-pixels are either the first or the second sub-data line.

[0207] Among them, 1 i N, where N is the total number of columns of sub-pixels.

[0208] The display substrate manufactured by the method disclosed herein has a similar implementation principle and effect, and will not be described in detail here.

[0209] In some possible implementations, step 200 may include: forming a semiconductor layer and a first insulating layer sequentially on a substrate; forming a first metal layer and a second insulating layer sequentially on the first insulating layer; forming a second metal layer and a third insulating layer sequentially on the second insulating layer; forming a third metal layer and a fourth insulating layer sequentially on the third insulating layer; forming a fourth metal layer, a fifth insulating layer and a planarization layer sequentially on the fourth insulating layer; and forming a fifth metal layer, an organic light-emitting layer of a light-emitting device and a cathode of a light-emitting device sequentially on the planarization layer.

[0210] Figure 12 This is a first schematic diagram illustrating the fabrication of a display substrate provided in this disclosure. Figure 13 This is a second schematic diagram illustrating the fabrication of a display substrate provided in this disclosure. Figure 14A This is a third manufacturing schematic diagram of a display substrate provided in this disclosure. Figure 14B This is another third schematic diagram of the fabrication of a display substrate provided in this disclosure. Figure 15A This is a fourth manufacturing schematic diagram of a display substrate provided in this disclosure. Figure 15B This is another fourth schematic diagram of the fabrication of a display substrate provided in this disclosure. Figure 16A This is a fifth schematic diagram illustrating the fabrication of a display substrate provided in this disclosure. Figure 16B This is another fifth schematic diagram of the fabrication of a display substrate provided in this disclosure.

[0211] The "patterning process" mentioned in this disclosure includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film of a certain material deposited on a substrate using deposition or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern."

[0212] Combination Figures 12-16B The manufacturing process of the display substrate provided in this disclosure may include the following operations.

[0213] Step 100: Provide a substrate 10, deposit a semiconductor thin film on the substrate 10, and process the semiconductor thin film using a patterning process to form a semiconductor layer 20, such as... Figure 12 As shown.

[0214] In an exemplary embodiment, the semiconductor layer 20 of each sub-pixel may include a first active region 101 at the location of the first transistor T1, a second active region 102 at the location of the second transistor T2, a third active region 103 at the location of the third transistor T3, a fourth active region 104 at the location of the fourth transistor T4, a fifth active region 105 at the location of the fifth transistor T5, a sixth active region 106 at the location of the sixth transistor T6, and a seventh active region 107 at the location of the seventh transistor T7, and the first active region 101 to the seventh active region 107 are an integral structure interconnected with each other.

[0215] In an exemplary embodiment, the first active region 101 and the seventh active region 107 are disposed on the side of the first region R1 away from the second region R2, the second active region 102 and the fourth active region 104 are disposed on the side of the first region R1 close to the second region R2, the third active region 103 is disposed in the second region R2, and the fifth active region 105 and the sixth active region 106 are disposed in the third region R3.

[0216] In an exemplary embodiment, the first active region 101 is connected to the second active region 102 and the seventh active region 107, the second active region 102 is connected to the third active region 103 and the sixth active region 106, and the fourth active region 104 is connected to the third active region 103 and the fifth active region 105.

[0217] In an exemplary embodiment, the first active region 101 is in an "n" shape, the seventh active region 107 is in an "L" shape, the seventh active region 107 is located on one side of the first active region 101 away from the sub-pixel center line, and the sub-pixel center line is a straight line that equally divides the sub-pixel in the first direction and extends in the second direction. The second active region 102 is in a "7" shape and is located on one side of the sub-pixel center line, and the fourth active region 104 is in a "1" shape and is located on the other side of the sub-pixel center line. The third active region 103 is in a "ji" shape, and the "ji" shape can be mirror-symmetrical with respect to the sub-pixel center line. The fifth active region 105 is in an "L" shape, and the shape of the sixth active region 106 is mirror-symmetrical with respect to the sub-pixel center line to the shape of the fifth active region 105. In this article, when the active region of a transistor is in a certain shape, it refers to the shape of the active region near the gate of the transistor, including but not limited to the channel region, source-drain region of the active region of the transistor, and the extended region of the part of the active region used for connecting to the source-drain regions of other transistors.

[0218] In an exemplary embodiment, the active region of each transistor includes a first region, a second region, and a channel region located between the first region and the second region. In an exemplary embodiment, the first region of the first active region 101 serves as the first region of the seventh active region 107 at the same time, and the second region of the first active region 101 serves as the first region of the second active region 102 at the same time. The second regions of the second active region 102, the third active region 103, and the first region of the sixth active region 106 are connected to each other, and the first region of the third active region 103, the second region of the fourth active region 104, and the second region of the fifth active region 105 are connected to each other. The first region of the fourth active region 14 is arranged on one side away from the third active region 103, and the first region of the fifth active region 105 is arranged on the other side away from the third active region 103. The second region of the sixth active region 106 serves as the second region of the seventh active region 107 at the same time.

[0219] In an exemplary embodiment, the distance in the first direction between the second active region 102 and the first active region 101 is less than the distance in the first direction between the second active region 102 and the seventh active region 107. The distance in the first direction between the second active region 102 and the third active region 103 is less than the distance in the first direction between the second active region 102 and the fourth active region 104, and the distance in the first direction between the second active region 102 and the third active region 103 is less than the distance in the first direction between the second active region 102 and the fifth active region 105; the distance in the first direction between the second active region 102 and the first active region 101 is comparable to the distance in the first direction between the second active region 102 and the third active region 103.

[0220] In an exemplary embodiment, the seventh active region 107 and the first active region 101 are arranged in sequence along the direction from the data line for writing data signals to the power supply line.

[0221] In an exemplary embodiment, the semiconductor layer 20 of the i-th row and j-th column sub-pixel has the same shape as the semiconductor layer 20 of the (i+1)-th row and j+1-th column sub-pixel, and the semiconductor layer 20 of the i-th row and j+1-th column sub-pixel has the same shape as the semiconductor layer 20 of the (i+1)-th row and j-th column sub-pixel. In a first direction, for the center line between adjacent sub-pixels, the semiconductor layers 20 of adjacent sub-pixels are mirror-symmetric about the center line, that is, in the first direction, the semiconductor layers of adjacent sub-pixels are symmetrical to each other. In this document, identical semiconductor layer shapes include, but are not limited to, identical overall shapes, identical connection relationships between individual parts, and identical signal flow trends.

[0222] In the exemplary embodiment, the schematic diagram of the active region fabrication in Embodiment 1 is the same as that in Embodiment 2.

[0223] The semiconductor layer layout of the exemplary embodiments disclosed herein is reasonable and the structure is simple, which can ensure the display effect of the display substrate.

[0224] Step 200: Sequentially deposit a first insulating film and a first metal film on the semiconductor layer 20. Process the first metal film using a patterning process to form a first insulating layer covering the semiconductor layer 20, and a first metal layer 30 disposed on the first insulating layer, as shown below. Figure 13 As shown.

[0225] In an exemplary embodiment, the first metal layer 30 may include: a gate line G, a reset signal line Reset, a light emission control line EM, and a first electrode C1 of a storage capacitor.

[0226] In an exemplary embodiment, the gate line G, the reset signal line Reset, and the light-emitting control line EM extend along a first direction. The gate line G and the reset signal line Reset are disposed in a first region R1, and the light-emitting control line EM is disposed in a third region R3. The first electrode C1 of the storage capacitor can be rectangular, and the corners of the rectangle can be chamfered. The first electrode C1 is disposed in a second region R2, located between the gate line G and the light-emitting control line EM. The orthographic projection of the first electrode C1 on the substrate overlaps with the orthographic projection of the third active region on the substrate. In an exemplary embodiment, the first electrode C1 also serves as the gate electrode of the third transistor.

[0227] In an exemplary embodiment, the reset signal line Reset of the first region R1 can be configured with a non-uniform width, and the width of the reset signal line Reset is the dimension of the reset signal line Reset in the second direction. The reset signal line Reset includes a region that overlaps with the semiconductor layer 20 and a region that does not overlap with the semiconductor layer 20. The width of the reset signal line Reset in the region that overlaps with the semiconductor layer 20 can be greater than the width of the reset signal line Reset in the region that does not overlap with the semiconductor layer 20.

[0228] In an exemplary embodiment, the gate line G of the first region R1 can be configured with non-uniform width, and the width of the gate line G is the dimension of the gate line G in the second direction. The gate line G has regions that overlap with the semiconductor layer 20 and regions that do not overlap with the semiconductor layer 20. The width of the gate line G in the regions that overlap with the semiconductor layer 20 can be greater than the width of the gate line G in the regions that do not overlap with the semiconductor layer 20.

[0229] In an exemplary embodiment, the light-emitting control line EM of the third region R3 can be configured with a non-uniform width, and the width of the light-emitting control line EM is the dimension of the light-emitting control line EM in the second direction. The light-emitting control line EM includes a region that overlaps with the semiconductor layer 20 and a region that does not overlap with the semiconductor layer 20. The width of the light-emitting control line EM in the region that overlaps with the semiconductor layer 20 can be greater than the width of the light-emitting control line EM in the region that does not overlap with the semiconductor layer 20.

[0230] In an exemplary embodiment, the gate line G in the i-th row may include a first gate line segment extending from the j-th column sub-pixel along a first direction to the (j+1)-th column sub-pixel. The first end of the first gate line segment is connected to the gate line G via a connecting strip located in the j-th column sub-pixel of the i-th row, and the second end of the first gate line segment is also connected to the gate line G via a connecting strip located in the (j+1)-th column sub-pixel of the i-th row, thus forming a double-gate structure simultaneously within both the j-th column sub-pixel and the (j+1)-th column sub-pixel of the i-th row. The gate line G in the (i+1)-th row may include a second gate line segment extending from the (j+1)-th column sub-pixel along a first direction to the (j+2)-th column sub-pixel. The first end of the second gate line segment is connected to the gate line G via a connecting strip located in the (j+1)-th column sub-pixel of the i+1-th row, and the second end of the second gate line segment is also connected to the gate line G via a connecting strip located in the (j+2)-th column sub-pixel of the i+1-th row, thus forming a double-gate structure simultaneously within both the j-th column sub-pixel and the (j+2)-th column sub-pixel of the i+1-th row. In this way, the second transistor T2 of the dual-gate structure is formed simultaneously in the j-th column sub-pixel and the (j+1)-th column sub-pixel, and the second transistor T2 of the j-th column sub-pixel and the second transistor T2 of the (j+1)-th column sub-pixel form the dual-gate region 110.

[0231] In an exemplary embodiment, the region where the first electrode C1 overlaps with the third active region serves as the third gate electrode (dual-gate structure), the region where the gate line G overlaps with the second active region serves as the second gate electrode (dual-gate structure), the region where the reset signal line Reset overlaps with the first active region serves as the first gate electrode (dual-gate structure), the region where the gate line G overlaps with the fourth active region serves as the fourth gate electrode, the region where the reset signal line Reset overlaps with the seventh active region serves as the seventh gate electrode, the region where the light emission control line EM overlaps with the fifth active region serves as the fifth gate electrode, and the region where the light emission control line EM overlaps with the sixth active region serves as the sixth gate electrode.

[0232] In an exemplary embodiment, since the first transistor T1, the second transistor T2, and the third transistor T3 are all dual-gate transistors, the distance in the first direction between the dual-gate second transistor T2 and the other dual-gate transistors (the first transistor T1 and the third transistor T3) is less than the distance in the first direction between the second transistor T2 and the single-gate fourth transistor T4, the fifth transistor T5, and the seventh transistor T7.

[0233] In an exemplary embodiment, after the pattern of the first metal layer 30 is formed, the first metal layer 30 can be used as a shield to conduct the semiconductor layer. The semiconductor layer in the region shielded by the first metal layer 30 forms the channel region of the first transistor T1 to the seventh transistor T7, and the semiconductor layer in the region not shielded by the first metal layer 30 is conducted, that is, the first region and the second region of the first transistor T1 to the seventh transistor T7 are conducted.

[0234] In an exemplary embodiment, the schematic diagram of the fabrication of the first metal layer in Embodiment 1 is the same as that in Embodiment 2.

[0235] The first metal layer of the exemplary embodiments disclosed herein has a reasonable layout and a simple structure, which can ensure the display effect of the display substrate.

[0236] Step 300: A second insulating film and a second metal film are sequentially deposited on the first metal layer 30. A patterning process is used to process the second metal film to form a second insulating layer covering the first metal layer 30, and a second metal layer 40 disposed on the second insulating layer. The second metal layer 40 includes at least the initial signal line Vinit and the second electrode C2 of the storage capacitor. Subsequently, a third insulating film is deposited on the second metal layer 40. A patterning process is used to process the third insulating film to form a third insulating layer covering the second metal layer 40. Multiple vias are provided on the third insulating layer, such as... Figure 14A and 14B As shown.

[0237] In an exemplary embodiment, the plurality of vias on the third insulating layer includes at least: a second via V2 exposing the second electrode C2, a sixth via V6 exposing the initial signal line Vinit, a seventh via V7 exposing the first electrode C1, an eighth via V8 exposing the fourth active region, a ninth via V9 exposing the second active region, a tenth via V10 exposing the first active region, and a plurality of vias exposing other active regions in the semiconductor layer. The third insulating layer in the second via V2 exposing the second electrode C2 and the sixth via V6 exposing the initial signal line Vinit is etched away; the second and third insulating layers in the seventh via V7 exposing the first electrode C1 are etched away; and the first, second, and third insulating layers in the eighth via V8 exposing the fourth active region, the ninth via V9 exposing the second active region, the tenth via V10 exposing the first active region, and the vias exposing other active regions in the semiconductor layer are etched away.

[0238] In an exemplary embodiment, the second via V2 is configured to connect the second electrode C2 to the first electrode of the subsequently formed fifth transistor T5; the sixth via V6 is configured to connect the initial signal line Vinit to the first electrode of the subsequently formed first transistor T1; the seventh via V7 is configured to connect the first electrode C1 to the first electrode of the subsequently formed second transistor T2; the eighth via V8 is configured to connect the active layer of the fourth transistor T4 to the first electrode of the subsequently formed fourth transistor T4; the ninth via V9 is configured to connect the active layer of the second transistor T2 to the first electrode of the subsequently formed second transistor T2; and the tenth via V10 is configured to connect the active layer of the first transistor T1 to the first electrode of the subsequently formed first transistor T1. Since the first electrode of the subsequently formed fourth transistor T4 is connected to the subsequently formed data line D, the eighth via V8 is a data write via.

[0239] In an exemplary embodiment, the distance in the first direction between the data writing hole and the second transistor T2 is greater than the distance in the first direction between the data writing hole and the first transistor T1, and the distance in the first direction between the data writing hole and the seventh transistor T7. The distance in the second direction between the data writing hole and the third transistor T3 is less than the distance in the second direction between the data writing hole and the fifth transistor T5, and the distance in the second direction between the data writing hole and the sixth transistor T6.

[0240] In an exemplary embodiment, there can be two second vias V2, which are sequentially arranged along the second direction. Since the width of the fifth first electrode is relatively narrow, providing two second vias V2 can improve the reliability of the connection between the second electrode and the fifth first electrode.

[0241] In an exemplary embodiment, the initial signal line Vinit extends along a first direction and is disposed in the first region R1, located on the side of the reset signal line Reset away from the second region R2. The outline of the second electrode C2 storing the capacitor in each sub-pixel can be rectangular, disposed in the second region R2, located between the gate line G and the light-emitting control line EM.

[0242] In an exemplary embodiment, the outline of the second electrode C2 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second electrode C2 onto the substrate overlaps with the orthographic projection of the first electrode C1 onto the substrate. An opening 111 is provided in the middle of the second electrode C2. The opening 111 can be rectangular, forming a ring structure for the second electrode C2. The opening 111 exposes a second insulating layer covering the first electrode C1, and the orthographic projection of the first electrode C1 onto the substrate includes the orthographic projection of the opening 111 onto the substrate. In an exemplary embodiment, the orthographic projection of the opening 111 onto the substrate includes the orthographic projection of the seventh via V7 exposing the first electrode C1 onto the substrate.

[0243] The orthographic projection of the edge of the second electrode C2 near the first region R1 on the substrate overlaps with the orthographic projection of the boundary line between the first region R1 and the second region R2 on the substrate. The orthographic projection of the edge of the second electrode C2 near the third region R3 on the substrate overlaps with the orthographic projection of the boundary line between the second region R2 and the third region R3 on the substrate. That is, the second length of the second electrode C2 is equal to the second length of the second region R2. The second length refers to the dimension in the second direction.

[0244] In Embodiment 1, the second electrodes C2 of adjacent sub-pixels in a row are an integral structure that is interconnected. This structure allows the second electrodes C2 of adjacent sub-pixels to be reused as power signal lines, ensuring that the power signals provided by the power lines of adjacent sub-pixels are the same, avoiding display defects on the display substrate, and guaranteeing the display effect of the display substrate.

[0245] In Embodiment 2, the second electrode C2 of the i-th row and j-th column sub-pixel and the second electrode C2 of the i-th row and (j+1)-th column sub-pixel are an integral structure connected to each other via a first connecting portion. The second electrode C2 of the i-th row and (j+1)-th column sub-pixel and the second electrode C2 of the i-th row and (j+2)-th column sub-pixel are disconnected. The second electrode C2 of the i-th row and (j+2)-th column sub-pixel and the second electrode C2 of the i-th row and (j+3)-th column sub-pixel are an integral structure connected to each other via a first connecting portion. Alternatively, the second electrode C2 of the i+1-th row and j-th column sub-pixel and the second electrode C2 of the i+1-th row and (j+1)-th column sub-pixel are disconnected. The second electrode C2 of the i+1-th row and (j+2)-th column sub-pixel and the second electrode C2 of the i+1-th row and (j+3)-th column sub-pixel are an integral structure connected to each other via a first connecting portion. This structure allows the second electrode C2 of adjacent sub-pixels to be reused as a power signal line, ensuring that the power signals provided by the power lines of adjacent sub-pixels are the same, avoiding display defects on the display substrate and ensuring the display effect of the display substrate.

[0246] Figure 14A This is a schematic diagram illustrating the manufacturing process of Implementation Method 1. Figure 14B This is a schematic diagram illustrating the manufacturing process of Implementation Method 2.

[0247] The second metal layer and vias of the exemplary embodiments disclosed herein are reasonably arranged and have a simple structure, which can ensure the display effect of the display substrate.

[0248] Step 400: Deposit a third metal thin film on the third insulating layer, and process the third metal thin film through a patterning process to form a third metal layer 50. The third metal layer 50 includes at least the first electrode 51 of the fifth transistor T5, the second electrode 52 of the sixth transistor T6, the first electrode 53 of the fourth transistor T4, the first electrode 54 of the first transistor T1, and the first electrode 55 of the second transistor T2. The first electrode 51 of the fifth transistor T5 is connected to the second electrode C2 through the second via V2. The second electrode 52 of the sixth transistor T6 is connected to the active layer of the sixth transistor through a via. The first electrode 53 of the fourth transistor T4 is connected to the active layer of the fourth transistor T4 through the eighth via V8. One end of the first electrode 54 of the first transistor T1 is connected to the initial signal line Vinit through the sixth via V6, and the other end is connected to the active layer of the first transistor T1 through the tenth via V10. One end of the first electrode 55 of the second transistor T2 is connected to the first electrode C1 through the seventh via V7, and the other end is connected to the active layer of the second transistor T2 through the ninth via V9. Subsequently, a fourth insulating film is deposited on the third metal layer 50. The fourth insulating film is then processed using a patterning process to form a fourth insulating layer covering the third metal layer 50. Multiple vias are provided on the fourth insulating layer, such as... Figure 15A and Figure 15B As shown.

[0249] In an exemplary embodiment, the plurality of vias on the fourth insulating layer include at least: a first via V1 exposing the first electrode 51 of the fifth transistor T5, a fourth via V4 exposing the second electrode 52 of the sixth transistor T6, and a third via V3 exposing the first electrode 53 of the fourth transistor T4. The first via V1 exposing the first electrode 51 of the fifth transistor T5 is configured to connect the first electrode 51 of the fifth transistor T5 to a subsequently formed power line VDD, the fourth via V4 exposing the second electrode 52 of the sixth transistor T6 is configured to connect the second electrode 52 of the sixth transistor T6 to a subsequently formed connection electrode, and the third via V3 exposing the first electrode 53 of the fourth transistor T4 is configured to connect the first electrode 53 of the fourth transistor T4 to a subsequently formed data line D.

[0250] In an exemplary embodiment, the orthographic projection of the first via V1 on the substrate overlaps with the orthographic projection of the gate line G on the substrate.

[0251] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate overlaps with the orthographic projection of the second electrode C2 onto the substrate.

[0252] In an exemplary embodiment, the orthographic projection of the third via V3 on the substrate overlaps with the orthographic projection of the gate line G on the substrate.

[0253] In an exemplary embodiment, the orthographic projection of the fourth via V4 onto the substrate overlaps with the orthographic projection of the light-emitting control line EM onto the substrate.

[0254] In Implementation Method 1, the first poles 51 of the fifth transistors T5 of adjacent sub-pixels located in the same row are spaced apart.

[0255] In the second embodiment, the first electrode 51 of the fifth transistor T5 in the i-th row and j+1-th column sub-pixel is connected to the first electrode 51 of the fifth transistor T5 in the i-th row and j+2-th column sub-pixel through the second connecting part, the first electrode 51 of the fifth transistor T5 in the i+1-th row and j-th column sub-pixel is connected to the first electrode 51 of the fifth transistor T5 in the i-th row and j+1-th column sub-pixel through the second connecting part, and the first electrode 51 of the fifth transistor T5 in the i+1-th row and j+2-th column sub-pixel is connected to the first electrode 51 of the fifth transistor T5 in the i-th row and j+3-th column sub-pixel through the second connecting part.

[0256] Figure 15A This is a schematic diagram illustrating the manufacturing process of Implementation Method 1. Figure 15B This is a schematic diagram illustrating the manufacturing process of Implementation Method 2.

[0257] The third metal layer and vias of the exemplary embodiments disclosed herein are rationally arranged and have a simple structure, which can ensure the display effect of the display substrate.

[0258] Step 500: Deposit a fourth metal thin film on the fourth insulating layer. Process the fourth metal thin film using a patterning process to form a fourth metal layer 60 including a first sub-data line DO, a second sub-data line DE, a power line VDD, and a connecting electrode 61. The first sub-data line DO and the second sub-data line DE are connected to the first electrode 53 of the fourth transistor T4 through a third via V3 exposing the first electrode 53 of the fourth transistor T4 in their respective sub-pixels. The power line VDD is connected to the first electrode 51 of the fifth transistor T5 through a first via V1 exposing the first electrode 51 of the fifth transistor T5. The connecting electrode 61 is connected to the second electrode 52 of the sixth transistor T6 through a fourth via V4 exposing the second electrode 52 of the sixth transistor T6. Subsequently, deposit a fifth insulating film on the fourth metal layer 60. Coat a planarization film on the fifth insulating film. Process the planarization film and the fifth insulating film using a patterning process to form a fifth insulating layer covering the fourth metal layer 60 and a planarization layer disposed on the fifth insulating layer. The planarization layer is provided with multiple vias, such as... Figure 16A and 16B As shown.

[0259] In an exemplary embodiment, a first sub-data line DO, a second sub-data line DE, and a power line VDD extend along a second direction. The first sub-data line DO is located on one side of a sub-pixel, the second sub-data line DE is located on the other side of the sub-pixel, and the power line VDD is located between the first sub-data line DO and the second sub-data line DE.

[0260] In an exemplary embodiment, the first sub-data line DO and the second sub-data line DE can be straight lines of equal width, and the width of the first sub-data line DO and the second sub-data line DE is the dimension of the first sub-data line DO and the second sub-data line DE in a first direction.

[0261] In an exemplary embodiment, the first terminals of the fourth transistors of adjacent sub-pixels located in the same column are connected to different sub-data lines. For example, the sub-pixel in the i-th row and j-th column is connected to the first sub-data line in the j-th column, and the sub-pixel in the (i+1)-th row and j-th column is connected to the second sub-data line in the j-th column. Alternatively, the sub-pixel in the i-th row and j-th column is connected to the second sub-data line in the j-th column, and the sub-pixel in the (i+1)-th row and j-th column is connected to the first sub-data line in the j-th column.

[0262] In an exemplary embodiment, in at least one sub-pixel, the first sub-data line DO is connected to the first electrode 53 of the fourth transistor T4 through the third via V3 in the sub-pixel. The first electrode 53 of the fourth transistor T4 is connected to the fourth active region through the eighth via V8, which is a data write hole. The first sub-data line DO is the data line with the write data line number of that sub-pixel. In at least one sub-pixel, the second sub-data line DE is connected to the first electrode 53 of the fourth transistor T4 through the third via V3 in the sub-pixel. The first electrode 53 of the fourth transistor T4 is connected to the fourth active region through the eighth via V8, which is a data write hole. The second sub-data line DE is the data line with the write data line number of that sub-pixel.

[0263] In an exemplary embodiment, the power line VDD of each sub-pixel is connected to the first electrode 51 of the fifth transistor T5 through the first via V1. Since the first electrode 51 of the fifth transistor T5 is connected to the second electrode C2 of the storage capacitor, the second electrodes C2 of the storage capacitors of adjacent sub-pixels are connected to each other. Thus, not only is the power line VDD connected to the second electrode C2, but the power connection line function of the second electrode C2 is also realized, so that the power signal provided to each sub-pixel is the same, ensuring the display effect of the display substrate.

[0264] In an exemplary embodiment, the power line VDD of each sub-pixel can be a broken line. Along the second direction, the power line VDD of each sub-pixel can include a first power section, a second power section, and a third power section connected in sequence. In the power line corresponding to the sub-pixel in the i-th row and j-th column, the first end of the first power section is connected to the second end of the third power section in the sub-pixel located in the (i-1)-th row and j-th column. The second end of the first power section extends along the second direction and is connected to the first end of the second power section. The second end of the second power section extends along an inclined direction and is connected to the first end of the third power section. The inclined direction has an angle with the second direction, and the angle can be greater than 0 degrees and less than 90 degrees. The second end of the third power section extends along the second direction and is connected to the first end of the first power section in the sub-pixel located in the (i+1)-th row and j-th column.

[0265] In an exemplary embodiment, the first power supply section can be a straight line of equal width, the second power supply section can be a diagonal line of equal width, and the third power supply section can be a straight line of equal width. The first power supply section and the second power supply section are parallel to the first sub-data line (or the second sub-data line), the angle between the second power supply section and the first power supply section can be greater than 90 degrees and less than 180 degrees, and the angle between the second power supply section and the third power supply section can be greater than 90 degrees and less than 180 degrees.

[0266] In an exemplary embodiment, the length of the first power supply unit extending along the first direction is greater than the average width of the first power supply unit, the length of the second power supply unit extending along the inclined direction is greater than the average width of the second power supply unit, and the length of the third power supply unit extending along the first direction is greater than the average width of the third power supply unit. The inclined direction is the direction in which the second power supply unit and the first power supply unit have an angle.

[0267] In an exemplary embodiment, the average width of the third power supply section can be smaller than the average width of the first power supply section, and the average width of the third power supply section can be smaller than the average width of the second power supply section. The power line VDD is configured with a variable-width polygonal line, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the power line VDD and the data line. Since the third power supply section is relatively close to the data line, reducing the average width of the third power supply section can reduce the parasitic capacitance between the third power supply section and the data line.

[0268] In an exemplary embodiment, the average width of the first power supply section may be greater than or equal to the average width of the second power supply section, or the average width of the first power supply section may be less than the average width of the second power supply section.

[0269] In an exemplary embodiment, the length of the second power supply portion extending in the direction of extension is equivalent to the second length of the first electrode C1, and the second length of the first electrode C1 is its dimension in the second direction. The length of the first power supply portion extending in the direction of extension is equivalent to the second length of the second electrode C2, and the length of the third power supply portion extending in the direction of extension is equivalent to the second length of the second electrode C2, and the second length of the second electrode C2 is its dimension in the second direction.

[0270] like Figure 3 , Figure 16A and 16B As shown, in an exemplary embodiment, the orthographic projection of the first power supply unit on the substrate overlaps with the orthographic projections of the first electrode 55 and the ninth via V9 of the second transistor T2 on the substrate. Therefore, the orthographic projection of the first power supply unit on the substrate overlaps with the orthographic projection of the second transistor T2 on the substrate. The orthographic projection of the second power supply unit on the substrate overlaps with the orthographic projection of the first via V1 on the substrate. The orthographic projection of the third power supply unit on the substrate overlaps with the orthographic projection of the first electrode 51 of the fifth transistor T5 on the substrate. Therefore, the orthographic projections of both the second and third power supplies on the substrate overlap with the first electrode 51 of the fifth transistor T5.

[0271] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate overlaps with the orthographic projection of the extension line of the first power supply portion in the second direction onto the substrate, and the orthographic projection of the first via V1 onto the substrate overlaps with the orthographic projection of the extension line of the third power supply portion in the second direction onto the substrate. Therefore, in the first direction, the distance between the first power supply portion and the third power supply portion is less than the first length of the first via V1 or the average width of the third power supply portion. That is, the distance between the edge of the first power supply portion near the third power supply portion and the edge of the third power supply portion near the first power supply portion is less than the first length of the first via V1 or the width of the third power supply portion. The first length of the first via V1 refers to its dimension in the first direction. Therefore, for the second power supply portion extending along the inclined direction, it can be understood that the second power supply portion bends the power line VDD. In the first direction, the degree of bend is equivalent to the first length of the first via V1 or the width of the third power supply portion; in the second direction, the degree of bend is equivalent to the second length of the first electrode C1. In this document, the edges of the two power supply portions refer to the edges of the overall outline of the two power supply portions.

[0272] In an exemplary embodiment, there is an overlap between the orthographic projection of the second power supply unit on the substrate and the orthographic projection of the second electrode on the substrate.

[0273] In an exemplary embodiment, the orthographic projection of the second power supply unit on the substrate overlaps with the orthographic projection of the first connection unit on the substrate.

[0274] In an exemplary embodiment, the orthographic projection of the second power supply unit on the substrate overlaps with the orthographic projection of the first electrode C1 on the substrate.

[0275] In an exemplary embodiment, the orthographic projection of the second power supply unit on the substrate overlaps with the orthographic projection of the gate line G on the substrate, that is, the orthographic projection of the second power supply unit on the substrate overlaps with the orthographic projections of the gate electrode of the second transistor T2 and the gate electrode of the fourth transistor T4 on the substrate.

[0276] In an exemplary embodiment, the connecting electrode 61 is a strip shape extending along the second direction, the extending direction of the connecting electrode 61 is parallel to the extending direction of the third power supply portion, and the length of the connecting electrode 61 in the second direction is equivalent to the length of the third power supply portion in the second direction.

[0277] In an exemplary embodiment, there is an overlap between the orthographic projection of the connecting electrode 61 on the substrate and the orthographic projection of the second electrode C2 on the substrate.

[0278] In an exemplary embodiment, there is an overlap between the orthographic projection of the connecting electrode 61 on the substrate and the orthographic projection of the opening 111 in the middle of the second electrode C2 on the substrate.

[0279] In an exemplary embodiment, there is an overlap between the orthographic projection of the connecting electrode 61 on the substrate and the orthographic projection of the second first electrode 55 on the substrate.

[0280] In an exemplary embodiment, the extending direction of the connecting electrode 61 overlaps with the extending direction of the first power supply portion, that is, there is an overlapping area between the orthographic projection of the connecting electrode 61 on the substrate and the orthographic projection of the virtual extension line of the second direction of the first power supply portion on the substrate.

[0281] In an exemplary embodiment, the eighth via V8 (i.e., the data writing hole) is located on the virtual extension line of the second direction of the third power supply section, that is, there is an overlapping area between the orthographic projection of the eighth via V8 on the substrate and the orthographic projection of the virtual extension line of the second direction of the third power supply section on the substrate.

[0282] In an exemplary embodiment, since the power line VDD of each sub-pixel is connected to the first electrode 51 of the fifth transistor T5 through the first via V1, and the first electrode 51 of the fifth transistor T5 is connected to the second electrode C2 of the storage capacitor through the second via V2, thereby connecting the power line VDD to the second electrode C2 of the storage capacitor, the first via V1 is called the power write hole.

[0283] In an exemplary embodiment, the orthographic projection of the power write hole onto the substrate lies within the orthographic projection range of the second power supply unit onto the substrate. The distance in the first direction between the power write hole and the fourth transistor T4 is comparable to the distance in the first direction between the power write hole and the second transistor T2. The distance in the second direction between the power write hole and the second transistor T2 is smaller than the distance in the second direction between the power write hole and the first transistor T1, the distance in the second direction between the power write hole and the seventh transistor T7, and the distance in the second direction between the power write hole and the third transistor T3, respectively. The distance in the second direction between the power write hole and the fifth transistor T5, and the distance in the second direction between the power write hole and the sixth transistor T6 are also smaller than these distances.

[0284] In an exemplary embodiment, the plurality of vias on the fifth insulating layer and the planarization layer include at least a fifth via V5 exposing the connection electrode 61, the fifth via V5 being configured to connect the connection electrode 61 to a subsequently formed fifth metal layer (anode). Due to the connection between the connection electrode 61 and the sixth second electrode 52, a connection is achieved between the sixth second electrode 52 and the fifth metal layer, enabling the driving circuit to drive the light-emitting device to emit light.

[0285] In an exemplary embodiment, the connection electrode 61 is connected to the second electrode 52 of the sixth transistor T6 via a fourth via V4, which is located at the end of the connection electrode 61 furthest from the second power supply portion. The connection electrode 61 is connected to the subsequently formed anode via a fifth via V5, which is located at the end of the connection electrode 61 closest to the second power supply portion. The orthographic projection of the fifth via V5 onto the substrate overlaps with the orthographic projection of the second electrode C2 of the storage capacitor onto the substrate.

[0286] In an exemplary embodiment, the fifth via V5 is located on the virtual extension line of the second direction of the first power supply section, that is, the orthographic projection of the fifth via V5 on the substrate and the orthographic projection of the virtual extension line of the second direction of the first power supply section on the substrate have an overlapping area.

[0287] Figure 16A This is a schematic diagram illustrating the manufacturing process of Implementation Method 1. Figure 16B This is a schematic diagram illustrating the manufacturing process of Implementation Method 2.

[0288] The fourth metal layer and vias of the exemplary embodiments disclosed herein are rationally arranged and have a simple structure, which can ensure the display effect of the display substrate.

[0289] Step 600: A fifth metal thin film is deposited on the planarization layer. The fifth metal thin film is processed using a patterning process to form a fifth metal layer 70. The fifth metal layer 70 includes at least an anode, which is connected to the connection electrode 61 through a fifth via exposing the connection electrode 61. Since the anode is connected to the connection electrode 61, and the connection electrode 61 is connected to the second electrode 52 of the sixth transistor T6, the connection between the second electrode 52 of the sixth transistor T6 and the anode is achieved, and the sixth transistor can drive the light-emitting device to emit light. Subsequently, a pixel definition film is coated on the fifth metal layer. The pixel definition film is processed using a patterning process to form a pixel definition layer. Each sub-pixel's pixel definition layer has a pixel opening that exposes the anode. Subsequently, an organic light-emitting layer is formed using a vapor deposition process, and a cathode is formed on the organic light-emitting layer.

[0290] The structure and fabrication process shown in this disclosure are merely illustrative examples. In the exemplary embodiments, the corresponding structure and the patterning process can be modified and increased or decreased according to actual needs. For example, the power line VDD and the first or second terminal of some transistors can be located on the third metal layer 50, and the data line D and the first or second terminal of some transistors can be located on the fourth metal layer 60. Alternatively, the data line D and the first or second terminal of some transistors can be located on the third metal layer 50, and the power line VDD and the first or second terminal of some transistors can be located on the fourth metal layer 60. Yet another example is that the power line VDD and the data line D can be located on the third metal layer 50, and the first and second terminals of the first to seventh transistors can be located on the fourth metal layer 60. This disclosure does not impose any limitations on these aspects.

[0291] Figure 17 This is a top view of a plurality of sub-pixels in another display substrate provided in this disclosure. Figure 18 This is a cross-sectional view of multiple sub-pixels in another display substrate provided in this disclosure. Figure 17 Let's illustrate this using an example with 8 sub-pixels (the first four columns and the first two rows of sub-pixels). Figure 1 , Figure 17 and Figure 18 As shown, the display substrate provided in this disclosure includes: a substrate 10 and a plurality of sub-pixels P disposed on the substrate 10, a plurality of power lines VDD and a data line D disposed on the same layer as the power lines VDD. Each sub-pixel P includes a driving circuit. The driving circuit may include a plurality of transistors and a storage capacitor. The storage capacitor includes a first electrode C1 and a second electrode C2 disposed opposite to each other. The active region 21 of the transistor is located on the side of the second electrode C2 of the storage capacitor closer to the substrate 10, and the power line VDD is located on the side of the second electrode C2 of the storage capacitor away from the substrate 10.

[0292] In an exemplary embodiment, at least one sub-pixel has its power line VDD connected to the second electrode C2 of a storage capacitor and the third connection portion of a semiconductor layer, respectively. The second electrode C2 of the storage capacitor of each sub-pixel is connected to the second electrode C2 of the storage capacitor of an adjacent sub-pixel located in the same row. The semiconductor layer of each sub-pixel is interconnected with the semiconductor layer of another adjacent sub-pixel located in the same row through the third connection portion.

[0293] In some possible implementations, such as Figure 17 As shown, the driving circuit of the i-th column sub-pixel is connected to the i-th column data line and the i-th column power line, 1 i N. Each column of data lines includes: a first sub-data line and a second sub-data line. The first sub-data line DOi and the second sub-data line DEi in the i-th column of data lines Di are located on both sides of the i-th column of sub-pixels, respectively. The i-th column of power lines VDDi is located between the first sub-data line DOi and the second sub-data line DEi in the i-th column of data lines Di.

[0294] In some possible implementations, adjacent sub-pixels in the same column are connected to different sub-data lines. That is, if the sub-pixel in the i-th row and j-th column is connected to the first sub-data line DOj in the j-th column, then the sub-pixel in the (i+1)-th row and j-th column is connected to the second sub-data line DEj in the j-th column. If the sub-pixel in the i-th row and j-th column is connected to the second sub-data line DEj in the j-th column, then the sub-pixel in the (i+1)-th row and j-th column is connected to the first sub-data line DOj in the j-th column.

[0295] In some possible implementations, the arrangement of the first and second sub-data lines in adjacent data lines is reversed. That is, when the first sub-data line DOi of the i-th column data line Di is located on the first side of the i-th column sub-pixel and the second sub-data line DEi of the i-th column data line Di is located on the second side of the i-th column sub-pixel, the second sub-data line DEi+1 of the (i+1)-th column data line Di+1 is located on the first side of the (i+1)-th column sub-pixel, and the first sub-data line DOi+1 of the (i+1)-th column data line Di+1 is located on the second side of the (i+1)-th column sub-pixel; or when the first sub-data line DOi of the i-th column data line Di is located on the second side of the i-th column sub-pixel and the second sub-data line DEi of the i-th column data line Di is located on the first side of the i-th column sub-pixel, the second sub-data line DEi+1 of the (i+1)-th column data line Di+1 is located on the second side of the (i+1)-th column sub-pixel, and the first sub-data line DOi+1 of the (i+1)-th column data line Di+1 is located on the first side of the (i+1)-th column sub-pixel.

[0296] like Figure 17 and Figure 18 As shown, in an exemplary embodiment, the display substrate may include: a first insulating layer 11, a second insulating layer 12, and a third insulating layer 13 sequentially disposed on a substrate 10; a gate line G; a reset signal line Reset; a light emission control signal line EM; and an initial signal line Vinit. The gate line G, the reset signal line Reset, the light emission control signal line EM, the first electrode C1 of the storage capacitor, and the gate electrode of the transistor are disposed on the same layer; the second electrode C2 of the storage capacitor and the initial signal line Vinit are disposed on the same layer; the data line D, the power supply line VDD, and the source and drain electrodes of the transistor are disposed on the same layer; the source and drain electrodes of the transistor include the first and second electrodes of the transistor.

[0297] In an exemplary embodiment, a first insulating layer 11 is disposed between the active region 21 of the transistor and the gate electrode of the transistor, a second insulating layer 12 is disposed between the gate electrode of the transistor and the second electrode C2 of the storage capacitor, and a third insulating layer 13 is disposed between the second electrode C2 of the storage capacitor and the data line.

[0298] In an exemplary embodiment, the gate electrode of the transistor, the source and drain electrodes of the transistor, the data line D, and the power line VDD are all made of metal, such as silver, aluminum, or copper, and this disclosure does not limit them in any way.

[0299] In an exemplary embodiment, the active region 21 is made of polycrystalline silicon, and this disclosure does not limit it in any way.

[0300] This disclosure ensures that the power supply signals provided by the power lines in all sub-pixels located in the same row are the same by using the second electrodes of interconnected storage capacitors and interconnected semiconductor layers, thereby avoiding display defects on the display substrate and ensuring the display effect of the display substrate.

[0301] This disclosure uses the second electrode of the storage capacitor and the semiconductor layer as a power connection line to transmit the power signal of the power line. Since the distance between the active region of the transistor and the data line is greater than the distance between the second electrode of the storage capacitor and the data line, the technical solution of this disclosure increases the distance between some power lines and data lines, reduces the load on the data lines, thereby reducing the power consumption of the display substrate and shortening the data signal writing time.

[0302] In an exemplary embodiment, the active regions of adjacent sub-pixels located in the same column are connected to each other through a third connecting portion.

[0303] In an exemplary embodiment, the pixel structure of the sub-pixel located in the i-th row and j-th column is the same as the pixel structure of the sub-pixel located in the (i+1)-th row and j+1-th column.

[0304] In an exemplary embodiment, adjacent power lines are symmetrical to each other, and the i-th column power line VDDi and the (i+1)-th column power line VDDi+1 are symmetrically arranged along the data line extension direction.

[0305] In an exemplary embodiment, the power line VDD is a polygonal line.

[0306] In an exemplary embodiment, each pixel in the display substrate may include four sub-pixels, and the pixel may include a first pixel and a second pixel. In the first pixel, the second electrode of the storage capacitor in the i-th sub-pixel is connected to the second electrode of the storage capacitor in the (i+1)-th sub-pixel via a first connection portion, and the active region of the transistor in the i-th sub-pixel is disconnected from the active region of the transistor in the (i+1)-th sub-pixel. The active region of the transistor in the second sub-pixel is connected to the active region of the transistor in the third sub-pixel via a third connection portion, and the second electrode of the storage capacitor in the second sub-pixel is disconnected from the second electrode of the storage capacitor in the third sub-pixel. Similarly, in the second pixel, the second electrode of the storage capacitor in the second sub-pixel is connected to the second electrode of the storage capacitor in the third sub-pixel via a first connection portion, and the active region of the transistor in the second sub-pixel is disconnected from the active region of the transistor in the third sub-pixel. The active region of the transistor in the i-th sub-pixel is connected to the active region of the transistor in the (i+1)-th sub-pixel via a third connection portion, and the second electrode of the storage capacitor in the i-th sub-pixel is disconnected from the second electrode of the storage capacitor in the (i+1)-th sub-pixel. Here, i is an odd number less than 4.

[0307] Figure 17 The following explanation uses two pixels arranged along the column direction as an example. The pixel at the top is the first pixel, and the pixel at the bottom is the second pixel. This disclosure does not make any limitation on this. Since the pixel structure of adjacent sub-pixels is symmetrical, the first pixel in the display substrate is arranged between adjacent second pixels, and the second pixel is arranged between adjacent first pixels.

[0308] Figure 19 This is a partial top view of a sub-pixel in another display substrate provided in this disclosure, excluding power lines, data lines, and the source / drain electrodes of transistors. Figure 20 This is a top view of another portion of a sub-pixel in a display substrate provided in this disclosure, including only the film layer where the second electrode of the storage capacitor is located and the film layer where the data line is located. Figure 21 This is a top view of another portion of a sub-pixel in a display substrate provided in this disclosure, including only the active region of the transistor and the film layer where the data lines are located. For example... Figure 19 As shown, an eleventh via V11 is provided on the third insulating layer of the display substrate.

[0309] In an exemplary embodiment, combined with Figure 19 and Figure 21 In each sub-pixel, the orthographic projection of the second electrode C2 of the storage capacitor onto the substrate includes the orthographic projection of the eleventh via V11 onto the substrate, and the power line is connected to the second electrode C2 of the storage capacitor through the eleventh via V11.

[0310] In an exemplary embodiment, the number of eleventh vias V11 is at least one. Specifically, the more eleventh vias V11 there are, the better the conductivity between the power line and the second electrode of the storage capacitor.

[0311] In an exemplary embodiment, such as Figure 19 As shown, a twelfth via V12 is provided in the first insulating layer, the second insulating layer and the third insulating layer of the display substrate.

[0312] In an exemplary embodiment, combined with Figure 19 and Figure 21 In each sub-pixel, the orthographic projection of the twelfth via V12 on the substrate overlaps with the orthographic projection of the third connection portion 22 on the substrate, and the power line is connected to the third connection portion 22 of the transistor through the twelfth via V12.

[0313] In an exemplary embodiment, the number of twelfth vias V12 is at least one, and the more vias there are, the better the conductivity of the components connected through the vias.

[0314] Figures 19 to 21 This explanation uses two eleventh vias V11 and one twelfth via V12 as an example, and this disclosure does not impose any limitations on them.

[0315] In an exemplary embodiment, through a reasonable layout design, the interconnection of the conductive layers of multiple sub-pixels can be achieved solely through a semiconductor layer, or solely through a first metal layer, or solely through a second metal layer, or solely through a third metal layer. This allows the power lines of sub-pixels located in the same row to be interconnected in the gate line extension direction via a driving circuit, which will not be elaborated further here.

[0316] This disclosure also provides another method for manufacturing a display substrate, used to manufacture another display substrate provided in the above embodiments. Figure 22 A flowchart illustrating another method for manufacturing a display substrate provided in this disclosure, such as... Figure 22 As shown, another method for manufacturing a display substrate provided in this disclosure includes the following steps:

[0317] Step B11: Provide a substrate.

[0318] Step B12: Form multiple sub-pixels, multiple columns of power lines, and data lines arranged on the same layer as the power lines on the substrate.

[0319] In an exemplary embodiment, each sub-pixel may include a driving circuit; the driving circuit may include a plurality of transistors and a storage capacitor; the storage capacitor may include a first electrode and a second electrode disposed opposite to each other; the active region of the transistor is located on the side of the second electrode of the storage capacitor closer to the substrate, and the power line is located on the side of the second electrode of the storage capacitor away from the substrate.

[0320] In an exemplary embodiment, for each sub-pixel, a power line is connected to the second electrode of a storage capacitor and the third connection portion of a semiconductor layer, respectively. The second electrode of the storage capacitor of each sub-pixel is connected to the second electrode of the storage capacitor of an adjacent sub-pixel in the same row through a first connection portion. The active region of the transistor of each sub-pixel is connected to the active region of the transistor of another adjacent sub-pixel in the same row through a third connection portion.

[0321] The method for manufacturing another display substrate provided in this disclosure is used to manufacture another display substrate provided in the above embodiments. Its implementation principle and effect are similar, and will not be described again here.

[0322] Taking the formation of two pixels along the direction of the data line as an example, each pixel includes four sub-pixels. Figure 23 A schematic diagram illustrating the fabrication of the active region of another display substrate provided in this disclosure. Figure 24 This diagram illustrates the fabrication of a first insulating layer and a first metal layer for another display substrate provided in this disclosure. Figure 25 This is a schematic diagram illustrating the fabrication of a second insulating layer and a second metal layer on another display substrate provided in this disclosure. Figure 26 This is a schematic diagram illustrating the fabrication of the third insulating layer on another display substrate provided in this disclosure, in conjunction with... Figures 23-26 The manufacturing method of the display substrate may include:

[0323] Step 1001: Provide a substrate and form a semiconductor layer on the substrate, such as... Figure 23 As shown.

[0324] In an exemplary embodiment, the semiconductor layer of each sub-pixel may include a first active region to a seventh active region, and the first active region to the seventh active region are an interconnected integral structure. In the exemplary embodiment, the positions of the first active region to the seventh active region are similar to those in the previous embodiments, and will not be repeated here.

[0325] In an exemplary embodiment, in the first direction, for the center line between adjacent sub-pixels, the semiconductor layers of adjacent sub-pixels are mirror-symmetric about the center line. The semiconductor layer shape of the sub-pixel in the i-th row and j-th column is the same as the semiconductor layer shape of the sub-pixel in the (i+1)-th row and j+1-th column, and the semiconductor layer shape of the sub-pixel in the i-th row and j-th column is the same as the semiconductor layer shape of the sub-pixel in the (i+1)-th row and j-th column.

[0326] In an exemplary embodiment, the semiconductor layer of each sub-pixel is connected to the semiconductor layer of another adjacent sub-pixel in the same row via a third connection portion, and the semiconductor layer of each sub-pixel is interconnected with the semiconductor layer of an adjacent sub-pixel in the same column.

[0327] In an exemplary embodiment, the semiconductor layer of at least one sub-pixel further includes a third connection portion 22. In the i-th row of sub-pixels, the semiconductor layer of the j-th column sub-pixel is disconnected from the semiconductor layer of the (j+1)-th column sub-pixel, the semiconductor layer of the (j+1)-th column sub-pixel is interconnected with the semiconductor layer of the (j+2)-th column sub-pixel through the third connection portion 22, and the semiconductor layer of the (j+2)-th column sub-pixel is disconnected from the semiconductor layer of the (j+3)-th column sub-pixel. In the i+1-th row of sub-pixels, the semiconductor layers of the j-th column sub-pixels are interconnected with the semiconductor layer of the (j+1)-th column sub-pixels through the third connection portion 22, the semiconductor layer of the (j+1)-th column sub-pixels is disconnected from the semiconductor layer of the (j+2)-th column sub-pixels, and the semiconductor layers of the (j+2)-th column sub-pixels are interconnected with the semiconductor layer of the (j+3)-th column sub-pixels through the third connection portion 22.

[0328] In an exemplary embodiment, the first end of the third connection portion 22 is connected to the active region 105 of the fifth transistor in the sub-pixel, and the second end of the third connection portion 22 is connected to the active region 105 of the fifth transistor in the adjacent sub-pixel.

[0329] In an exemplary embodiment, the orthographic projection of the third connection portion 22 on the substrate overlaps with the orthographic projections of the subsequently formed data line and power line on the substrate.

[0330] In an exemplary embodiment, by setting the semiconductor layers of adjacent sub-pixels to be interconnected, the third connection portion 22 of the semiconductor layer can be multiplexed as a power connection line to transmit the power signal of the power line.

[0331] The semiconductor layer layout of the exemplary embodiments disclosed herein is reasonable and the structure is simple, which can ensure the display effect of the display substrate.

[0332] Step 1002: Form a first insulating layer on the semiconductor layer, and form a first metal layer on the first insulating layer, such as... Figure 24 As shown.

[0333] In an exemplary embodiment, the first metal layer may include: a gate line G, a reset signal line Reset, a light emission control signal line EM, and a first electrode C1 of a storage capacitor.

[0334] In an exemplary embodiment, the gate line G, the reset signal line Reset, and the light-emitting control line EM extend along a first direction, with the gate line G disposed between the reset signal line Reset and the light-emitting control line EM. The first electrode C1 of the storage capacitor can be rectangular, with chamfered corners, and is disposed between the gate line G and the light-emitting control line EM. The orthographic projection of the first electrode C1 onto the substrate overlaps with the orthographic projection of the third active region onto the substrate. In an exemplary embodiment, the first electrode C1 also serves as the gate electrode of the third transistor.

[0335] In an exemplary embodiment, the gate line G, the reset signal line Reset, and the light emission control line EM can be configured with non-uniform widths. The gate line G is provided with a gate block protruding towards the reset signal line Reset side, and the orthogonal projection of the gate block on the substrate overlaps with the orthogonal projection of the second active region on the substrate to form a dual-gate structure.

[0336] In an exemplary embodiment, after the first metal layer pattern is formed, the first metal layer can be used as a shield to conduct the semiconductor layer. The semiconductor layer in the region shielded by the first metal layer forms the channel region from the first transistor T1 to the seventh active region, and the semiconductor layer in the region not shielded by the first metal layer is conducted.

[0337] The first metal layer of the exemplary embodiments disclosed herein has a reasonable layout and a simple structure, which can ensure the display effect of the display substrate.

[0338] Step 1003: Form a second insulating layer on the first metal layer, and then form a second metal layer on the second insulating layer, such as... Figure 25 As shown.

[0339] In an exemplary embodiment, the second metal layer may include: an initial signal line Vinit and a second electrode C2 of a storage capacitor.

[0340] In an exemplary embodiment, the initial signal line Vinit extends along a first direction and is positioned on the side of the reset signal line Reset away from the gate line G. The outline of the second electrode C2 storing the capacitor in each sub-pixel can be rectangular and located between the gate line G and the light emission control line EM.

[0341] In an exemplary embodiment, the outline of the second electrode C2 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second electrode C2 onto the substrate overlaps with the orthographic projection of the first electrode C1 onto the substrate. An opening is provided in the middle of the second electrode C2, and the opening can be rectangular, so that the second electrode C2 forms a ring structure. The opening exposes the second insulating layer covering the first electrode C1, and the orthographic projection of the first electrode C1 onto the substrate includes the orthographic projection of the opening onto the substrate.

[0342] In an exemplary embodiment, the second electrode C2 of the i-th row and j-th column sub-pixel and the second electrode C2 of the i-th row and (j+1)-th column sub-pixel are an integral structure connected to each other via a first connecting portion C3; the second electrode C2 of the i-th row and (j+1)-th column sub-pixel and the second electrode C2 of the i-th row and (j+2)-th column sub-pixel are disconnected; and the second electrode C2 of the i-th row and (j+2)-th column sub-pixel and the second electrode C2 of the i-th row and (j+3)-th column sub-pixel are an integral structure connected to each other via the first connecting portion C3. Alternatively, the second electrode C2 of the i+1-th row and j-th column sub-pixel and the second electrode C2 of the i+1-th row and (j+1)-th column sub-pixel are disconnected; the second electrode C2 of the i+1-th row and (j+2)-th column sub-pixel and the second electrode C2 of the i+1-th row and (j+3)-th column sub-pixel are an integral structure connected to each other via the first connecting portion C3; and the second electrode C2 of the i+1-th row and (j+2)-th column sub-pixel are disconnected. This structure allows the second electrode C2 of adjacent sub-pixels to be reused as a power signal line, ensuring that the power signals provided by the power lines of adjacent sub-pixels are the same, avoiding display defects on the display substrate and ensuring the display effect of the display substrate.

[0343] In an exemplary embodiment, the second metal layer may further include a shielding electrode C4, the orthographic projection of the shielding electrode C4 onto the substrate overlapping the orthographic projection of a subsequently formed power line onto the substrate, and the power line being connected to the shielding electrode C4 via a via. In an exemplary embodiment, the shielding electrode C4 is configured to shield the data line from the influence of the driving circuit.

[0344] In an exemplary embodiment, the shielding electrode C4 is shaped like a "7" and includes a first part extending along a first direction and a second part extending along a second direction. The end of the first part near the second part is connected to the end of the second part near the first part to form a right-angled broken line.

[0345] In an exemplary embodiment, in the second direction, the shielding electrode C4 is disposed between the gate line G and the reset signal line Reset, and in the first direction, the second part of the shielding electrode C4 is disposed between the subsequently formed data line and the power line.

[0346] In an exemplary embodiment, the second part of the shielding electrode C4 and the gate block of the first metal layer both extend along the second direction, and there is a region where they face each other, that is, there is a region where the edge of the shielding electrode C4 near the first direction side of the gate block and the edge of the gate block near the first direction side of the shielding electrode C4 are disposed opposite to each other.

[0347] The second metal layer of the exemplary embodiments disclosed herein has a reasonable layout and simple structure, which can ensure the display effect of the display substrate.

[0348] Step 1004: A third insulating layer is formed on the second metal layer. The third insulating layer has an eleventh via V11 exposing the second electrode of the storage capacitor. The first, second, and third insulating layers have a twelfth via V12 exposing the third connection portion. Figure 26 As shown.

[0349] In an exemplary embodiment, the eleventh via V11 is configured to connect the second electrode C2 to a subsequently formed power line, and the twelfth via V12 is configured to connect the third connection portion of the semiconductor layer to a subsequently formed power line, so that the second electrode C2 interconnected in adjacent sub-pixels and the third connection portion interconnected in adjacent sub-pixels are multiplexed together as a power connection line.

[0350] In an exemplary embodiment, the number of eleventh vias V11 can be two, and the two eleventh vias V11 are arranged sequentially along the second direction, which can improve the reliability of the connection between the second electrode and the power line.

[0351] The via layout of the exemplary embodiments disclosed herein is reasonable and the structure is simple, which can ensure the display effect of the display substrate.

[0352] Step 1005: Form a third metal layer on the third insulating layer, such as... Figure 17 As shown.

[0353] In an exemplary embodiment, the third metal layer includes a data line D, a power line VDD, and source / drain electrodes of a plurality of transistors, wherein the data line D includes a first sub-data line DO and a second sub-data line DE.

[0354] In an exemplary embodiment, a first sub-data line DO, a second sub-data line DE, and a power line VDD extend along a second direction. The first sub-data line DO is located on one side of a sub-pixel, the second sub-data line DE is located on the other side of the sub-pixel, and the power line VDD is located between the first sub-data line DO and the second sub-data line DE.

[0355] In an exemplary embodiment, adjacent sub-pixels located in the same column are connected to different sub-data lines. For example, a sub-pixel in the i-th row and j-th column is connected to the first sub-data line in the j-th column, and a sub-pixel in the (i+1)-th row and j-th column is connected to the second sub-data line in the j-th column. Alternatively, a sub-pixel in the i-th row and j-th column is connected to the second sub-data line in the j-th column, and a sub-pixel in the (i+1)-th row and j-th column is connected to the first sub-data line in the j-th column.

[0356] In an exemplary embodiment, the power line VDD of each sub-pixel is connected to the second electrode C2 through the eleventh via V11, and the power line VDD of each sub-pixel is connected to the third connection portion of the semiconductor layer through the twelfth via V12. Thus, in a row, the second electrodes C2 of the storage capacitors of adjacent sub-pixels are interconnected, and the third connection portions of the semiconductor layers of other adjacent sub-pixels are interconnected. The interconnected second electrodes C2 and interconnected semiconductor layers of adjacent sub-pixels are multiplexed together as power connection lines, ensuring that the power signal supplied to each sub-pixel is identical, thereby guaranteeing the display effect of the display substrate.

[0357] In an exemplary embodiment, the power line VDD of each sub-pixel can be a broken line. Along the second direction, the power line VDD of each sub-pixel can include a first power section, a second power section, and a third power section connected in sequence. In the power line corresponding to the sub-pixel in the i-th row and j-th column, the first end of the first power section is connected to the second end of the third power section in the sub-pixel located in the (i-1)-th row and j-th column. The second end of the first power section extends along the second direction and is connected to the first end of the second power section. The second end of the second power section extends along an inclined direction and is connected to the first end of the third power section. The inclined direction has an angle with the second direction, and the angle can be greater than 0 degrees and less than 90 degrees. The second end of the third power section extends along the second direction and is connected to the first end of the first power section in the sub-pixel located in the (i+1)-th row and j-th column.

[0358] In an exemplary embodiment, the first power supply section can be a straight line of equal width, the second power supply section can be a diagonal line of varying width, and the third power supply section can be a straight line of equal width. The first power supply section and the second power supply section are parallel to the first sub-data line (or the second sub-data line), the angle between the second power supply section and the first power supply section can be greater than 90 degrees and less than 180 degrees, and the angle between the second power supply section and the third power supply section can be greater than 90 degrees and less than 180 degrees.

[0359] In an exemplary embodiment, the width of the third power supply section may be smaller than the width of the first power supply section. The power line VDD is configured with a variable-width polygonal line, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the power line VDD and the data line.

[0360] In an exemplary embodiment, the orthographic projection of the third power supply unit on the substrate overlaps with the orthographic projection of the second electrode C2 on the substrate.

[0361] In an exemplary embodiment, the orthographic projection of the third power supply unit on the substrate overlaps with the orthographic projection of the first electrode C1 on the substrate.

[0362] In an exemplary embodiment, the orthographic projection of the third power supply unit on the substrate overlaps with the orthographic projection of the gate line G on the substrate.

[0363] The structure and fabrication process shown in this disclosure are merely illustrative examples. In the exemplary embodiments, the corresponding structure and the patterning process can be modified and increased or decreased according to actual needs. For example, the display substrate may include a fourth metal layer, and the data line D, the power line VDD, and the source and drain electrodes of multiple transistors may be located on different metal layers. This disclosure does not limit the scope of the invention.

[0364] This disclosure uses the second plate of the storage capacitor and the active region of the transistor as a power connection line to transmit the power signal of the power line. Since the active region of the transistor is far from the data line, the solution of this disclosure increases the distance between the power connection line and the data line, reduces the load on the data line, thereby reducing the power consumption of the display substrate and shortening the data signal writing time.

[0365] This disclosure also provides a display device, in an exemplary embodiment of which the display device includes the aforementioned display substrate.

[0366] In some possible implementations, the display substrate can be an OLED display substrate. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator, and the embodiments of the present invention are not limited thereto.

[0367] The display substrate is the same as the display substrate provided in the aforementioned embodiments, and its implementation principle and effect are similar, so it will not be described again here.

[0368] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0369] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit the invention. Any person skilled in the art may make any modifications and variations in the form and details of the implementation without departing from the spirit and scope of this invention; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, comprising, in a plane parallel to the display substrate, a plurality of gate lines, a plurality of data lines, a plurality of power lines, and a plurality of sub-pixels disposed on a substrate, at least one sub-pixel including a light-emitting device and a driving circuit configured to drive the light-emitting device to emit light, the driving circuit including a plurality of transistors and a storage capacitor; and, in a plane perpendicular to the display substrate, the display substrate including a substrate and a plurality of functional layers disposed on the substrate; the plurality of functional layers including a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed sequentially; a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer respectively disposed between the plurality of functional layers; and, in the direction of the gate lines extending, the power lines being interconnected through at least one functional layer. in, The display substrate further includes a first connection portion, wherein the second electrode of the storage capacitor in at least one sub-pixel is connected to the second electrode of the storage capacitor in an adjacent sub-pixel in the gate line extension direction through the first connection portion, so that the second electrode is multiplexed as a power signal line, ensuring that the power lines of adjacent sub-pixels provide the same power signal.

2. The display substrate according to claim 1, wherein, In the direction of data line extension, the power line includes a plurality of sub-power lines connected in sequence, and at least one sub-power line is disposed in a sub-pixel; The sub-power line of at least one sub-pixel includes a plurality of power supply sections connected in sequence, and there is an angle greater than 90 degrees and less than 180 degrees between at least one power supply section and the power supply section connected to the power supply section.

3. The display substrate according to claim 2, wherein, Of the at least one power supply unit and the power supply unit connected to the power supply unit, one of the power supply units is arranged parallel to the data line.

4. The display substrate according to claim 2, wherein, The sub-power line includes a first power section, a second power section, and a third power section; the second power section is configured to connect the first power section and the third power section, the first power section and the third power section are arranged parallel to the data line, the angle between the second power section and the first power section is greater than 90 degrees and less than 180 degrees, and the angle between the second power section and the third power section is greater than 90 degrees and less than 180 degrees.

5. The display substrate according to claim 4, wherein, The first power supply unit is connected to the third power supply unit located in the previous row of sub-pixels in the same column, and the third power supply unit is connected to the first power supply unit located in the next row of sub-pixels in the same column.

6. The display substrate according to claim 4, wherein, The length of the first power supply unit extending along the data line extension direction is greater than the average width of the first power supply unit, the length of the second power supply unit extending along the inclined direction is greater than the average width of the second power supply unit, and the length of the third power supply unit extending along the data line extension direction is greater than the average width of the third power supply unit. The tilting direction is the direction in which the second power supply unit and the first power supply unit form the included angle.

7. The display substrate according to claim 4, wherein, The average width of the third power supply section is less than the average width of the first power supply section.

8. The display substrate according to claim 4, wherein, The average distance between the edge of the first power supply unit near the side extending in the gate line direction of the third power supply unit and the edge of the third power supply unit near the side extending in the gate line direction of the first power supply unit is equivalent to the average width of the third power supply unit.

9. The display substrate according to claim 4, wherein, In at least one sub-pixel, the orthographic projection of the second power supply portion on the substrate overlaps with the orthographic projection of the second electrode of the storage capacitor on the substrate, or the orthographic projection of the second power supply portion on the substrate overlaps with the orthographic projection of the first connection portion on the substrate.

10. The display substrate according to claim 4, wherein, The orthographic projection of the second power supply unit on the substrate overlaps with the orthographic projection of the first electrode of the storage capacitor on the substrate.

11. The display substrate according to claim 4, wherein, The orthographic projection of the second power supply unit on the substrate overlaps with the orthographic projection of the gate line on the substrate.

12. The display substrate according to claim 4, wherein, The plurality of transistors includes a second transistor, and the orthographic projection of the first power supply on the substrate overlaps with the orthographic projection of the second transistor on the substrate.

13. The display substrate according to claim 2, wherein, The display substrate further includes a fifth insulating layer disposed on the fourth conductive layer and a fifth conductive layer disposed on the fifth insulating layer. A fifth via is disposed on the fifth insulating layer. The fifth via is configured to connect the fifth conductive layer to the fourth conductive layer. The orthographic projection of the fifth via on the substrate does not overlap with the orthographic projection of the sub-power line on the substrate.

14. The display substrate according to claim 13, wherein, In at least one sub-pixel, the orthographic projection of the fifth via on the substrate overlaps with the orthographic projection of the virtual extension line of the first power part in the sub-power line in the data line extension direction on the substrate.

15. The display substrate according to claim 13, wherein, An eighth via is provided on the first insulating layer, the second insulating layer and the third insulating layer, and the eighth via is configured to allow the data line to write data signals to the semiconductor layer; The orthographic projection of the eighth via on the substrate does not overlap with the orthographic projections of the first power supply section and the second power supply section in the sub-power supply line on the substrate.

16. The display substrate according to claim 15, wherein, In at least one sub-pixel, the orthographic projection of the eighth via on the substrate overlaps with the orthographic projection of the virtual extension line of the third power part in the sub-power line in the data line extension direction on the substrate.

17. The display substrate according to any one of claims 1 to 16, wherein, The power line is disposed on the third conductive layer or on the fourth conductive layer, and the power line is disposed on the same layer as the data line.

18. The display substrate according to any one of claims 1 to 16, wherein, The power line is disposed on the third conductive layer, and the data line is disposed on the fourth conductive layer, or the data line is disposed on the third conductive layer and the power line is disposed on the fourth conductive layer.

19. The display substrate according to any one of claims 1 to 16, wherein, There exists at least one region comprising 2*4 sub-pixels, in which the second electrodes of the capacitors stored in the first sub-pixel of a row are interconnected with each other through the first connecting part; the second electrodes of the capacitors stored in the second sub-pixel are directly connected with each other; and the second electrodes of the capacitors stored in the third sub-pixel and the fourth sub-pixel are interconnected with each other through the first connecting part. In another row, the second electrodes of the capacitors stored in the first sub-pixel are directly connected with each other; the second electrodes of the capacitors stored in the second sub-pixel and the third sub-pixel are interconnected with each other through the first connecting part; and the second electrodes of the capacitors stored in the third sub-pixel and the fourth sub-pixel are directly connected.

20. The display substrate according to claim 19, wherein, The semiconductor layers in the first sub-pixel and the second sub-pixel are spaced apart, the semiconductor layers in the second sub-pixel and the third sub-pixel are spaced apart, and the semiconductor layers in the third sub-pixel and the fourth sub-pixel are spaced apart.

21. The display substrate according to claim 19, wherein, The third conductive layer includes the first electrode of the fifth transistor; the first electrode of the fifth transistor in the first sub-pixel is spaced apart from the first electrode of the fifth transistor in the second sub-pixel, the first electrode of the fifth transistor in the second sub-pixel is spaced apart from the first electrode of the fifth transistor in the third sub-pixel, and the first electrode of the fifth transistor in the third sub-pixel is spaced apart from the first electrode of the fifth transistor in the fourth sub-pixel.

22. The display substrate according to any one of claims 1 to 16, wherein, There exists at least one region comprising 2*4 sub-pixels. In one row, the second electrodes of the capacitors stored in the first sub-pixel and the second electrodes of the capacitors stored in the second sub-pixel are connected to each other through the first connecting part. The second electrodes of the capacitors stored in the second sub-pixel and the second electrodes of the capacitors stored in the third sub-pixel are disconnected. The second electrodes of the capacitors stored in the third sub-pixel and the second electrodes of the capacitors stored in the fourth sub-pixel are connected to each other through the first connecting part. In another row, the second electrodes of the capacitors stored in the first sub-pixel and the second electrodes of the capacitors stored in the second sub-pixel are disconnected. The second electrodes of the capacitors stored in the second sub-pixel and the second electrodes of the capacitors stored in the third sub-pixel are connected to each other through the first connecting part. The second electrodes of the capacitors stored in the third sub-pixel and the second electrodes of the capacitors stored in the fourth sub-pixel are disconnected.

23. The display substrate according to claim 22, wherein, The third conductive layer includes a first electrode and a second connection portion of a fifth transistor; in a row, the first electrode of the fifth transistor in the first sub-pixel is disconnected from the first electrode of the fifth transistor in the second sub-pixel, the first electrode of the fifth transistor in the second sub-pixel is connected to the first electrode of the fifth transistor in the third sub-pixel through the second connection portion, and the first electrode of the fifth transistor in the third sub-pixel is disconnected from the first electrode of the fifth transistor in the fourth sub-pixel; in another row, the first electrode of the fifth transistor in the first sub-pixel is connected to the first electrode of the fifth transistor in the second sub-pixel through the second connection portion, the first electrode of the fifth transistor in the second sub-pixel is disconnected from the first electrode of the fifth transistor in the third sub-pixel, and the first electrode of the fifth transistor in the third sub-pixel is connected to the first electrode of the fifth transistor in the fourth sub-pixel through the second connection portion.

24. The display substrate according to claim 21 or 23, wherein, In the direction of gate line extension, the power line is interconnected through the second electrode of the storage capacitor and the first electrode of the fifth transistor.

25. The display substrate according to claim 24, wherein, The fourth insulating layer has a first via that exposes the first electrode of the fifth transistor, and the third insulating layer has a second via that exposes the second electrode of the storage capacitor. The power line is connected to the first electrode of the fifth transistor through the first via, and the first electrode of the fifth transistor is connected to the second electrode of the storage capacitor through the second via.

26. The display substrate according to claim 25, wherein, In at least one sub-pixel, the number of first vias is one, and the number of second vias is multiple, with the multiple second vias arranged along the extension direction of the data line; The orthographic projection of the power line onto the substrate includes the orthographic projection of the first via onto the substrate, and the orthographic projection of the first electrode of the fifth transistor onto the substrate includes the orthographic projection of the second via onto the substrate.

27. The display substrate according to claim 22, wherein, The semiconductor layer includes a third connection portion; in one row, the semiconductor layer in the first sub-pixel is disconnected from the semiconductor layer in the second sub-pixel, the semiconductor layer in the second sub-pixel is connected to the semiconductor layer in the third sub-pixel through the third connection portion, and the semiconductor layer in the third sub-pixel is disconnected from the semiconductor layer in the fourth sub-pixel; in another row, the semiconductor layer in the first sub-pixel is connected to the semiconductor layer in the second sub-pixel through the third connection portion, the semiconductor layer in the second sub-pixel is disconnected from the semiconductor layer in the third sub-pixel, and the semiconductor layer in the third sub-pixel is connected to the semiconductor layer in the fourth sub-pixel through the third connection portion.

28. The display substrate according to claim 27, wherein, In the direction of gate line extension, the power line is interconnected with the second electrode of the storage capacitor through the third connection portion of the semiconductor layer.

29. The display substrate according to claim 28, wherein, The third insulating layer has an eleventh via that exposes the second electrode of the storage capacitor. The first, second, and third insulating layers have twelfth vias that expose the third connection portion of the semiconductor layer. The power line is connected to the second electrode of the storage capacitor through the eleventh via and to the third connection portion of the semiconductor layer through the twelfth via.

30. The display substrate according to claim 29, wherein, In at least one sub-pixel, the number of the eleventh via is one, and the number of the twelfth via is multiple, with the multiple twelfth vias arranged along the extension direction of the data line; the orthogonal projection of the power line on the substrate includes the orthogonal projections of the eleventh via and the twelfth via on the substrate.

31. The display substrate according to any one of claims 1 to 16, wherein, The plurality of transistors includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; In at least one sub-pixel, the semiconductor layer includes at least a first active region at the location of the first transistor, a second active region at the location of the second transistor, a third active region at the location of the third transistor, a fourth active region at the location of the fourth transistor, a fifth active region at the location of the fifth transistor, a sixth active region at the location of the sixth transistor, and a seventh active region at the location of the seventh transistor, wherein the first active region, the second active region, the third active region, the fourth active region, the fifth active region, the sixth active region, and the seventh active region are an integral structure.

32. The display substrate according to claim 31, wherein, The distance between the second active region and the first active region in the direction of the extension of the gate line is less than the distance between the second active region and the seventh active region in the direction of the extension of the gate line.

33. The display substrate according to claim 31, wherein, The seventh active region and the first active region are arranged sequentially along the direction from the data line to the power line of the data signal being written.

34. The display substrate according to claim 31, wherein, At least one sub-pixel includes a first region, a second region, and a third region arranged sequentially along the data line extension direction; the first active region and the seventh active region are located on the side of the first region away from the second region, the second active region and the fourth active region are located on the side of the first region closer to the second region; the third active region is located within the second region; and the fifth active region and the sixth active region are located within the third region.

35. The display substrate according to claim 31, wherein, The first terminal of the first transistor is connected to the initial signal line; the second terminal of the first transistor T1 is connected to the first electrode of the storage capacitor; the first terminal of the second transistor is connected to the first electrode of the storage capacitor; the second terminal of the second transistor is connected to the second terminal of the sixth transistor; the first terminal of the third transistor is connected to the second terminal of the fourth transistor; the second terminal of the third transistor is connected to the second terminal of the sixth transistor; the first terminal of the fourth transistor is connected to the data line; the first terminal of the fifth transistor is connected to the power line; the second terminal of the fifth transistor is connected to the first terminal of the third transistor; the second terminal of the sixth transistor is connected to the anode of the light-emitting device; the first terminal of the seventh transistor is connected to the initial signal line; and the second terminal of the seventh transistor is connected to the anode of the light-emitting device. The first active region is connected to the second active region and the seventh active region, the second active region is connected to the third active region and the sixth active region, and the fourth active region is connected to the third active region and the fifth active region.

36. The display substrate according to claim 31, wherein, In the direction of gate line extension, the semiconductor layers of adjacent sub-pixels are symmetrical to each other.

37. The display substrate according to claim 31, wherein, There exists at least one region comprising 2*2 sub-pixels, where the semiconductor layer shape in the first sub-pixel of one row is the same as the semiconductor layer shape in the second sub-pixel of another row, and the semiconductor layer shape in the second sub-pixel of one row is the same as the semiconductor layer shape in the first sub-pixel of another row.

38. The display substrate according to claim 31, wherein, The semiconductor layer includes a third connection portion, and the semiconductor layer in at least one sub-pixel is connected to the semiconductor layer in an adjacent sub-pixel in the gate line extension direction through the third connection portion.

39. The display substrate according to claim 38, wherein, The third connection portion is connected to the active region of the fifth transistor.

40. The display substrate according to claim 38, wherein, The orthographic projection of the third connection portion on the substrate overlaps with the orthographic projection of the power line on the substrate.

41. The display substrate according to claim 38, wherein, The first insulating layer, the second insulating layer, and the third insulating layer are provided with a twelfth through hole that exposes the third connection portion, and the power line is connected to the third connection portion through the twelfth through hole.

42. The display substrate according to claim 38, wherein, There exists at least one region comprising 2*4 sub-pixels, in which the semiconductor layer in the first sub-pixel of one row is disconnected from the semiconductor layer in the second sub-pixel, the semiconductor layer in the second sub-pixel is connected to the semiconductor layer in the third sub-pixel through the third connecting portion, and the semiconductor layer in the third sub-pixel is disconnected from the semiconductor layer in the fourth sub-pixel; in another row, the semiconductor layer in the first sub-pixel is connected to the semiconductor layer in the second sub-pixel through the third connecting portion, the semiconductor layer in the second sub-pixel is disconnected from the semiconductor layer in the third sub-pixel, and the semiconductor layer in the third sub-pixel is connected to the semiconductor layer in the fourth sub-pixel through the third connecting portion.

43. The display substrate according to any one of claims 1 to 16, wherein, In the direction of data line extension, the data line includes a plurality of sequentially connected sub-data lines; there is at least one sub-pixel, and two sub-data lines are provided between the sub-pixel and the adjacent sub-pixel in the direction of gate line extension.

44. The display substrate according to claim 43, wherein, The two sub-data lines are parallel to each other.

45. The display substrate according to claim 43, wherein, Within at least one sub-pixel, an eighth via is provided on the first insulating layer, the second insulating layer, and the third insulating layer to expose the semiconductor layer, and a third via is provided on the fourth insulating layer to expose the first electrode of the fourth transistor. The data line is connected to the first electrode of the fourth transistor through the third via, and the first electrode of the fourth transistor is connected to the semiconductor layer through the eighth via.

46. ​​The display substrate according to claim 45, wherein, In the direction of the gate line extension, the eighth vias of adjacent sub-pixels are symmetrical to each other.

47. The display substrate according to claim 43, wherein, The data line is disposed on the third conductive layer, and the power line is disposed on the third conductive layer.

48. The display substrate according to claim 43, wherein, The data line is disposed on the fourth conductive layer, and the power line is disposed on the third or fourth conductive layer.

49. The display substrate according to claim 43, wherein, In at least one column of sub-pixels, the data line includes a first sub-data line and a second sub-data line, which are located on both sides of the column of sub-pixels, respectively.

50. The display substrate according to claim 49, wherein, The power line is located between the first sub-data line and the second sub-data line.

51. The display substrate according to any one of claims 1 to 16, wherein, In the direction of the grid line extension, the pixel structure of adjacent sub-pixels is symmetrical.

52. The display substrate according to claim 51, wherein, There exists at least one region comprising 2*2 sub-pixels, where the pixel structure of the first sub-pixel in one row is the same as that of the second sub-pixel in another row, and the pixel structure of the second sub-pixel in one row is the same as that of the first sub-pixel in another row.

53. The display substrate according to any one of claims 1 to 16, wherein, The display substrate further includes a reset signal line, a light emission control line, and an initial signal line; the semiconductor layer includes at least the active regions of multiple transistors, the first conductive layer includes at least a gate line, a light emission control line, a reset signal line, a first electrode of a storage capacitor, and a gate electrode of multiple transistors, the second conductive layer includes at least an initial signal line and a second electrode of a storage capacitor; the third conductive layer includes at least the source and drain electrodes of multiple transistors, and the fourth conductive layer includes at least a data line and a power line.

54. The display substrate according to claim 53, wherein, At least one sub-pixel includes a first region, a second region, and a third region arranged sequentially along the data line extension direction; the gate line, the initial signal line, and the reset signal line are located in the first region, the first electrode and the second electrode of the storage capacitor are located in the second region, and the light emission control line is located in the third region.

55. The display substrate according to claim 53, wherein, The second conductive layer further includes a shielding electrode, and in at least one sub-pixel, the orthographic projection of the shielding electrode on the substrate overlaps with the orthographic projection of the power line on the substrate.

56. The display substrate according to claim 55, wherein, The power line is connected to the shielding electrode through a via.

57. The display substrate according to claim 55, wherein, In the direction of data line extension, the shielding electrode is disposed between the gate line and the reset signal line.

58. The display substrate according to claim 55, wherein, The shielding electrode includes a first part extending along the grid line extension direction and a second part extending along the data line extension direction, wherein one end of the first part near the second part is connected to one end of the second part near the first part.

59. The display substrate according to claim 58, wherein, The first conductive layer further includes a gate block extending along the data line extension direction, the gate block being connected to the gate line; in the data line extension direction, the gate block and the second part of the shielding electrode have a directly opposite region.

60. The display substrate according to claim 53, wherein, The source and drain electrodes of the plurality of transistors include the first electrode of the second transistor. A seventh via is provided on the second insulating layer and the third insulating layer to expose the first electrode of the storage capacitor. A ninth via is provided on the first insulating layer, the second insulating layer and the third insulating layer to expose the active region of the second transistor. One end of the first electrode of the second transistor is connected to the first electrode of the storage capacitor through the seventh via, and the other end is connected to the active region of the second transistor through the ninth via.

61. The display substrate according to claim 60, wherein, The orthographic projection of the first electrode of the second transistor on the substrate overlaps with the orthographic projection of the gate line on the substrate, but the orthographic projection of the first electrode of the second transistor on the substrate does not overlap with the orthographic projections of the light emission control line, the reset signal line, and the initial signal line on the substrate.

62. The display substrate according to claim 53, wherein, The source and drain electrodes of the plurality of transistors include the first electrode of the first transistor. A sixth via is provided on the third insulating layer to expose the initial signal line. A tenth via is provided on the first, second and third insulating layers to expose the active region of the first transistor. One end of the first electrode of the first transistor is connected to the initial signal line through the sixth via, and the other end is connected to the active region of the first transistor through the tenth via.

63. The display substrate according to claim 62, wherein, The orthographic projection of the first electrode of the first transistor on the substrate overlaps with the orthographic projection of the reset signal line on the substrate, but the orthographic projection of the first electrode of the first transistor on the substrate does not overlap with the orthographic projections of the gate line and the light emission control line on the substrate.

64. The display substrate according to claim 53, wherein, The display substrate further includes a fifth insulating layer disposed on the fourth conductive layer and a fifth conductive layer disposed on the fifth insulating layer; the fourth conductive layer further includes a connection electrode, and the source and drain electrodes of the plurality of transistors include the second electrode of the sixth transistor; the fourth insulating layer is provided with a fourth via exposing the second electrode of the sixth transistor, the fifth insulating layer is provided with a fifth via exposing the connection electrode, the connection electrode is connected to the second electrode of the sixth transistor through the fourth via, and the fifth conductive layer is connected to the connection electrode through the fifth via.

65. The display substrate according to claim 64, wherein, There is an overlap between the orthogonal projection of the connecting electrode on the substrate and the orthogonal projection of the first electrode of the second transistor on the substrate.

66. The display substrate according to claim 53, wherein, At least one sub-pixel includes at least: a first via exposing a first electrode of a fifth transistor, the first via configured to connect the first electrode of the fifth transistor to the power line; a second via exposing a second electrode of a storage capacitor, the second via configured to connect the second electrode to the first electrode of the fifth transistor; a third via exposing a first electrode of a fourth transistor, the third via configured to connect the first electrode of the fourth transistor to the data line; a fourth via exposing a second electrode of a sixth transistor, the fourth via configured to connect the second electrode of the sixth transistor to a connection electrode; and a fifth via exposing a connection electrode, the fifth via configured to connect the connection electrode to the anode of a fifth conductive layer; and exposing... A sixth via exposes the initial signal line, the sixth via being configured to connect the initial signal line to the first electrode of the first transistor; a seventh via exposes the first electrode of the storage capacitor, the seventh via being configured to connect the first electrode to the first electrode of the second transistor; an eighth via exposes the active region of the fourth transistor, the eighth via being configured to connect the active region of the fourth transistor to the first electrode of the fourth transistor; a ninth via exposes the active region of the second transistor, the ninth via being configured to connect the active region of the second transistor to the first electrode of the second transistor; and a tenth via exposes the active region of the first transistor, the tenth via being configured to connect the active region of the first transistor to the first electrode of the first transistor.

67. The display substrate according to claim 53, wherein, At least one sub-pixel includes at least: an eleventh via exposing a second electrode of a storage capacitor, the eleventh via being configured to connect the second electrode to a power line; and a twelfth via exposing a third connection portion, the twelfth via being configured to connect the third connection portion to a power line.

68. A display device comprising a display substrate as described in any one of claims 1 to 67.

69. A method for manufacturing a display substrate, configured to manufacture a display substrate as described in any one of claims 1 to 67, wherein, in a plane parallel to the display substrate, the display substrate includes gate lines, data lines, power lines, and a plurality of sub-pixels disposed on a substrate, at least one sub-pixel including a light-emitting device and a driving circuit configured to drive the light-emitting device to emit light, the driving circuit including a plurality of transistors and a storage capacitor; the manufacturing method includes: Provide a base; Multiple functional layers are formed on the substrate; the multiple functional layers include a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer arranged sequentially; a first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer are respectively disposed between the multiple functional layers; in the gate line extension direction, the power lines are interconnected through at least one functional layer.

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