An asynchronous sparse matrix external product multiplier based on event-driven circuit design

Abstract

This invention discloses an asynchronous sparse matrix outer product multiplier based on an event-driven circuit design. The multiplier employs a merging strategy that explicitly associates data with storage unit addresses, mapping matrix data address indices to corresponding addresses in the storage modules. Identical indices indicate identical storage locations, necessitating a merging operation. This strategy ensures the determinism of the data merging process and avoids complex sorting operations. Furthermore, the event-driven, clockless circuit used in this multiplier effectively mitigates some problems associated with synchronous circuits due to the absence of a clock and the use of an asynchronous controller to control data transmission. It also features low power consumption, high adaptability, and a certain degree of electromagnetic interference resistance, making it suitable for processing scenarios requiring ultra-low power consumption.

Description

Technical Field

[0001] This invention belongs to the field of large-scale scientific computing, and in particular relates to an asynchronous sparse matrix outer product multiplier based on event-driven circuit design. Background Technology

[0002] Sparse matrices are generated in almost all large-scale scientific computing fields, including computational fluid dynamics, statistical physics, circuit simulation, image processing, and nanomaterials computing. Sparse matrix multiplication is a key core of sparse computing, playing a crucial role in accelerating computations in areas such as deep neural networks, distributed graph processing, nonlinear seismic simulation, and high-resolution atmospheric prediction. It is also a core component of algorithms such as Markov clustering, search algorithms, large-scale data matching algorithms, explicit solutions to partial differential equations, and finite element conjugate gradients. However, compared to dense matrices, sparse matrices have irregular structures, resulting in more flexible and diverse storage methods. Although sparse matrix multiplication only requires operations on effective values, the complexity and diversity of their structures lead to irregular memory access. Traditional processors (such as CPUs and GPUs) suffer from high energy consumption and significant access latency due to the need to support various processing requirements. Therefore, designing specific architectures for sparse matrix multiplication to improve processing performance and reduce power consumption has become a top research priority.

[0003] Currently, mainstream asynchronous sparse matrix outer product multipliers primarily accelerate processing based on inner or outer product methods. Inner product maximizes data reuse in the output result because each calculation yields only one final output matrix, eliminating the generation of intermediate matrices and thus mitigating the potential for bursts in intermediate matrix data. However, the inner product method sacrifices input data reuse, making it more suitable for relatively dense input matrices and less efficient for highly sparse matrices. The outer product method, on the other hand, maximizes input reuse by iterating through a column of the sparse left matrix and a row of the sparse right matrix each time, calculating a complete intermediate matrix, and finally merging all intermediate matrices to obtain the final result. Therefore, its cost lies in storing and merging the intermediate matrices.

[0004] Since the outer product algorithm is suitable for processing highly sparse matrices, and the percentage of non-zero elements in matrices involved in graph analysis, machine learning, and large-scale scientific and engineering computing is currently very small, it is essential to optimize and improve the current state-of-the-art SpArch (Reference: Z. Zhang, H. Wang, S. Han and W. J. Dally, "SpArch: Efficient Architecture for Sparse Matrix Multiplication," 2020 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2020.) outer product asynchronous sparse matrix multiplier, based on the outer product algorithm for sparse matrix multiplication.

[0005] The SpArch multiplier incorporates a parallel merging unit that sorts matrix data based on their position indices, merges data at the same positions, and finally combines these parallel merging units into a merging tree to complete the merging operation. When the root node of the merging tree is full, data needs to be output to storage, introducing uncertainty into subsequent merging processes because it's impossible to know whether subsequent merging operations will require data already written to storage. Furthermore, test results show that the merging tree accounts for a significant portion of SpArch's area and power consumption, at 60.6% and 55.4%, respectively. Therefore, there is still considerable room for optimization in the data merging operation.

[0006] Furthermore, with the development of integrated circuits, chip integration is becoming increasingly higher. The improvement in chip performance and the reduction in chip area can no longer be synchronized as before; that is, Moore's Law is gradually becoming less applicable. Achieving higher clock frequencies, better performance, higher integration, and lower circuit power consumption has become the future trend of integrated circuit development. This is very challenging for synchronous circuits, as power consumption often increases along with improvements in the other two performance metrics. Simultaneously, in synchronous clock circuit design, as the design scale increases, clock skew and clock jitter become increasingly severe, often requiring a series of measures to address these issues. These solutions, to some extent, further increase the design scale, potentially leading to an increase in chip area. Moreover, large-scale designs often face complex clock routing, which to some extent affects the efficiency of back-end implementation. Furthermore, because synchronous clock circuits consume power even when the circuit is not in operation, they cannot meet the ultra-low power processing requirements of certain special application areas. Summary of the Invention

[0007] The purpose of this invention is to provide an asynchronous sparse matrix external product multiplier based on event-driven circuit design, which aims to solve the problems of complex data merging process and uncertainty in current SpArch multipliers. At the same time, it adopts an event-driven circuit design method to solve the problems of clock jitter and clock skew in current large-scale integrated circuits.

[0008] This invention is implemented as follows: an asynchronous sparse matrix outer product multiplier based on event-driven circuit design. The multiplier includes a storage module, a data scheduling module, a data matching module, an asynchronous calculation module, a data merging module, and a calculation result processing module. The data scheduling module includes a data output module and a data input module. The data output module generates corresponding address information according to scheduling rules and a counter, transmits this address information to the storage module via a handshake signal to retrieve the corresponding left and right matrix data, and finally sends them to the data matching module for sparse matrix matching. The data output module also receives the address information output by the data merging module and sends the corresponding intermediate matrix data to the data merging module to complete the intermediate matrix data merging operation.

[0009] The data input module is used to transmit the address information and data information output by the data merging module to the storage module through a handshake signal to complete the data storage operation after receiving the address information and data information output by the data merging module.

[0010] The data matching module is used to receive the left and right matrix data output by the data scheduling module, and perform corresponding matching according to the index position to ensure the correctness of the subsequent asynchronous calculation module calculation.

[0011] Preferably, the asynchronous calculation module includes a multiply-accumulate unit and an index information processing module; wherein,

[0012] The index information processing module is used to receive the left matrix data and the right matrix data, save the index bits in the left matrix data and the right matrix data, and input the left matrix data and the right matrix data after removing the index bits into the multiply-accumulate unit for calculation.

[0013] The multiply-accumulator is used to perform multiplication operations on the data of the left matrix and the data of the right matrix. The result of the operation is then indexed and added by the index information processing module so that the data merging module can perform subsequent correct merging operations.

[0014] Preferably, the index is composed of the row coordinate index of the left matrix data and the column coordinate index of the right matrix.

[0015] Preferably, the data merging module includes an address generator, a data detector, and an adder; wherein,

[0016] The address generator is used to complete address mapping by parsing data index information and generate storage addresses;

[0017] The data detector is used to detect the storage address and then activate the handshake signal of the corresponding SRAM, and then retrieve the corresponding intermediate matrix data through the data output module in the data scheduling.

[0018] The adder is used to perform the combined calculation of the output data of the asynchronous calculation module and the output data of the storage module, and then transmit the result to the storage module for storage through the data input module.

[0019] Preferably, the calculation result processing module further includes an error information processing module and a stop information processing module; wherein,

[0020] The data merging module is also used to accumulate the calculation results of the asynchronous calculation module according to the index information, and at the same time output an overflow flag to the error information processing module in the calculation result information processing.

[0021] The data merging module is also used to accumulate the calculation results of the asynchronous calculation module according to the index information and output a flag to the output error information processing module;

[0022] The error information processing module is used to receive and judge the overflow flag output by the data merging module. If the overflow flag is judged to be 1, the overflow information is output to the outside and the operation of the entire sparse matrix outer product multiplier is stopped. If the overflow flag is judged to be 0, the merging result is written to the storage module through the data input module of the data scheduling.

[0023] The stop information processing module is used to determine whether all calculations have been completed based on the calculation result index flag bit output by the asynchronous calculation module. If not completed, it continues to send a handshake signal to the data merging module to ensure that the sparse matrix multiplication operation continues. If the end flag bit is detected, it outputs the stop information to the outside and stops the operation of the entire sparse matrix outer product multiplier.

[0024] Preferably, the calculation result processing module is also used to process error information or stop information of this operation, generate the final calculation result according to different information, and output the result to the outside to inform the outside of the completion status of this sparse matrix operation.

[0025] Compared with the shortcomings and deficiencies of existing technologies, the present invention has the following beneficial effects:

[0026] (1) A clear, straightforward, and simple data merging method avoids uncertainty in the merging process.

[0027] The key bottleneck limiting the performance of outer product methods lies in merging the intermediate matrices, as this involves not only storage access but also complex data processing to ensure correct merging. The SpArch multiplier first designed a merging unit and, to improve parallelism, hierarchically combined these units to create a layered merging unit. Finally, multiple layered merging units are stacked to form a merging tree to achieve the merging process. However, its most basic merging unit actually sorts the matrix data based on their position indices, merging data with the same index. This sorting requires significant hardware resources, increasing the multiplier's power consumption. Furthermore, in practice, due to hardware limitations, it's often impossible to complete all merging operations before writing the data to storage. Therefore, the merging process is uncertain, as it's impossible to know whether subsequent merging operations will require data already written to storage. This asynchronous sparse matrix outer product multiplier, however, adopts a merging strategy that explicitly associates data with storage addresses. It maps matrix data address indices to corresponding addresses in the storage module; identical indices indicate identical storage locations, meaning a merging operation is necessary. This strategy ensures the determinism of the data merging process and avoids complex sorting operations.

[0028] (2) Low power consumption advantage of event-driven clockless circuits

[0029] Currently, most mainstream asynchronous sparse matrix external product multipliers are designed using synchronous clock circuits. However, as the design scales up, clock skew and jitter become increasingly severe, often requiring additional measures to address these issues. These solutions, to some extent, further increase the design scale, potentially leading to increased chip area and consequently higher power consumption. In contrast, the event-driven, clockless circuit used in this multiplier effectively mitigates some of the problems associated with synchronous circuits because it lacks a built-in clock and uses an asynchronous controller to manage data transmission. Furthermore, it features low power consumption, high adaptability, and a degree of electromagnetic interference immunity, making it suitable for processing scenarios requiring ultra-low power consumption. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the structure of an asynchronous sparse matrix outer product multiplier;

[0031] Figure 2 This is a structural diagram of the data scheduling module;

[0032] Figure 3 This is a schematic diagram of the asynchronous computing module.

[0033] Figure 4 This is a structural diagram of the data merging module;

[0034] Figure 5This is a schematic diagram of the calculation result processing module;

[0035] Figure 6 This is a schematic diagram of the Click asynchronous controller. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0037] like Figure 1 As shown, the multiplier includes a storage module, a data scheduling module, a data matching module, an asynchronous computation module, a data merging module, and a computation result processing module. Addressing the shortcomings of existing technologies, the asynchronous sparse matrix outer product multiplier disclosed in this embodiment of the invention has the following structure for its data scheduling module: Figure 2 As shown, this module is mainly divided into two modules: data output and data input. First, the data output module generates corresponding address information according to the scheduling rules and counters. It then transmits this address information to the storage module via a handshake signal to retrieve the corresponding left and right matrix data, and finally sends it to the data matching module for sparse matrix matching. Simultaneously, the data output module also receives address information from the data merging module and sends the corresponding intermediate matrix data to the data merging module to complete the intermediate matrix data merging operation. The data input module, after receiving the address and data information from the data merging module, transmits this information to the storage module via a handshake signal to complete the data storage operation. Correspondingly, the data matching module receives the left and right matrix data output by the data scheduling module and performs corresponding matching according to the index bits to ensure the correctness of the subsequent asynchronous calculation module's calculations.

[0038] Correspondingly, the asynchronous computing module, such as Figure 3 As shown, the system includes a multiply-accumulate unit and an index information processing module. The index information processing module receives left and right matrix data, saves the index bits in the left and right matrix data, and inputs the left and right matrix data (with the index bits removed) into the multiply-accumulate unit for calculation. The multiply-accumulate unit performs multiplication on the left and right matrix data, and the result is then indexed again by the index information processing module for subsequent correct merging operations by the data merging module.

[0039] The asynchronous calculation module first receives the left and right matrix data. The index information processing module then saves the index bits in the left and right matrix data (the index bit represents the coordinate position of the data in the matrix; for example, in this invention, the row coordinate index has 7 bits, and the column coordinate index has 7 bits, meaning both the left and right matrix indexes are 14 bits, and are composed of row-first, then column coordinate indices). After saving, the left and right matrix data, with the index bits removed, are input into the multiply-accumulate unit for calculation. The multiply-accumulate unit performs multiplication on the left and right matrix data. After the calculation, the result is again indexed by the index information processing module. The indexing process involves adding index bits to the calculation result so that the subsequent data merging module can perform the correct merging operation. The index bits are composed of the row coordinate indices of the previous left matrix data and the column coordinate indices of the right matrix.

[0040] The key bottleneck limiting the performance of outer product methods lies in merging the intermediate matrices, as this involves not only storage access but also complex data processing to ensure correct merging. Existing SpArch multipliers first design a merging unit, and to improve parallelism, they hierarchically combine these units to create layered merging units, ultimately stacking multiple layered units to form a merging tree. However, their most basic merging unit actually sorts the matrix data based on its position index, merging data with the same index. This sorting requires significant hardware resources, increasing multiplier power consumption. Furthermore, in practical implementations, due to hardware limitations, it's often impossible to complete all merging operations before writing the data to storage. Therefore, the merging process is uncertain, as it's impossible to know whether subsequent merging operations will require data already written to storage. This invention's asynchronous sparse matrix outer product multiplier adopts a merging strategy that explicitly associates data with storage unit addresses. It maps matrix data address indices to corresponding addresses in the storage module; identical indices indicate identical storage locations, meaning a merging operation is necessary. This strategy ensures the determinism of the data merging process and avoids complex sorting operations.

[0041] Based on this, specifically, the data merging module of the present invention includes an address generator, a data detector, and an adder; the specific structure is as follows: Figure 4 As shown, the address generator is used to complete the address mapping by parsing the data index information and generate the storage address; the data detector is used to detect the storage address and then activate the handshake signal of the corresponding SRAM, and then retrieve the corresponding intermediate matrix data through the data output module in the data scheduling; the adder is used to complete the merging calculation of the output data of the asynchronous calculation module and the output data of the storage module and transmit the result to the storage module for storage through the data input module.

[0042] In this invention, the data merging module first uses an arbitrator that responds to handshake signals according to a "first-come, first-served" principle, thus achieving the goal of receiving the calculation results from multiple asynchronous computing modules. Next, the address generator parses the data index information to complete address mapping and generate storage addresses. Because the storage module consists of multiple SRAM chips, the data detector needs to detect the storage address to activate the corresponding SRAM's handshake signal. Then, the data output module in the data scheduler retrieves the corresponding intermediate matrix data, completing the preparatory work before merging. The adder ultimately completes the merging calculation of the output data from the asynchronous computing module and the storage module. The final calculation result is still transmitted to the storage module for storage by the data input module in the data scheduler. After all matrix data calculations are completed, the intermediate matrix merging operation is also completed, avoiding situations where the merging status of some data elements is uncertain. The data merging module accumulates the calculation results from the asynchronous computing modules according to the index information and simultaneously outputs an overflow flag to the error information processing module in the calculation result information processing.

[0043] To facilitate understanding of the calculation process and results, such as Figure 5 As shown, the calculation result processing module also includes an error information processing module and a stop information processing module. The error information processing module receives and judges the overflow flag output by the data merging module. If the overflow flag is 1, the overflow information is output externally, and the entire sparse matrix outer product multiplier is stopped. If the overflow flag is 0, the merged result is written to the storage module through the data input module of the data scheduling module. The stop information processing module determines whether all calculations are complete based on the calculation result flag output by the asynchronous calculation module. If not, it continues to send a handshake signal to the data merging module to ensure the sparse matrix multiplication operation continues. If an end flag is detected, the stop information is output externally, and the entire sparse matrix outer product multiplier is stopped. The final calculation result processing module processes the error or stop information of this operation, generates the final calculation result based on the different information, and outputs the result externally to inform the outside world of the completion status of this sparse matrix operation.

[0044] Currently, most mainstream asynchronous sparse matrix external product multipliers are designed using synchronous clock circuits. However, as the design scale increases, clock skew and jitter become increasingly severe, often requiring additional measures to address these issues. These solutions, to some extent, further increase the design scale, potentially leading to increased chip area and consequently higher power consumption. In contrast, the event-driven, clockless circuit used in the multiplier of this invention effectively mitigates some of the problems associated with synchronous circuits because there is no clock within the circuit and data transmission is controlled by an asynchronous controller. Furthermore, it features low power consumption, high adaptability, and a certain degree of electromagnetic interference immunity, making it suitable for processing scenarios requiring ultra-low power consumption.

[0045] The entire asynchronous controller structure is as follows: Figure 6 As shown, the multiplier processes the four handshake signals inR, inA, outR, and outA through its structure to generate a fire pulse signal. This fire pulse signal is then connected to the CK terminal of the D flip-flop (DFF). Ultimately, the D flip-flop controls and transmits data by detecting the fire signal, unlike synchronous clock circuits which control and transmit data by detecting the clock signal. Each module in the multiplier contains multiple asynchronous controllers, each performing a specific function. These asynchronous controllers are then combined to complete the function of the entire module and the entire multiplier.

[0046] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An asynchronous sparse matrix outer product multiplier based on event-driven circuit design, the multiplier comprising a storage module, a data scheduling module, a data matching module, an asynchronous calculation module, a data merging module, and a calculation result processing module; characterized in that, The data scheduling module includes a data output module and a data input module. The data output module is used to generate corresponding address information according to the scheduling rules and counters, and transmit the address information to the storage module through a handshake signal to retrieve the corresponding left matrix data and right matrix data, and finally send them to the data matching module for sparse matrix matching operation. The data output module is also used to receive the address information output by the data merging module and send the corresponding intermediate matrix data to the data merging module to complete the intermediate matrix data merging operation. The data input module is used to transmit the address information and data information output by the data merging module to the storage module through a handshake signal to complete the data storage operation after receiving the address information and data information output by the data merging module. The data matching module is used to receive the left and right matrix data output by the data scheduling module, and perform corresponding matching according to the index position to ensure the correctness of the subsequent asynchronous calculation module calculation. The asynchronous calculation module includes a multiply-accumulate unit and an index information processing module; wherein... The index information processing module is used to receive the left matrix data and the right matrix data, save the index bits in the left matrix data and the right matrix data, and input the left matrix data and the right matrix data after removing the index bits into the multiply-accumulate unit for calculation. The multiply-accumulator is used to perform multiplication operations on the data of the left matrix and the data of the right matrix. The result of the operation is then indexed and added by the index information processing module so that the data merging module can perform subsequent correct merging operations.

2. The asynchronous sparse matrix outer product multiplier as described in claim 1, characterized in that, The index is composed of the row coordinate index of the left matrix data and the column coordinate index of the right matrix.

3. The asynchronous sparse matrix outer product multiplier as described in claim 1, characterized in that, The data merging module includes an address generator, a data detector, and an adder; wherein... The address generator is used to complete address mapping by parsing data index information and generate storage addresses; The data detector is used to detect the storage address and then activate the handshake signal of the corresponding SRAM, and then retrieve the corresponding intermediate matrix data through the data output module in the data scheduling. The adder is used to perform the combined calculation of the output data of the asynchronous calculation module and the output data of the storage module, and then transmit the result to the storage module for storage through the data input module.

4. The asynchronous sparse matrix outer product multiplier as described in claim 1, characterized in that, The calculation result processing module also includes an error information processing module and a stop information processing module; wherein... The data merging module is also used to accumulate the calculation results of the asynchronous calculation module according to the index information, and at the same time output an overflow flag to the error information processing module in the calculation result information processing; the error information processing module is used to receive and judge the overflow flag output by the data merging module. If the overflow flag is judged to be 1, the overflow information is output to the outside and the work of the entire sparse matrix outer product multiplier is stopped. If the overflow flag is judged to be 0, the merging result is written to the storage module through the data input module of the data scheduling. The stop information processing module is used to determine whether all calculations have been completed based on the calculation result index flag bit output by the asynchronous calculation module. If not completed, it continues to send a handshake signal to the data merging module to ensure that the sparse matrix multiplication operation continues. If the end flag bit is detected, it outputs the stop information to the outside and stops the operation of the entire sparse matrix outer product multiplier.

5. The asynchronous sparse matrix outer product multiplier as described in claim 4, characterized in that, The calculation result processing module is also used to process error information or stop information of this operation, generate the final calculation result according to different information, and output the result to the outside to inform the outside of the completion status of this sparse matrix operation.

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