An afifo-based chip internal signal waveform acquisition and storage method and device

Abstract

The present application relates to chip design technical field, provide a kind of based on AFIFO's chip internal signal waveform acquisition storage method and device.The method includes: chip has default trigger condition, the internal signal data satisfying default trigger condition is collected, and the internal signal data satisfying default trigger condition is written in AFIFO in chip interior;When the internal storage of AFIFO has been written full, continue to write subsequent internal signal data in AFIFO before the internal signal data previously written in AFIFO is overwritten.The present application is integrated by internal signal acquisition function in chip interior, and sets default trigger condition, directly collects the internal signal of chip, realizes the observation to the internal signal of chip, and, the present application also considers the finiteness of chip internal storage space, and by using new acquisition data to cover previously collected data, ensure that the data obtained during debugging is always the expected observation data for the debugging personnel, to facilitate debugging.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip design technical field, particularly to a chip internal signal waveform collection and storage method and device based on AFIFO. BACKGROUND

[0002] In the prior art, during the early stage of chip design, it is usually necessary to observe the internal signals of the chip through debugging means. The most commonly used method in the prior art is to use the JTAG (Joint Test Action Group) protocol standard, reserve a special debugging interface in the chip, that is, reserve a debugging IO (Input / output), and in the case of insufficient IO resources, the application of this method is limited. In this case, how to collect and store the internal signals of the chip and observe the expected internal signals of the chip for chip debugging has become a technical difficulty to be solved.

[0003] Therefore, overcoming the defects of the prior art is an urgent problem to be solved in the technical field. SUMMARY

[0004] The technical problem to be solved by the present application is how to collect and store the internal signals of the chip and observe the expected internal signals of the chip for chip debugging in the case of insufficient IO resources.

[0005] In a first aspect, the present application provides a chip internal signal waveform collection and storage method based on AFIFO, comprising:

[0006] The chip uses a default trigger condition to collect internal signal data satisfying the default trigger condition, and writes the internal signal data satisfying the trigger condition into an AFIFO in the chip;

[0007] When the internal storage of the AFIFO is full, it is selected according to the debugging requirement whether to continue to write subsequent internal signal data into the AFIFO, and the subsequent internal signal data is used to overwrite the data already written into the AFIFO.

[0008] Preferably, the subsequent internal signal data is written into the AFIFO, and the subsequent internal signal data is used to overwrite the data already written into the AFIFO, specifically comprising:

[0009] Discarding the earliest data written into the AFIFO, releasing the storage location at the head of the AFIFO; moving the data stored in the AFIFO to the head of the AFIFO as a whole, so that an unoccupied storage location appears at the tail of the AFIFO; and writing the subsequent internal signal data into the unoccupied storage location at the tail of the AFIFO;

[0010] Or using subsequent internal signal data to directly overwrite the data of the head of the AFIFO, and making the AFIFO form a head-tail connected ring storage structure by moving the position of the pointer of the AFIFO.

[0011] Preferably, the making the AFIFO form a head-tail connected ring storage structure by moving the position of the pointer of the AFIFO specifically comprises:

[0012] After using subsequent internal data to overwrite the data of the head of the AFIFO, the initial read pointer of the AFIFO is moved one position in the direction of the tail of the AFIFO, and the write pointer is moved to the position of the subsequent internal data.

[0013] In the second aspect, the application further provides a chip internal signal waveform acquisition and storage method based on an AFIFO, which uses an overwrite enable indication signal to control whether subsequent internal signal data is continuously written into the AFIFO after the AFIFO is full, and specifically comprises:

[0014] If the overwrite enable indication signal is enabled, the chip internal signal waveform acquisition and storage method based on an AFIFO in the first aspect is executed.

[0015] If the overwrite enable indication signal is not enabled, when the internal storage of the AFIFO is full, subsequent internal signal data is no longer continuously written into the AFIFO.

[0016] In the third aspect, the application further provides a chip internal signal waveform acquisition and storage method based on an AFIFO, which comprises:

[0017] If the internal signal data satisfying the preset trigger condition is located before the preset trigger point position, the data stored at the preset trigger point position is made to be the internal signal data satisfying the preset trigger condition by overall translation of the data.

[0018] If the internal signal data satisfying the preset trigger condition is located after the preset trigger point position, the data stored at the preset trigger point position is made to be the internal signal data satisfying the preset trigger condition by using the chip internal signal waveform acquisition and storage method based on an AFIFO in the first aspect.

[0019] Preferably, the making the data stored at the preset trigger point position to be the internal signal data satisfying the preset trigger condition by overall translation of the data specifically comprises:

[0020] The overall internal signal data in the AFIFO is translated backward until the internal signal data satisfying the preset trigger condition reaches the preset trigger point position.

[0021] Continuously write the internal signal data satisfying the default trigger condition into the AFIFO until the number of data after the preset trigger point position reaches the target number.

[0022] Preferably, the method further comprises:

[0023] After all the internal signal data in the AFIFO is shifted backward as a whole, write preset data into the storage location not occupied by the head of the AFIFO.

[0024] Preferably, the AFIFO-based chip internal signal waveform acquisition and storage method of the first aspect is used to store data at the preset trigger point position as internal signal data satisfying a preset trigger condition, and specifically comprises:

[0025] The AFIFO-based chip internal signal waveform acquisition and storage method of the first aspect is used to write internal signal data satisfying a default trigger condition after the position of the internal signal data satisfying the preset trigger condition.

[0026] Record the number of internal signal data satisfying the default trigger condition written after the position of the internal signal data satisfying the preset trigger condition, and if the number is less than the target number, continue to write data into the AFIFO until the number of internal signal data satisfying the default trigger condition written after the position of the internal signal data satisfying the preset trigger condition reaches the target number.

[0027] Preferably, the target number is calculated according to the preset trigger point position and the storage depth of the AFIFO, and specifically comprises:

[0028] The number of storage locations between the tail of the AFIFO and the preset trigger point position is used as the target number.

[0029] In a fourth aspect, the present application further provides an AFIFO-based chip internal signal waveform acquisition and storage device, which comprises:

[0030] An acquisition module is configured to acquire internal signal data satisfying a default trigger condition and write the internal signal data into an AFIFO in the chip.

[0031] A write module is configured to continue to write subsequent internal signal data into the AFIFO when the internal storage of the AFIFO has been written full, and use the subsequent internal signal data to overwrite the data already written into the AFIFO.

[0032] In a fifth aspect, the present application further provides an electronic device, which comprises:

[0033] A processor;

[0034] a memory in communication connection with the processor;

[0035] The memory stores instructions executable by the processor, and the instructions are executed by the processor to enable the processor to perform the AFIFO-based chip internal signal waveform acquisition and storage method as described above.

[0036] In a sixth aspect, the present application further provides a non-volatile computer storage medium, which stores computer executable instructions, and the computer executable instructions are executed by one or more processors to complete the AFIFO-based chip internal signal waveform acquisition and storage method as described above.

[0037] The present application integrates the function of internal signal acquisition and storage in the chip, sets a default trigger condition, directly acquires the internal signals of the chip, realizes the observation of the internal signals of the chip, and further uses the mode of covering the newly acquired data with the later acquired data to ensure that the data obtained during debugging is always the desired observation data, thereby facilitating the debugging. BRIEF DESCRIPTION OF DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0039] Figure 1 is a flowchart of an AFIFO-based chip internal signal waveform acquisition and storage method provided by the embodiments of the present application;

[0040] Figure 2 is a flowchart of an AFIFO-based chip internal signal waveform acquisition and storage method provided by the embodiments of the present application;

[0041] Figure 3 is a schematic diagram of an AFIFO-based chip internal signal waveform acquisition and storage method provided by the embodiments of the present application;

[0042] Figure 4 is a flowchart of an AFIFO-based chip internal signal waveform acquisition and storage method provided by the embodiments of the present application;

[0043] Figure 5 is a schematic diagram of an AFIFO-based chip internal signal waveform acquisition and storage method provided by the embodiments of the present application;

[0044] Figure 6A chip module schematic diagram applied by a chip internal signal waveform collection and storage method based on AFIFO provided by the embodiment of the present application is shown in FIG. 1.

[0045] Figure 7 A schematic diagram of a chip internal signal waveform collection and storage method based on AFIFO provided by the embodiment of the present application is shown in FIG. 2.

[0046] Figure 8 A flowchart of a chip internal signal waveform collection and storage method based on AFIFO provided by the embodiment of the present application is shown in FIG. 3.

[0047] Figure 9 A flowchart of a chip internal signal waveform collection and storage method based on AFIFO provided by the embodiment of the present application is shown in FIG. 4.

[0048] Figure 10 A flowchart of a chip internal signal waveform collection and storage method based on AFIFO provided by the embodiment of the present application is shown in FIG. 5.

[0049] Figure 11 A schematic diagram of a chip internal signal waveform collection and storage method based on AFIFO provided by the embodiment of the present application is shown in FIG. 6.

[0050] Figure 12 A schematic diagram of a chip internal signal waveform collection and storage method based on AFIFO provided by the embodiment of the present application is shown in FIG. 7.

[0051] Figure 13 A flowchart of a chip internal signal waveform collection and storage method based on AFIFO provided by the embodiment of the present application is shown in FIG. 8.

[0052] Figure 14 A flowchart of a chip internal signal waveform collection and storage method based on AFIFO provided by the embodiment of the present application is shown in FIG. 9.

[0053] Figure 15 An architecture schematic diagram of a chip internal signal waveform collection and storage device based on AFIFO provided by the embodiment of the present application is shown in FIG. 10.

[0054] Figure 16 A structure block diagram of an electronic device of the embodiment of the present application is shown in FIG. 11. DETAILED DESCRIPTION

[0055] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application.

[0056] In the description of the present application, the terms "inner", "outer", "longitudinal", "transverse", "upper", "lower", "top", "bottom" and the like indicate the orientation or positional relationship shown in the drawings, which are only for the convenience of describing the present application and are not required to be constructed and operated in a particular orientation, and therefore should not be understood as a limitation on the present application.

[0057] In addition, the technical features involved in each embodiment of the present application described below can be combined with each other as long as there is no conflict.

[0058] The embodiment of the present application provides a chip internal signal waveform acquisition and storage method based on an AFIFO, as shown in the figure, comprising: Figure 1

[0059] In step 201, the chip acquires internal signal data satisfying a default trigger condition and writes the internal signal data satisfying the default trigger condition into an AFIFO inside the chip; wherein the chip has a default trigger condition.

[0060] In step 202, when the internal storage of the AFIFO is full, continue to write subsequent internal signal data into the AFIFO, and use the subsequent internal signal data to overwrite the data already written into the AFIFO.

[0061] Wherein, the asynchronous FIFO internal signal storage device is collectively referred to as AFIFO.

[0062] The embodiment integrates the function of internal signal acquisition inside the chip and sets a default trigger condition, directly acquires the internal signal of the chip, realizes the observation of the expected internal signal of the chip, and considers the finiteness of the internal storage space of the chip, and also uses the newly acquired data to overwrite the later acquired data, so as to ensure that the data obtained during debugging is always the latest expected observation data, thereby facilitating debugging.

[0063] In actual situations, the reading and writing of the data of the AFIFO is in order, the AFIFO follows the first-in-first-out reading and writing rule, and the data is usually read from the head of the AFIFO and written from the tail of the AFIFO, when the internal storage of the AFIFO is full, therefore, the earliest written data is located at the head of the AFIFO, if the data at the head is directly overwritten by new data, the order of the AFIFO data reading will be disordered, in order to solve this problem, there is the following preferred embodiment, that is, the subsequent internal signal data is continuously written into the AFIFO, and the subsequent internal signal data is used to overwrite the data already written into the AFIFO, as shown in the figure, specifically comprising: Figure 2

[0064] ​​In step 301, the data written earliest into the AFIFO is discarded, so that the storage position at the head of the AFIFO is released.

[0065] In step 302, the data stored in the AFIFO is moved as a whole to the head of the AFIFO, so that an unoccupied storage position appears at the tail of the AFIFO.

[0066] In step 303, the subsequent internal signal data is written into the unoccupied storage position at the tail of the AFIFO.

[0067] As shown in Figure 3 , the AFIFO has n storage positions, when the n storage positions are successively occupied by data0 to data n , at this time, the newly collected internal signal data data n+1 that satisfies the trigger condition is written into the unoccupied storage position at the tail of the AFIFO. n , at this time, the newly collected internal signal data data n+1 that satisfies the trigger condition is written into the unoccupied storage position at the tail of the AFIFO.

[0068] Figure 3 The above is the case of writing one data at a time, and one data occupying exactly one storage position. When one data occupies multiple storage positions, or multiple data are written at a time, the whole is translated according to the required storage positions to ensure that the tail is reserved for storing new data.

[0069] There is also an alternative to the above embodiment, as shown in Figure 5 , specifically comprising:

[0070] Using the subsequent internal signal data to directly overwrite the data at the head of the AFIFO, and moving the position of the pointer of the AFIFO to form a ring-shaped storage structure with the head and tail connected.

[0071] The moving of the position of the pointer of the AFIFO to form a ring-shaped storage structure with the head and tail connected, specifically comprises:

[0072] Each time the subsequent internal data is used to overwrite the data at the head of the AFIFO, the initial read pointer of the AFIFO is moved one position in the direction of the tail of the AFIFO, and the write pointer is moved to the position of the subsequent internal data.

[0073] The initial read pointer can be understood as the read position corresponding to the first time the user reads data from the AFIFO.

[0074] It should be noted that the "tail" and "head" of the AFIFO refer to the storage space level. When the storage space occupied by the AFIFO is fixed, its head and tail are also fixed. The "head" and "tail" refer to the storage structure level of the AFIFO, indicating the read and write positions of data. The head and tail may change depending on the positions of the initial read and write pointers. By default, the initial read pointer of the AFIFO points to the head, and the write pointer points to the last written data, meaning the head and tail of the AFIFO coincide. When the AFIFO is full, the tail and tail of the AFIFO coincide. However, when the positions of the initial read and write pointers are manually changed, the head and head may not coincide, and the tail and tail of the AFIFO may also not coincide. The circular storage structure with the head and tail connected refers to the AFIFO having its head and tail connected.

[0075] For example, such as Figure 5 As shown, when AFIFO writes data... n+1 At that time, it is directly written to the header position in the AFIFO, that is Figure 5 At position 0, the initial read pointer Rptx_intial is moved one position towards the tail, i.e., to position 1, and the write pointer is moved to position 0. If data is read at this time, the data reading order is: read from position 1 to position n, and then continue reading the data at position 0.

[0076] When data needs to be written again n+2 When the data is written to position 1, the initial read pointer Rptx_intial moves to position 2, and the write pointer moves to position 1. If data is read at this time, the data reading order is: read from position 2 to position n, and then continue to read the data from position 0 and position 1 in sequence. This forms a circular data structure.

[0077] Compared to the previous implementation, this alternative solution requires the same amount of storage space. However, the previous implementation, through the overall shift of data, only requires attention to the control of the data writing end, while the control of the reading end can be satisfied by simply reading data according to the ordinary AFIFO design, that is, control is performed from the data writing.

[0078] In this alternative approach, the focus during data writing is primarily on controlling the initial read pointer. The data writing end does not need to perform a complete data shift and can directly write the data into the AFIFO, i.e., control is achieved from reading the data.

[0079] Both methods require the same amount of storage space, but since they focus on different aspects, those skilled in the art can analyze and choose the appropriate method based on their debugging and data reading / writing needs.

[0080] In actual use, the debug personnel can also wish to control whether to perform data override, and for this requirement, the embodiment also provides an AFIFO-based chip internal signal waveform acquisition and storage method, which uses an override enable indication signal to control whether to continue writing subsequent internal signal data after the AFIFO is full, as shown in Figure 4 , and specifically includes:

[0081] In step 401, if the override enable indication signal is enabled, the AFIFO-based chip internal signal waveform acquisition and storage method described above is performed. The override enable indication signal will also use COVER_EN as its alternative expression in the subsequent.

[0082] In step 402, if the override enable indication signal is not enabled, when the internal storage of the AFIFO is full, subsequent internal signal data is no longer written into the AFIFO.

[0083] It should be noted that the focus of the embodiment is the processing when the internal storage of the AFIFO is full, and before the internal storage of the AFIFO is full in step 402, the process of collecting internal signal data that meets the trigger condition by the chip and writing the internal signal data that meets the trigger condition into the AFIFO in the chip in the above embodiment is still performed.

[0084] The embodiment works in a corresponding chip, which, as shown in Figure 6 , includes an AFIFO write control module, an AFIFO storage module, and an AFIFO read control module, wherein the input signals of the AFIFO write control module include INPUT_SIGNALS (chip internal signals that need to be viewed, which can be a multi-bit wide signal or a combination of multiple signals).

[0085] TIGGER_EN (chip internal signal trigger condition storage enable signal, as shown in Figure 14 , if the signal is enabled, how to write the subsequent internal signal data and adjust the storage position of the data previously written into the AFIFO (step 803 as shown in Figure 14 ) according to the debugging requirements, that is, the process described in the above embodiment, which is not repeated here; if the signal is not enabled, the processes described in steps 401 to 402 are performed).

[0086] TRIGGER_CONDITION (chip internal signal trigger condition setting, which can be set by, such as equal to a specific value, or the logical AND, logical OR, or logical NOT between different groups of internal signals between multiple modules, but not limited to these conditions).

[0087] COVER_EN (cover enable indication signal, if the signal is enabled, when the internal storage of AFIFO is full, the data stored in AFIFO can continue to be stored and the data written at the beginning can be covered; if the signal is not enabled, when the internal storage of AFIFO is full, even if the internal signal signal that meets the trigger condition is valid, it will not continue to be stored in AFIFO).

[0088] The input signals of the AFIFO write control module include TRIGGER_POS (trigger point position information) and WFULL (AFIFO full flag signal), and the AFIFO write control module controls the storage data written into the AFIFO storage module and the corresponding storage position in the AFIFO according to the input. The input signals of the AFIFO read control module include RDEN (read enable signal) and EMPTY (AFIFO read empty flag signal), and the AFIFO read control module controls the data read from the AFIFO storage module according to the input.

[0089] When the cover enable indication signal COVER_EN is enabled, the input signal TRIGGER_EN of the AFIFO write module should be set to 1'b0, and the cover enable function will be started only when the number of times that the internal trigger signal meets the default trigger condition exceeds the storage depth of AFIFO (that is, the number of stored data exceeds the number of storage positions in AFIFO). During the whole chip working process, if the number of times that the internal signal storage trigger is less than the storage depth of AFIFO, that is, the internal storage of AFIFO is not full, the write control of AFIAO will write data into AFIFO according to the general AFIFO characteristics (that is, write from the tail direction).

[0090] As shown in Figure 3 , in the case that the AFIFO storage has been full, the latest valid internal signal will be written into the last address of AFIFO, and the data stored in AFIFO will be moved forward by one address accordingly, and the earliest written data will be discarded. The purpose of this is to ensure that when reading the internal signal data stored in AFIFO, the change process of the stored internal signal in the chip working can still be known clearly.

[0091] When the cover enable indication signal COVER_EN is not enabled, as shown in Figure 7 , if the internal storage of AFIFO has been full, that is, the number of times that the internal signal data meets the default trigger condition is greater than the storage depth of AFIFO, the latest collected internal signal data that meets the default trigger condition will be discarded and will not be written into the AFIFO storage module, as shown in Figure 7 , where the internal storage of AFIFO has been full, the latest collected data data n+1Discarded.

[0092] In this embodiment, in the case that the AFIFO storage has been written full, if the cover enable indication signal COVER_EN is valid, the latest valid internal signal will be written into the last address of the AFIFO, and the data stored in the AFIFO will be moved forward by one address accordingly, and the earliest written data will be discarded. The purpose of this is to ensure that when the internal signal information stored in the AFIFO is read subsequently, the change process of the stored internal signal during the operation of the chip can still be known clearly.

[0093] In actual use, the debugging personnel may also need to view a certain specific signal and the signal change before or after the appearance of the specific signal. For example, the debugging personnel wants to observe 50 signals after the appearance of a specific signal a, and in the case of limited internal storage space, when the specific signal a is stored at the head of the AFIFO, the data before the specific signal a cannot be effectively stored, or when the specific signal a is stored at the tail of the AFIFO, the data after the specific signal a cannot be effectively stored. To solve this problem, this embodiment also provides an AFIFO-based chip internal signal waveform acquisition and storage method, as shown in Figure 8 , which comprises the following steps.

[0094] In step 501, if the internal signal data satisfying the preset trigger condition is located before the preset trigger point position, the data stored at the preset trigger point position is made to be the internal signal data satisfying the preset trigger condition through overall translation of the data.

[0095] The preset trigger condition is equivalent to the setting trigger condition in the above embodiment, and this embodiment can be regarded as an AFIFO-based chip internal signal waveform acquisition and storage method realized under the condition that the TRRIGGER_EN enable in the above embodiment. It should be noted that this embodiment is still realized on the basis of the process of collecting internal signal data satisfying a trigger condition and writing the internal signal data satisfying the trigger condition into the AFIFO in the chip.

[0096] The data satisfying the default condition may appear multiple times, and the internal signal data satisfying the preset trigger condition usually refers to the first obtained internal signal satisfying the preset trigger condition after the TRRIGGER_EN enable. As long as the data satisfying the default trigger condition is collected, it will be stored in the AFIFO, and there may be internal signal data satisfying the preset trigger condition, that is, the range of the default trigger condition is greater than the setting range of the setting trigger condition, and the signal satisfying the setting trigger condition must satisfy the default trigger condition.

[0097] In step 502, if the internal signal data satisfying the preset trigger condition is located after the preset trigger point position, the data stored at the preset trigger point position is the internal signal data satisfying the preset trigger condition by using the chip internal signal waveform collection and storage method based on AFIFO as described above.

[0098] The preset trigger point position is obtained by a debugging personnel or a person skilled in the art according to debugging requirement analysis, and a corresponding space is reserved before or after the preset trigger point position to store the signals appearing before or after the internal signal satisfying the preset trigger condition, so as to satisfy the requirement of the debugging personnel to observe the signal change before or after the specific signal appears. The preset trigger point position can be understood as TRIGGER POS (trigger point position information) in another embodiment.

[0099] It should be noted that the "before" and "after" are described with respect to the AFIFO queue, wherein the direction close to the AFIFO queue head is the front direction, and the direction close to the AFIFO queue tail is the rear direction. That is, the internal signal data satisfying the preset trigger condition located before the preset trigger point position can also be understood as that the storage position of the internal signal data satisfying the preset trigger condition is closer to the AFIFO queue head than the preset trigger point position; the internal signal data satisfying the preset trigger condition located after the preset trigger point position can be understood as that the storage position of the internal signal data satisfying the preset trigger condition is closer to the AFIFO queue tail than the preset trigger point position.

[0100] The preset trigger condition is generally a specific situation appearing during chip debugging, and in actual application scenarios, it is required to view the signal change before and after the specific situation appears. For example, in a debugging application, it is required to view the signal change after the specific situation appears, and at this time, the trigger point position can be set to be close to the front; it is required to view the signal change before the specific situation appears, and at this time, the trigger point position can be set to be close to the rear, so as to satisfy the requirement of the debugging personnel to monitor the signal change before and after the specific data.

[0101] As an optional implementation, the data stored at the preset trigger point position is the internal signal data satisfying the preset trigger condition by overall translation of the data, as shown in Figure 9 The specific implementation includes the following steps.

[0102] In step 601, all the internal signal data in the AFIFO is translated backward as a whole until the internal signal data satisfying the preset trigger condition reaches the preset trigger point position.

[0103] In step 602, continue to write the internal signal data satisfying the default trigger condition into the AFIFO until the number of data located after the preset trigger point position reaches the target number.

[0104] The target number is calculated according to the preset trigger point position and the storage depth of the AFIFO, and specifically includes:

[0105] The number of storage positions between the tail of the AFIFO and the preset trigger point position is taken as the target number.

[0106] In actual cases, the debug personnel usually first obtain the number of data required to be stored after the internal signal data satisfying the preset trigger condition according to the debugging requirements, and determine the preset trigger point position according to the number of data, so that the number of storage positions after the preset trigger point position (i.e. the target number) meets the debugging requirements of the debug personnel.

[0107] After the data is shifted backward as a whole, the head of the AFIFO will have unoccupied storage positions, which will cause reading errors or random numbers during data reading. In order to solve this problem, the embodiment also provides a preferred implementation, as shown in Figure 10 The method further includes:

[0108] In step 603, after shifting all the internal signal data in the AFIFO backward as a whole, write preset data into the unoccupied storage positions at the tail of the AFIFO.

[0109] For example, as shown in Figure 11 TRIGGER_POS is the preset trigger point position, REAL_POS is the internal signal data data real_pos satisfying the preset trigger condition, and REAL_POS is closer to the front than TRIGGER_POS. Shift the data in the AFIFO backward as a whole until, as shown in Figure 12 data real_pos reaches TRIGGER_POS. At this time, due to the backward shift of the data as a whole, the head of the AFIFO will have unoccupied storage positions, and preset data special_data is written into these unoccupied storage positions. The preset data is obtained by experienced analysis and setting by those skilled in the art.

[0110] As an optional implementation, the use of the above-mentioned AFIFO-based chip internal signal waveform acquisition and storage method makes the data stored at the preset trigger point position the internal signal data satisfying the preset trigger condition, as shown in Figure 13 The method specifically includes:

[0111] In step 701, using the AFIFO-based chip internal signal waveform acquisition and storage method described in the above embodiment, after the position of the internal signal data satisfying the preset trigger condition, write the internal signal data satisfying the default trigger condition.

[0112] In step 702, record the number of internal signal data satisfying the default trigger condition written after the position of the internal signal data satisfying the preset trigger condition, and if the number is less than the target number, continue to write data into the AFIFO until the number of internal signal data satisfying the default trigger condition written after the position of the internal signal data satisfying the preset trigger condition reaches the target number.

[0113] After the internal signal satisfying the set trigger condition actually appears after the set trigger point, continue to write M internal signal information satisfying the default trigger condition into the last address of the AFIFO storage module, and in the writing process, record the number N of internal signal data satisfying the default trigger condition appearing after the internal signal satisfying the set trigger condition appears, that is, the number of internal signal data satisfying the default trigger condition collected after the internal signal data satisfying the set trigger condition is collected. Wherein, M can be understood as the target number.

[0114] If N is less than M, the position of the internal signal satisfying the set trigger condition appears relatively late than the set trigger point, write the N internal signal data collected into the AFIFO, and when it is not possible to continue to collect internal signal data satisfying the default trigger condition, write the preset data set by those skilled in the art, and in the writing process, use the method as described above to make the data move forward as a whole until the position of the internal signal satisfying the set trigger condition appears consistent with the set trigger point.

[0115] If N is greater than or equal to M, use the method as described above to write M internal signal information satisfying the default trigger condition into the AFIFO, so that the position of the internal signal satisfying the set trigger condition appears equal to the set trigger point.

[0116] As shown in Figure 15 The architecture schematic diagram of the AFIFO-based chip internal signal waveform acquisition and storage device of the embodiment of the application is shown in the figure. It includes an acquisition module for acquiring internal signal data satisfying a default trigger condition and writing the internal signal data into an AFIFO inside the chip; it also includes a writing module for continuing to write subsequent internal signal data into the AFIFO when the internal storage of the AFIFO has been written full, and using the subsequent internal signal data to overwrite the data already written into the AFIFO.

[0117] The more specific implementation of each module of the AFIFO-based chip internal signal waveform acquisition and storage device of the application can refer to the description of the AFIFO-based chip internal signal waveform acquisition and storage method of the application, and has similar beneficial effects, which will not be repeated here.

[0118] Figure 16 The structural block diagram of the electronic device according to an embodiment of the application includes one or more processors 21 and a memory 22. Among them, Figure 16 In the embodiment, the processor 21 is taken as an example.

[0119] The processor 21 and the memory 22 can be connected by a bus or other means, Figure 16 In the embodiment, the connection by the bus is taken as an example.

[0120] The memory 22 is a kind of non-volatile computer readable storage medium, which can be used to store non-volatile software programs and non-volatile computer executable programs, such as the AFIFO-based chip internal signal waveform acquisition and storage method described above. The processor 21 executes the AFIFO-based chip internal signal waveform acquisition and storage method by running the non-volatile software programs and instructions stored in the memory 22.

[0121] The memory 22 can include a high-speed random access memory, and can also include a non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 22 can optionally include a memory remotely arranged relative to the processor 21, and these remote memories can be connected to the processor 21 through a network. Examples of the above-mentioned network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0122] The program instructions / modules are stored in the memory 22, and when executed by the one or more processors 21, the AFIFO-based chip internal signal waveform acquisition and storage method in the embodiment is executed.

[0123] It is worth noting that the information interaction, execution process, etc. between the modules and units in the above-mentioned device and system, since the same concept as the processing method embodiment of the application, the specific content can refer to the description in the method embodiment of the application, which will not be repeated here.

[0124] Those skilled in the art can understand that all or part of the steps in the various methods of the embodiments can be completed by instructing the related hardware with a program, and the program can be stored in a computer readable storage medium, which can include Read Only Memory (ROM), Random Access Memory (RAM), a magnetic disk or an optical disk, etc.

[0125] The above description is merely the preferred embodiments of the present application, and is not used to limit the present application. Any modification, equivalent replacement and improvement made in the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for acquiring and storing signal waveforms within a chip based on AFIFO, characterized in that, include: Collect internal signal data that meets the default triggering conditions; If the internal signal data that meets the preset trigger condition is located before the preset trigger point position, then all the internal signal data in the AFIFO are shifted backward as a whole until the internal signal data that meets the preset trigger condition reaches the preset trigger point position; continue to write internal signal data that meets the default trigger condition into the AFIFO until the number of data after the preset trigger point position reaches the target number; If the internal signal data that meets the preset trigger condition is located after the preset trigger point position, the internal signal data is written into the AFIFO inside the chip. When the internal storage of the AFIFO is full, subsequent internal signal data is written into the AFIFO. The subsequent internal signal data is used to overwrite the data already written into the AFIFO, so that the data stored at the preset trigger point position is the internal signal data that meets the preset trigger condition.

2. The chip-internal signal waveform acquisition and storage method based on AFIFO according to claim 1, characterized in that, The step of continuing to write subsequent internal signal data into the AFIFO and using the subsequent internal signal data to overwrite the data already written into the AFIFO includes: The earliest data written to the AFIFO is discarded, freeing up the storage space at the head of the AFIFO; the entire data stored in the AFIFO is moved towards the head of the AFIFO, creating an unoccupied storage space at the tail of the AFIFO; the subsequent internal signal data is written into the unoccupied storage space at the tail of the AFIFO. Alternatively, the subsequent internal signal data can be used to directly overwrite the data in the AFIFO header, and the position of the AFIFO pointer can be moved to make the AFIFO form a ring storage structure with the head and tail connected.

3. The chip-internal signal waveform acquisition and storage method based on AFIFO according to claim 2, characterized in that, The step of moving the pointer of the AFIFO to form a ring-shaped storage structure with the head and tail connected includes: Each time the subsequent internal signal data is used to overwrite the data in the AFIFO header, the initial read pointer of the AFIFO is moved one position toward the tail of the AFIFO, and the write pointer is moved to the position where the subsequent internal signal data is located.

4. The chip-internal signal waveform acquisition and storage method based on AFIFO according to claim 1, characterized in that, Also includes: After shifting all internal signal data in the AFIFO backwards, preset data is written to the unoccupied storage location at the head of the AFIFO queue.

5. The chip-internal signal waveform acquisition and storage method based on AFIFO according to claim 1, characterized in that, The data stored at the preset trigger point location as internal signal data that satisfies the preset trigger conditions includes: After the location of the internal signal data that meets the preset triggering condition, write the internal signal data that meets the default triggering condition; Record the number of internal signal data that meet the default trigger condition after the location of the internal signal data that meets the preset trigger condition. If the number is less than the target number, continue to write data into the AFIFO until the number of internal signal data that meet the default trigger condition after the location of the internal signal data that meets the preset trigger condition reaches the target number.

6. The chip-internal signal waveform acquisition and storage method based on AFIFO according to claim 5, characterized in that, The target quantity is calculated based on the preset trigger point position and the storage depth of the AFIFO, with the number of storage positions between the tail of the AFIFO and the preset trigger point position being used as the target quantity.

7. A method for acquiring and storing signal waveforms within a chip based on AFIFO, characterized in that, include: The overwrite enable indicator signal is used to control whether internal signal data continues to be written after the AFIFO is full. If the overlay enable indicator signal is enabled, the chip internal signal waveform acquisition and storage design method based on AFIFO as described in any one of claims 1 to 3 shall be executed. If the overwrite enable indicator signal is not enabled, when the internal storage of the AFIFO is full, no further internal signal data will be written into the AFIFO.

8. A chip-internal signal waveform acquisition and storage device based on AFIFO, characterized in that, include: The acquisition module is used to acquire internal signal data that meets the default triggering conditions; The writing module is used to shift all internal signal data in the AFIFO backwards when the internal signal data meeting the preset trigger conditions is located before the preset trigger point position, until the internal signal data meeting the preset trigger conditions reaches the preset trigger point position; continue writing internal signal data meeting the default trigger conditions into the AFIFO until the number of data after the preset trigger point position reaches the target number; and when the internal signal data meeting the preset trigger conditions is located after the preset trigger point position, write the internal signal data into the AFIFO inside the chip. When the internal storage of the AFIFO is full, continue writing subsequent internal signal data into the AFIFO, using the subsequent internal signal data to overwrite the data already written to the AFIFO, so that the data stored at the preset trigger point position is the internal signal data meeting the preset trigger conditions.

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