A calculation method based on vector processor sorting

Abstract

The present invention provides a vector processor-based sorting operation method, which includes the following two cases: the first case is that the amount of data to be processed is small and the Level 2 Cache (L2Cache) can fully accommodate the data. In this case, all even-numbered column elements are selected from an off-chip memory (DDR) and transferred to the upper half of the L2Cache, and all odd-numbered column elements are selected and transferred to the lower half of the L2Cache. First, the elements in the upper half are compared one-to-one with the elements in the lower half. Then, the staggered elements in the upper half are compared one-to-one with the elements in the lower half. This process is repeated until the end. The second case is that the L2Cache cannot fully accommodate the data to be processed. First, the data in the off-chip memory (DDR) is divided into N+1 blocks according to the size of the L2Cache. The N+1 blocks of data are respectively transferred to the L2Cache and sorting operations are performed according to the first case. Then, data of sizeof(L2Cache) / (N+1) in size is sequentially transferred from each block of the DDR to the L2Cache space to fill the L2Cache. Then, sorting operations are performed according to the first case, with min being the last data sorted at that time. Find the location ddrLocAddr of the smallest data block greater than min in the ordered data blocks in the DDR. Starting from ddrLocAddr, transfer data of sizeof(L2Cache) / (N+1) to the L2Cache space until the L2Cache is full. Then, perform the sorting operation according to the first case. Repeat this process until all data blocks in the DDR are sorted.

Description

Technical Field

[0001] The present invention relates to a data processing algorithm, and more specifically, to an operation method based on vector processor sorting. Background Art

[0002] Vector processors typically consist of multiple processing units, supporting vector-based data loading, operations, and storage. Each processing unit contains multiple independent multifunctional components, typically including addition, multiplication, shifting, and comparison. Vector processors generally support Single Instruction Multiple Data (SIMD) operations. This means that under the control of a single vector instruction, all processing units simultaneously perform the same operation on corresponding local registers, enabling data-level parallelism in application development. To accelerate data access, vector processors typically have an external secondary cache: Level 2 Cache (L2 Cache).

[0003] The parity sorting algorithm is a type of swapping algorithm. First, all elements in odd-numbered columns are compared with their adjacent elements to the right, placing the smaller element first. Then, all elements in even-numbered columns are compared with their adjacent elements to the right, placing the smaller element first. This process is repeated until the sorting is complete. Based on the characteristics of vector processors, the present invention modifies the parity sorting algorithm when the data volume is small and can fit into the L2 cache. When the data volume is large and cannot fit into the L2 cache, data is repeatedly transferred from the off-chip DDR memory to the L2 cache to complete the sorting function.

[0004] A data parallel sorting method and system (CN103530084A) overcomes the shortcomings of existing serial sampling parallel sorting methods by implementing a fast sorting method using a message passing interface. This method eliminates the need for a message passing interface to achieve sorting. A vector sorting method and system (CN112464157B) reads a target vector, generates a sorting position vector from it, and expands it into a transformation matrix. This transformation matrix is ​​then used to sort the target vector. This method eliminates the need for a transformation matrix. Summary of the Invention

[0005] In order to solve the above technical problems, the present invention proposes an operation method based on vector processor sorting.

[0006] The technical solution of the present invention is as follows: comprising the following steps, which are described by taking ascending order as an example:

[0007] Step 1: When the amount of data to be sorted is small and the L2Cache can hold all the data, sorting is performed directly.

[0008] Step 2: When the amount of data to be sorted is large, the L2Cache cannot hold all the data, so the data is sorted in batches.

[0009] The specific method of the above step 1 of the present invention includes the following steps:

[0010] Step 1.1: Select all even-numbered column elements from the DDR and transfer them to the upper half of the L2Cache, and select all odd-numbered column elements and transfer them to the lower half of the L2Cache. When the number of data S is divisible by 2, the first S / 2 data are assumed to be even-numbered column elements, and the rest are odd-numbered column elements. When S is not divisible by 2, the first floor(S / 2)+1 data are assumed to be even-numbered column elements. Floor() means taking the integer and the rest are odd-numbered column elements.

[0011] Step 1.2: compare the elements in the upper half with the elements in the lower half one by one. The elements with smaller values ​​are kept in the upper half, and the elements with larger values ​​are kept in the lower half.

[0012] Step 1.3: compare the element position +1 in the upper half with the elements in the lower half one-to-one. The element with smaller value is kept in the lower half, and the element with larger value is kept in the upper half.

[0013] Step 1.4: Determine whether the permutation is complete. If not, proceed to step 1.2. If the permutation is complete, save the data in the L2Cache to the off-chip memory DDR through index transfer. The sign of the completion of the permutation is that the value of each element in the upper half is less than the corresponding element value in the lower half.

[0014] The specific method of the above step 2 of the present invention includes the following steps:

[0015] Step 2.1: Divide the data in the DDR into N+1 blocks according to the L2Cache size, numbered 0, 1, 2, 3, ..., N. Transfer the N+1 blocks of data to the L2Cache and perform the sorting operation according to step 1. After the operation is completed, transfer them back to the DDR space. At this time, the data from blocks 0 to N are in order.

[0016] Step 2.2: For the 0th time, sequentially transfer data of size sizeof(L2Cache) / (N+1) from each block in the DDR to the L2Cache space. Let the maximum value of the data transferred from each block in the DDR to the L2Cache, that is, the rightmost value, be max00, max01, max02, max03, max…, max0N. Then find the minimum value among all the maximum values, min0=Min(max00,max01,max02,max03,max…,max0N);

[0017] In step 2.3, after each block of data in DDR is transferred to L2Cache, the data needs to be adjusted. The following parameters are used in the adjustment process: num: the total number of data to be sorted; DataNum: the number of data transferred from DDR to L2Cache. At the beginning, DataNum = floor(L2Cache / (N+1))* (N+1), that is, the lower integer of L2Cache / (N+1) multiplied by (N+1). As the calculation proceeds, the data of some blocks will be completely sorted, and DataNum will change; evenCloNum: the number of data in even columns; oddCloNum: the number of data in odd columns; halfL2CacheNum: the number of data that can be stored in half of the L2Cache space; outputAddr: the starting address of the output sorted data. If DataNum is divisible by 2, evenCloNum=oddCloNum=DataNum / 2. If DataNum is not divisible by 2, evenCloNum= floor(DataNum / 2)+1, oddCloNum=floor(DataNum / 2).

[0018] The reason for data adjustment is that, assuming that the number of data processed by the vector processing unit at the same time is a fixed value P, when the vector processing unit takes data from the L2Cache, the starting address of the L2Cache data should be aligned according to P, such as Figure 2 As shown, P = 3, indicating that the vector processing unit can simultaneously compare the sizes of three even-numbered column elements and three odd-numbered column elements. If evenCloNum (the number of even-numbered column elements) > oddCloNum (the number of odd-numbered column elements) + P, or oddCloNum > evenCloNum + P, the sorting algorithm will compare some invalid values ​​and cannot obtain the correct sorting result, so data adjustment is required.

[0019] Data adjustment occurs in two cases. In the first case, when DataNum is less than or equal to halfL2CacheNum, the data between 0 and (evenCloNum - 1) in the L2Cache remains unchanged. The data between evenCloNum and (DataNum - 1) (data length oddCloNum) is transferred from the L2Cache to the DDR starting at outputAddr + num - oddCloNum and with a length of oddCloNum. After the transfer, this data is transferred from the DDR to the L2Cache starting at halfL2CacheNum.

[0020] Case 2: DataNum > halfL2CacheNum. The data between 0 and (evenCloNum - 1) in the L2Cache remains unchanged. The data between evenCloNum and (halfL2CacheNum - 1) (data length is halfL2CacheNum - evenCloNum) is transferred from the L2Cache to the DDR starting at outputAddr + num - (halfL2CacheNum - evenCloNum) and with a length of halfL2CacheNum - evenCloNum. After the transfer is complete, this data is transferred from the DDR to the L2Cache starting at DataNum.

[0021] In step 2.4, after the data is transferred to the L2Cache, the sort operation is performed according to step 1. After the operation is completed, the result data is returned to the DDR data space. In the DDR result data returned by the L2Cache, the location loc0Addr of the min0 value is found. The data from location 0 to loc0Addr is the final sorted data for the 0th time.

[0022] Step 2.5: For the first pass, find the location ddrLocAddr of the smallest data block greater than min0 from each block of sorted data in the DDR. Starting at ddrLocAddr, transfer data of sizeof(L2Cache) / (N+1) to the L2Cache space. Let the maximum value of the data transferred from each block in the DDR to the L2Cache, i.e., the rightmost value, be max10, max11, max12, max13, max…, max1N. Then, find the minimum value among all the maximum values: min1 = Min(max10, max11, max12, max13, max…, max1N). After the data is transferred to the L2Cache, perform data adjustments according to step 2.3 and then perform the sort operation according to step 1. After completion, transfer the result data back to the DDR data space. Find the location loc1Addr of the min1 value in the DDR data transferred back from the L2Cache. The data from loc0Addr to loc1Addr is the final sorted data for the first pass, and place this data after the final sorted data for the 0th pass.

[0023] Step 2.6: Follow step 2.5 until all data blocks in the DDR are sorted.

[0024] Compared with the prior art, the advantages of the present invention are:

[0025] The present invention is an operation method based on vector processor sorting, which is simple to implement and easy to operate. It fully utilizes the high parallel computing performance of the vector processing unit and can compare multiple data at the same time, greatly shortening the algorithm operation time, having good reliability and reducing hardware computing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a schematic diagram of the overall process of the present invention.

[0027] Figure 2 Schematic diagram of the operation flow of the L2Cache of the present invention that can accommodate all data.

[0028] Figure 3 This is a schematic diagram of the operation flow when the L2Cache of the present invention cannot fully load data.

[0029] Figure 4 Schematic diagram of data adjustment in L2Cache of the present invention. DETAILED DESCRIPTION

[0030] The present invention will now be further described with reference to the accompanying drawings and embodiments. Figure 1 Schematic diagram of the overall process of the present invention. This method includes the following two cases: In the first case, the amount of data to be processed is small and the L2Cache can accommodate all the data. In this case, all even-numbered column elements are selected from the DDR and transferred to the upper half of the L2Cache, and all odd-numbered column elements are selected and transferred to the lower half of the L2Cache. First, the elements in the upper half are compared one-to-one with the elements in the lower half. Then, the staggered elements in the upper half are compared one-to-one with the elements in the lower half. This loop is repeated until the end. In the second case, the L2Cache cannot accommodate all the data to be processed. First, the data in the off-chip DDR memory is divided into N+1 blocks according to the size of the L2Cache. The N+1 blocks of data are transferred to the L2Cache separately and sorted according to the first case. Then, each block of DDR data is sequentially transferred to the L2Cache space with a size of data of sizeof(L2Cache) / (N+1), filling the L2Cache. Then, the sorting operation is performed according to the first case, with min being the last data sorted at that time. Find the location ddrLocAddr of the smallest data block greater than min in the sorted data blocks in the DDR. Starting from ddrLocAddr, copy data of sizeof(L2Cache) / (N+1) to the L2Cache space until the L2Cache is full. Then, perform the sort operation according to the first case. Repeat this process until all data blocks in the DDR are sorted.

[0031] refer to Figure 2, the schematic diagram of the operation flow of the L2Cache of the present invention can accommodate all data. The data elements to be sorted in DDR are {6,4,2,5,3,1}, including the following steps:

[0032] Step 1: Select the first three elements {6, 4, 2} from the DDR and transfer them to the upper half of the L2Cache, and select the last three elements {5, 3, 1} and transfer them to the lower half of the L2Cache.

[0033] Step 2: Compare the elements {6, 4, 2} in the upper half with the elements {5, 3, 1} in the lower half one-to-one. The elements with smaller values ​​are retained in the upper half, which is {5, 3, 1}, and the elements with larger values ​​are retained in the lower half, which is {6, 4, 2}.

[0034] Step 3: Compare the elements in the upper half of the block at position +1 with the elements in the lower half one-to-one, specifically {3,6} and {1,4}. The elements with smaller values ​​are retained in the lower half, and the elements with larger values ​​are retained in the upper half. Finally, the elements in the upper half are {5,6,4}, and the elements in the lower half are {3,1,2}.

[0035] Step 4: Determine whether the sorting loop is finished. If all the even-numbered column elements in step 2 are smaller than the corresponding odd-numbered column elements, the even-numbered column sorting is completed. If the even-numbered column elements compared in step 3 are larger than the corresponding odd-numbered column elements, the odd-numbered column sorting is completed. Only when both the even-numbered column sorting and the odd-numbered column sorting are completed can the sorting be finished. Otherwise, enter step 2 and loop again.

[0036] Step 5: Transfer the data from the L2 cache to the DDR using index transfer. In this example, the elements in the upper half of the L2 cache are {1, 3, 5}, and the elements in the lower half are {2, 4, 6}. The result of index transfer to the DDR is {1, 2, 3, 4, 5, 6}.

[0037] refer to Figure 3 , a schematic diagram of the operation flow of the L2Cache of the present invention that cannot fully load data.

[0038] First, the data in DDR is divided into N+1 blocks according to the size of L2Cache, numbered 0, 1, 2, 3, ..., N. The data size of blocks 0 to N-1 is the same as the size of L2Cache, and the data of block N is smaller than or equal to L2Cache. The N+1 blocks of data are transferred to L2Cache respectively according to Figure 2 The steps shown perform sorting operations, and after the operations are completed, the data is returned to the DDR space. At this time, the data from block 0 to block N are in order.

[0039] Transfer data of sizeof(L2Cache) / (N+1) from each block of DDR to L2Cache space in an orderly manner, fill L2Cache, and press Figure 4 Adjust the data by following the procedure shown, and then press Figure 2 The steps shown are used to perform the sorting operation, and after the operation is completed, the data is transferred back to the DDR space. Assume that the maximum value of the data transferred from each block in the DDR to the L2Cache is max00, max01, max02, max03, max…, max0N. Then find the minimum value among all the maximum values, min0=Min(max00, max01, max02, max03, max…, max0N). Find the location loc0Addr of the min0 value in the DDR data moved back by the L2Cache. The data from position 0 to loc0Addr is the final sorted data for the 0th time;

[0040] First, find the location ddrLocAddr of the smallest data greater than min0 from each block of ordered data in DDR, and start from ddrLocAddr to transfer data of sizeof(L2Cache) / (N+1) to L2Cache space to fill L2Cache. Figure 4 Adjust the data and then follow Figure 1 The process shown performs a sorting operation and returns it to the DDR space after the operation is completed. Assume that the maximum value of the data transferred from each block in the DDR to the L2Cache, that is, the rightmost value is max10, max11, max12, max13, max…, max1N. Then find the minimum value among all the maximum values, min1=Min(max10, max11, max12, max13, max…, max1N). Find the location loc1Addr of the min1 value in the DDR data moved back by the L2Cache. The data from loc0Addr to loc1Addr is the final sorted data for the first time. Place this data after the final sorted data for the 0th time.

[0041] This process is repeated until all data blocks in the DDR are sorted.

[0042] refer to Figure 4 , a schematic diagram of data adjustment in L2Cache of the present invention.

[0043] After each block in DDR transfers data to L2Cache, the data needs to be adjusted to make the data meet the calculation requirements. The adjustment process is as follows:

[0044] num: the total number of data to be sorted; evenCloNum: the number of even-numbered column data; oddCloNum: the number of odd-numbered column data; DataNum: the number of data transferred from DDR to L2Cache; halfL2CacheNum: the number of data that can be stored in half of the L2Cache space; outputAddr: the starting address of the output sorted data.

[0045] Case 1: DataNum <= halfL2CacheNum. The data between 0 and (evenCloNum - 1) in the L2Cache remains unchanged. The data between evenCloNum and (DataNum - 1) (data length is oddCloNum) is transferred from the L2Cache to the DDR starting at outputAddr + num - oddCloNum and with a length of oddCloNum. After the transfer is complete, this data is transferred from the DDR to the L2Cache starting at halfL2CacheNum.

[0046] Case 2: DataNum > halfL2CacheNum. The data between 0 and (evenCloNum - 1) in the L2Cache remains unchanged. The data between evenCloNum and (halfL2CacheNum - 1) (data length is halfL2CacheNum - evenCloNum) is transferred from the L2Cache to the DDR starting at outputAddr + num - (halfL2CacheNum - evenCloNum) and with a length of halfL2CacheNum - evenCloNum. After the transfer is complete, this data is transferred from the DDR to the L2Cache starting at DataNum.

[0047] In summary, after reading the present invention document, ordinary technicians in this field can make various other corresponding transformation schemes based on the technical solutions and technical concepts of the present invention without creative mental work, and all of them fall within the scope of protection of the present invention.

Claims

1. A vector processor-based sorting operation method, characterized in that: The following steps are included, and the following steps are sorted in ascending order: Step 1: When the amount of data to be sorted is small, the Level 2 Cache (L2Cache) can hold all the data and perform sorting directly. Step 2: When the amount of data to be sorted is large, the L2Cache cannot hold all the data, so the data is sorted in batches. The specific method of step 1 includes the following steps: Step 1.1: Select all even-numbered column elements from the off-chip memory DDR and transfer them to the upper half of the L2Cache, and select all odd-numbered column elements and transfer them to the lower half of the L2Cache. When the number of data S is divisible by 2, the first S / 2 data are assumed to be even-numbered column elements, and the rest are odd-numbered column elements. When S is not divisible by 2, the first floor(S / 2)+1 data are assumed to be even-numbered column elements. Floor() means taking the integer and the rest are odd-numbered column elements. Step 1.2: compare the elements in the upper half with the elements in the lower half one by one. The elements with smaller values ​​are kept in the upper half, and the elements with larger values ​​are kept in the lower half. Step 1.3: compare the element position +1 in the upper half with the elements in the lower half one-to-one. The element with smaller value is kept in the lower half, and the element with larger value is kept in the upper half. Step 1.4: Determine whether the permutation is complete. If not, proceed to step 1.

2. If the permutation is complete, save the data in the L2Cache to the off-chip memory DDR through index transfer. The sign of the completion of the permutation is that the value of each element in the upper half is less than the corresponding element value in the lower half. The specific method of step 2 includes the following steps: Step 2.1: Divide the data in the DDR into N+1 blocks based on the L2Cache size, numbered 0, 1, 2, 3, ..., N. Transfer each N+1 block to the L2Cache and perform the sorting operation according to step 1. After the operation is completed, transfer the data back to the DDR space. At this point, the data from blocks 0 to N are in order. Step 2.2, for the 0th time, sequentially transfer data of sizeof(L2Cache) / (N+1) from each block in the DDR to the L2Cache space. Let the maximum value of the data transferred from each block in the DDR to the L2Cache, that is, the rightmost value, be max00, max01, max02, max03, max…, max0N; then find the minimum value among all the maximum values, min0=Min(max00, max01, max02, max03, max…, max0N); 1) , DataNum = floor(L2Cache / (N+1))*(N+1), which is the lower integer of L2Cache / (N+1) multiplied by (N+1). As the calculation proceeds, the data of some blocks will be sorted and DataNum will change. evenCloNum: the number of even-numbered column data; oddCloNum: the number of odd-numbered column data; halfL2CacheNum: the number of data that can be stored in half of the L2Cache space; outputAddr: the starting address of the output sorted data. If DataNum is divisible by 2, evenCloNum = oddCloNum = DataNum / 2. If DataNum is not divisible by 2, evenCloNum = floor(DataNum / 2)+1, oddCloNum = floor(DataNum / 2)+1. um / 2); the reason for data adjustment is that, assuming that the number of data processed by the vector processing unit at the same time is a fixed value P, when the vector processing unit takes data from the L2Cache, the starting address of the L2Cache data should be aligned with P. If the difference between the number of even column data and the number of odd column data is greater than P, the sorting algorithm will compare some illegal values ​​and cannot obtain the correct sorting result, so data adjustment is required; data adjustment is divided into two cases, the first case: DataNum <= halfL2CacheNum; the data between 0 and (evenCloNum-1) in the L2Cache remains unchanged, and the data between evenCloNum and (DataNum-1) (data length is oddCloNum) is transferred from the L2Cache to the interval of outputAddr+num-oddCloNum and length of oddCloNum in the DDR. After the transfer is completed, this part of data is transferred from the DDR to the interval of L2Cache starting at halfL2CacheNum; the second case: DataNum> halfL2CacheNum;The data between 0 and (evenCloNum-1) in L2Cache remains unchanged. The data between evenCloNum and (halfL2CacheNum-1) (the data length is halfL2CacheNum-evenCloNum) is transferred from L2Cache to the interval in DDR starting at outputAddr+num-(halfL2CacheNum-evenCloNum) and with a length of halfL2CacheNum-evenCloNum. After the transfer is completed, this part of data is transferred from DDR to the interval in L2Cache starting at DataNum. In step 2.4, after the data is transferred to the L2Cache, the sort operation is performed according to step 1. After the operation is completed, the result data is returned to the DDR data space. In the DDR result data returned by the L2Cache, the location loc0Addr of the min0 value is found. The data from location 0 to loc0Addr is the final sorted data for the 0th time. Step 2.5: For the first time, find the location ddrLocAddr of the minimum data greater than min0 from each block of ordered data in the DDR. Starting from ddrLocAddr, transfer data of sizeof(L2Cache) / (N+1) to the L2Cache space. Let the maximum value of the data transferred from each block in the DDR to the L2Cache, that is, the rightmost value, be max10, max11, max12, max13, max..., max1N; then find the minimum value of all maximum values, min1 = Min(max10, max11, max12, max13, max..., max1N); After the data is transferred to the L2Cache, adjust the data according to step 2.3, and then perform the sort operation according to step 1. After the operation is completed, return the result data space to the DDR; find the location loc1Addr of the min1 value in the DDR data moved back to the L2Cache. The data from loc0Addr to loc1Addr is the final sorted data for the first time, and place this data after the final sorted data for the 0th time. Step 2.6: Follow step 2.5 until all data blocks in the DDR are sorted.

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