Serial data metastability elimination circuit, system, and method

Abstract

The application relates to a serial port data metastable state elimination circuit, system and method. The serial port data metastable state elimination circuit is provided with a high-frequency clock signal generation circuit. A third clock signal with a higher frequency than the frequencies of two clock signals (a first clock signal and a second clock signal) in data synchronization can be introduced. UART data conforming to a single-bit asynchronous serial communication of a UART protocol is output through a data serial port. A metastable state elimination circuit is arranged to eliminate the metastable state. The first clock signal and the second clock signal after synchronization are output to a metastable state detection circuit. After processing by the metastable state detection circuit, a flag signal indicating whether the metastable state is generated can be output. Whether the metastable state is eliminated can be judged.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and in particular to a serial port data metastability elimination circuit, system, and method. Background Technology

[0002] In data transmission, synchronous transmission is typically used, meaning the sending and receiving ends use the same clock. This ensures that data transmission and reception are synchronized and prevents data transmission anomalies. However, data is often transmitted between multiple different clock domains, requiring the design of asynchronous sequential circuits for data transmission. Asynchronous sequential circuits contain multiple independent clock sources with differences in frequency and phase, inevitably leading to metastability. When a data signal passes through the boundary between two clock domains, its value will be controlled by these two clocks respectively. If the sensitive edges of the two clock signals are very close and exceed permissible limits, data signal instability will occur, and the asynchronous sequential circuit will exhibit metastability.

[0003] Flip-flops are among the most commonly used basic components in digital circuit design, frequently appearing in asynchronous sequential circuits. Metastability refers to the failure of data to maintain a stable state within a specified time, thus failing to meet the setup time (Tsu) and hold time (Th) of the flip-flop. To ensure stable data transmission for a period before and after the rising edge of the clock (or the active clock edge), allowing the flip-flop to achieve correct data sampling at the rising edge, eliminating metastability is essential, especially for frequently used asynchronous serial communication ports (Universal Asynchronous Receiver / Transmitter, UART).

[0004] Currently, there are three main methods commonly used to eliminate metastability:

[0005] (1) The method of "two-step" is adopted, that is, registering twice. This method is simple to design and can eliminate metastability with a high probability when the clock frequencies of the preceding and following stages are close, but it cannot completely eliminate it. In particular, when the clock frequency of the following stage is much lower than the clock frequency of the preceding stage, this method will fail and cannot eliminate metastability.

[0006] (2) FIFO (First In First Out) and (3) Gray code.

[0007] FIFO and Gray code methods are mainly designed for parallel communication of multi-bit data across clock domains, and are not suitable for UART data in single-bit asynchronous serial communication.

[0008] Therefore, there is currently a lack of a serial data metastability elimination circuit that can fully eliminate metastability and is suitable for UART data in single-bit asynchronous serial communication. Summary of the Invention

[0009] Therefore, it is necessary to provide a serial port data metastability elimination circuit, system, and method to address the problem that traditional metastability elimination methods cannot simultaneously satisfy the requirements of fully eliminating metastability and being applicable to UART data in single-bit asynchronous serial communication.

[0010] This application provides a serial port data metastability elimination circuit, electrically connected to a trigger, the serial port data metastability elimination circuit comprising:

[0011] The first clock signal generation circuit is used to output the first clock signal;

[0012] The second clock signal generation circuit is used to output the second clock signal;

[0013] A high-frequency clock signal generation circuit is used to output a third clock signal; the frequency of the third clock signal is greater than the frequency of the first clock signal, and the frequency of the third clock signal is greater than the frequency of the second clock signal.

[0014] The metastability elimination circuit is connected to the first clock signal generation circuit; the metastability elimination circuit is also connected to the second clock signal generation circuit; the metastability elimination circuit is also connected to the high-frequency clock signal generation circuit.

[0015] Metastability detection circuit, which is signal-connected to the metastability elimination circuit;

[0016] The data serial port is connected to the metastability elimination circuit and is used to output a single-bit serial port data signal.

[0017] The detection port is connected to the signal of the metastable detection circuit.

[0018] This application also provides a serial port data metastability elimination system, including:

[0019] As mentioned above, the serial data metastability elimination circuit;

[0020] The level detection device is electrically connected to the detection port in the serial port data metastability elimination circuit.

[0021] This application also provides a method for eliminating metastability in serial port data, applied to the serial port data metastability elimination system mentioned above, wherein the method includes:

[0022] Set the initial output frequency of the high-frequency clock signal generation circuit;

[0023] The third clock signal output from the high-frequency clock signal generation circuit is input to the metastability elimination circuit;

[0024] Obtain the output level of the detection port;

[0025] Determine whether the output level of the detection port is high.

[0026] If the output level of the detection port is high, metastability is confirmed, and the first detection result data is output.

[0027] If the output level of the detection port is not high, it is confirmed that metastability has not occurred, and the second detection result data is output.

[0028] This application relates to a serial port data metastability elimination circuit, system, and method. By setting a high-frequency clock signal generation circuit, a third clock signal with a higher frequency than the clock signals (first clock signal and second clock signal) of the two clock domains in data synchronization can be introduced. By setting the data serial port to output UART data conforming to the UART protocol for single-bit asynchronous serial communication, and by setting a metastability elimination circuit to eliminate metastability, the synchronized first clock signal and second clock signal are output to a metastability detection circuit. After processing by the metastability detection circuit, a flag signal indicating whether metastability has occurred can be output, thereby determining whether metastability has been eliminated. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the structure of a serial port data metastability elimination circuit provided in an embodiment of this application.

[0030] Figure 2 This is a schematic diagram of the serial port data metastability elimination circuit provided in another embodiment of this application.

[0031] Figure 3 This is a schematic diagram showing the connection relationship between the metastability elimination circuit and other circuits or components in a serial port data metastability elimination circuit provided in an embodiment of this application.

[0032] Figure 4 This is a schematic diagram showing the connection relationship between the metastability detection circuit and other circuits or components in a serial port data metastability elimination circuit provided in an embodiment of this application.

[0033] Figure 5 This is a schematic diagram showing the connection relationship between the frequency adjustment circuit and other circuits or components in a serial port data metastability elimination circuit provided in an embodiment of this application.

[0034] Figure 6 This is a schematic diagram of the timing waveform of the metastability elimination circuit in a serial port data metastability elimination circuit provided in an embodiment of this application.

[0035] Figure 7 This is a schematic diagram of the timing waveform of the metastability detection circuit in a serial port data metastability elimination circuit provided in an embodiment of this application.

[0036] Figure 8 This is a schematic diagram of the structure of a serial port data metastability elimination system provided in an embodiment of this application.

[0037] Figure 9 A flowchart of a serial port data metastability elimination method provided in an embodiment of this application.

[0038] Figure label:

[0039] 10 - Serial port data metastability elimination circuit; 110 - First clock signal generation circuit;

[0040] 120 - Second clock signal generation circuit; 130 - High-frequency clock signal generation circuit;

[0041] 140 - Metastability elimination circuit; 141 - First delay unit; 141a - Input terminal of the first delay unit;

[0042] 141b - Output of the first delay unit; 142 - First OR gate; 142a - Input of the first OR gate;

[0043] 142b - Input of the second OR gate; 142c - Output of the first OR gate; 143 - First AND gate;

[0044] 143a - First AND gate input; 143b - Second AND gate input; 143c - Third AND gate input;

[0045] 143d - First AND gate output; 144 - First D flip-flop; 144a - First asynchronous clear input;

[0046] 144b - First clock port; 144c - First data input port; 144d - First data output port;

[0047] 145 - Second delay unit; 145a - Input terminal of the second delay unit; 145b - Output terminal of the second delay unit;

[0048] 146 - Second OR gate; 146a - Third OR gate input; 146b - Fourth OR gate input;

[0049] 146c - Output of the second OR gate; 147 - Output of the second AND gate; 147a - Input of the fourth AND gate;

[0050] 147b - Input of the fifth AND gate; 147c - Input of the sixth AND gate; 147d - Output of the second AND gate;

[0051] 148 - Second D flip-flop; 148a - Second asynchronous clear input; 148b - Second clock port;

[0052] 148c - Second data input port; 148d - Second data output port; 149 - Inverter;

[0053] 150 - Metastable detection circuit; 151 - Third D flip-flop; 151a - Third clock port;

[0054] 151b - Third data input port; 151c - Third data output port; 152 - Fourth D flip-flop;

[0055] 152a - Fourth clock port; 152b - Fourth data input port; 152c - Fourth data output port;

[0056] 153 - Fifth D flip-flop; 153a - Fifth clock port; 153b - Fifth data input port;

[0057] 152c - Fifth data output port; 154 - Sixth D flip-flop; 154a - Sixth clock port;

[0058] 154b - Sixth data input port; 154c - Sixth data output port; 155 - First NOT gate;

[0059] 155a - Input of the first NOT gate; 155b - Output of the first NOT gate; 156 - Second NOT gate;

[0060] 156a - Input of the second NOT gate; 156b - Output of the second NOT gate; 157 - XNOR gate;

[0061] 157a - Input of the first XNOR gate; 157b - Input of the second XNOR gate; 157c - Output of the XNOR gate;

[0062] 158 - Seventh D flip-flop; 158a - Seventh clock port; 158b - Seventh data input port;

[0063] 158c - Seventh data output port; 160 - Data serial port; 170 - Detection port; 180 - Adjustment circuit;

[0064] 181 - Input terminal of the first adjustment circuit; 182 - Input terminal of the second adjustment circuit;

[0065] 183 - Output terminal of adjustment circuit; 184 - First frequency division control module; 185 - Frequency and phase detector;

[0066] 186 - Loop filter; 187 - Voltage-controlled oscillator; 188 - Second frequency divider control module;

[0067] 20-Level detection device. Detailed Implementation

[0068] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0069] This application provides a serial port data metastability elimination circuit 10.

[0070] like Figure 1 As shown, in one embodiment of this application, the serial port data metastability elimination circuit 10 includes a first clock signal generation circuit 110, a second clock signal generation circuit, a high-frequency clock signal generation circuit 130, a metastability elimination circuit 140, a metastability detection circuit 150, a data serial port 160, and a detection port 170.

[0071] The metastability elimination circuit 140 is connected to the first clock signal generation circuit 110. The metastability elimination circuit 140 is also connected to the second clock signal generation circuit. The metastability elimination circuit 140 is also connected to the high-frequency clock signal generation circuit 130. The metastability detection circuit 150 is connected to the metastability elimination circuit 140. The data serial port 160 is connected to the metastability elimination circuit 140. The detection port 170 is connected to the metastability detection circuit 150.

[0072] The first clock signal generation circuit 110 is used to output a first clock signal. The second clock signal generation circuit is used to output a second clock signal. The high-frequency clock signal generation circuit 130 is used to output a third clock signal. The frequency of the third clock signal is greater than the frequency of the first clock signal. The frequency of the third clock signal is greater than the frequency of the second clock signal. The data serial port 160 is used to output a single-bit serial port data signal.

[0073] Specifically, the first clock signal is Figure 1 In i_clka, the second clock signal is Figure 1 The i_clkb in the code refers to clock signals from two different clock domains used in data synchronization.

[0074] The third clock signal is Figure 1 i_clk_high in the code is an externally introduced clock signal with a higher frequency.

[0075] The data serial port 160 is used to output serial data input signals, which are single-bit serial data signals conforming to the UART protocol. These single-bit serial data signals are... Figure 1i_uart_data in.

[0076] After the three clock signals are input to the metastability elimination circuit 140, a synchronized first clock signal o_clka and a synchronized second clock signal o_clkb are obtained. Further, the synchronized first clock signal o_clka and the synchronized second clock signal o_clkb are sent to the metastability detection circuit 150. After processing by the metastability detection circuit 150, a flag signal can be output, i.e. Figure 1 The o_judge_flag flag in the code can be used to determine whether metastability has been eliminated.

[0077] In this embodiment, by setting a high-frequency clock signal generation circuit 130, a third clock signal with a higher frequency than the clock signals (first clock signal and second clock signal) of the two clock domains in data synchronization can be introduced. By setting the data serial port 160 to output UART data conforming to the UART protocol for single-bit asynchronous serial communication, and by setting a metastability elimination circuit 140 to eliminate metastability, the synchronized first clock signal and second clock signal are output to the metastability detection circuit 150. After processing by the metastability detection circuit 150, a flag signal indicating whether metastability has occurred can be output, thereby determining whether metastability has been eliminated.

[0078] In one embodiment of this application, the serial port data metastability elimination circuit 10 further includes a frequency adjustment circuit 180. The frequency adjustment circuit 180 is disposed between the high-frequency clock signal generation circuit 130 and the metastability elimination circuit 140.

[0079] The frequency adjustment circuit 180 includes a first adjustment circuit input terminal 181, a second adjustment circuit input terminal 182, and an adjustment circuit output terminal 183. The first adjustment circuit input terminal 181 is connected to the high-frequency clock signal generation circuit 130. The second adjustment circuit input terminal 182 is connected to the high-frequency clock signal generation circuit 130. The adjustment circuit output terminal 183 is connected to the metastability elimination circuit 140.

[0080] Specifically, the difference between this embodiment and the previous embodiment is that a frequency adjustment circuit 180 is additionally provided between the high-frequency clock signal generation circuit 130 and the metastability elimination circuit 140. The function of the frequency adjustment circuit 180 is to adjust the output frequency of the high-frequency clock signal generation circuit 130. Each time it is adjusted, the adjusted output frequency of the high-frequency clock signal generation circuit 130 is made lower than the original output frequency of the high-frequency clock signal generation circuit 130. The signal output by the high-frequency clock signal generation circuit 130 after adjusting the output frequency is defined as the adjusted third clock signal.

[0081] The frequency adjustment circuit 180 is configured so that the third clock signal i_clk_high output by the high-frequency clock signal generation circuit 130 can be adaptively adjusted based on the clock of the third clock signal i_clk_high and then output to the metastability elimination module. The adjusted third clock signal is denoted as o_clk_high_apt, as follows: Figure 2 As shown.

[0082] This adjustment method effectively eliminates metastability while ensuring real-time performance. Furthermore, the system adaptively adjusts the clock frequency fed to metastability elimination, resulting in high system robustness and eliminating the need for manual searching for the optimal clock frequency (the frequency fed to metastability elimination).

[0083] In one embodiment of this application, the metastability elimination circuit 140 includes a first delay 141, a first OR gate 142, a first AND gate 143, and a first D flip-flop 144.

[0084] The input terminal 141a of the first delay unit 141 is connected to the first clock signal generation circuit 110.

[0085] The first OR gate 142 includes a first OR gate 142 input terminal 142a, a second OR gate 146 input terminal 142b, and a first OR gate output terminal 142c. The output terminal 141b of the first delay unit 141 is signal-connected to the first OR gate 142 input terminal 142a. The first clock signal generation circuit 110 is signal-connected to the second OR gate 146 input terminal 142b.

[0086] The first AND gate 143 includes a first AND gate input 143a, a second AND gate input 147 143b, a third AND gate input 143c, and a first AND gate output 143d. The output 141b of the first delay unit 141 is connected to the first AND gate input 143a. The first clock signal generation circuit 110 is connected to the second AND gate input 143b. The output 183 of the adjustment circuit is connected to the third AND gate input 143c.

[0087] The first D flip-flop 144 includes a first asynchronous clear terminal 144a, a first clock port 144b, a first data input port 144c, and a first data output port 144d. The first asynchronous clear terminal 144a is connected to the output terminal 142c of the first OR gate. The first data input port 144c is connected to the output terminal 142c of the first OR gate. The first data output port 144d is connected to the metastable detection circuit 150. The first clock port 144b is connected to the output terminal 143d of the first AND gate.

[0088] Specifically, the metastability elimination circuit 140 mainly includes two D flip-flops with asynchronous reset terminals, two two-input OR gates, two three-input AND gates, and two delays. This embodiment describes one set of delays, OR gates, AND gates, and flip-flops.

[0089] like Figure 3 As shown, the first clock signal i_clka enters the input terminal 141a of the first delay unit 141, and the first delay unit 141 generates a delayed first clock signal, denoted as i_clka_d. The delay time Td1 of the first clock signal i_clka is a preset fixed time.

[0090] In one embodiment of this application, the delay time Td1 of the first clock signal i_clka is greater than the setup time Tsu of the flip-flop. In this application, we assume that all D flip-flops are from the same manufacturer, of the same model, and manufactured at the same time (i.e., with the same degree of wear and tear). Therefore, the setup time of all D flip-flops is the same, which is Tsu. In this embodiment, we set Td1 to be greater than Tsu; optionally, Td1 is equal to 1.5 times Tsu. The value of Tsu can be obtained by referring to the flip-flop's datasheet.

[0091] The delayed first clock signal i_clka_d and the first clock signal i_clka are input into the first OR gate 142 to obtain the first OR signal, denoted as clka_or. Figure 3 As shown.

[0092] The first clock signal i_clka, the delayed first clock signal i_clka_d, and the adjusted third clock signal o_clk_high_apt are input into the first AND gate 143 to obtain the first AND signal, denoted as clka_and, as follows. Figure 3 As shown.

[0093] The first OR signal clka_or is input to the first data input port 144c of the first D flip-flop 144, and the first AND signal clka_and is input to the first clock port 144b of the first D flip-flop 144, to obtain the synchronized first clock signal o_clka output by the first D flip-flop 144. The synchronized first clock signal o_clka is then input to the metastability detection circuit 150 for further processing.

[0094] In one embodiment of this application, the metastability elimination circuit 140 further includes a second delay 145, a second OR gate 146, a second AND gate 147, a second D flip-flop 148, and an inverter 149.

[0095] The input terminal 145a of the second delay unit 145 is connected to the second clock signal generation circuit.

[0096] The second OR gate 146 includes a third OR gate input terminal 146a, a fourth OR gate input terminal 146b, and a second OR gate output terminal 146c. The output terminal 145b of the second delay unit 145 is signal-connected to the third OR gate input terminal 146a. The second clock signal generation circuit is signal-connected to the fourth OR gate input terminal 146b.

[0097] The second AND gate 147 includes a fourth AND gate input 147a, a fifth AND gate input 147b, a sixth AND gate input 147c, and a second AND gate output 147d. The output 145b of the second delay unit 145 is connected to the fourth AND gate input 147a. The second clock signal generation circuit is connected to the fifth AND gate input 147b. The output 183 of the adjustment circuit is connected to the sixth AND gate input 147c.

[0098] The second D flip-flop 148 includes a second asynchronous clear terminal 148a, a second clock port 148b, a second data input port 148c, and a second data output port 148d. The second asynchronous clear terminal 148a is connected to the output terminal 146c of the second OR gate. The second data input port 148c is connected to the output terminal 146c of the second OR gate. The second data output port 148d is connected to the metastable detection circuit 150; the output terminal 147d of the second AND gate is connected to the second clock port 148b.

[0099] The inverter 149 is located on the signal connection link between the output terminal 183 of the adjustment circuit and the input terminal 147c of the sixth AND gate.

[0100] Specifically, as mentioned above, the metastability elimination circuit 140 mainly includes two D flip-flops with asynchronous reset terminals, two two-input OR gates, two three-input AND gates, and two delays. This embodiment describes another set of delays, OR gates, AND gates, and flip-flops.

[0101] like Figure 3 As shown, the second clock signal i_clkb enters the input terminal 145a of the second delay unit 145, and the second delay unit 145 generates a delayed second clock signal, denoted as i_clkb_d. The delay time Td2 of the second clock signal i_clkb is a preset fixed time.

[0102] In one embodiment of this application, the delay time Td2 of the second clock signal i_clkb is greater than the setup time Tsu of the flip-flop. In this application, we assume that all D flip-flops are from the same manufacturer, of the same model, and manufactured at the same time (i.e., with the same degree of wear and tear). Therefore, the setup time of all D flip-flops is the same, which is Tsu. In this embodiment, we set Td2 to be greater than Tsu; optionally, Td2 is equal to 1.5 times Tsu. The value of Tsu can be obtained by referring to the flip-flop's datasheet.

[0103] The delayed second clock signal i_clkb_d and the second clock signal i_clkb are input into the second OR gate 146 to obtain the second OR signal, denoted as clkb_or. Figure 3 As shown.

[0104] The adjusted third clock signal o_clk_high_apt is input into inverter 149 for inversion, resulting in the third clock signal output by inverter 149 after adjustment and inversion.

[0105] The second clock signal i_clkb, the third clock signal that is first adjusted and then inverted, and the delayed second clock signal i_clkb_d are input into the second AND gate 147 to obtain the second AND signal, denoted as clkb_bnd. Figure 3 As shown.

[0106] The second OR signal clkb_or is input to the second data input port 148c of the second D flip-flop 148, and the second AND signal clkb_bnd is input to the second clock port 148b of the second D flip-flop 148, resulting in the synchronized second clock signal o_clkb output by the second D flip-flop 148. The synchronized second clock signal o_clkb is then input to the metastability detection circuit 150 for further processing.

[0107] It is important to note that the synchronized first clock signal o_clka and the synchronized second clock signal o_clkb differ by half a clock cycle of the adjusted third clock signal o_clk_high_apt. That is, half a clock cycle of o_clk_high_apt = the start of the clock cycle of o_clka - the start of the clock cycle of o_clkb > Tsu.

[0108] The timing waveform diagram of the metastability elimination circuit 140 is shown below. Figure 6 As shown.

[0109] In this embodiment, by synchronizing two asynchronous clock signals i_clka and i_clkb to the rising and falling edges of the higher-frequency oclkhihapt clock respectively, a half-clock cycle interval can be generated (half a clock cycle refers to half a clock cycle of o_clk_high_apt, i.e. Figure 6 Metastability can be eliminated by setting an appropriate clock period for o_clk_high_apt (i.e., ensuring that half a clock period of o_clk_high_apt is greater than the setup time Tsu of the flip-flop).

[0110] In one embodiment of this application, the metastable detection circuit 150 includes a third D flip-flop 151, a fourth D flip-flop 152, a fifth D flip-flop 153, a sixth D flip-flop 154, a first NOT gate 155, a second NOT gate 156, an XNOR gate 157, and a seventh D flip-flop 158.

[0111] The third D flip-flop 151 includes a third clock port 151a, a third data input port 151b, and a third data output port 151c. The third data input port 151b is connected to the data serial port 160. The third clock port 151a is connected to the metastability elimination circuit 140.

[0112] The fourth D flip-flop 152 includes a fourth clock port 152a, a fourth data input port 152b, and a fourth data output port 152c. The fourth data input port 152b is signal-connected to the third data output port 151c.

[0113] The fifth D flip-flop 153 includes a fifth clock port 153a, a fifth data input port 153b, and a fifth data output port 152c.

[0114] The sixth D flip-flop 154 ​​includes a sixth clock port 154a, a sixth data input port 154b, and a sixth data output port 154c. The sixth clock port 154a is signal-connected to the fifth clock port 153a.

[0115] The first NOT gate 155 includes a first NOT gate input terminal 155a and a first NOT gate output terminal 155b. The first NOT gate output terminal 155b is signal-connected to the sixth data input port 154b.

[0116] The second NOT gate 156 includes a second NOT gate input terminal 156a and a second NOT gate output terminal 156b. The second NOT gate output terminal 156b is signal-connected to the sixth clock port 154a.

[0117] The XNOR gate 157 includes a first XNOR gate input terminal 157a, a second XNOR gate input terminal 157b, and an XNOR gate output terminal 157c. The first XNOR gate input terminal 157a is signal-connected to the fifth data output port 152c. The second XNOR gate input terminal 157b is signal-connected to the sixth data output port 154c.

[0118] The seventh D flip-flop 158 includes a seventh clock port 158a, a seventh data input port 158b, and a seventh data output port 158c. The seventh data input port 158b is signal-connected to the output terminal 157c of the XOR gate. The seventh data output port 158c is signal-connected to the frequency adjustment circuit 180.

[0119] The fourth data output port 152c, the detection port 170, the fifth data input port 153b, and the first NOT gate input terminal 155a are connected to the same point X. The fourth clock port 152a, the second NOT gate input terminal 156a, the seventh clock port 158a, and the metastability elimination circuit 140 are connected to the same point Y.

[0120] Specifically, the metastability detection circuit 150 can detect the metastability elimination effect of the metastability elimination module and feed the detection result back to the frequency adjustment circuit 180, so that the frequency adjustment circuit 180 can subsequently perform adaptive frequency adjustment.

[0121] The metastable detection circuit 150 consists of five D flip-flops, two NOT gates, and a two-input XOR gate.

[0122] like Figure 4 As shown, Qa is the signal output of the fourth D flip-flop 152. Qb is the signal output of the fifth D flip-flop 153. Qc is the signal output of the sixth D flip-flop 154. Qd is the signal output of the seventh D flip-flop 158.

[0123] like Figure 4 As shown, i_uart_data is the single-bit serial port data signal detected by the serial port input. Based on the synchronized first clock signal o_clka, i_uart_data of the data serial port 160 is sampled, and the uart_data signal is output. Based on the synchronized second clock signal o_clkb, which serves as the sampling clock for the metastability detection circuit 150, the asynchronous data uart_data is sampled, and the o_uart_data signal is output.

[0124] Qd (also known as o_judge_flag, where Qd = o_judge_flag in all the attached diagrams) is the output signal of the metastability detection circuit 150. If Qd is high, it indicates the presence of metastability, and also indicates that the parameter setting of o_clk_high_apt in the metastability elimination circuit 140 is unreasonable and needs to be adjusted. Specifically, the modulation involves reducing the output frequency of the high-frequency clock signal generation circuit 130 to increase the time period of o_clk_high_apt.

[0125] Figure 7 This is a schematic diagram of the timing waveforms of the metastability detection circuit 150 in the serial port data metastability elimination circuit 10 provided in an embodiment of this application. Figure 7 As shown, the asynchronous input data `i_uart_data` is sampled on the rising edge of the `o_clkb` clock (after passing through the fourth flip-flop, see the waveform of Qa), while the fifth flip-flop (see the waveform of Qb) and the sixth flip-flop (see the waveform of Qc) are sampled on the falling edge. This design aims to capture metastability. When the signal passes through the first NOT gate 155 and the second NOT gate 156, it forms two complementary signals. When metastability exists, the signal output by the XOR gate 157 is a high pulse signal. This is because the XOR gate 157 works as follows: when only one of the two signals entering the first XOR gate input terminal 157a and the second XOR gate input terminal 157b is a low-level (logic 0) signal, the XOR gate 157 outputs a low-level (logic 0) signal. When both signals entering the first XOR gate input terminal 157a and the second XOR gate input terminal 157b are high-level (logic 1) signals or both are low-level (logic 0) signals, the XOR gate 157 outputs a high-level (logic 1) signal.

[0126] In one embodiment of this application, the frequency adjustment circuit 180 includes a first adjustment circuit input terminal 181, a first distribution controller module, a second adjustment circuit input terminal 182, a frequency and phase detector 185, a loop filter 186, a voltage-controlled oscillator 187, a second frequency division control module 188, and an adjustment circuit output terminal 183.

[0127] The first frequency division control module 184 is signal-connected to the input terminal 181 of the first adjustment circuit. The first frequency division control module 184 is also signal-connected to the high-frequency clock signal generation circuit 130 via the first adjustment circuit input terminal 181. The second adjustment circuit input terminal 182 is connected to the first frequency division control module 184. The first frequency division control module 184 is signal-connected to the metastable state detection circuit 150 via the second adjustment circuit input terminal 182. The second frequency division control module 188 is signal-connected to the metastable state detection circuit 150 via the second adjustment circuit input terminal 182.

[0128] The frequency and phase detector 185 is signal-connected to the first frequency division control module 184. The loop filter 186 is signal-connected to the frequency and phase detector 185. The voltage-controlled oscillator 187 is signal-connected to the loop filter 186. The second frequency division control module 188 is signal-connected to the second adjustment circuit input terminal 182, the first frequency division control module 184, the frequency and phase detector 185, and the voltage-controlled oscillator 187, respectively. The adjustment circuit output terminal 183 is connected to the signal connection link between the second frequency division control module 188 and the voltage-controlled oscillator 187.

[0129] Specifically, the frequency adjustment circuit 180 is equipped with two frequency division control modules: a first frequency division control module 184 and a second frequency division control module 188. Both the first frequency division control module 184 and the second frequency division control module 188 are connected to the metastability detection circuit 150, and both frequency division control modules receive the output result signal o_judge_flag from the metastability detection circuit 150. Triggered by the output result signal o_judge_flag from the metastability detection circuit 150, the output frequency of the third clock signal is dynamically adjusted by continuously adjusting the count values ​​of the first frequency division control module 184 and the second frequency division control module 188, thereby outputting o_clk_high_apt to fully and in real-time eliminate metastability.

[0130] This application also provides a serial port data metastability elimination system.

[0131] In one embodiment of this application, the serial port data metastability elimination system includes a serial port data metastability elimination circuit 10 and a level detection device 20 as mentioned above. The level detection device 20 is electrically connected to the detection port 170 in the serial port data metastability elimination circuit 10.

[0132] Specifically, the serial port data metastability elimination circuit 10 can eliminate the metastability of the serial port signal and perform real-time detection of metastability phenomena during the asynchronous transmission of the serial port signal.

[0133] This application also provides a method for eliminating metastability in serial port data.

[0134] like Figure 4 As shown, in one embodiment of this application, the serial port data metastability elimination method is applied to the serial port data metastability elimination system mentioned above. The serial port data metastability elimination method includes the following steps S100 to S600:

[0135] S100 sets the initial output frequency of the high-frequency clock signal generation circuit 130.

[0136] S200 inputs the third clock signal output by the high-frequency clock signal generation circuit 130 to the metastability elimination circuit 140.

[0137] S300, obtain the output level of detection port 170.

[0138] S400 determines whether the output level of detection port 170 is high.

[0139] If the output level of detection port 170 is high, the metastability is confirmed and the first detection result data is output.

[0140] S600: If the output level of detection port 170 is not high, it confirms that metastability has not occurred and outputs the second detection result data.

[0141] Specifically, if the output level of detection port 170 is high, it indicates that metastability has occurred. If the output level of detection port 170 is low, it indicates that metastability has not occurred.

[0142] In this embodiment, metastability is eliminated by the metastability elimination circuit 140. Since the metastability elimination circuit 140 is connected to the metastability detection circuit 150, the metastability detection circuit 150 can further process the signal that has been eliminated from metastability. After processing by the metastability detection circuit 150, a flag signal indicating whether metastability has occurred can be output, thereby determining whether metastability has been eliminated.

[0143] In one embodiment of this application, after S500, the serial port data metastability elimination method further includes the following S710 to S730:

[0144] S710, according to Formula 1, adjust the division values ​​of the first frequency division control module 184 and the second frequency division control module 188 respectively to obtain the adjusted output frequency of the high-frequency clock signal generation circuit 130. During the adjustment process, the adjusted output frequency of the high-frequency clock signal generation circuit 130 is made lower than the original output frequency of the high-frequency clock signal generation circuit 130.

[0145]

[0146] Wherein, fo_clk_apt is the adjusted output frequency of the high-frequency clock signal generation circuit 130. fi_clk_high is the original output frequency of the high-frequency clock signal generation circuit 130. M is the division value of the first frequency division control module 184. N is the division value of the second frequency division control module 188. Round is the rounding symbol.

[0147] S720 inputs the adjusted third clock signal output from the high-frequency clock signal generation circuit 130 to the metastability elimination circuit 140.

[0148] S730, return to S300.

[0149] Specifically, counters can be set in the first frequency division control module 184 and the second frequency division control module 188 respectively to set different frequency division values. The counting range of the counter can be greater than or equal to 0 and less than or equal to 4095, that is, the counter is a 12-bit counter. The initial count value of the counter can be 1000, that is, the initial value of M can be set to 1000, and the initial value of N can be set to 1000.

[0150] During the adjustment process, the initial output frequency of the high-frequency clock signal generation circuit 130 is a fixed value, so the adjustment step value needs to be set. Since the required frequency modulation granularity is different when the serial port data metastability elimination system operates at different frequencies (which can be understood as different speeds), two adjustment parameters, stepM and stepN, are designed here. These two adjustment parameters are used as user-configurable step values, i.e., the adjustment amplitude each time.

[0151] Specifically, each time S710 is executed, M and N are adjusted once. The adjustment methods for M and N are as follows: M is adjusted using formula 1.1, and N is adjusted using formula 1.2.

[0152] M = M0 - stepM (Formula 1.1)

[0153] N=N0+stepN Formula 1.2.

[0154] Where M is the adjusted value of M after this adjustment. M0 is the adjusted value of M after the previous adjustment. N is the adjusted value of N after this adjustment. N0 is the adjusted value of N after the previous adjustment.

[0155] For example, the initial output frequency of the high-frequency clock signal generation circuit 130i_clk_high is 20MHz.

[0156] We set stepM = 4 and stepN = 2. During the first adjustment of M and N values, M0 is the initial value of M (1000), and N0 is the initial value of N (1000). Therefore, M = M0 - stepM = 1000 - 4 = 996. N = N0 - stepN = 1000 + 2 = 1002.

[0157] Furthermore, substitute M and N into Formula 1.

[0158] After this adjustment, the adjusted output frequency of the high-frequency clock signal generation circuit 130 is: Round[(996 / 1002)*20000000] = Round(19880239.52) = 19880240Hz ≈ 19.88MHz

[0159] Therefore, the output frequency of the high-frequency clock signal generation circuit 130 can be adjusted by setting the two parameters stepM and stepN.

[0160] In one embodiment of this application, all D flip-flops in the serial data metastability elimination system have the same setup time. The initial output frequency of the high-frequency clock signal generation circuit 130 satisfies Formula 2.

[0161]

[0162] Where fi_clk_high_f is the initial output frequency of the high-frequency clock signal generation circuit. Tsu is the flip-flop setup time.

[0163] Specifically, we define T_i_clk_high as the time period of the third clock signal output by the high-frequency clock signal generation circuit 130. Timestart_o_clka is defined as the start time of the rising edge of the clock signal o_clka. Timestart_o_clkb is defined as the start time of the rising edge of the clock signal o_clkb. Tsu is the flip-flop setup time.

[0164] Combination Figure 6 and Figure 7 Then the following formula derivation can be obtained:

[0165] T_i_clk_high / 2=|Timestart_o_clka-Timestart_o_clkb|≥Tsu, from which we can deduce that the initial output frequency of the high-frequency clock signal generation circuit satisfies Formula 2, that is:

[0166] This is the only way to stably eliminate metastable states. The technical features of the above embodiments can be combined arbitrarily, and there is no restriction on the execution order of the method steps. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered to be within the scope of this specification.

[0167] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A serial port data metastability elimination circuit, characterized in that, include: The first clock signal generation circuit is used to output the first clock signal; The second clock signal generation circuit is used to output the second clock signal; A high-frequency clock signal generation circuit is used to output a third clock signal; The frequency of the third clock signal is greater than the frequency of the first clock signal, and the frequency of the third clock signal is greater than the frequency of the second clock signal; The metastability elimination circuit is connected to the first clock signal generation circuit; the metastability elimination circuit is also connected to the second clock signal generation circuit; the metastability elimination circuit is also connected to the high-frequency clock signal generation circuit. Metastability detection circuit, which is signal-connected to the metastability elimination circuit; The data serial port is connected to the metastability elimination circuit and is used to output a single-bit serial port data signal. The detection port is connected to the signal of the metastable detection circuit. It also includes a frequency adjustment circuit disposed between the high-frequency clock signal generation circuit and the metastability elimination circuit; The frequency adjustment circuit includes a first adjustment circuit input terminal, a second adjustment circuit input terminal, and an adjustment circuit output terminal; The input terminal of the first adjustment circuit is connected to the high-frequency clock signal generation circuit. The input terminal of the second adjustment circuit is connected to the signal of the metastable detection circuit; The output terminal of the adjustment circuit is connected to the signal of the metastability elimination circuit. The metastability elimination circuit includes: The first delay unit has its input terminal connected to the first clock signal generating circuit. The first OR gate includes a first OR gate input, a second OR gate input, and a first OR gate output; the output of the first delay is connected to the first OR gate input; the first clock signal generation circuit is connected to the second OR gate input. The first AND gate includes a first AND gate input terminal, a second AND gate input terminal, a third AND gate input terminal, and a first AND gate output terminal; the output terminal of the first delay unit is connected to the first AND gate input terminal, the first clock signal generating circuit is connected to the second AND gate input terminal, and the output terminal of the adjustment circuit is connected to the third AND gate input terminal. The first D flip-flop includes a first asynchronous clear terminal, a first clock port, a first data input port, and a first data output port; the first asynchronous clear terminal is connected to the output of the first OR gate, the first data input port is connected to the output of the first OR gate, the first data output port is connected to the metastable detection circuit, and the first clock port is connected to the output of the first AND gate.

2. The serial port data metastability elimination circuit according to claim 1, characterized in that, The metastability elimination circuit also includes: The second delay unit has its input terminal connected to the second clock signal generation circuit. The second OR gate includes a third OR gate input, a fourth OR gate input, and a second OR gate output; the output of the second delay is connected to the third OR gate input; the second clock signal generation circuit is connected to the fourth OR gate input. The second AND gate includes a fourth AND gate input, a fifth AND gate input, a sixth AND gate input, and a second AND gate output; the output of the second delay is connected to the fourth AND gate input, the second clock signal generation circuit is connected to the fifth AND gate input, and the output of the adjustment circuit is connected to the sixth AND gate input. The second D flip-flop includes a second asynchronous clear terminal, a second clock port, a second data input port, and a second data output port; the second asynchronous clear terminal is connected to the output of the second OR gate, the second data input port is connected to the output of the second OR gate, and the second data output port is connected to the metastable detection circuit; the output of the second AND gate is connected to the second clock port. An inverter is installed on the signal connection link between the output of the adjustment circuit and the input of the sixth AND gate.

3. The serial port data metastability elimination circuit according to claim 1, characterized in that, The metastable detection circuit includes: The third D flip-flop includes a third clock port, a third data input port, and a third data output port; the third data input port is connected to the data serial port signal, and the third clock port is connected to the metastability elimination circuit signal. The fourth D flip-flop includes a fourth clock port, a fourth data input port, and a fourth data output port; the fourth data input port is signal-connected to the third data output port. The fifth D flip-flop includes a fifth clock port, a fifth data input port, and a fifth data output port; The sixth D flip-flop includes a sixth clock port, a sixth data input port, and a sixth data output port; the sixth clock port is signal-connected to the fifth clock port. The first NOT gate includes a first NOT gate input terminal and a first NOT gate output terminal, and the first NOT gate output terminal is signal-connected to the sixth data input port. The second NOT gate includes a second NOT gate input terminal and a second NOT gate output terminal, and the second NOT gate output terminal is connected to the sixth clock port signal. The XOR gate includes a first XOR gate input, a second XOR gate input, and an XOR gate output; the first XOR gate input is signal-connected to the fifth data output port; the second XOR gate input is signal-connected to the sixth data output port. The seventh D flip-flop includes a seventh clock port, a seventh data input port, and a seventh data output port; the seventh data input port is connected to the output of the XOR gate, and the seventh data output port is connected to the frequency adjustment circuit. The fourth data output port, the detection port, the fifth data input port, and the first NOT gate input are connected to the same point X. The fourth clock port, the second NOT gate input, the seventh clock port, and the metastability elimination circuit are connected to the same point Y.

4. The serial port data metastability elimination circuit according to claim 1, characterized in that, The frequency adjustment circuit includes: Input terminal of the first adjustment circuit; The first frequency division control module is connected to the input terminal of the first adjustment circuit and is also connected to the high-frequency clock signal generation circuit through the input terminal of the first adjustment circuit. The input terminal of the second adjustment circuit is connected to the first frequency division control module. The first frequency division control module is connected to the metastable detection circuit signal through the input terminal of the second adjustment circuit. The second frequency division control module is connected to the metastable detection circuit signal through the input terminal of the second adjustment circuit. The frequency and phase detector is connected to the signal of the first frequency division control module; A loop filter is connected to the signal of the frequency and phase detector. A voltage-controlled oscillator is connected to the loop filter signal; The second frequency division control module is signal-connected to the input terminal of the second adjustment circuit, the first frequency division control module, the frequency and phase detector, and the voltage-controlled oscillator, respectively. The output of the adjustment circuit is connected to the signal connection link between the second frequency division control module and the voltage-controlled oscillator.

5. A serial port data metastability elimination system, characterized in that, include: The serial port data metastability elimination circuit as described in any one of claims 1-4; The level detection device is electrically connected to the detection port in the serial port data metastability elimination circuit.

6. A method for eliminating metastability in serial port data, characterized in that, The serial port data metastability elimination method, applied to the serial port data metastability elimination system as described in claim 5, includes: Set the initial output frequency of the high-frequency clock signal generation circuit; The third clock signal output from the high-frequency clock signal generation circuit is input to the metastability elimination circuit; Obtain the output level of the detection port; Determine whether the output level of the detection port is high. If the output level of the detection port is high, metastability is confirmed, and the first detection result data is output. If the output level of the detection port is not high, it is confirmed that metastability has not occurred, and the second detection result data is output.

7. The serial port data metastability elimination method as described in claim 6, characterized in that, After confirming the occurrence of metastability and outputting the first detection result data, the serial port data metastability elimination method further includes: According to Formula 1, the frequency division values ​​of the first frequency division control module and the second frequency division control module are adjusted respectively to obtain the adjusted output frequency of the high-frequency clock signal generation circuit; during the adjustment process, the adjusted output frequency of the high-frequency clock signal generation circuit is made smaller than the original output frequency of the high-frequency clock signal generation circuit. Official 1; in, The adjusted output frequency of the high-frequency clock signal generation circuit. M is the pre-adjustment output frequency of the high-frequency clock signal generation circuit, N is the division value of the first frequency division control module, and Round is the rounding symbol. The adjusted third clock signal output from the high-frequency clock signal generation circuit is input to the metastability elimination circuit; Return to the step of obtaining the output level of the detection port.

8. The serial port data metastability elimination method as described in claim 6 or 7, characterized in that, In the serial data metastability elimination system, all D flip-flops have the same setup time, and the initial output frequency of the high-frequency clock signal generation circuit satisfies Formula 2. Official 2; in, Tsu is the initial output frequency of the high-frequency clock signal generation circuit, and Tsu is the flip-flop setup time.

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