Display device and display driver

Abstract

The present invention provides a display device and a display driver that can suppress erroneous display of a display panel caused by the influence of noise, etc. The source driver of the present invention receives a serial data signal from a display controller via an interface, and the serial data signal is a pre-synchronization code and image data of the display panel alternating continuously. The source driver controls the timing of the gate signal supplied by the gate driver based on the image data contained in the serial data signal, and supplies the grayscale voltage signal corresponding to the image data to the multiple data lines of the display panel. The source driver has: a detection unit that detects the situation where the interface is in an unstable state; and a gate reset signal output unit that outputs a gate reset signal for stopping the operation of the gate driver when the unstable state of the interface is detected during the supply of image data.

Description

[0001] This application is a divisional application of the invention patent application with the application date of March 12, 2020, application number 202010170319.4, and invention name “Display device and display driver”. Technical Field

[0002] The present invention relates to a display device and a display driver. Background Art

[0003] As a driving method for display elements such as liquid crystal display devices or organic electroluminescence (EL), an active matrix driving method is adopted. In a display device of the active matrix driving method, a display panel includes a semiconductor substrate in which pixel portions and pixel switches are arranged in a matrix shape. A gate pulse is used to control the on / off of the pixel switch, and when the pixel switch is turned on, a grayscale voltage signal corresponding to the image data signal is supplied to the pixel portion to control the brightness of each pixel portion, thereby displaying. The driving circuit of the display device includes, for example, a gate control circuit that controls the gate pulse, a driver integrated circuit (IC) that supplies a data signal to the data line, and a timing controller (timing controller) for controlling their operating timing.

[0004] As such a display device, a display device having a driver IC that performs clock training to stably fix the phase and frequency of an internal clock has been proposed (e.g., Patent Document 1). A timing controller is connected to the driver IC via a peer-to-peer (P2P) interface and supplies serial data including a preamble signal and image data to the driver IC via a differential signaling method such as mini-LVDS (mini-Low Voltage Differential Signaling). The driver IC performs clock training using the preamble signal, which serves as a data pattern for clock training.

[0005] [Prior art literature]

[0006] [Patent Document]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-79236 Summary of the Invention

[0008] [Problems to be solved by the invention]

[0009] When the timing controller supplies data to the driver IC, it supplies a data switching signal to the driver IC. The data switching signal enables the driver IC to distinguish whether the data is a data pattern for clock training or data for display. For example, the timing controller supplies an "L" level data switching signal to the driver IC, and supplies the data pattern for clock training to the driver IC. Thereafter, when the P2P interface between the timing controller and the driver IC switches from an unlocked state to a locked state (stable state), the timing controller switches the switching signal to an "H" level and supplies the data for display to the driver IC. In response to this, the driver IC supplies a gate control signal to the gate control circuit to control the gate control circuit, thereby applying a gate pulse to the display pulse, and supplies a data signal to the data line. Thus, an image is displayed on the display panel.

[0010] However, during the normal display period when an image is displayed on the display panel, the P2P interface between the timing controller and the driver IC may become unlocked due to noise caused by electrostatic discharge (ESD). When the P2P interface becomes unlocked, data is not properly input to the driver IC, and the driver IC cannot output gate control signals and data signals of normal values. As a result, the display panel may display something different from the intended display.

[0011] The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a display device capable of suppressing erroneous display on a display panel caused by the influence of noise or the like.

[0012] [Technical means to solve the problem]

[0013] The display device of the present invention includes: a display panel having multiple data lines and multiple scan lines, and pixel switches and pixel portions arranged at each intersection of the multiple data lines and the multiple scan lines; a gate driver supplying gate signals to the multiple scan lines to control the pixel switches to be conductive; a display controller outputting a serial data signal, wherein the serial data signal is a pre-synchronization code and image data displayed on the display panel alternating continuously; and a source driver connected to the display controller via an interface, detecting a stable state or an unstable state of the interface based on the serial data signal transmitted from the display controller via the interface, and outputting a gate reset signal for stopping the supply of the gate signal from the gate driver when an unstable state of the interface is detected during the supply of the image data.

[0014] In addition, the display driver of the present invention is connected to a display panel and a gate driver, the display panel includes multiple data lines and multiple scan lines, and pixel switches and pixel portions arranged at each intersection of the multiple data lines and the multiple scan lines, the gate driver supplies gate signals to the multiple scan lines to control the pixel switches to be conductive, and the display driver supplies grayscale voltage signals corresponding to image data to the multiple data lines, wherein the display driver is connected to a display controller via an interface and receives a serial data signal from the display controller via the interface, the serial data signal being an alternating sequence of a preamble and the image data, and the display driver includes: a detection portion for detecting whether the interface is in a stable state or an unstable state based on the serial data signal transmitted via the interface; and a gate reset signal output portion for outputting a gate reset signal for stopping the operation of the gate driver when the detection portion detects an unstable state of the interface during the supply of the image data.

[0015] [Effects of the Invention]

[0016] According to the display device of the present invention, it is possible to suppress erroneous display on the display panel when the interface between the timing controller and the driver IC becomes unlocked due to noise or the like. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a block diagram showing the configuration of the display device of Example 1.

[0018] Figure 2 This is a timing chart showing the states of various components and output signals of the display device of Example 1.

[0019] Figure 3 1 is a timing chart showing the states of the components of the display device of Comparative Example 1 and output signals.

[0020] Figure 4 1 is a diagram schematically showing a display mode in a display panel of Comparative Example 1.

[0021] Figure 5 A diagram schematically showing a display mode in the display panel of Example 1.

[0022] Figure 6 This is a block diagram showing the configuration of a display device according to the second embodiment.

[0023] Figure 7 This is a circuit diagram showing the configuration of a reset signal generating circuit according to the second embodiment.

[0024] Figure 8 This is a timing chart showing the states of various components and output signals of the display device of Example 2.

[0025] Figure 9 1 is a timing chart showing the states of the components and output signals of the display device of Comparative Example 2.

[0026] Figure 10 A diagram schematically showing a display mode in a display panel of Comparative Example 2.

[0027] Figure 11 A diagram schematically showing a display mode in a display panel of Example 2.

[0028] [Explanation of Symbols]

[0029] 100: Display device

[0030] 10: Display panel

[0031] 11: Timing controller

[0032] 12: Source driver

[0033] 12A: First driver IC

[0034] 12B: Second driver IC

[0035] 13: Gate driver

[0036] 20: Display panel

[0037] 21: Unlock status detection circuit

[0038] 22: Reset signal generation circuit

[0039] 31: Gate control circuit

[0040] 32: Reset circuit DETAILED DESCRIPTION

[0041] Hereinafter, preferred embodiments of the present invention will be described in detail. In the following descriptions of the embodiments and the accompanying drawings, substantially the same or equivalent parts are denoted by the same reference numerals.

[0042] [Example 1]

[0043] Figure 1 1 is a block diagram showing the configuration of a display device 100 according to this embodiment. The display device 100 includes a display panel 10 , a timing controller 11 , a source driver 12 , and a gate driver 13 .

[0044] The display panel 10 is an image display element including, for example, a liquid crystal display panel or an organic electroluminescence (EL) panel. The display panel 10 includes m (m is a natural number greater than or equal to 2) horizontal scan lines S1 to Sm extending in the horizontal direction of the two-dimensional screen, and n (n is a natural number greater than or equal to 2) source lines D1 to Dn extending in the vertical direction of the two-dimensional screen. The intersections of the horizontal scan lines and the source lines, i.e., the source lines D1 to Dn, are formed. Figure 1 In the area surrounded by the dotted line in FIG, a display unit with pixels is formed.

[0045] The timing controller 11 is a display controller (so-called T-CON) that controls the display timing of an image on the display panel 10 by supplying data line signals DATAP / N to the source driver 12. The timing controller 11 is connected to the source driver 12 via a peer-to-peer interface (hereinafter referred to as P2PIF) and transmits the data line signals DATAP / N using a differential signaling method such as mini-LVDS.

[0046] The data line signal DATAP / N is a serial data signal formed by alternating and continuously transmitting a preamble signal and one frame's worth of display image data (hereinafter referred to as display data). The preamble signal includes training pattern data for clock training. The so-called training pattern data is data used for clock training performed in the source driver 12 to stably fix the phase and frequency of the internal clock. During the display period of one frame, the timing controller first supplies the preamble signal including the training pattern data to the source driver 12, and then supplies one frame's worth of display data to the source driver 12.

[0047] By transmitting the training pattern data, the P2PIF between the timing controller 11 and the source driver 12 switches from an unlocked state (unstable state) to a locked state (stable state). Therefore, the transmission of display data in the display period after the clock training period is normally performed via the locked P2PIF (i.e., without the influence of noise, etc.).

[0048] The timing controller 11 also supplies a data switching signal SFC to the source driver 12. This data switching signal SFC allows the source driver 12 to determine whether the data line signal DATAP / N is training pattern data or display data. For example, when the timing controller 11 supplies training pattern data as the data line signal DATAP / N, it supplies the data switching signal SFC at an "L" level to the source driver 12. Alternatively, when the timing controller 11 supplies display data as the data line signal DATAP / N, it supplies the data switching signal SFC at an "H" level to the source driver 12.

[0049] The source driver 12 is a display driver that generates n image drive voltages per horizontal scan line based on display data supplied from the timing controller 11 via the P2PIF. These voltages are applied to source lines D1 through Dn of the display panel 10. In this embodiment, the source driver 12 comprises an integrated circuit (IC). Furthermore, the source driver 12 supplies a gate control signal CS to the gate driver 13 for controlling its operation.

[0050] The source driver 12 also includes an unlocked state detection circuit 21 and a reset signal generation circuit 22. The unlocked state detection circuit 21 detects whether the P2PIF is unlocked based on data transmitted via the P2PIF. For example, data containing an error code is transmitted from the timing controller 11 to the unlocked state detection circuit 21 as the data line signal DATAP / N. The unlocked state detection circuit 21 performs error detection based on this data, thereby detecting the unlocked state of the P2PIF.

[0051] The reset signal generation circuit 22 generates a gate reset signal RS for stopping the operation of the gate driver 13. For example, the reset signal generation circuit 22 generates an "H" level gate reset signal RS when the unlocked state of the P2PIF is detected, and generates an "L" level gate reset signal RS when the unlocked state is not detected. Furthermore, in this embodiment, the source driver 12 is directly connected to the gate driver 13 via a signal line, so that the gate reset signal RS generated by the reset signal generation circuit 22 is supplied to the gate driver 13.

[0052] The gate driver 13 includes a gate control circuit 31 and a reset circuit 32. The gate control circuit 31 generates gate pulses based on a gate control signal CS supplied from the source driver 12 and sequentially and selectively applies the gate pulses to the scanning lines S1 to Sm of the display panel 10. The reset circuit 32 stops the gate control circuit 31 from applying the gate pulses in response to a gate reset signal RS supplied from the source driver 12, thereby resetting the gate control circuit 31.

[0053] Next, refer to Figure 2 The operation of the display device 100 of this embodiment will be described with reference to the timing diagram of FIG. Furthermore, the operation will be described here in the case where an unlocked state occurs in the P2PIF between the timing controller 11 and the source driver 12 during the display period.

[0054] First, during the clock training period (in Figure 2In the period (indicated as CT period), the timing controller 11 supplies the data switching signal SFC of "L" level to the source driver 12. In addition, in the period, the timing controller 11 supplies the training pattern data (indicated as CT period) of the source driver 12. Figure 2 The data (represented as T-data) is supplied to the source driver 12. The interface between the timing controller 11 and the source driver 12, that is, the P2PIF, switches from the unlocked state to the locked state.

[0055] Next, during the normal data display period (in Figure 2 In the display period L1DP (indicated as L1DP, L2DP, ..., LNDP), the timing controller 11 supplies the data switching signal SFC at an "H" level to the source driver 12. Furthermore, the timing controller 11 supplies display data as data line signals DATAP / N to the source driver 12. For example, the timing controller 11 first supplies display data D1 for displaying an image in the display cells of the first line (i.e., the display cells along the horizontal scan line S1) to the source driver 12 in the display period L1DP.

[0056] The source driver 12 generates a gate control signal CS based on the display data D1 and supplies it to the gate driver 13. In response to the gate control signal CS, the gate control circuit 31 of the gate driver 13 becomes active, applying a gate pulse to the first horizontal scan line S1. Furthermore, the source driver 12 applies n image drive voltages, corresponding to one horizontal scan line, to the source lines D1 through Dn of the display panel 10. This enables display on one line of the display panel 10.

[0057] Next, during the display period L2DP, the timing controller 11 supplies display data D2, used to display an image on the display cells of the second line (i.e., the display cells along the horizontal scan line S2), to the source driver 12 as data line signals DATAP / N. At this time, if the P2PIF, an interface between the timing controller 11 and the source driver 12, becomes unlocked due to noise such as ESD, an abnormality may occur in the transmission of the data line signals DATAP / N.

[0058] The unlocked state detection circuit 21 of the source driver 12 detects the unlocked state of the P2PIF based on the data line signal DATAP / N supplied from the timing controller 11. In response to the unlocked state being detected by the unlocked state detection circuit 21, the reset signal generation circuit 22 supplies an "H" level gate reset signal RS to the gate driver 13.

[0059] In response to the supply of the "H" level gate reset signal RS, the reset circuit 32 of the gate driver 13 stops the operation of the gate control circuit 31, thereby resetting the operation state. As a result, the gate control circuit 31 stops applying the gate pulse, and the display panel 10 maintains the previous display state.

[0060] The reset signal generating circuit 22 of the source driver 12 continues to supply the gate reset signal RS at an "H" level until the end of one frame period (i.e., until the display period LNDP). In response to this, the reset circuit 32 of the gate driver 13 stops the operation of the gate control circuit 31, thereby maintaining the previous display state in the display panel 10 until the end of one frame period.

[0061] When the next frame period begins, the source driver 12 returns the gate reset signal RS to "L" level. Since the beginning of a frame period is a clock training period, the timing controller 11 supplies the data switching signal SFC at "L" level and the training pattern data to the source driver 12. The P2PIF between the timing controller 11 and the source driver 12 switches from an unlocked state to a locked state.

[0062] In the following display period, the timing controller 11 sequentially supplies the display data D1, display data D2, ... display data Dn as data line signals DATAP / N to the source driver 12. The source driver 12 supplies the gate control signal CS to the gate driver 13. The gate control circuit 31 of the gate driver 13 becomes active and applies gate pulses to each horizontal scan line S1 to horizontal scan line Sm. The source driver 12 applies the image drive voltage to the source lines D1 to Dn of the display panel 10. When the unlocked state due to ESD noise or the like does not occur in the P2PIF, the image is displayed normally in sequence starting from the first line in the display panel 10.

[0063] As described above, in the display device 100 of this embodiment, when the source driver 12 detects that the P2PIF has become unlocked during the display period, the source driver 12 supplies the gate reset signal RS to the gate driver 13, thereby stopping the operation of the gate control circuit 31. In response, the display panel 10 maintains the previous display state.

[0064] According to the display device 100 of this embodiment, it is possible to suppress erroneous display of the display panel 10 caused by the unlocking of the P2PIF between the timing controller 11 and the source driver 12 during the display period of the image. Figures 3 to 5 While explaining.

[0065] Figure 3This is a timing diagram illustrating the operation of the display device of Comparative Example 1. Unlike this embodiment, the source driver 12 of the display device of Comparative Example 1 does not generate and supply the gate reset signal RS. Operations during the clock training period and the display period L1DP are the same as those of the display device 100 of this embodiment.

[0066] During the display period L2DP, if noise caused by ESD occurs and the P2PIF becomes unlocked, the display data output from the timing controller 11 will not be normally input to the source driver 12. Therefore, the source driver 12 cannot output the gate control signal CS and pixel driving voltage (i.e., source output) of normal values.

[0067] Figure 4 This figure schematically illustrates the display mode of the display panel in the display device of Comparative Example 1. If the P2PIF is unlocked during the display period L2DP, normal gate pulses and pixel drive voltages are not applied. As a result, the image displayed on the second line (horizontal scan line S2) and beyond is different from the intended display content (i.e., an erroneous display).

[0068] In contrast, Figure 5 This figure schematically illustrates the display state of the display panel 10 in the display device 100 of this embodiment. When the P2PIF is unlocked during the display period L2DP, the gate reset signal RS is supplied from the source driver 12 to the gate driver 13, stopping the application of the gate pulse and maintaining the previous display state of the display panel 10. Therefore, unlike the display device of Comparative Example 1, no erroneous display occurs in the display panel 10.

[0069] As described above, according to the display device of this embodiment, it is possible to suppress erroneous display on the display panel due to the influence of noise or the like.

[0070] [Example 2]

[0071] Next, a second embodiment of the present invention will be described. The display device of this embodiment differs from the display device of the first embodiment in that the source driver of the display device of this embodiment includes a plurality of driver ICs.

[0072] Figure 6 1 is a block diagram showing the configuration of a display device 200 according to this embodiment. The display device 200 includes a display panel 20 , a timing controller 11 , a first driver IC 12A, a second driver IC 12B, and a gate driver 13 .

[0073] The display panel 20 is an image display element including a liquid crystal display panel or an organic EL panel. The display panel 20 includes m (m is a natural number greater than or equal to 2) horizontal scan lines S1 to Sm extending horizontally across the two-dimensional screen, and 2n (n is a natural number greater than or equal to 2) source lines D1 to D2n extending vertically across the two-dimensional screen. In other words, the display panel 20 of this embodiment has a horizontal width approximately twice that of the display panel 10 of Example 1. Display cells with pixels are formed in the regions where the horizontal scan lines and source lines intersect.

[0074] The timing controller 11 is connected to the first driver IC 12A and the second driver IC 12B via the P2PIF to supply data line signals DATAP / N. The timing controller 11 supplies display data or training pattern data as data line signals DATAP / N to the first driver IC 12A and the second driver IC 12B, respectively. Similar to Example 1, the P2PIF switches from an unlocked state to a locked state by transmitting the training pattern data during the clock training period. Therefore, the transmission of display data during the display period after the clock training period is normally performed (i.e., without the influence of noise, etc.) via the locked P2PIF.

[0075] The timing controller 11 also supplies a data switching signal SFC to each of the first driver IC 12A and the second driver IC 12B. The timing controller 11 supplies the data switching signal SFC at an "L" level to each of the first driver IC 12A and the second driver IC 12B when supplying training pattern data, and supplies the data switching signal SFC at an "H" level to each of the first driver IC 12A and the second driver IC 12B when supplying display data.

[0076] The first driver IC 12A is a driver IC that generates n image drive voltages for each horizontal scan line based on display data supplied from the timing controller 11 via the P2PIF, and applies these voltages to the source lines D1 through Dn of the display panel 10. Similar to the source driver 12 in Example 1, the first driver IC 12A generates and outputs a gate control signal CS1 and a gate reset signal RS1. However, since the first driver IC 12A and the gate driver 13 are not connected by signal lines, the gate control signal CS and gate reset signal RS output from the first driver IC 12A are not supplied to the gate driver 13.

[0077] On the other hand, the second driver IC 12B is a driver IC that generates n image drive voltages for each horizontal scan line based on display data supplied from the timing controller 11 via the P2PIF, and applies these voltages to source lines Dn+1 through D2n of the display panel 20. Unlike the first driver IC 12A, the second driver IC 12B is connected to the gate driver 13 via a signal line. The second driver IC 12B generates a gate control signal CS2 and supplies it to the gate driver 13. Furthermore, the second driver IC 12B generates a gate reset signal RS2 and supplies it to the gate driver 13.

[0078] Furthermore, the first driver IC 12A and the second driver IC 12B are connected via a transmission line L1 for a lock signal S1. The lock signal S1 is a signal that reaches an "L" level when either the first driver IC 12A or the second driver IC 12B detects the unlocked state of the P2PIF, and reaches an "H" level otherwise. Transmission line L1 is connected to a power supply that supplies the power supply voltage VDD, so that the lock signal S1 has a voltage level equal to the power supply voltage VDD when it is "H."

[0079] Figure 7 1 is a circuit diagram showing the configuration of the reset signal generating circuit of each of the first driver IC 12A and the second driver IC 12B. The gate driver 13 and the unlock state detection circuit of each driver IC are also shown here.

[0080] The first driver IC 12A includes an unlocked state detection circuit 21A and a reset signal generation circuit 22A. The unlocked state detection circuit 21A detects whether the P2PIF between the timing controller 11 and the first driver IC 12A is in the unlocked state based on the data line signal DATAP / N supplied from the timing controller 11. Upon detecting the unlocked state of the P2PIF, the unlocked state detection circuit 21A supplies an "H" level state detection signal DS1 to the reset signal generation circuit 22A.

[0081] Reset signal generation circuit 22A includes transistor MN1 and inverter INV1. Transistor MN1 is an N-channel metal oxide semiconductor (MOS) transistor. The source of transistor MN1 is grounded, and the gate receives the state detection signal DS1. The drain of transistor MN1 serves as an open-drain terminal connected to transmission line L1 of lock signal S1.

[0082] Inverter INV1 is an inverter circuit that inverts an input signal and outputs it. The input of inverter INV1 is connected to the drain of transistor MN1 and to transmission line L1 for lock signal S1. Therefore, the output of inverter INV1 outputs a signal having a logic opposite to that of lock signal S1 as gate reset signal RS1. Furthermore, as described above, first driver IC 12A is not directly connected to gate driver 13, so reset signal RS1 is not supplied to gate driver 13.

[0083] The second driver IC 12B includes an unlocked state detection circuit 21B and a reset signal generation circuit 22B. The unlocked state detection circuit 21B detects whether the P2PIF between the timing controller 11 and the second driver IC 12B is in the unlocked state based on the data line signal DATAP / N supplied from the timing controller 11. Upon detecting that the P2PIF is in the unlocked state, the unlocked state detection circuit 21B supplies an "H" level state detection signal DS2 to the reset signal generation circuit 22B.

[0084] Reset signal generation circuit 22B includes transistor MN2 and inverter INV2. Transistor MN2 is an N-channel MOS transistor. The source of transistor MN2 is grounded, and the gate receives the state detection signal DS2. The drain of transistor MN2 is connected as an open-drain terminal to transmission line L1 of lock signal S1.

[0085] Inverter INV2 is an inverter circuit that inverts the input signal and outputs it. The input of inverter INV2 is connected to the drain of transistor MN2 and to transmission line L1 for lock signal S1. Therefore, the output of inverter INV2 outputs a signal having a logic opposite to that of lock signal S1 as gate reset signal RS2. Unlike the first driver IC 12A, the second driver IC 12B is connected to the gate driver 13 via a signal line, so the gate reset signal RS2 is supplied to the gate driver 13.

[0086] For example, when the unlocked state detection circuit 21A of the first driver IC 12A detects the unlocked state of the P2PIF, the unlocked state detection circuit 21A applies an "H" level state detection signal DS1 to the gate of the transistor MN1. As a result, the transistor MN1 becomes conductive, and the signal level of the lock signal S1 becomes "L" level (i.e., the ground potential VSS level). The "L" level lock signal S1 output from the reset signal generation circuit 22A is input to the inverter INV2 of the reset signal generation circuit 22B via the transmission line L1. The inverter INV2 outputs an "H" level reset signal RS2, which is an inverted version of the "L" level lock signal S1, and supplies it to the gate driver 13.

[0087] On the other hand, when the unlocked state detection circuit 21B of the second driver IC 12B detects that the P2PIF is in the unlocked state, the unlocked state detection circuit 21B applies an "H" level state detection signal DS2 to the gate of the transistor MN2. This turns on the transistor MN2, and the signal level of the lock signal S1 becomes "L" level (i.e., the ground potential VSS level). The inverter INV2 outputs an "H" level reset signal RS2, which is an inverted version of the "L" level lock signal S1, and supplies it to the gate driver 13.

[0088] When the unlock state of the P2PIF is not detected in any driver IC, the transistor MN1 and the transistor MN2 are not turned on, and the signal level of the lock signal S1 is maintained at the “H” level (ie, the power supply potential VDD level).

[0089] As described above, in the display device 200 of this embodiment, when either the first driver IC 12A or the second driver IC 12B detects the unlocked state of the P2PIF, the gate reset signal RS at an "H" level is supplied to the gate driver 13. On the other hand, when neither the first driver IC 12A or the second driver IC 12B detects the unlocked state of the P2PIF, the gate reset signal RS at an "L" level is supplied to the gate driver 13.

[0090] Refer again Figure 6 The gate driver 13 includes a gate control circuit 31 and a reset circuit 32. The gate control circuit 31 generates gate pulses based on a gate control signal CS2 supplied from the second driver IC 12B, and sequentially and selectively applies the gate pulses to the scanning lines S1 to Sm of the display panel 20. In response to a gate reset signal RS2 supplied from the second driver IC 12B, the reset circuit 32 stops the gate control circuit 31 from applying the gate pulses, thereby resetting the gate control circuit 31.

[0091] Next, refer to Figure 8 The operation of the display device 200 of this embodiment will be described with reference to the timing chart of FIG. Furthermore, the operation will be described here in the case where an unlocked state occurs in the P2PIF between the timing controller 11 and the first driver IC 12A during the display period.

[0092] First, during the clock training period (in Figure 8 In the period (indicated as CT period), the timing controller 11 supplies the data switching signal SFC of “L” level to the first driver IC 12A and the second driver IC 12B. In addition, in the period, the timing controller 11 supplies the training pattern data (indicated as CT period) to the first driver IC 12A and the second driver IC 12B. Figure 8 The P2PIF (represented as T-data in FIG) is supplied to the first driver IC 12A and the second driver IC 12B. The interface between the timing controller 11 and the first driver IC 12A, namely, the P2PIF, switches from the unlocked state to the locked state. Similarly, the interface between the timing controller 11 and the second driver IC 12B, namely, the P2PIF, switches from the unlocked state to the locked state.

[0093] Next, during the normal data display period (in Figure 8 During the display period L1DP (indicated as L1DP, L2DP, ..., LNDP in the figure), the timing controller 11 supplies an "H" level data switching signal SFC to the first driver IC 12A and the second driver IC 12B. Furthermore, the timing controller 11 supplies display data as data line signals DATAP / N to the first driver IC 12A and the second driver IC 12B. For example, during the display period L1DP, the timing controller 11 first supplies display data D1 for displaying an image on the display cells of the first line (i.e., the display cells along the horizontal scan line S1) to the first driver IC 12A and the second driver IC 12B.

[0094] The second driver IC 12B supplies the gate control signal CS2 to the gate driver 13. In response, the gate control circuit 31 of the gate driver 13 becomes active, applying a gate pulse to the first horizontal scan line S1. Furthermore, the first driver IC 12A applies n image drive voltages corresponding to one horizontal scan line to the source lines D1 through Dn of the display panel 20. Similarly, the second driver IC 12B applies n image drive voltages corresponding to one horizontal scan line to the source lines Dn+1 through D2n of the display panel 20. This enables display on one line of the display panel 20.

[0095] Next, during the display period L2DP, the timing controller 11 supplies display data D2, used to display an image on the display cells of the second line (i.e., the display cells along the horizontal scan line S2), to the first driver IC 12A and the second driver IC 12B as data line signals DATAP / N. At this time, if the P2PIF, the interface between the timing controller 11 and the first driver IC 12A, becomes unlocked due to noise such as ESD, an abnormality may occur in the transmission of the data line signals DATAP / N between the timing controller 11 and the first driver IC 12A.

[0096] The unlocked state detection circuit 21A of the first driver IC 12A detects the unlocked state of the P2PIF between the timing controller 11 and the first driver IC 12A based on the data line signal DATAP / N supplied from the timing controller 11. The circuit then applies an "H" level state detection signal DS1 to the gate of the transistor MN1. This turns on the transistor MN1, and the signal level of the lock signal S1 becomes "L."

[0097] The inverter INV2 of the reset signal generating circuit 22B of the second driver IC 12B receives the “L” level lock signal S1 at its input terminal and outputs the “H” level gate reset signal RS2 which is an inversion of the lock signal S1 . The gate reset signal RS2 is supplied to the gate driver 13 .

[0098] In response to the supply of the "H" level gate reset signal RS, the reset circuit 32 of the gate driver 13 stops the operation of the gate control circuit 31, thereby resetting the operation state. As a result, the gate control circuit 31 stops applying the gate pulse, and the display panel 20 maintains the previous display state.

[0099] When the next frame period begins, the second driver IC 12B returns the gate reset signal RS2 to "L" level. Since the beginning of a frame period is a clock training period, the timing controller 11 supplies the "L" level data switching signal SFC and training pattern data to the first and second driver ICs 12A and 12B. The P2PIF between the timing controller 11 and the first driver IC 12A switches from an unlocked state to a locked state. The P2PIF between the timing controller 11 and the second driver IC 12B remains locked.

[0100] In the following display period, the timing controller 11 sequentially supplies display data D1, display data D2, ..., display data Dn as data line signals DATAP / N to the first driver IC 12A and the second driver IC 12B. The second driver IC 12B supplies the gate control signal CS to the gate driver 13. The gate control circuit 31 of the gate driver 13 becomes active and applies gate pulses to each horizontal scan line S1 to horizontal scan line Sm. The first driver IC 12A applies the image drive voltage to the source lines D1 to Dn of the display panel 20. The second driver IC 12B applies the image drive voltage to the source lines Dn+1 to D2n of the display panel 20. When an unlocked state due to ESD noise or the like does not occur in the P2PIF, the image is displayed normally in sequence starting from the first line on the display panel 20.

[0101] As described above, in the display device 200 of this embodiment, when the first driver IC 12A detects that the P2PIF between the timing controller 11 and the first driver IC 12A has become unlocked during the display period, it supplies an "L" level lock signal S1 to the second driver IC 12B. The second driver IC 12B then supplies an "H" level gate reset signal RS, which is an inverted version of the "L" level lock signal S1, to the gate driver 13, thereby stopping the operation of the gate control circuit 31. In response, the display panel 20 maintains the previous display state.

[0102] According to the display device 200 of this embodiment, even if the P2PIF between the first driver IC 12A not directly connected to the gate driver 13 and the timing controller 11 is in the unlocked state, erroneous display of the display panel 20 can be suppressed. Figures 9 to 11 Provide explanation.

[0103] Figure 9 This is a timing diagram illustrating the operation of a display device according to Comparative Example 2. Unlike this embodiment, the first driver IC 12A and the second driver IC 12B of the display device according to Comparative Example 2 do not have a signal terminal for the lock signal S1 (i.e., the lock signal S1 is not transmitted via the transmission line L1). Operations during the clock training period and the display period L1DP are the same as those of the display device 200 according to this embodiment.

[0104] During the display period L2DP, if ESD-induced noise occurs and the P2PIF between the timing controller 11 and the first driver IC 12A becomes unlocked, the display data output from the timing controller 11 will not be properly fed into the first driver IC 12A. Consequently, the first driver 12A will not be able to output a normal pixel driving voltage (i.e., source output).

[0105] Furthermore, since the first driver IC 12A and the gate driver 13 are not connected by a signal line, the gate reset signal RS outputted from the first driver IC 12A is not supplied to the gate driver 13. Therefore, the gate control circuit 31 continues the same gate pulse application operation as usual.

[0106] Figure 10Schematic diagram of the display panel in the display device of Comparative Example 2. If the P2PIF between the timing controller 11 and the first driver IC 12A is unlocked during the display period L2DP, normal pixel drive voltages are not applied to the source lines D1 to Dn. Consequently, the image displayed on the second line (horizontal scan line S2) and beyond in the left half of the display device 20 differs from the intended display content (i.e., an erroneous display).

[0107] In contrast, Figure 11 This diagram schematically illustrates the display configuration of the display panel 20 in the display device 200 of this embodiment. When the P2PIF between the timing controller 11 and the first driver IC 12A is unlocked during the display period L2DP, the lock signal S1 reaches an "L" level, and the reset signal generation circuit 22B of the second driver IC 12B supplies an "H" level gate reset signal RS2 to the gate driver 13. This stops the application of gate pulses, maintaining the previous display state of the display panel 20. Therefore, unlike the display device of Comparative Example 2, no erroneous display occurs in the display panel 20.

[0108] As described above, according to the display device of this embodiment, when the source driver includes a plurality of driver ICs, it is possible to suppress erroneous display on the display panel due to the influence of noise or the like.

[0109] For example, in the second embodiment, the source driver includes two driver ICs. However, the number of driver ICs is not limited to this, and the present invention is also applicable to a case where three or more driver ICs are included.

[0110] The method used by the unlocked state detection circuit 21 (21A, 21B) to detect the unlocked state of the P2PIF is not particularly limited. For example, the timing controller 11 may supply data containing an error code as the data line signals DATAP / N to the source driver 12, and the source driver 12 may detect the unlocked state of the P2PIF by performing error detection. Alternatively, the unlocked state of the P2PIF may be detected based on the waveform of the data line signals DATAP / N.

Claims

1. A display device, characterized in that: include: A display panel having a plurality of data lines and a plurality of scan lines, and pixel switches and pixel portions arranged at respective intersections of the plurality of data lines and the plurality of scan lines; a gate driver for supplying gate signals to the plurality of scanning lines to control the pixel switches to be turned on; A display controller outputs a serial data signal, wherein the serial data signal is formed by alternating and continuous preambles and image data displayed on the display panel; as well as a source driver connected to the display controller via an interface, detecting a locked state or an unlocked state of the interface based on the serial data signal transmitted from the display controller via the interface, and outputting a gate reset signal for stopping supply of the gate signal from the gate driver when the unlocked state of the interface is detected during supply of the image data; The preamble of the serial data signal includes a data pattern for clock training. By transmitting the data pattern for clock training, the interface switches from the unlocked state to the locked state. The source driver detects that the interface becomes unlocked during the transmission of the image data which starts with the interface in the locked state after the transmission of the clock training data pattern.

2. The display device according to claim 1, wherein The source driver includes: a detection unit that detects a locked state or an unlocked state of the interface based on the serial data signal; and a gate reset signal output unit that is connected to the detection unit and supplies the gate reset signal to the gate driver.

3. The display device according to claim 1 or 2, characterized in that The serial data signal is a signal in which a preamble and one frame of the image data of the display panel are alternately continuous. In response to stopping supply of the gate signal from the gate driver based on the gate reset signal, the display panel maintains a display state of a previous frame.

4. A display driver connected to a display panel and a gate driver, wherein the display panel includes a plurality of data lines and a plurality of scan lines, and pixel switches and pixel portions disposed at respective intersections of the plurality of data lines and the plurality of scan lines, the gate driver supplies gate signals to the plurality of scan lines to control the pixel switches to be conductive, and the display driver supplies grayscale voltage signals corresponding to image data to the plurality of data lines, wherein: The display controller is connected to the display controller via an interface and receives a serial data signal from the display controller via the interface. The serial data signal is a preamble and the image data that are alternately transmitted continuously. The display driver includes: a detection unit configured to detect whether the interface is in a locked state or an unlocked state based on the serial data signal transmitted via the interface; as well as a gate reset signal output unit that outputs a gate reset signal for stopping the operation of the gate driver when the detection unit detects the unlocked state of the interface during the supply of the image data; The preamble of the serial data signal includes a data pattern for clock training. By transmitting the data pattern for clock training, the interface switches from the unlocked state to the locked state. The detection unit detects that the interface is unlocked during the transmission of the video data which is started with the interface in the locked state after the transmission of the clock training data pattern.

Images