SSD video recorder and data processing method

Abstract

An SSD video recorder and data processing method provided by an embodiment of the present application are applied to the field of information technology. The SSD video recorder includes a SOC chip and an SSD chip, and the SOC chip and the SSD chip are connected via a data channel established by a PIN pin; the SOC chip is used to obtain target data; forward the target data to the SSD chip via the data channel; the SSD chip is used to receive the target data; store the target data in its own designated location; and / or, the SOC chip is used to receive a first read instruction to read the target data; send a second read instruction for reading the target data to the SSD chip; the SSD chip is used to receive the second read instruction; send the target data to the SOC chip; the SOC chip is also used to receive the target data sent by the SSD chip and output it. By replacing the mechanical hard disk or solid-state SSD hard disk in the prior art with an SSD chip that is much smaller than the mechanical hard disk or solid-state SSD hard disk, the size of the video recorder can be reduced and the convenience of the SSD video recorder can be improved.

Description

Technical Field

[0001] The present application relates to the field of information technology, and in particular to an SSD video recorder and a data processing method. Background Art

[0002] DVRs are now widely used. They enable long-term recording, audio recording, remote monitoring, and control of audio and video. For example, when using a surveillance camera, the captured audio and video data can be stored in a DVR for easy playback and viewing.

[0003] However, in the related art, hard disk recorders often use mechanical disks or solid-state SSD hard disks to store data. Figure 1 The hard disk recorder on the middle left not only takes up a large space for the mechanical disk or solid-state SSD hard disk, but also requires a dedicated board interface to connect with the mechanical disk or solid-state SSD hard disk, which results in the hard disk recorder chassis being often large and inconvenient to use. Summary of the Invention

[0004] The purpose of the embodiments of the present application is to provide an SSD video recorder and a data processing method to reduce the size of the hard disk video recorder. The specific technical solution is as follows:

[0005] In a first aspect of an embodiment of the present application, an SSD video recorder is provided, comprising:

[0006] An SOC chip and an SSD chip, wherein the SOC chip and the SSD chip are connected via a data channel established by a PIN pin;

[0007] The SOC chip is used to obtain target data; forward the target data to the SSD chip through the data channel; the SSD chip is used to receive the target data; and store the target data in its own designated location;

[0008] and / or,

[0009] The SOC chip is used to receive a first read instruction for reading target data, wherein the first read instruction is an instruction sent by the client requesting to obtain the target data; send a second read instruction for reading the target data to the SSD chip, wherein the second read instruction is an instruction sent by the SOC chip requesting to obtain the target data in the SSD chip; the SSD chip is used to receive the second read instruction; send the target data to the SOC chip; the SOC chip is also used to receive the target data sent by the SSD chip and output it.

[0010] In a possible implementation, the SSD recorder further includes an audio and video AD chip;

[0011] The audio and video AD chip is used to receive audio and video data of analog signals; convert the audio and video data of the analog signals into digital signals to obtain the target data; and send the target data to the SOC chip.

[0012] In a possible implementation, the data channel is SATA or PCIE.

[0013] In a possible implementation manner, the SOC chip and the SSD chip are further connected via a first management channel;

[0014] The SOC chip is further configured to obtain status information of the SSD chip through the first management channel, and to send a control instruction to the SSD chip when the status information meets a preset trigger condition.

[0015] In a possible implementation, the first management channel is at least one of GPIO, UART, RS232, SMBus, and I2C.

[0016] In a possible implementation, the SOC chip is further connected to a control terminal of a power module of the SSD chip through a second management channel, and the SSD chip is connected to a power supply terminal of the power module;

[0017] The SOC chip is further configured to send a power control instruction to the control terminal of the power module of the SSD chip through the second management channel.

[0018] In a possible implementation, the second management channel is at least one of GPIO, UART, RS232, SPI, and SMBus.

[0019] In a possible implementation manner, the control instruction is a level signal;

[0020] The SOC chip is specifically used to send a level signal to the control end of the power module of the SSD chip to control the restart of the SSD chip when the status information of the SSD chip cannot be obtained through the data channel and / or the first management channel, and / or a restart instruction is received, and / or the obtained status information meets the preset restart conditions.

[0021] In one possible embodiment, the SOC chip is specifically used to input a first level signal to the power control pin of the power module of the SSD chip to power off the SSD chip; after a preset time period, input a second level signal to the power control pin of the power module of the SSD chip to power on the SSD chip.

[0022] In one possible implementation, the SOC chip is further used to obtain an SSD upgrade package; detect the file header information of the SSD upgrade package, and determine whether the file header information meets preset requirements; if so, obtain the type information of the SSD chip; when the type information indicates SSD, send the SSD upgrade package to the SSD chip, so that the SSD chip is upgraded through the SSD upgrade package.

[0023] In a possible implementation, the SOC chip is specifically configured to obtain the SSD upgrade package through one of the ISAPI protocol, the HIK SDK protocol, and a preset private protocol.

[0024] In a possible implementation, the SSD recorder further includes NAND Flash, a CVBS interface, an alarm expansion interface, and DDR particles;

[0025] The NAND Flash is used to store onboard programs and user configurations;

[0026] The CVBS interface is used to connect to an external CVBS display;

[0027] The alarm expansion interface is used to access the matching alarm board;

[0028] The DDR particles are used to operate as the running memory of the SOC chip.

[0029] A second aspect of an embodiment of the present application provides a data processing method applied to an SSD video recorder, wherein the SSD video recorder includes a SOC chip and an SSD chip, wherein the SOC chip and the SSD chip are connected via a data channel established by a PIN pin;

[0030] The method comprises:

[0031] Acquire target data through the SOC chip; forward the target data to the SSD chip through the data channel through the SOC chip; receive the target data through the SSD chip; store the target data in its own designated location through the SSD chip;

[0032] and / or,

[0033] A first read instruction for reading target data is received through the SOC chip, wherein the first read instruction is an instruction sent by the client requesting to obtain the target data; a second read instruction for reading the target data is sent to the SSD chip through the SOC chip, wherein the second read instruction is an instruction sent by the SOC chip requesting to obtain the target data in the SSD chip; the second read instruction is received through the SSD chip; the target data is sent to the SOC chip through the SSD chip; the target data sent by the SSD chip is received through the SOC chip and outputted.

[0034] In a possible implementation, the SSD recorder further includes an audio and video AD chip;

[0035] The method further comprises:

[0036] receiving the audio and video data of the analog signal through the audio and video AD chip; converting the audio and video data of the analog signal into a digital signal through the audio and video AD chip to obtain the target data; and sending the target data to the SOC chip through the audio and video AD chip;

[0037] In a possible implementation, the data channel is SATA or PCIE;

[0038] In a possible implementation, the SOC chip and the SSD chip are further connected via a first management channel; the SOC chip obtains status information of the SSD chip using the first management channel, and sends a control instruction to the SSD chip when the status information meets a preset trigger condition;

[0039] In a possible implementation, the first management channel is at least one of GPIO, UART, RS232, SMBus, and I2C;

[0040] In one possible implementation, the SOC chip is further connected to a control terminal of a power module of the SSD chip via a second management channel, and the SSD chip is connected to a power supply terminal of the power module; the SOC chip sends a power control instruction to the control terminal of the power module of the SSD chip via the second management channel;

[0041] In a possible implementation manner, the second management channel is at least one of GPIO, UART, RS232, SPI, and SMBus;

[0042] In one possible implementation, the control instruction is a level signal; when the SOC chip cannot obtain status information of the SSD chip through the data channel and / or the first management channel, and / or receives a restart instruction, and / or the obtained status information meets a preset restart condition, the SOC chip sends a level signal to the control terminal of the power module of the SSD chip to control the SSD chip to restart;

[0043] In one possible implementation, the SOC chip inputs a first level signal to a power control pin of a power module of the SSD chip to power off the SSD chip; and after a preset time has passed, the SOC chip inputs a second level signal to the power control pin of the power module of the SSD chip to power on the SSD chip.

[0044] In one possible implementation, an SSD upgrade package is obtained through the SOC chip; file header information of the SSD upgrade package is detected through the SOC chip, and it is determined whether the file header information meets preset requirements; if so, type information of the SSD chip is obtained; and when the type information indicates SSD, the SSD upgrade package is sent to the SSD chip, so that the SSD chip is upgraded using the SSD upgrade package;

[0045] In a possible implementation, the SSD upgrade package is obtained by the SOC chip using one of the ISAPI protocol, the HIK SDK protocol, and a preset private protocol;

[0046] In a possible implementation, the SSD recorder further includes NAND Flash, a CVBS interface, an alarm expansion interface, and DDR particles; the NAND Flash is used to store onboard programs and user configurations; the CVBS interface is used to connect to an external CVBS display; the alarm expansion interface is used to connect to a matching alarm board; and the DDR particles are used to operate as the running memory of the SOC chip.

[0047] Beneficial effects of the embodiments of the present application:

[0048] An embodiment of the present application provides an SSD video recorder and a data processing method. The SSD video recorder includes a SOC chip and an SSD chip, wherein the SOC chip and the SSD chip are connected via a data channel established by a PIN pin; the SOC chip is used to obtain target data; forward the target data to the SSD chip via the data channel; the SSD chip is used to receive the target data; store the target data in its own designated location; and / or, the SOC chip is used to receive a first read instruction for reading target data, wherein the first read instruction is an instruction sent by a client requesting to obtain the target data; send a second read instruction for reading the target data to the SSD chip, wherein the second read instruction is an instruction sent by the SOC chip requesting to obtain the target data in the SSD chip; the SSD chip is used to receive the second read instruction; send the target data to the SOC chip; the SOC chip is also used to receive the target data sent by the SSD chip and output it. Through the solution of the embodiment of the present application, not only can the SSD chip be used to receive and store the audio and video data sent by the SOC chip through the data channel between the SOC chip and the SSD chip, but the target data can also be read from the SSD chip after the SOC chip receives the read instruction sent by the client. Moreover, the mechanical hard disk or solid-state SSD hard disk in the prior art can be replaced by an SSD chip whose volume is much smaller than that of the mechanical hard disk or solid-state SSD hard disk, thereby reducing the volume of the video recorder and improving the convenience of the SSD video recorder.

[0049] Of course, it is not necessary to achieve all the advantages described above at the same time when implementing any product or method of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0051] Figure 1 A schematic diagram comparing the structures of the SSD video recorder provided in the embodiment of the present application and the SSD video recorder in the prior art;

[0052] Figure 2 A schematic structural diagram of an SSD video recorder provided in an embodiment of the present application;

[0053] Figure 3 Another structural diagram of an SSD video recorder provided in an embodiment of the present application;

[0054] Figure 4 This is a schematic diagram of an example of an SSD video recorder provided in an embodiment of the present application;

[0055] Figure 5 A schematic diagram of another structure of the SSD video recorder provided in an embodiment of the present application;

[0056] Figure 6 A schematic diagram of the power-off restart process of the SSD chip provided in an embodiment of the present application;

[0057] Figure 7 A schematic diagram of the interaction of the SSD chip provided in an embodiment of the present application;

[0058] Figure 8 A schematic diagram of another example of an SSD video recorder provided in an embodiment of the present application;

[0059] Figure 9 A flowchart of a data processing method provided in an embodiment of the present application;

[0060] Figure 10 Another flowchart of the data processing method provided in an embodiment of the present application;

[0061] Figure 11 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0062] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field based on this application are within the scope of protection of this application.

[0063] First, the professional terms that may be used in the embodiments of this application are explained:

[0064] SATA interface (Serial Advanced Technology Attachment) is an industry-standard serial hardware drive interface.

[0065] SSD: Solid State Disk, solid state drive;

[0066] GPIO: (General-purpose input / output, general-purpose input and output management channel);

[0067] UART: (Universal Asynchronous Receiver / Transmitter)

[0068] PCIE: PCI-Express (peripheral component interconnect express, a high-speed serial computer expansion bus standard).

[0069] In a first aspect of the embodiment of the present application, an SSD video recorder is first provided. Figure 2 include:

[0070] The SOC chip 101 and the SSD chip 102 are connected via a data channel established by PIN pins;

[0071] The SOC chip 101 is used to obtain target data and forward the target data to the SSD chip through the data channel; the SSD chip 102 is used to receive the target data and store the target data in its own designated location;

[0072] and / or,

[0073] SOC chip 101 is used to receive a first read instruction for reading target data, wherein the first read instruction is an instruction sent by the client to request obtaining the target data; and send a second read instruction for reading target data to the SSD chip, wherein the second read instruction is an instruction sent by the SOC chip to request obtaining the target data in the SSD chip; SSD chip 102 is used to receive the second read instruction; and send the target data to the SOC chip; SOC chip 101 is also used to receive the target data sent by the SSD chip and output it.

[0074] Among them, the SSD recorder in the present application can be applied to a variety of application scenarios, for example, it can be applied to monitoring scenarios, such as collecting audio and video data through a camera, sending the audio and video data to the SSD recorder, and storing the audio and video data in the SSD recorder, so as to facilitate video playback and analysis based on the audio and video data stored in the SSD recorder. Specifically, the SSD recorder in the embodiment of the present application can be a DVR (Digital Video Recorder) or an NVR (Network Video Recorder). The audio and video data in the embodiment of the present application can be various types of data. For example, when applied to monitoring scenarios, it is the video and sound captured by the monitoring camera. Specifically, it can be audio and video data in various formats, such as MP4 (Moving Picture Experts Group 4, a compression encoding format for video and audio information), AVI (Audio Video Interleaved, audio and video interleaved format), etc., and this application does not limit this.

[0075] The SOC (System on Chip) chip in the embodiment of the present application can be a main control chip, through which target data can be received and forwarded so that the SSD chip receives the target data and stores it, and / or, through which the SOC chip requests to obtain the target data in the SSD chip, and receives the target data sent by the SSD chip and outputs it.

[0076] The SSD chip in the implementation of this application can be a chip packaged by various packaging methods in the prior art. In one example, the SSD chip in the embodiment of this application can be a chip packaged by, but not limited to, BGA technology (Ball Grid Array, ball pin grid array packaging technology). Through this packaging technology, the PCB (printed circuit board), Flash controller, Flash (flash memory), SDRAM (synchronous dynamic random access memory), etc. in the traditional SSD board-level system can be integrated into an IC (Integrated Circuit Chip, a large number of microelectronic components) chip. By using SSD to replace the mechanical hard disk or solid-state SSD hard disk in the prior art, the SSD chip can be used to store audio and video data. Since a large storage unit is packaged into a small chip using BGA packaging technology, the size of the video recorder can be reduced. For example Figure 1 As shown, Figure 1 The left side is a schematic diagram of an SSD video recorder in the related art. Figure 1 The right side in the middle is a schematic diagram of the SSD video recorder in the embodiment of the present application. It can be seen that the size of the SSD video recorder in the embodiment of the present application is significantly smaller.

[0077] In the embodiment of the present application, the SSD chip is integrated into the circuit board of the SSD video recorder, omitting the cables connected to the traditional hard disk and the assembly process of the entire machine. Not only is the SSD video recorder simpler, but also because the SSD chip is smaller in size, by replacing the mechanical hard disk or solid-state SSD hard disk with this chip, the hard disk video recorder can be made smaller in size, thinner in appearance, and lower in chassis cost. Compared with traditional mechanical hard disks or solid-state SSD hard disks, the SSD chip has lower power consumption, which can be reduced by more than 30%, making the product more energy-saving and environmentally friendly. And unlike mechanical hard disks or solid-state SSD hard disks that require an independent power supply, the SSD chip can share a power module with the SOC chip, reducing the power adapter specifications and significantly reducing the cost of the video recorder. In addition, compared with traditional solid-state SSD hard disks, the SSD chip has better shock resistance and can improve the security of stored data.

[0078] The SOC chip acquires the target data and forwards it to the SSD chip through the data channel. The SSD chip receives the target data and stores it in its own designated location. This can be the process of an SSD recorder storing target data. The SOC chip receives a first read instruction to read the target data, sends a second read instruction to the SSD chip to read the target data, the SSD chip receives the second read instruction, and the SOC chip sends the target data. The SOC chip receives and outputs the target data sent by the SSD chip. This can refer to the process of reading data pre-stored in the SSD chip.

[0079] It can be seen that through the solution of the embodiment of the present application, not only can the SSD chip be used to receive and store and read the audio and video data sent by the SOC chip through the data channel connection between the SOC chip and the SSD chip, but the SSD can also be used to replace the mechanical hard disk or solid-state SSD hard disk in the prior art. Since a large storage unit is packaged into a small chip using BGA packaging technology, the size of the video recorder can be reduced.

[0080] In one possible implementation, see Figure 3 , the SSD video recorder also includes an audio and video AD (analog-to-digital conversion) chip 103;

[0081] The audio and video AD chip is used to receive audio and video data of analog signals; convert the audio and video data of analog signals into digital signals to obtain target data; and send the target data to the SOC chip.

[0082] In actual use, the audio and video data sent through the camera is often an analog signal, and the SSD recorder needs to convert the analog information into a digital signal for storage. Therefore, an audio and video AD chip is required to achieve the conversion of the signal form of the audio and video data. Specifically, the input end of the audio and video AD chip can be connected to the analog signal input port of the SSD recorder. The audio and video AD chip converts the analog signal into a digital signal to obtain the digital signal of the audio and video data to be stored. The output end of the audio and video AD chip is connected to the SOC chip to send the digital signal of the audio and video data to be stored to the SOC chip, and the SOC chip then sends the target data to the SSD chip for storage.

[0083] It can be seen that through the method of the embodiment of the present application, the audio and video AD chip can be used to convert the audio and video data of the analog signal into a digital signal to obtain the target data, so that the SOC chip can send the audio and video data to the SSD chip to realize the storage of the audio and video data.

[0084] In some scenarios, the camera sends audio and video data in the form of digital signals. For example, the SSD recorder also includes a digital signal interface. The audio and video data received through the digital signal interface can be processed by the SOC chip and sent directly to the SSD chip for storage without undergoing analog-to-digital conversion.

[0085] In one possible implementation, the data channel is SATA or PCIE. In one example, see Figure 4 The SOC chip can write audio and video data to the SSD chip through a data channel, or read data from the SSD chip. Specifically, the data channel can be a SATA channel.

[0086] In one possible implementation, see Figure 5 ,The SOC chip and the SSD chip are also connected via a first management channel;

[0087] The SOC chip is further configured to obtain status information of the SSD chip through the first management channel, and to send a control instruction to the SSD chip when the status information meets a preset trigger condition.

[0088] The management channel in the embodiment of the present application is used for low-speed data transmission between the SOC chip and the SSD chip. The management channel interface type may include one or more of GPIO, UART, RS232 (asynchronous transmission standard interface), SMBus (an interface standard), and I2C (a two-wire serial bus).

[0089] In one possible implementation, the SOC chip is further connected to a control terminal of a power module of the SSD chip through a second management channel, and the SSD chip is connected to a power supply terminal of the power module;

[0090] The SOC chip is further configured to send a power control instruction to the control terminal of the power module of the SSD chip through the second management channel.

[0091] In a possible implementation, the second management channel is at least one of GPIO, UART, RS232, SPI (Serial Peripheral Interface), and SMBus.

[0092] In a possible implementation, the control instruction is a level signal;

[0093] The SOC chip is specifically used to send a level signal to the control end of the power module of the SSD chip to control the restart of the SSD chip when the status information of the SSD chip cannot be obtained through the data channel and / or the first management channel, and / or a restart instruction is received, and / or the obtained status information meets the preset restart conditions.

[0094] In one possible embodiment, the SOC chip is specifically used to input a first level signal to the power control pin of the power module of the SSD chip to power off the SSD chip; after a preset time period, input a second level signal to the power control pin of the power module of the SSD chip to power on the SSD chip.

[0095] Specifically, in embodiments of the present application, the SSD chip status information may include the SSD chip's temperature, remaining capacity, and SSD chip voltage. For example, the SOC chip may obtain the SSD chip's current temperature through a universal management channel, and when it detects that the current temperature is greater than a preset threshold, it may generate and send a control instruction. The control instruction may be to control the SSD chip's power module to power on or off the SSD chip.

[0096] In one example, the SOC chip can implement SSD power switch control through a management channel. For example, the SOC chip can send a power-off or power-on instruction to the control terminal of the power module of the SSD chip through a GPIO.

[0097] In actual use, the first level signal and the second level signal are different level signals, and the first level signal and the second level signal are merely different signals used to distinguish between power-off and power-on. For example, the first level signal and the second level signal can be a high level signal and a low level signal, respectively, or a low level signal and a high level signal, respectively. For example, a power-off or power-on instruction can be generated and sent when any of the following conditions are met: for example, when the SOC chip cannot identify the SSD chip through the data channel, detects that the SSD chip is offline, receives a restart instruction sent by the client, and determines based on the acquired SSD chip status information that the SSD chip needs to be restarted. For example, when the SOC chip does not receive handshake feedback information from the SSD chip, or when the received feedback information is incorrect, the SOC chip inputs a high level signal to the power control pin of the power module of the SSD chip via the GPIO to power off the SSD chip; after a preset time period, the SOC chip inputs a low level signal to the power control pin of the power module of the SSD chip via the GPIO to power on the SSD chip, thereby powering on the SSD chip, thereby restarting the SSD chip by powering off and on.

[0098] For example, see Figure 6 , managing the SSD chip through the SOC chip includes: when the SOC chip cannot identify the SSD chip or fails to identify the SSD chip, the SOC chip can control the power on and off of the SSD chip through the GPIO interface to restore the SSD to work. The specific steps of power on and off control include: the SOC identifies the SSD through the data channel, sets the SSD identification status, and obtains the SSD status information; based on the identified status information, it is determined whether the SSD exists; if it exists, it can be determined that the SSD chip is normal and directly returns to wait for the next cycle of detection. Specifically, the status information can be obtained again at a preset interval; if it does not exist, the GPIO pin in the management channel is pulled high to power off the SSD, and after waiting for 30 seconds, the GPIO pin in the management channel is pulled low to power on the SSD to restart it.

[0099] It can be seen that through the method implemented in this application, the status of the SSD chip can be obtained through the SOC chip, and when the SSD chip cannot be identified or the SSD chip is offline, the SSD chip can be controlled to power off and restart.

[0100] In one possible implementation, the SOC chip is also used to obtain an SSD upgrade package; detect the SSD upgrade package file header information, and determine whether the file header information meets preset requirements; if so, obtain the type information of the SSD chip; when the type information is indicated as SSD, send the SSD upgrade package to the SSD chip, so that the SSD chip is upgraded through the SSD upgrade package.

[0101] In a possible implementation, the SOC chip is specifically used to obtain the SSD upgrade package through one of the ISAPI (Internet Server Application Programming Interface) protocol, the HIK SDK (Hikvision Software Development Kit) protocol, and a preset private protocol.

[0102] In one example, the SOC chip can perform module upgrades on the SSD chip through a data channel or a management channel, such as GPIO, UART, RS232, SMBus, or I2C. For example, the SOC chip can receive an upgrade package downloaded by a user through a client, and send the upgrade package to the SSD chip through a data channel or a management channel. After receiving the upgrade package, the SSD chip can parse the upgrade package and perform the upgrade. For another example, the SOC chip can obtain the log information of the SSD through a management channel or a data channel. For example, the SOC chip can send a log information acquisition instruction to the SSD through a management channel or a data channel, and then the SSD can feed the log back to the SOC chip after receiving the log acquisition instruction. In one example, the above-mentioned preset private protocol can be a Hikvision protocol or a EZVIZ protocol.

[0103] For an example, see Figure 7 During the use of the SSD chip, it may be necessary to upgrade the SSD firmware through the IE client. For example, when the SSD recorder in the embodiment of the present application is a DVR / NVR (digital video recorder / network video recorder), the user can upgrade the DVR / NVR through the client. The specific steps include: the user downloads the SSD upgrade package through the client and sends the downloaded SSD upgrade package to the DVR / NVR; then the DVR / NVR determines the legitimacy by detecting the SSD upgrade package file header information. Specifically, the SOC chip in the DVR / NVR can detect the SSD upgrade package file header information and determine the legitimacy. For example, if the upgrade package file header information meets the preset specifications, it is legal; if not, it is determined to be illegal; if it is legal, the SOC chip reads the node information of the BGA SSD chip. Specifically, the node information is an identifier indicating that the SSD chip is an SSD; then, the node information is read through the corresponding reading tool to obtain a node descriptor, and then the upgrade package data is sent to the SSD through the node descriptor, so that the SSD is upgraded according to the upgrade package; after the SSD upgrade is completed, an upgrade result, such as upgrade success or failure information, can be returned. During the upgrade process, the DVR / NVR may also receive a query request from the client to query the upgrade progress, and the DVR / NVR may feed back the current upgrade progress to the client.

[0104] In one possible implementation, the SSD recorder also includes NAND Flash (open NAND flash memory interface), CVBS (composite video broadcast signal) interface, alarm expansion interface, and DDR (Double Data Rate) particles; NAND Flash is used to store onboard programs and user configurations; the CVBS interface is used to connect to an external CVBS display; the alarm expansion interface is used to connect to a matching alarm board; and the DDR particles are used to run as the running memory of the SOC chip.

[0105] Specifically, the stored onboard program can be a program running after the SOC chip's startup program. User configuration can be user settings, such as a user name, password, and other information. A CVBS (Composite Video Broadcast Signal) interface is used to connect to an external CVBS display. Specifically, the display can be used to display audio and video data stored in the SSD recorder. Specifically, the CVBS interface can connect to an external display and output baseband video or RCA video to the external display, allowing the external display to receive and play the baseband video or RCA (Lotus socket) video. An alarm expansion interface is used to connect to a supporting alarm board, allowing the alarm board to display alarm information. The alarm board can receive alarm signals and generate alarm information, for example, receiving an alarm signal from a sensor and converting the alarm signal to generate alarm information. DDR chips are used to operate as the SOC chip's running memory. Specifically, the SOC chip can cache running cached data in the DDR chips. Specifically, during the operation of the SOC chip, the cached data can be stored in the DDR chips, and then data processing can be performed based on the cached data in the DDR chips. For example, during the calculation process of the SOC chip, the SOC chip can cache the data to be calculated in the DDR particles, and then perform calculations based on the data cached in the DDR particles.

[0106] In actual use, see Figure 8The SSD video recorder in the embodiment of the present application may further include an external power supply, an ETH (Ethernet) interface, a USB (Universal Serial Bus) interface, a VGA (Video Graphics Array) interface, an HDMI interface (High Definition Multimedia Interface), a BNC (Bayonet Nut Connector) analog video input interface, etc. Specifically, in actual use, the USB interface may be an ETH+USB2.0 interface (a combination of a network interface and a USB2.0 (Universal Serial Bus 2.0) interface), the external power supply may be a DC12V (12-volt DC power supply), Power12V is a 12-volt power interface, the BNC interface may be a 4-channel BNC analog video input interface, and in actual use, may further include a CVBS socket (reserved) reserved for connecting a CVBS socket, and a fan power socket for powering a fan.

[0107] A second aspect of an embodiment of the present application provides a data processing method applied to an SSD video recorder, the SSD video recorder including a SOC chip and an SSD chip, the SOC chip and the SSD chip being connected via a data channel established by a PIN pin;

[0108] See also Figure 9 and Figure 10 , the above method includes:

[0109] Step S91, acquiring target data through the SOC chip;

[0110] Step S92, forwarding the target data to the SSD chip through the data channel via the SOC chip;

[0111] Step S93, receiving target data through the SSD chip;

[0112] Step S94, storing the target data to a designated location of the SSD chip;

[0113] and / or,

[0114] Step S101: receiving a first read instruction for reading target data through the SOC chip, wherein the first read instruction is an instruction sent by a client requesting to obtain target data;

[0115] Step S102: Sending a second read instruction for reading target data to the SSD chip via the SOC chip, wherein the second read instruction is an instruction sent by the SOC chip to request to obtain the target data in the SSD chip;

[0116] Step S103, receiving a second read instruction through the SSD chip;

[0117] Step S104, sending target data to the SOC chip via the SSD chip;

[0118] Step S105 : receiving the target data sent by the SSD chip through the SOC chip and outputting it.

[0119] In a possible implementation, the SSD recorder further includes an audio and video AD chip;

[0120] The above method further includes:

[0121] Receive the audio and video data of the analog signal through the audio and video AD chip; convert the audio and video data of the analog signal into a digital signal through the audio and video AD chip to obtain the target data; send the target data to the SOC chip through the audio and video AD chip;

[0122] In one possible implementation, the data channel is SATA or PCIE;

[0123] In one possible implementation, the SOC chip and the SSD chip are further connected via a first management channel; the SOC chip obtains status information of the SSD chip via the first management channel, and sends a control instruction to the SSD chip when the status information meets a preset trigger condition;

[0124] In one possible implementation, the first management channel is at least one of GPIO, UART, RS232, SMBus, and I2C;

[0125] In one possible implementation, the SOC chip is further connected to the control terminal of the power module of the SSD chip via a second management channel, and the SSD chip is connected to the power supply terminal of the power module; the SOC chip uses the second management channel to send a power control instruction to the control terminal of the power module of the SSD chip;

[0126] In one possible implementation, the second management channel is at least one of GPIO, UART, RS232, SPI, and SMBus;

[0127] In one possible implementation, the control instruction is a level signal; when the SOC chip cannot obtain status information of the SSD chip through the data channel and / or the first management channel, and / or receives a restart instruction, and / or the obtained status information meets a preset restart condition, the level signal is sent to the control terminal of the power module of the SSD chip to control the SSD chip to restart;

[0128] In one possible implementation, the SOC chip inputs a first level signal to a power control pin of a power module of the SSD chip to power off the SSD chip; and after a preset time has passed, the SOC chip inputs a second level signal to the power control pin of the power module of the SSD chip to power on the SSD chip.

[0129] In one possible implementation, an SSD upgrade package is obtained through a SOC chip; file header information of the SSD upgrade package is detected through the SOC chip, and it is determined whether the file header information meets preset requirements; if so, type information of the SSD chip is obtained; when the type information indicates SSD, the SSD upgrade package is sent to the SSD chip, so that the SSD chip is upgraded using the SSD upgrade package;

[0130] In a possible implementation, the SSD upgrade package is obtained through the SOC chip using one of the ISAPI protocol, the HIK SDK protocol, and a preset private protocol;

[0131] In one possible implementation, the SSD recorder further includes NAND Flash, a CVBS interface, an alarm expansion interface, and DDR particles; NAND Flash is used to store onboard programs and user configurations; the CVBS interface is used to connect to an external CVBS display; the alarm expansion interface is used to connect to a matching alarm board; and the DDR particles are used to run as the running memory of the SOC chip.

[0132] It can be seen that through the solution of the embodiment of the present application, not only can the SSD chip be used to receive and store the audio and video data sent by the SOC chip through the data channel between the SOC chip and the SSD chip, but the target data can also be read from the SSD chip after the SOC chip receives the read instruction sent by the client. Moreover, the mechanical hard disk or solid-state SSD hard disk in the prior art can be replaced by an SSD chip whose volume is much smaller than that of the mechanical hard disk or solid-state SSD hard disk, thereby reducing the size of the video recorder and improving the convenience of the SSD video recorder.

[0133] The present application also provides an electronic device, such as Figure 11 Shown, including:

[0134] Memory 1101, used for storing computer programs;

[0135] The processor 1102 is configured to implement the following steps when executing the program stored in the memory 1101:

[0136] Acquire target data through the SOC chip; forward the target data to the SSD chip through the data channel through the SOC chip; receive the target data through the SSD chip; store the target data in its own designated location through the SSD chip;

[0137] and / or,

[0138] A first read instruction for reading target data is received through the SOC chip, wherein the first read instruction is an instruction sent by the client to request obtaining the target data; a second read instruction for reading target data is sent to the SSD chip through the SOC chip, wherein the second read instruction is an instruction sent by the SOC chip to request obtaining the target data in the SSD chip; the second read instruction is received through the SSD chip; the target data is sent to the SOC chip through the SSD chip; the target data sent by the SSD chip is received through the SOC chip and output.

[0139] Furthermore, the electronic device may further include a communication bus and / or a communication interface, and the processor 1102 , the communication interface, and the memory 1101 communicate with each other via the communication bus.

[0140] The communication bus mentioned in the electronic device mentioned above may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. This communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is used in the figure, but this does not mean that there is only one bus or only one type of bus.

[0141] The communication interface is used for communication between the above electronic device and other devices.

[0142] The memory may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage. In one possible implementation, the memory may also be at least one storage device located away from the aforementioned processor.

[0143] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, and discrete hardware components.

[0144] In another embodiment provided in the present application, a computer-readable storage medium is further provided, wherein a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, the steps of any of the above-mentioned data processing methods are implemented.

[0145] In another embodiment provided by the present application, a computer program product including instructions is also provided, which, when executed on a computer, enables the computer to execute any one of the data processing methods in the above embodiments.

[0146] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When software is used for implementation, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server or data center to another website, computer, server or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrations. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)).

[0147] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0148] Each embodiment in this specification is described in a related manner. Similar portions between the embodiments can be referenced to each other. Each embodiment focuses on the differences from other embodiments. In particular, the method embodiment is generally similar to the video recorder embodiment, so its description is relatively simple. For related portions, refer to the description of the method embodiment.

[0149] The above description is only a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application are included in the scope of protection of the present application.

Claims

1. An SSD video recorder, characterized in that: include: An SOC chip and an SSD chip, wherein the SOC chip and the SSD chip are connected via a data channel established by PIN pins, the SSD chip comprises an SSD chip packaged using BGA technology, and the SSD chip is integrated into a circuit board of the SSD video recorder; The SOC chip is used to obtain target data; forward the target data to the SSD chip through the data channel; the SSD chip is used to receive the target data; Store the target data in its own designated location; and / or, The SOC chip is configured to receive a first read instruction for reading target data, wherein the first read instruction is an instruction sent by a client requesting to obtain the target data; and to send a second read instruction for reading the target data to the SSD chip, wherein the second read instruction is an instruction sent by the SOC chip requesting to obtain the target data in the SSD chip; the SSD chip is configured to receive the second read instruction and send the target data to the SOC chip; and the SOC chip is further configured to receive and output the target data sent by the SSD chip. The SOC chip and the SSD chip are also connected via a first management channel; The SOC chip is further configured to obtain status information of the SSD chip through the first management channel, and to send a control instruction to the SSD chip when the status information meets a preset trigger condition.

2. The SSD video recorder according to claim 1, wherein: The SSD video recorder also includes an audio and video AD chip; The audio and video AD chip is used to receive audio and video data of analog signals; convert the audio and video data of the analog signals into digital signals to obtain the target data; and send the target data to the SOC chip.

3. The SSD video recorder according to claim 1, wherein: The data channel is SATA or PCIE.

4. The SSD video recorder according to claim 1, wherein: The first management channel is at least one of GPIO, UART, RS232, SMBus, and I2C.

5. The SSD video recorder according to claim 1, wherein: The SOC chip is also connected to the control end of the power module of the SSD chip through a second management channel, and the SSD chip is connected to the power supply end of the power module; The SOC chip is further configured to send a power control instruction to the control terminal of the power module of the SSD chip through the second management channel.

6. The SSD video recorder according to claim 5, characterized in that: The second management channel is at least one of GPIO, UART, RS232, SPI, and SMBus.

7. The SSD video recorder according to claim 1, wherein: The control instruction is a level signal; The SOC chip is specifically used to send a level signal to the control end of the power module of the SSD chip to control the restart of the SSD chip when the status information of the SSD chip cannot be obtained through the data channel and / or the first management channel, and / or a restart instruction is received, and / or the obtained status information meets the preset restart conditions.

8. The SSD video recorder according to claim 7, wherein: The SOC chip is specifically used to input a first level signal to the power control pin of the power module of the SSD chip to power off the SSD chip; after a preset time, input a second level signal to the power control pin of the power module of the SSD chip to power on the SSD chip.

9. The SSD video recorder according to claim 1, wherein: The SOC chip is also used to obtain an SSD upgrade package; detect the file header information of the SSD upgrade package and determine whether the file header information meets the preset requirements; if so, obtain the type information of the SSD chip; when the type information indicates SSD, send the SSD upgrade package to the SSD chip so that the SSD chip is upgraded through the SSD upgrade package.

10. The SSD video recorder according to claim 9, wherein: The SOC chip is specifically used to obtain the SSD upgrade package through one of the ISAPI protocol, the HIK SDK protocol, and the preset private protocol.

11. The SSD video recorder according to claim 1, wherein: The SSD recorder also includes NAND Flash, CVBS interface, alarm expansion interface, and DDR particles; The NAND Flash is used to store onboard programs and user configurations; The CVBS interface is used to connect to an external CVBS display; The alarm expansion interface is used to access the matching alarm board; The DDR particles are used to operate as the running memory of the SOC chip.

12. A data processing method, characterized in that: Applicable to an SSD video recorder, the SSD video recorder includes a SOC chip and an SSD chip, the SOC chip and the SSD chip are connected via a data channel established by a PIN pin, the SSD chip includes an SSD chip packaged using BGA technology, and the SSD chip is integrated into the circuit board of the SSD video recorder; The method comprises: Acquire target data through the SOC chip; forward the target data to the SSD chip through the data channel through the SOC chip; receive the target data through the SSD chip; store the target data in its own designated location through the SSD chip; and / or, Receiving, through the SOC chip, a first read instruction for reading target data, wherein the first read instruction is an instruction sent by a client requesting to obtain the target data; sending, through the SOC chip, a second read instruction for reading the target data to the SSD chip, wherein the second read instruction is an instruction sent by the SOC chip requesting to obtain the target data in the SSD chip; receiving, through the SSD chip, the second read instruction; sending, through the SSD chip, the target data to the SOC chip; receiving, through the SOC chip, the target data sent by the SSD chip and outputting it; The SOC chip and the SSD chip are also connected via a first management channel; the SOC chip obtains status information of the SSD chip via the first management channel, and sends a control instruction to the SSD chip when the status information meets a preset trigger condition.

13. The method according to claim 12, characterized in that The SSD video recorder also includes an audio and video AD chip; The method further comprises: receiving the audio and video data of the analog signal through the audio and video AD chip; converting the audio and video data of the analog signal into a digital signal through the audio and video AD chip to obtain the target data; and sending the target data to the SOC chip through the audio and video AD chip; and / or, The data channel is SATA or PCIE; and / or, The first management channel is at least one of GPIO, UART, RS232, SMBus, and I2C; and / or, The SOC chip is also connected to the control end of the power module of the SSD chip through a second management channel, and the SSD chip is connected to the power supply end of the power module; the SOC chip uses the second management channel to send a power control instruction to the control end of the power module of the SSD chip; and / or, The second management channel is at least one of GPIO, UART, RS232, SPI, and SMBus; and / or, The control instruction is a level signal; when the SOC chip cannot obtain the status information of the SSD chip through the data channel and / or the first management channel, and / or receives a restart instruction, and / or the obtained status information meets the preset restart condition, the SOC chip sends a level signal to the control terminal of the power module of the SSD chip to control the SSD chip to restart; and / or, Inputting a first level signal to the power control pin of the power module of the SSD chip through the SOC chip to power off the SSD chip; and inputting a second level signal to the power control pin of the power module of the SSD chip through the SOC chip after a preset time period to power on the SSD chip; and / or, Obtaining an SSD upgrade package through the SOC chip; detecting file header information of the SSD upgrade package through the SOC chip, and determining whether the file header information meets preset requirements; if so, obtaining type information of the SSD chip; and when the type information indicates SSD, sending the SSD upgrade package to the SSD chip, so that the SSD chip is upgraded through the SSD upgrade package; and / or, Obtain an SSD upgrade package through the SOC chip using one of the ISAPI protocol, the HIK SDK protocol, and a preset private protocol; and / or, The SSD video recorder also includes NAND Flash, CVBS interface, alarm expansion interface, and DDR particles; the NAND Flash is used to store onboard programs and user configurations; the CVBS interface is used to connect to an external CVBS display; the alarm expansion interface is used to connect to a matching alarm board; and the DDR particles are used to run as the running memory of the SOC chip.

Images