Liquid crystal display device

Abstract

Provided is a liquid crystal display device of a dual cell structure that prevents image loss when viewed from an oblique direction. The liquid crystal display device includes a first liquid crystal panel having a display region and including a color filter layer; an illumination device provided on a back surface side of the first liquid crystal panel; and a second liquid crystal panel disposed between the first liquid crystal panel and the illumination device and not including a color filter layer. The second liquid crystal panel has a first light adjustment region defined by a plurality of pixels arranged in a matrix shape including a plurality of rows and a plurality of columns, and a second light adjustment region defined by a plurality of additional pixels each including an opening region that is not light-shielded, and located outside the first light adjustment region.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a liquid crystal display device. BACKGROUND

[0002] As a technique for greatly improving the contrast ratio of a liquid crystal display device, a technique of dividing a backlight into a plurality of regions and controlling the luminance for each region (referred to as "division driving", "area driving", or "local dimming") is known. The division driving of a backlight is disclosed, for example, in Patent Literature 1.

[0003] In a case where the division driving of the backlight is performed, when the luminance difference between adjacent regions is large, bleeding of white can occur in the display screen. This phenomenon is referred to as "halo", and becomes a cause of degradation of display quality.

[0004] Therefore, as a technique capable of greatly improving the contrast ratio without generating halo, a liquid crystal display device having a configuration in which two pieces of liquid crystal display panels are stacked (hereinafter referred to as "dual cell structure") is proposed in Patent Literature 2.

[0005] Prior Art Documents

[0006] Patent Documents

[0007] Patent Literature 1: Japanese Patent Application Laid-Open No. 2002-99250

[0008] Patent Literature 2: International Publication No. 2008 / 053724 SUMMARY

[0009] Problem to be Solved by the Invention

[0010] In the liquid crystal display device of the dual cell structure, when the display screen is observed from a diagonal direction, sometimes an image is not normally displayed at the end edge of the screen ("image loss").

[0011] An embodiment of the present application is made in view of the above problems, and has an object to provide a liquid crystal display device of the dual cell structure which prevents image loss when observed from a diagonal direction.

[0012] Means for Solving the Problem

[0013] According to the embodiment of the present application, the following items are provided.

[0014] [Item 1]

[0015] A liquid crystal display device includes:

[0016] A first liquid crystal panel having a display region, including a color filter layer;

[0017] a lighting device provided on a back surface side of the first liquid crystal panel; and

[0018] a second liquid crystal panel disposed between the first liquid crystal panel and the lighting device, not including a color filter layer,

[0019] the second liquid crystal panel has:

[0020] a first light adjustment region defined by a plurality of pixels arranged in a matrix shape including a plurality of rows and a plurality of columns, opposite to the display region; and

[0021] a second light adjustment region defined by a plurality of additional pixels each including an opening region not blocked by a light shield, located outside the first light adjustment region.

[0022] [Item 2]

[0023] The liquid crystal display device according to Item 1, wherein

[0024] the second liquid crystal panel has a plurality of gate lines extending in a row direction and a plurality of source lines extending in a column direction.

[0025] [Item 3]

[0026] The liquid crystal display device according to Item 2, wherein

[0027] the second light adjustment region includes a first portion and a second portion, the first portion and the second portion extending in the column direction and being disposed in the row direction in a manner sandwiching the first light adjustment region.

[0028] [Item 4]

[0029] The liquid crystal display device according to Item 3, wherein

[0030] provided with a source line drive circuit that supplies source signals to the plurality of source lines,

[0031] the plurality of source lines include a plurality of first source lines provided corresponding to the plurality of pixels, and a plurality of second source lines provided corresponding to additional pixels of the plurality of additional pixels located in the first portion and the second portion of the second light adjustment region,

[0032] the source line drive circuit has a plurality of source output terminals that output the source signals, and the plurality of source output terminals is more than the plurality of source lines,

[0033] The plurality of source output terminals include a plurality of first source output terminals electrically connected to the plurality of first source wirings, a plurality of second source output terminals electrically connected to the plurality of second source wirings, and a plurality of third source output terminals not electrically connected to either of the plurality of first source wirings and the plurality of second source wirings.

[0034] [Item 5]

[0035] The liquid crystal display device according to Item 4, wherein

[0036] When the number of the plurality of first source wirings is n, the number of the plurality of source output terminals is 3n.

[0037] [Item 6]

[0038] The liquid crystal display device according to Item 4 or 5, wherein

[0039] The source wiring drive circuit has a plurality of terminal groups each including three source output terminals of the plurality of source output terminals that are consecutively arranged, and the three source output terminals output a source signal of the same gray scale.

[0040] [Item 7]

[0041] The liquid crystal display device according to Item 6, wherein

[0042] One of the three source output terminals is the first source output terminal.

[0043] [Item 8]

[0044] The liquid crystal display device according to Item 7, wherein

[0045] When a pixel column of the plurality of pixel columns composed of the plurality of pixels that is adjacent to the first portion of the second light adjustment region is referred to as a first endmost pixel column, and a pixel column adjacent to the second portion of the second light adjustment region is referred to as a second endmost pixel column,

[0046] When a terminal group of the plurality of terminal groups that includes a first source output terminal electrically connected to a first source wiring provided corresponding to the first endmost pixel column is referred to as a first endmost terminal group, and a terminal group that includes a first source output terminal electrically connected to a first source wiring provided corresponding to the second endmost pixel column is referred to as a second endmost terminal group,

[0047] One or two of the three source output terminals of each of the first endmost terminal group and the second endmost terminal group is the second source output terminal.

[0048] [Item 9]

[0049] The liquid crystal display device according to Item 8, wherein

[0050] Two of the three source output terminals included in each of the terminal groups other than the first endmost terminal group and the second endmost terminal group are third source output terminals.

[0051] [Item 10]

[0052] The liquid crystal display device according to Item 8 or 9, wherein

[0053] The plurality of source output terminals are arranged such that a source output terminal outputting a source signal of a first polarity and a source output terminal outputting a source signal of a second polarity opposite to the first polarity are alternately arranged in the row direction within one horizontal scanning period,

[0054] The plurality of source wirings are electrically connected to some of the plurality of source output terminals so that the second liquid crystal panel is driven by source inversion driving or dot inversion driving.

[0055] [Item 11]

[0056] The liquid crystal display device according to Item 10, wherein

[0057] The additional pixels in each of the first portion and the second portion are arranged in a plurality of columns,

[0058] The plurality of second source wirings include two or more second source wirings provided in the first portion and two or more second source wirings provided in the second portion,

[0059] Two of the three source output terminals included in each of the first endmost terminal group and the second endmost terminal group are second source output terminals outputting source signals of opposite polarities to each other,

[0060] Some of the two or more second source wirings provided in the first portion are electrically connected to one of the two second source output terminals of the first endmost terminal group, and the remaining second source wirings are electrically connected to the other of the two second source output terminals of the first endmost terminal group,

[0061] One of the plurality of second source wirings provided in the first portion is electrically connected to one of the two first source output terminals of the first endmost terminal group, and the remaining second source wirings are electrically connected to the other of the two first source output terminals of the first endmost terminal group.

[0062] [Item 12]

[0063] The liquid crystal display device according to any one of Items 4 to 11, wherein

[0064] Further comprising a plurality of buffer amplifiers,

[0065] The plurality of second source output terminals are each electrically connected to a corresponding second source wiring via at least one buffer amplifier of the plurality of buffer amplifiers.

[0066] [Item 13]

[0067] The liquid crystal display device according to Item 12, wherein

[0068] The plurality of second source output terminals are each electrically connected to a corresponding second source wiring via two or more buffer amplifiers of the plurality of buffer amplifiers.

[0069] [Item 14]

[0070] The liquid crystal display device according to Item 12 or 13, wherein

[0071] The source wiring drive circuit includes the plurality of buffer amplifiers.

[0072] [Item 15]

[0073] The liquid crystal display device according to any one of Items 12 to 14, wherein

[0074] The second liquid crystal panel has a connection wiring for electrically connecting each second source output terminal to a corresponding second source wiring via the at least one buffer amplifier.

[0075] [Item 16]

[0076] The liquid crystal display device according to any one of Items 3 to 15, wherein

[0077] The plurality of additional pixels include a plurality of first additional pixels located in the first portion of the second light adjustment region and a plurality of second additional pixels located in the second portion of the second light adjustment region,

[0078] When a pixel column adjacent to the first part of the second light adjustment region is referred to as a first endmost pixel column and a pixel column adjacent to the second part of the second light adjustment region is referred to as a second endmost pixel column,

[0079] Each of the plurality of first additional pixels exhibits substantially the same luminance as a pixel in the same row of the first endmost pixel column,

[0080] Each of the plurality of second additional pixels exhibits substantially the same luminance as a pixel in the same row of the second endmost pixel column.

[0081] [Item 17]

[0082] The liquid crystal display device according to any one of Items 3 to 16, wherein

[0083] Each of the first part and the second part of the second light adjustment region has a width Whr in the row direction of 2 mm or less.

[0084] [Item 18]

[0085] The liquid crystal display device according to any one of Items 3 to 17, wherein

[0086] Each of the first part and the second part of the second light adjustment region has a number Phr of pixel columns of additional pixels of 25 or less.

[0087] [Item 19]

[0088] The liquid crystal display device according to any one of Items 2 to 18, wherein

[0089] The second light adjustment region includes a third part and a fourth part, the third part and the fourth part extend in the row direction and are arranged in the column direction so as to sandwich the first light adjustment region.

[0090] [Item 20]

[0091] The liquid crystal display device according to Item 19, wherein

[0092] The plurality of gate wirings include a plurality of first gate wirings provided corresponding to the plurality of pixels, at least one second gate wiring provided corresponding to the additional pixels in the third part of the second light adjustment region, and at least one third gate wiring provided corresponding to the additional pixels in the fourth part of the second light adjustment region,

[0093] The at least one second gate wire is electrically connected to a first gate wire of the plurality of first gate wires that is disposed corresponding to a pixel row adjacent to the third portion of the second light adjustment region,

[0094] The at least one third gate wire is electrically connected to a first gate wire of the plurality of first gate wires that is disposed corresponding to a pixel row adjacent to the fourth portion of the second light adjustment region.

[0095] [Item 21]

[0096] The liquid crystal display device according to any one of Items 19 to 20, wherein

[0097] The plurality of additional pixels include a plurality of third additional pixels that are located in the third portion of the second light adjustment region and a plurality of fourth additional pixels that are located in the fourth portion of the second light adjustment region,

[0098] When a pixel row of the plurality of pixel rows that is adjacent to the third portion of the second light adjustment region is referred to as a first endmost pixel row and a pixel row that is adjacent to the fourth portion of the second light adjustment region is referred to as a second endmost pixel row,

[0099] Each of the plurality of third additional pixels exhibits substantially the same luminance as a pixel of the same column of the first endmost pixel row,

[0100] Each of the plurality of fourth additional pixels exhibits substantially the same luminance as a pixel of the same column of the second endmost pixel row.

[0101] [Item 22]

[0102] The liquid crystal display device according to any one of Items 19 to 21, wherein

[0103] A width Wvr in a column direction of each of the third portion and the fourth portion of the second light adjustment region is 2 mm or less.

[0104] [Item 23]

[0105] The liquid crystal display device according to any one of Items 19 to 22, wherein

[0106] A number Pvr of additional pixel rows in each of the third portion and the fourth portion of the second light adjustment region is 25 or less.

[0107] [Item 24]

[0108] The liquid crystal display device according to any one of Items 1 to 23, wherein

[0109] The first light adjustment region is substantially rectangular,

[0110] The second light adjustment region is a frame shape surrounding the first light adjustment region.

[0111] [Item 25]

[0112] The liquid crystal display device according to Item 2, wherein

[0113] The second light adjustment region includes:

[0114] a first portion and a second portion extending in the column direction and arranged in the row direction so as to sandwich the first light adjustment region; and

[0115] a third portion and a fourth portion extending in the row direction and arranged in the column direction so as to sandwich the first light adjustment region.

[0116] [Item 26]

[0117] The liquid crystal display device according to Item 25, wherein

[0118] The width Whr in the row direction of each of the first portion and the second portion of the second light adjustment region and the width Wvr in the column direction of each of the third portion and the fourth portion of the second light adjustment region satisfy a relationship of Whr / Wvr < 2.

[0119] [Item 27]

[0120] The liquid crystal display device according to Item 25 or 26, wherein

[0121] The number Phr of additional pixel columns in each of the first portion and the second portion of the second light adjustment region and the number Pvr of additional pixel rows in each of the third portion and the fourth portion of the second light adjustment region satisfy a relationship of Phr / Pvr < 2.

[0122] [Item 28]

[0123] The liquid crystal display device according to any one of Items 1 to 27, wherein

[0124] display is performed in a horizontal electric field mode.

[0125] Effects of the Invention

[0126] According to the embodiment of the present application, it is possible to provide a liquid crystal display device of a dual cell structure that prevents image loss when viewed from an oblique direction. BRIEF DESCRIPTION OF DRAWINGS

[0127] FIG. 1FIG. 1 is a cross-sectional view schematically showing a liquid crystal display device 1000 of an embodiment of the present application.

[0128] FIG. 2 FIG. 2 is a block diagram showing the overall configuration of the liquid crystal display device 1000.

[0129] FIG. 3 FIG. 3 is a block diagram for explaining signal processing in the liquid crystal display device 1000.

[0130] FIG. 4 FIG. 4 is a view for explaining regions of the front panel 100 and the back panel 200 of the liquid crystal display device 1000.

[0131] FIG. 5 FIG. 5 is a plan view schematically showing the back panel 200.

[0132] FIG. 6A FIG. 6 is a view schematically showing a case where image omission occurs in the liquid crystal display device 2000 of the comparative example.

[0133] FIG. 6B FIG. 7 is a view schematically showing a case where image omission is prevented in the liquid crystal display device 1000.

[0134] FIG. 7A FIG. 8 is a view showing the vicinity of the leftmost source driver SD among the plurality of source drivers SD of the liquid crystal display device 1000.

[0135] FIG. 7B FIG. 9 is a view showing the vicinity of the rightmost source driver SD among the plurality of source drivers SD of the liquid crystal display device 1000.

[0136] FIG. 8 FIG. 10 is a view showing the vicinity of the gate line driver circuit 15 on the left side of the liquid crystal display device 1000.

[0137] FIG. 9A FIG. 11 is a cross-sectional view along the 9A-9A' line in FIG. 10, showing a connection wiring CL1 for electrically connecting the green terminal 0001G with the buffer amplifier 17A. FIG. 7A

[0138] FIG. 12 is a cross-sectional view along the 9B-9B' line in FIG. 10, showing a connection wiring CL2 for electrically connecting the red terminal 0001R with the buffer amplifier 17B. FIG. 9B FIG. 7A FIG. 13 is a cross-sectional view along the 9C-9C' line in FIG. 10, showing a connection wiring CL3 for electrically connecting the blue terminal 0001B with the buffer amplifier 17C.

[0139] FIG. 9C FIG. 7A ​​The cross-sectional view of line 9C-9C' in the figure shows the connection wiring CL3 used to electrically connect the buffer amplifier 17B to the second source wiring (additional source wiring) SLb_1, SLb_3, SLb_5.

[0140] FIG. 9D It is along FIG. 7A The cross-sectional view of line 9D-9D' in the figure shows the connection wiring CL4 used to electrically connect the buffer amplifier 17A to the second source wiring (additional source wiring) SLb_2, SLb_4, SLb_6.

[0141] FIG. 10A It is used to describe the expected horizontal angle θ h and the expected vertical angle θ v The image.

[0142] FIG. 10B It is used to describe the expected horizontal angle θ h The expected horizontal angle θ within the liquid crystal display device 1000 h A diagram illustrating the relationship between '.

[0143] FIG. 10C This is a chart showing the trial calculation results of the width Whr of the left appended region CR2a and the right appended region CR2b in the row direction.

[0144] FIG. 10D This is a chart showing the calculated results of the column-direction width Wvr of the upper appended region CR2c and the lower appended region CR2d.

[0145] FIG. 10E This is a graph showing the ratio Whr / Wvr of the widths Whr of the left appended region CR2a and the right appended region CR2b relative to the widths Wvr of the upper appended region CR2c and the lower appended region CR2d.

[0146] FIG. 10F This is a chart showing the calculated number of additional pixel columns Phr in each of the left additional region CR2a and the right additional region CR2b.

[0147] FIG. 10G This is a graph showing the calculated results of the number of additional pixel rows Pvr in the upper additional region CR2c and the lower additional region CR2d.

[0148] FIG. 10H This is a graph showing the ratio of the number of additional pixel columns Phr in the left appended region CR2a and the right appended region CR2b to the number of additional pixel rows Pvr in the upper appended region CR2c and the lower appended region CR2d, Phr / Pvr.

[0149] FIG. 11A is a view showing the vicinity of the leftmost source driver SD among the plurality of source drivers SD of the liquid crystal display device 1000.

[0150] FIG. 11B is a view showing the vicinity of the rightmost source driver SD among the plurality of source drivers SD of the liquid crystal display device 1000.

[0151] FIG. 12 is a schematic plan view showing the back panel 200.

[0152] FIG. 13 is a plan view showing another example of the connection method using the buffer amplifier 17.

[0153] FIG. 14 is a plan view showing still another example of the connection method using the buffer amplifier 17.

[0154] FIG. 15 is a plan view showing still another example of the connection method using the buffer amplifier 17.

[0155] FIG. 16 is a plan view showing still another example of the connection method using the buffer amplifier 17.

[0156] FIG. 17 is a plan view showing another example of the configuration of the 2nd dimming region CR2.

[0157] FIG. 18 is a plan view showing still another example of the configuration of the 2nd dimming region CR2.

[0158] Explanation of Reference Numerals

[0159] 10 system circuit

[0160] 11 video processing circuit

[0161] 12, 13 controller substrate

[0162] 14 backlight driving circuit

[0163] 15 gate line driving circuit

[0164] 16 source line driving circuit

[0165] 17 buffer amplifier

[0166] 100 1st liquid crystal panel (front panel)

[0167] 110 TFT substrate (active matrix substrate)

[0168] 120 counter substrate (color filter substrate)

[0169] 121 color filter layer

[0170] 130 liquid crystal layer

[0171] 200 second liquid crystal panel (back panel)

[0172] 210 TFT substrate (active matrix substrate)

[0173] 220 counter substrate

[0174] 230 liquid crystal layer

[0175] 1000 liquid crystal display device

[0176] BL illumination device (backlight)

[0177] DR display region

[0178] FR peripheral region (bezel region)

[0179] CR1 first light adjustment region

[0180] CR2 second light adjustment region

[0181] CR2a first portion of second light adjustment region

[0182] CR2b second portion of second light adjustment region

[0183] CR2c third portion of second light adjustment region

[0184] CR2d fourth portion of second light adjustment region

[0185] GD, GD' gate driver

[0186] SD source driver

[0187] GL gate line

[0188] GLa first gate line (normal gate line)

[0189] GLb second gate line (additional gate line)

[0190] GLc third gate line (additional gate line)

[0191] SL source line

[0192] Sla first source line (normal gate line)

[0193] SLb second source line (additional gate line)

[0194] CL connection line

[0195] AL preparatory wiring

[0196] P pixel

[0197] AP additional pixel

[0198] ot source output terminal

[0199] ot1 first source output terminal

[0200] ot2 second source output terminal

[0201] ot3 third source output terminal

[0202] Ts terminal group

[0203] TsA first endmost terminal group

[0204] TsB second endmost terminal group DETAILED DESCRIPTION

[0205] Embodiments of the present application will be described below with reference to the accompanying drawings. Note that embodiments of the present application are not limited to the following examples.

[0206] Reference FIG. 1 will be described below with reference to the accompanying drawings. Note that embodiments of the present application are not limited to the following examples. FIG. 1 is a cross-sectional view schematically showing the liquid crystal display device 1000.

[0207] As FIG. 1 shown, the liquid crystal display device 1000 includes a first liquid crystal panel (hereinafter referred to as a "front panel") 100, a backlight (illumination device) BL provided on the back surface side (the side opposite to the side of the observer) of the front panel 100, and a second liquid crystal panel (hereinafter referred to as a "rear panel") 200 provided between the front panel 100 and the backlight BL. The liquid crystal display device 1000 performs display in a horizontal electric field mode, more specifically, in a fringe field switching (FFS) mode.

[0208] The front panel 100 includes a TFT substrate (active matrix substrate) 110, a counter substrate (color filter substrate) 120 which is opposite to the TFT substrate 110, and a liquid crystal layer 130 provided between the TFT substrate 110 and the counter substrate 120. A color filter layer 121 is provided on the counter substrate 120 of the front panel 100. The color filter layer 121 includes a red color filter 121R, a green color filter 121G, and a blue color filter 121B. The thickness of the liquid crystal layer 130 is defined by a plurality of columnar spacers (not shown), for example.

[0209] The back panel 200 has a TFT substrate (active matrix substrate) 210, an opposing substrate 220 that opposes the TFT substrate 210, and a liquid crystal layer 230 that is provided between the TFT substrate 210 and the opposing substrate 220. The opposing substrate 220 of the back panel 200 is not provided with a color filter layer. That is, the back panel 200 does not include a color filter layer. The thickness of the liquid crystal layer 230 is defined by, for example, a plurality of columnar spacers (not shown).

[0210] The backlight BL includes a light source (not shown) that irradiates light to the back panel 200. The backlight BL can be of an edge light type or a direct type. The backlight BL of the edge light type includes a light guide plate in addition to the light source.

[0211] The front panel 100 is a display color liquid crystal panel that is capable of displaying a color image. In contrast, the back panel 200 is a dimming monochrome liquid crystal panel that adjusts the amount of light incident on the front panel 100 on a per region (each pixel described later) basis.

[0212] FIG. 2 is a block diagram showing the overall configuration of the liquid crystal display device 1000. As shown in FIG. 2 , the liquid crystal display device 1000 further includes a system circuit 10 that controls the front panel 100, the back panel 200, and the backlight BL.

[0213] In the example shown in FIG. 2 , the system circuit 10 includes a video processing circuit 11 that performs prescribed signal processing on an input video signal (input signal), a controller substrate (C-PWB) 12 for driving the front panel 100, a controller substrate (C-PWB) 13 for driving the back panel 200, and a backlight driving circuit 14 for driving the backlight BL.

[0214] FIG. 3 is a block diagram for explaining the signal processing for the input signal. Here, the input signal is a digital RGB signal. As shown in FIG. 3 , the signal output to the front panel 100 is a signal that has been subjected to timing adjustment on the input signal. In contrast, the signal output to the back panel 200 is a signal that has been subjected to γ conversion and monochrome conversion on the input signal.

[0215] The γ conversion is performed in order to make the γ of the output signal a desired value. The γ conversion can be performed, for example, with reference to a LUT (Look-Up Table). The monochrome conversion is a process of setting the maximum value among the gradation values of R, G, and B represented by the RGB signal as the gradation value of each pixel.

[0216] It is also possible to FIG. 3As exemplified, smoothing processing is performed after the monochrome conversion. The smoothing processing is a processing of vignetting the light-shielding pattern of the back panel 200 (may also be referred to as "monochrome display"), and by the smoothing processing, it is possible to prevent a decrease in display quality due to parallax generated when the front panel 100 and the back panel 200 are overlapped. The smoothing processing is disclosed, for example, in Japanese Patent Application Publication No. 2008-191269 and Japanese Patent Application Publication No. 2011-76107. The disclosure of Japanese Patent Application Publication No. 2008-191269 and Japanese Patent Application Publication No. 2011-76107 is incorporated herein by reference.

[0217] FIG. 4 is a view for explaining a region provided in the front panel 100 and the back panel 200.

[0218] As FIG. 4 indicated, the front panel 100 has a display region DR and a peripheral region (frame region) FR. The display region DR is defined by a plurality of pixels arranged in a matrix shape including a plurality of rows and a plurality of columns. The plurality of pixels include red pixels that display red, green pixels that display green, and blue pixels that display blue. One color display pixel is constituted by the three pixels of the red pixel, the green pixel, and the blue pixel. Although not illustrated here, each pixel has an electrode structure for the FFS mode. The peripheral region FR is located around the display region DR. In the present embodiment, the resolution of the front panel 100 is 4K (3840 x 2160).

[0219] The back panel 200 has a first light-shielding region CR1 and a second light-shielding region CR2. The first light-shielding region CR1 is opposed to the display region DR of the front panel 100. Here, "the first light-shielding region CR1 is opposed to the display region DR" means that the first light-shielding region CR1 at least partially overlaps the display region DR when viewed from the display surface normal direction. It is not necessarily required that the first light-shielding region CR1 completely overlaps the display region DR, and a deviation due to a fitting error or a slight difference in size between the first light-shielding region CR1 and the display region DR is allowed. The second light-shielding region CR2 is located outside the first light-shielding region CR1.

[0220] In FIG. 4In the illustrated example, the first light adjustment region CR1 is substantially rectangular. In contrast, the second light adjustment region CR2 is frame-shaped that surrounds the first light adjustment region CR1, and includes a first portion CR2a and a second portion CR2b that extend in the column direction, and a third portion CR2c and a fourth portion CR2d that extend in the row direction. The first portion CR2a and the second portion CR2b are arranged in the row direction so as to sandwich the first light adjustment region CR1. The third portion CR2c and the fourth portion CR2d are arranged in the column direction so as to sandwich the first light adjustment region CR1. Hereinafter, the first light adjustment region CR1 will be sometimes referred to as a "normal light adjustment region", and the second light adjustment region CR2 will be sometimes referred to as an "additional light adjustment region". In addition, the first portion CR2a, the second portion CR2b, the third portion CR2c, and the fourth portion CR2d of the second light adjustment region CR2 will be sometimes referred to as a "left additional region", a "right additional region", an "upper additional region", and a "lower additional region", respectively.

[0221] Referring to FIG. 5 The first light adjustment region CR1 and the second light adjustment region CR2 of the back panel 200 will be described more specifically. FIG. 5 is a schematic plan view of the back panel 200.

[0222] As FIG. 5 indicated, the first light adjustment region (normal light adjustment region) CR1 is defined by a plurality of pixels P arranged in a matrix shape including a plurality of rows and a plurality of columns. A pixel electrode 211 and a thin film transistor (TFT) 212 electrically connected to the pixel electrode 211 are provided at each pixel P. In the present embodiment, the resolution of the first light adjustment region CR1 of the back panel 200 is 4K (3840 x 2160), and the size of one pixel P of the back panel 200 is substantially the same as the size of one color display pixel of the front panel 100.

[0223] The second light adjustment region (additional light adjustment region) CR2 is defined by a plurality of additional pixels AP. At each additional pixel AP, a pixel electrode 211 and a TFT 212 are provided similarly to the pixel P. The additional pixels AP in each of the left additional region (first portion) CR2a and the right additional region (second portion) CR2b among the plurality of additional pixels AP are arranged in a plurality of columns (six columns in this example). In addition, the additional pixels AP in each of the upper additional region (third portion) CR2c and the lower additional region (fourth portion) CR2d among the plurality of additional pixels AP are arranged in a plurality of rows (four rows in this example).

[0224] Although not shown here, the plurality of pixels P and the plurality of additional pixels AP have an electrode structure for FFS mode. That is, in addition to the pixel electrode 211, a common electrode opposing the pixel electrode 211 via an insulating layer is provided in the TFT substrate 210, and one of the pixel electrode 211 and the common electrode (the one closer to the liquid crystal layer 230) has at least one slit.

[0225] The back panel 200 has a plurality of gate lines GL extending in the row direction and a plurality of source lines SL extending in the column direction. Each gate line GL applies a gate signal to the corresponding TFT 212. Each source line SL applies a source signal to the corresponding TFT 212.

[0226] The plurality of gate lines GL includes a plurality of first gate lines GLa provided corresponding to the plurality of pixels P, at least one (four in this example) second gate line GLb provided corresponding to the additional pixels AP in the upper additional area CR2c, and at least one (four in this example) third gate line GLc provided corresponding to the additional pixels AP in the lower additional area CR2d. Hereinafter, the first gate lines GLa are sometimes referred to as "normal gate lines", and the second gate lines GLb and the third gate lines GLc are sometimes referred to as "additional gate lines".

[0227] The plurality of source lines SL includes a plurality of first source lines SLa provided corresponding to the plurality of pixels P, and a plurality of second source lines SLb provided corresponding to the additional pixels AP in the left additional area CR2a and the right additional area CR2b. Hereinafter, the first source lines SLa are sometimes referred to as "normal source lines", and the second source lines SLb are sometimes referred to as "additional source lines".

[0228] The liquid crystal display device 1000 includes a plurality of gate drivers GD that supply gate signals to the plurality of gate lines GL of the back panel 200, and a plurality of source drivers SD that supply source signals to the plurality of source lines SL of the back panel 200. In this specification, the plurality of gate drivers GD are collectively referred to as a "gate line driver circuit" (referenced by reference numeral 15 in FIG. 5 ), and the plurality of source drivers SD are collectively referred to as a "source line driver circuit" (referenced by reference numeral 16 in FIG. 5 ). The back panel 200 is subjected to source inversion driving or dot inversion driving. With the source inversion driving or the dot inversion driving, occurrence of flicker is suppressed, and display quality is improved.

[0229] As already explained, the opposing substrate 220 of the back panel 200 is not provided with a color filter layer. However, it is also possible to provide the opposing substrate 220 with a TFT light-shielding layer configured in a manner so as to overlap the TFTs 212 and / or a spacer light-shielding layer configured in a manner so as to overlap the columnar spacers. By providing the TFT light-shielding layer, it is possible to prevent deterioration of the characteristics of the TFTs due to light, and by providing the spacer light-shielding layer, it is possible to prevent a decrease in the contrast ratio due to the columnar spacers.

[0230] Each pixel P includes a region that is not light-shielded (referred to as an "opening region"). Likewise, each additional pixel AP also includes an opening region. Therefore, not only each pixel P, but also each additional pixel AP has a light adjustment function (a function of adjusting the amount of transmitted light).

[0231] As explained above, the liquid crystal display device 1000 of the present embodiment has a front panel 100 having a display region DR and a back panel 200 disposed between the front panel 100 and the backlight BL. That is, the liquid crystal display device 1000 has a dual cell structure. Therefore, it is possible to perform display with a high contrast ratio, and in addition, occurrence of light leakage is suppressed.

[0232] In addition, in the liquid crystal display device 1000 of the present embodiment, since the back panel 200 has a second light adjustment region (additional light adjustment region) CR2 located outside the first light adjustment region (normal light adjustment region) CR1, it is possible to prevent image loss when viewed from an oblique direction. This will be explained below with reference to FIG. 6A and FIG. 6B .

[0233] FIG. 6A is a diagram schematically showing a case where image loss occurs in the liquid crystal display device 2000 of the comparative example. The liquid crystal display device 2000 of the comparative example differs from the liquid crystal display device 1000 in that the back panel 200' does not have the second light adjustment region CR2. In FIG. 6A , a plurality of pixels P F that define the display region DR of the front panel 100 are shown. FIG. 6A In the configuration shown in

[0234] In the liquid crystal display device 2000 of the comparative example, there is no problem when viewing the pixels P F of the display region DR from the front direction (the pixels P F are normally visually recognized). However, when viewing the pixels P F of the end portion of the display region DR from an oblique direction, since the pixels P FIt does not overlap with the pixel P of the rear panel 200' (it overlaps with the black matrix BM), therefore, it is sometimes not recognized by normal vision.

[0235] FIG. 6B This diagram schematically illustrates a situation in which image loss can be prevented in the liquid crystal display device 1000 of this embodiment. In the liquid crystal display device 1000 of this embodiment, when viewed from the front direction, the pixel P of the display area DR... F At that time, of course, no problem will occur (pixel P). F (It will be normally visually recognized). Additionally, the pixel P at the end of the display area DR when viewed from an angle... F At that time, due to pixel P F The additional pixel AP overlaps with the second dimming area CR2 of the rear panel 200, so no image loss occurs.

[0236] Thus, in the liquid crystal display device 1000 of the embodiment of the present invention, image loss when viewed from an oblique direction is prevented. However, when an additional pixel AP is set (i.e., a second dimming region CR2 is set), an input signal is required for the additional pixel AP. Therefore, new problems may arise, such as the inability to use the peripheral circuits (timing controller, gate driver, source driver, etc.) for a conventional liquid crystal panel as is, or the need to change the specifications of the input signal (for example, in the case of a 4K resolution, the rear panel requires an input signal of (3840+α)×(2160+α).

[0237] The liquid crystal display device 1000 according to an embodiment of the present invention, by having the configuration described below, can use the peripheral circuitry for a conventional liquid crystal panel or without changing the specifications of the input signal. Hereinafter, also referring to... FIG. 7A , FIG. 7B as well as FIG. 8 To illustrate this point.

[0238] FIG. 7A This is a diagram showing the leftmost source driver SD among multiple source driver SDs. FIG. 7B This is a diagram showing the rightmost source driver SD among multiple source driver SDs. FIG. 7A and FIG. 7B In this context, the nth first source-polarity line SLa from the left in a plurality of first source-polarity lines (normal source-polarity lines) SLa is labeled "SLa_n". Similarly, the nth second source-polarity line SLb from the left in a plurality of second source-polarity lines (additional source-polarity lines) SLb is labeled "SLb_n". FIG. 7AThe first to sixth first source lines (normal source lines) SLa_1 to SLa_6 and the first to sixth second source lines (additional source lines) SLb_1 to SLb_6 are shown in FIG. 1. In addition, the seventh to twelfth first source lines (normal source lines) SLa_7 to SLa_12 and the first to sixth second source lines (additional source lines) SLb_1 to SLb_6 are shown in FIG. 3. FIG. 7B The 3835th to 3840th first source lines (normal source lines) SLa_3835 to SLa_3840 and the seventh to twelfth second source lines (additional source lines) SLb_7 to SLb_12 are shown in FIG. 38.

[0239] As shown in FIG. 1, the source line drive circuit 16 (a plurality of source drivers SD) has a plurality of source output terminals ot that output source signals. In the present embodiment, the number of the plurality of source output terminals ot is larger than the number of the plurality of source lines SL. Specifically, when the number of the first source lines (normal source lines) SLa is n, the number of the source output terminals ot is 3n. FIG. 7A FIG. 7B The plurality of source output terminals ot are arranged so that a source output terminal ot that outputs a source signal of a first polarity (for example, a negative polarity) and a source output terminal ot that outputs a source signal of a second polarity (for example, a positive polarity) opposite to the first polarity are alternately arranged along the row direction within one horizontal scanning period.

[0240] Here, a group Ts of three source output terminals ot that are consecutively arranged among the plurality of source output terminals ot of the source line drive circuit 16 is referred to as a "terminal group". When the number of the source output terminals ot is 3n, the number of the terminal groups Ts is n (that is, the source output terminals ot that constitute a certain terminal group Ts do not constitute other terminal groups Ts).

[0241] In a source driver for a normal liquid crystal panel, each terminal group includes a source output terminal that outputs a source signal supplied to a red pixel, a source output terminal that outputs a source signal supplied to a green pixel, and a source output terminal that outputs a source signal supplied to a blue pixel. Therefore, in the present specification, the three source output terminals ot that constitute each terminal group Ts are sometimes referred to (labeled) as source output terminals of a source driver for a normal liquid crystal panel. Specifically, the three source output terminals ot that constitute each terminal group Ts are sometimes referred to in order from the left as a "red terminal", a "green terminal", and a "blue terminal", and the red terminal, the green terminal, and the blue terminal of the nth terminal group Ts from the left are sometimes referred to (labeled) as a "red terminal nR", a "green terminal nG", and a "blue terminal nB". For example, the three source output terminals ot that constitute the first terminal group Ts (that is, the leftmost terminal group Ts) from the left are sometimes referred to (labeled) as a "red terminal 0001R", a "green terminal 0001G", and a "blue terminal 0001B".

[0242] In a source driver for a normal liquid crystal panel, each terminal group includes a source output terminal that outputs a source signal supplied to a red pixel, a source output terminal that outputs a source signal supplied to a green pixel, and a source output terminal that outputs a source signal supplied to a blue pixel. Therefore, in the present specification, the three source output terminals ot that constitute each terminal group Ts are sometimes referred to (labeled) as source output terminals of a source driver for a normal liquid crystal panel. Specifically, the three source output terminals ot that constitute each terminal group Ts are sometimes referred to in order from the left as a "red terminal", a "green terminal", and a "blue terminal", and the red terminal, the green terminal, and the blue terminal of the nth terminal group Ts from the left are sometimes referred to (labeled) as a "red terminal nR", a "green terminal nG", and a "blue terminal nB". For example, the three source output terminals ot that constitute the first terminal group Ts (that is, the leftmost terminal group Ts) from the left are sometimes referred to (labeled) as a "red terminal 0001R", a "green terminal 0001G", and a "blue terminal 0001B". ​

[0243] As already explained, in the present embodiment, the signal inputted to the back panel 200 is a signal in which the input signal has been monochrome-converted. Therefore, the three source output terminals (red terminal, green terminal, and blue terminal) ot constituting each terminal group Ts output source signals of the same gray scale.

[0244] In addition, in the present embodiment, the plurality of source output terminals ot include: a plurality of first source output terminals otl electrically connected to a plurality of first source wirings (normal source wirings) SL a; a plurality of second source output terminals ot2 electrically connected to a plurality of second source wirings (additional source wirings) SLb; and a plurality of third source output terminals ot3 not electrically connected to either the first source wirings SL a or the second source wirings SLb (in the present embodiment, indicated as "NC" in FIG. 6). FIG. 7A and FIG. 7B In addition, in the present embodiment, the plurality of source output terminals ot include: a plurality of first source output terminals otl electrically connected to a plurality of first source wirings (normal source wirings) SL a; a plurality of second source output terminals ot2 electrically connected to a plurality of second source wirings (additional source wirings) SLb; and a plurality of third source output terminals ot3 not electrically connected to either the first source wirings SL a or the second source wirings SLb (in the present embodiment, indicated as "NC" in FIG. 6).

[0245] One of the three source output terminals ot constituting each terminal group Ts is electrically connected to a corresponding first source wiring (normal source wiring) SL a (i.e., is a first source output terminal otl). More specifically, the blue terminal of each terminal group Ts is a first source output terminal otl, and the blue terminal nB of the nth terminal group Ts is electrically connected to the nth first source wiring SL a_n.

[0246] Here, the pixel column of the plurality of pixel columns constituted by the plurality of pixels P adjacent to the left-side additional area (first portion) CR2a is referred to as a "first endmost pixel column", and the pixel column adjacent to the right-side additional area (second portion) CR2b is referred to as a "second endmost pixel column". Similarly, the pixel row of the plurality of pixel rows constituted by the plurality of pixels P adjacent to the upper-side additional area (third portion) CR2c is referred to as a "first endmost pixel row", and the pixel row adjacent to the lower-side additional area (fourth portion) CR2d is referred to as a "second endmost pixel row". In addition, the terminal group TSA of the plurality of terminal groups Ts including the first source output terminal otl electrically connected to the first source wiring SL a_1 corresponding to the first endmost pixel column is referred to as a "first endmost terminal group", and the terminal group TsB including the first source output terminal otl electrically connected to the first source wiring SL a_3840 corresponding to the second endmost pixel column is referred to as a "second endmost terminal group".

[0247] Two of the three source output terminals ot of the first outermost edge terminal group TsA are electrically connected to the second source wiring (additional source wiring) SLb (i.e., the second source output terminal ot2) of the left-side additional area CR2a. More specifically, the red terminal 0001R and the green terminal 0001G of the first outermost edge terminal group TsA are the second source output terminal ot2. The red terminal 0001R and the green terminal 0001G output source signals of opposite polarities.

[0248] Additionally, two of the three source output terminals ot of the second outermost edge terminal group TsB are electrically connected to the second source wiring (additional source wiring) SLb (i.e., the second source output terminal ot2) of the right-side additional area CR2b. More specifically, the red terminal 3840R and the green terminal 3840G of the second outermost edge terminal group TsB are the second source output terminal ot2. The red terminal 3840R and the green terminal 3840G output source signals of opposite polarities.

[0249] exist FIG. 5 In the example shown, the multiple second source polarity lines SLb include six second source polarity lines SLb_1 to SLb_6 located in the left additional region CR2a and six second source polarity lines SLb7 to SLb_12 located in the right additional region CR2b.

[0250] A portion of the second source wiring SLb in the left-side additional area CR2a, specifically the first, third, and fifth second source wirings SLb_1, SLb_3, and SLb_5, are electrically connected to the red terminal 0001R of the first outermost edge terminal group TsA. The remaining second source wiring SLb, specifically the second, fourth, and sixth second source wirings SLb_2, SLb_4, and SLb_6, are electrically connected to the green terminal 0001G of the first outermost edge terminal group TsA.

[0251] A portion of the second source wiring SLb in the right-side additional area CR2b, specifically the 7th, 9th, and 11th second source wirings SLb_7, SLb_9, and SLb_11, are electrically connected to the green terminal 3840G of the second outermost edge terminal group TsB. The remaining second source wiring SLb, specifically the 8th, 10th, and 12th second source wirings SLb_8, SLb_10, and SLb_12, are electrically connected to the red terminal 3840R of the second outermost edge terminal group TsB.

[0252] The red terminal and the green terminal of each terminal group Ts other than the first endmost terminal group TsA and the second endmost terminal group TsB are not electrically connected to both the first source wiring SLa and the second source wiring SLb (i.e., is the third source output terminal ot3).

[0253] Thus, the plurality of source wirings SLa and SLb are selectively connected to a part of the plurality of source output terminals ot so that the back panel 200 is driven by source inversion driving or dot inversion driving.

[0254] In the illustrated example, the source wiring drive circuit 16 (the plurality of source drivers SD) includes a plurality of buffer amplifiers (Buffer Amps) 17. The buffer amplifiers 17 can be, for example, buffer amplifiers that are originally provided to correct disconnection of the source wirings SLa and SLb. The plurality of second source output terminals ot2, i.e., the red terminal 0001R, the green terminal 0001G, the red terminal 3840R, and the green terminal 3840G are each electrically connected to the corresponding second source wiring SLb via a certain one of the plurality of buffer amplifiers 17.

[0255] Specifically, the red terminal 0001R is electrically connected to the second source wirings SLb_1, SLb_3, and SLb_5 via one of the two buffer amplifiers 17A and 17B illustrated in FIG. 17B, and the green terminal 0001G is electrically connected to the second source wirings SLb_2, SLb_4, and SLb_6 via the other buffer amplifier 17A. FIG. 7A The red terminal 3840R is electrically connected to the second source wirings SLb_8, SLb_10, and SLb_12 via one of the two buffer amplifiers 17C and 17D illustrated in FIG. 17C, and the green terminal 3840G is electrically connected to the second source wirings SLb_7, SLb_9, and SLb_11 via the other buffer amplifier 17D. FIG. 7B The red terminal 3840R is electrically connected to the second source wirings SLb_8, SLb_10, and SLb_12 via one of the two buffer amplifiers 17C and 17D illustrated in FIG. 17C, and the green terminal 3840G is electrically connected to the second source wirings SLb_7, SLb_9, and SLb_11 via the other buffer amplifier 17D.

[0256] The back panel 200 has a connection wiring (an intra-panel wiring) CL for electrically connecting each second source output terminal ot2 to the corresponding second source wiring SLb via the buffer amplifier 17. The detailed structure of the connection wiring CL will be described later.

[0257] FIG. 8 is a view illustrating the vicinity of the gate wiring drive circuit 15 on the left side. In FIG. 8In the following description, the nth first gate line GLa from the upper side among the plurality of first gate lines (normal source lines) GLa is denoted as "GLa_n". In addition, the nth second gate line GLb from the upper side among the plurality of second gate lines (additional gate lines) GLb is denoted as "GLb_n", and the nth third gate line GLc from the upper side among the plurality of third gate lines (additional gate lines) GLc is denoted as "GLc_n". In FIG. 8 The first to third, 2158th to 2160th first gate lines (normal gate lines) GLa_1 to GLa_3, GLa_2158 to GLa_2160, the first to fourth second gate lines (additional gate lines) GLb_1 to GLb_4, and the first to fourth third gate lines (additional gate lines) GLc_1 to GLc_4 are shown in FIG. 21.

[0258] The four second gate lines GLb_1 to GLb_4 provided in the upper additional area (third portion) CR2c are electrically connected to the first gate line GLa_1 provided corresponding to the first endmost pixel row (pixel row adjacent to the upper additional area CR2c). In addition, the four third gate lines GLc_1 to GLc_4 provided in the lower additional area (fourth portion) CR2d are electrically connected to the first gate line GLa_2160 provided corresponding to the second endmost pixel row (pixel row adjacent to the lower additional area CR2d).

[0259] By making the connection of the additional source line (second source line) SLb and the additional gate lines (second gate line, third gate line) GLb, GLc as described above, the plurality of additional pixels AP are lit as follows.

[0260] Each additional pixel (first additional pixel) AP in the plurality of additional pixels AP located in the left additional area CR2a exhibits substantially the same luminance as the pixel P of the same row of the first endmost pixel column (pixel column adjacent to the left additional area CR2a), and each additional pixel (second additional pixel) AP located in the right additional area CR2b exhibits substantially the same luminance as the pixel P of the same row of the second endmost pixel column (pixel column adjacent to the right additional area CR2b).

[0261] In addition, each additional pixel (third additional pixel) AP located in the upper additional area CR2c exhibits substantially the same luminance as the pixel P of the same column of the first endmost pixel row (pixel row adjacent to the upper additional area CR2c), and each additional pixel (fourth additional pixel) AP located in the lower additional area CR2d exhibits substantially the same luminance as the pixel P of the same column of the second endmost pixel row (pixel row adjacent to the lower additional area CR2d).

[0262] As described above, in the liquid crystal display device 1000 of the embodiment of the present application, the source output terminals ot other than the source output terminal ot (here, blue terminals 0001B, 3840B) that source-outputs the normal source wiring SLa from the source output terminals ot that constitute the terminal groups TsA and TsB corresponding to the most edge pixel columns (the 1st most edge pixel column and the 2nd most edge pixel column) (it can be said that the source output terminals ot are "free" source output terminals ot, here, red terminals 0001R, 3840R and green terminals 0001G, 3840G) source-output the additional source wiring (2nd source wiring) SLa. In addition, the additional gate wirings (2nd gate wiring and 3rd gate wiring) GLb and GLc are connected to the normal gate wiring (1st gate wiring) GLa corresponding to the most edge pixel rows (1st most edge pixel row and 2nd most edge pixel row). With this configuration, it is not necessary to separately prepare an input signal for the additional pixels AP in the system circuit 10, and therefore, it is possible to use a periphery circuit (a timing controller, a gate driver, a source driver) for a normal liquid crystal panel, or it is not necessary to change the specification of the input signal (for example, in the case of 4K resolution, a signal input of 3840 x 2160 is sufficient).

[0263] Further, in the present embodiment, since the normal source wiring (1st source wiring) SLa and the additional source wiring (2nd source wiring) SLb are connected to different source output terminals ot and are separated from each other, there is no adverse effect on the pixels P of the 1st dimming region CR1. In contrast, for example, if the additional source wiring (2nd source wiring) SLb is branched from the normal source wiring (1st source wiring) SLa_1, SLa_3840 corresponding to the most edge pixel columns, the wiring load is increased and the normal source wiring (1st source wiring) SLa_1, SLa_3840 can not be sufficiently charged.

[0264] In addition, when the additional source wiring (second source wiring) SLb is connected to the source output terminal ot via the buffer amplifier 17 as in the present embodiment, even in the case where one source output terminal ot is connected to two or more additional source wirings (second source wirings) SLb, it is possible to prevent an increase in load of the source driver SD or a drop in signal level. Further, in the above description, a configuration in which the buffer amplifier 17 is provided in the source driver SD is exemplified, but the buffer amplifier 17 can be provided in a source-side printed wiring board (S-PWB). Since there are source drivers or S-PWBs in which a buffer amplifier for correcting a disconnection of a source wiring SL as described later is provided in a source driver or S-PWB for a general liquid crystal panel, as the buffer amplifier 17 used for connection of the additional source wiring (second source wiring) SLb, it is possible to use the buffer amplifier provided for correction of disconnection (i.e., it is not necessary to develop a source driver or S-PWB having a buffer amplifier separately).

[0265] Further, in the above description, the liquid crystal display device 1000 that performs display in the horizontal electric field mode (more specifically, the FFS mode) is exemplified, but the display mode of the liquid crystal display device 1000 is not limited to the horizontal electric field mode. When display is performed in the horizontal electric field mode, excellent viewing angle characteristics are obtained.

[0266] [Example of Connection Wiring CL Provided in Back Panel 200]

[0267] With reference to FIG. 9A , FIG. 9B , FIG. 9C and FIG. 9D , an example of the connection wiring (in-panel wiring) CL provided in the back panel 200 will be described.

[0268] FIG. 9A is a cross-sectional view along the 9A-9A' line in FIG. 7A , illustrating a connection wiring CL1 for electrically connecting the green terminal 0001G and the buffer amplifier 17A.

[0269] The connection wiring CL1 includes a gate metal portion GM1 formed of the same conductive film as the gate wiring GL, and source metal portions SM1 and SM2 formed of the same conductive film as the source wiring SL. The gate metal portion GM1 extends in the row direction, and the source metal portions SM1 and SM2 extend in the column direction.

[0270] A gate metal portion GM1 is disposed on a substrate (e.g., a glass substrate) 210a and is covered by a gate insulating layer 213. Source metal portions SM1 and SM2 are disposed on the gate insulating layer 213 and are covered by a first interlayer insulating layer 214. A planarization layer 215 and a second interlayer insulating layer 216 are further stacked on the first interlayer insulating layer 214. FIG. 9A The diagram also shows columnar spacers 231 that define the thickness of the liquid crystal layer 230.

[0271] The source signal from the green terminal 0001G is input to the source metal section SM1. The source metal section SM2 provides the output to the buffer amplifier 17A. The gate metal section GM1 electrically connects the source metal sections SM1 and SM2. The source metal sections SM1 and SM2 are connected to the gate metal section GM1 through contact holes CH1 and CH2 formed in the gate insulating layer 213, respectively.

[0272] FIG. 9B It is along FIG. 7A The cross-sectional view of line 9B-9B' shows the connection wiring CL2 used to electrically connect the red terminal 0001R to the buffer amplifier 17B.

[0273] The connection wiring CL2 includes a gate metal portion GM2 and source metal portions SM3 and SM4. The gate metal portion GM2 extends in the row direction, and the source metal portions SM3 and SM4 extend in the column direction.

[0274] The source signal from the red terminal 0001R is input to the source metal section SM3. The source metal section SM4 provides the output to the buffer amplifier 17B. The gate metal section GM2 electrically connects the source metal sections SM3 and SM4. The source metal sections SM3 and SM4 are connected to the gate metal section GM2 through contact holes CH3 and CH4 formed in the gate insulating layer 213, respectively.

[0275] FIG. 9C It is along FIG. 7A The cross-sectional view of line 9C-9C' in the figure shows the connection wiring CL3 used to electrically connect the buffer amplifier 17B to the second source wiring (additional source wiring) SLb_1, SLb_3, SLb_5.

[0276] The connection wiring CL3 includes a gate metal portion GM3 and a source metal portion SM5. The gate metal portion GM3 extends in the row direction, and the source metal portion SM5 extends in the column direction.

[0277] The source signal output from the buffer amplifier 17B is input to the 2nd source lines SLb_1, SLb_3, SLb_5 via the source metal portion SM5 and the gate metal portion GM3 of the connection line CL3. The source metal portion SM5 is connected to the gate metal portion GM3 in the contact hole CH5 formed in the gate insulating layer 213. The 2nd source lines SLb_1, SLb_3, SLb_5 are connected to the gate metal portion GM3 in the contact holes CH6, CH7, and CH8 formed in the gate insulating layer 213, respectively.

[0278] FIG. 9D is a cross-sectional view along the 9D-9D' line in FIG. 7A , showing a connection line CL4 for electrically connecting the buffer amplifier 17A and the 2nd source lines (additional source lines) SLb_2, SLb_4, SLb_6.

[0279] The connection line CL4 includes a gate metal portion GM4 and a source metal portion SM6. The gate metal portion GM4 extends in the row direction, and the source metal portion SM6 extends in the column direction.

[0280] The source signal output from the buffer amplifier 17A is input to the 2nd source lines SLb_2, SLb_4, SLb_6 via the source metal portion SM6 and the gate metal portion GM4 of the connection line CL4. The source metal portion SM6 is connected to the gate metal portion GM4 in the contact hole CH9 formed in the gate insulating layer 213. The 2nd source lines SLb_2, SLb_4, SLb_6 are connected to the gate metal portion GM4 in the contact holes CH10, CH11, and CH12 formed in the gate insulating layer 213, respectively.

[0281] [Regarding the number of additional pixel columns and additional pixel rows]

[0282] In FIG. 5 and the like, an example is shown in which the additional pixels AP are arranged in a plurality of rows and a plurality of columns within the 2nd light modulation region (additional light modulation region) CR2, but the arrangement of the additional pixels AP is not limited to this example. For example, it can also be that, in each of the left-side additional region CR2a and the right-side additional region CR2b, the additional pixels AP are arranged in one column. In this case, each of the 1st endmost edge terminal group TsA and the 2nd endmost edge terminal group TsB includes one 1st source output terminal ot1, one 2nd source output terminal ot2, and one 3rd source output terminal ot3. It can also be that, in each of the upper-side additional region CR2c and the lower-side additional region CR2d, the additional pixels AP are arranged in one row.

[0283] The number of preferred additional pixel columns and additional pixel rows in the 2nd light modulation region CR2 can be calculated, for example, in the following manner.

[0284] The number of the additional pixel columns and the additional pixel rows is preferably determined in accordance with the desired viewing angle (the angle below which image loss is not required to occur) and the module configuration (picture size, resolution, thickness, etc.). In the following description, the viewing angle in the left-right direction (horizontal direction) as shown in FIG. 1 is referred to as "horizontal viewing angle", and the viewing angle in the up-down direction (vertical direction) is referred to as "vertical viewing angle". In Table 1 below, a calculation example is shown for the case where the horizontal viewing angle θ FIG. 10A h is 50° and the vertical viewing angle θ v is 35°. h v

[0285]

Table 1

[0286] Trial Calculation Conditions Screen Size 31.52 inches (inch) Display Area Size 697.7 mm x 392.5 mm Resolution of Back Panel (Generally Light Modulating Area) 3840×2160 Back Panel Pixel Pitch p 0.18170 mm Horizontal expected angle θ h ]] 50° vertical expected angle θ v ]]> 35.0° Gap G between TFT Substrates 1.49 mm Panel Attachment Precision A 0.1 mm

[0287] FIG. 10B A situation is schematically shown in which light from an observer who is viewing the end edge in the horizontal direction of the display region DR at the horizontal viewing angle θ h advances from inside the liquid crystal display device 1000 toward the observer side. In the example shown in FIG. 1, a pair of polarizing plates 20A and 20B are arranged so as to sandwich the front panel 100, and a pair of polarizing plates 20C and 20D are arranged so as to sandwich the rear panel 200. The front panel 100 and the rear panel 200 are adhered by an optical clear adhesive (OCA) 22 provided therebetween (more specifically, between the polarizing plate 20D on the front side of the rear panel 200 and the polarizing plate 20A on the back side of the front panel 100). FIG. 10B

[0288] According to the Snell's law, the horizontal viewing angle θ h ' inside the liquid crystal display device 1000 is represented by the following formula (1). FIG. 10B h

[0289] n A sinθ h ' = n g sinθ h '…(1)

[0290] In formula (1), n A is the refractive index of air, and n g is the refractive index of the substrate glass. When the refractive index of air is set to 1 and the refractive index of the substrate glass is set to 1.52, the horizontal viewing angle θ h ' inside the liquid crystal display device 1000 is calculated to be 30.3° according to formula (1). ​​​​​​

[0291] On the other hand, when the gap between the TFT substrate 110 and the TFT substrate 210 is set to G, and the bonding accuracy of the front panel 100 and the rear panel 200 is set to A, the width Wh in the horizontal direction (row direction) of each of the left-side additional area CR2a and the right-side additional area CR2b is represented by the following equation (2).

[0292] Wh = G x tan θ h + A... (2)

[0293] According to equation (2), the width Wh of each of the left-side additional area CR2a and the right-side additional area CR2b is calculated to be 0.97 mm. The number Ph of the additional pixel columns that should be arranged in each of the left-side additional area CR2a and the right-side additional area CR2b is the width Wh of the left-side additional area CR2a and the right-side additional area CR2b divided by the pixel pitch p (i.e., Wh / p), and thus is calculated to be 5.3.

[0294] Similarly, the width Wv in the vertical direction (column direction) of each of the upper-side additional area CR2c and the lower-side additional area CR2d, and the number Pv of the additional pixel rows that should be arranged in each of the upper-side additional area CR2c and the lower-side additional area CR2d are respectively calculated to be 0.71 mm and 3.9. The results of the trial calculation are shown in Table 2 below.

[0295] [Table 2]

[0296] Trial Calculation Results Horizontal Direction Width Wh of Left Side Additional Area and Right Side Additional Area 0.97 mm Vertical Direction Width Wv of Upper Side Additional Area and Lower Side Additional Area 0.71 mm Number of Added Pixel Columns Ph to Left Side Additional Area and Right Side Additional Area 5.3 Number of Added Pixel Rows Pv to Upper Side Additional Area and Lower Side Additional Area 3.9

[0297] According to the results of the trial calculation shown in Table 2, in the configuration exemplified in Embodiment 1, FIG. 5 In the configuration exemplified in Embodiment 1, the number of the additional pixel columns in each of the left-side additional area (1st portion) CR2a and the right-side additional area (2nd portion) CR2b is set to 6, and the number of the additional pixel rows in each of the upper-side additional area (3rd portion) CR2c and the lower-side additional area (4th portion) CR2d is set to 4.

[0298] Thus, the actual number of added pixel columns and the actual number of added pixel rows are integer values obtained by rounding up the calculated (i.e., computational) number of added pixel columns and the calculated number of added pixel rows. Hereinafter, the actual number of added pixel columns and the actual number of added pixel rows are denoted as "Phr" and "Pvr", respectively. In addition, the actual width of each of the left-side added region CR2a and the right-side added region CR2b is a value obtained by multiplying the actual number of added pixel columns Phr by the pixel pitch p, and is denoted as "Whr". Similarly, the actual width of each of the upper-side added region CR2c and the lower-side added region CR2d is a value obtained by multiplying the actual number of added pixel rows Pvr by the pixel pitch p, and is denoted as "Wvr". In addition, hereinafter, in the case where only the "number of added pixel columns" or the "number of added pixel rows" is mentioned, the actual number of added pixel columns Phr or the actual number of added pixel rows Pvr is meant. Similarly, in the case where only the "width of the left-side added region CR2a (or the right-side added region CR2b)" is mentioned, the actual width Whr of the left-side added region CR2a (or the right-side added region CR2b) is meant, and in the case where only the "width of the upper-side added region CR2c (or the lower-side added region CR2d)" is mentioned, the actual width Wvr of the upper-side added region CR2c (or the lower-side added region CR2d) is meant.

[0299] In Tables 3 and 4 below, and FIG. 10C and FIG. 10D the picture size, the resolution, the horizontal intended angle θ h and the vertical intended angle θ v are changed, and the trial calculation results of the widths Whr of the left-side added region CR2a and the right-side added region CR2b, and the widths Wvr of the upper-side added region CR2c and the lower-side added region CR2d are shown.

[0300] [Table 3]

[0301]

[0302] [Table 4]

[0303]

[0304] As is apparent from Tables 3 and FIG. 10C , the width Whr in the row direction of each of the left-side added region CR2a and the right-side added region CR2b is 2 mm or less, and thus image loss can be prevented. In addition, as is apparent from Tables 4 and FIG. 10D , the width Wvr in the column direction of each of the upper-side added region CR2c and the lower-side added region CR2d is 2 mm or less, and thus image loss can be prevented.

[0305] In Tables 5 and FIG. 10EThe ratio Whr / Wvr of the width Whr of the left and right additional regions CR2a and CR2b to the width Wvr of the upper and lower additional regions CR2c and CR2d is shown.

[0306] [Table 5]

[0307]

[0308] According to Table 5 and FIG. 10E It is known that the width Whr of each of the left and right additional regions CR2a and CR2b in the row direction satisfies the relationship of Whr / Wvr < 2 with respect to the width Wvr of each of the upper and lower additional regions CR2c and CR2d in the column direction.

[0309] In the following Table 6 and Table 7, and FIG. 10F and FIG. 10G the size of the screen, the resolution, the horizontal intended angle θ h and the vertical intended angle θ v are changed, and the results of trial calculations of the number Phr of additional pixel columns in the left and right additional regions CR2a and CR2b, and the number Pvr of additional pixel rows in the upper and lower additional regions CR2c and CR2d are shown.

[0310] [Table 6]

[0311]

[0312] [Table 7]

[0313]

[0314] According to Table 6 and FIG. 10F it is known that the number Phr of additional pixel columns in each of the left and right additional regions CR2a and CR2b is 25 or less, and thus image loss can be prevented. Further, according to Table 7 and FIG. 10G it is known that the number Pvr of additional pixel rows in each of the upper and lower additional regions CR2c and CR2d is 25 or less, and thus image loss can be prevented.

[0315] In the following Table 8 and FIG. 10H the ratio Phr / Pvr of the number Phr of additional pixel columns in the left and right additional regions CR2a and CR2b to the number Pvr of additional pixel rows in the upper and lower additional regions CR2c and CR2d is shown.

[0316] [Table 8]

[0317]

[0318] According to Table 8 and FIG. 10H It is known that the number Phr of the added pixel columns in each of the left and right added regions CR2a and CR2b preferably satisfies a relationship of Phr / Pvr≤2 with the number Pvr of the added pixel rows in each of the upper and lower added regions CR2c and CR2d.

[0319] [Another connection example of the source wiring SL and the source output terminal ot]

[0320] In FIG. 11A and FIG. 11B , another connection example of the source wiring SL and the source output terminal ot is shown. In the example shown in FIG. 11A and FIG. 11B , the red terminal of each terminal group Ts is the 1st source output terminal ot1, and the red terminal nR of the n-th terminal group Ts is electrically connected to the n-th 1st source wiring (normal source wiring) SLa_n.

[0321] In addition, the green terminal 0001G and the blue terminal 0001B of the 1st endmost terminal group TsA are electrically connected to the 2nd source wiring (added source wiring) SLb of the left added region CR2a (i.e., the 2nd source output terminal ot2), and the green terminal 3840G and the blue terminal 3840B of the 2nd endmost terminal group TsB are electrically connected to the 2nd source wiring (added source wiring) SLb of the right added region CR2b (i.e., the 2nd source output terminal ot2).

[0322] The 1st, 3rd, and 5th of the 2nd source wirings SLb_1, SLb_3, and SLb_5 provided in the 2nd source wiring SLb of the left added region CR2a are electrically connected to the blue terminal 0001B of the 1st endmost terminal group TsA, and the 2nd, 4th, and 6th of the 2nd source wirings SLb_2, SLb_4, and SLb_6 are electrically connected to the green terminal 0001G of the 1st endmost terminal group TsA.

[0323] The 7th, 9th, and 11th of the 2nd source wirings SLb_7, SLb_9, and SLb_11 provided in the 2nd source wiring SLb of the right added region CR2b are electrically connected to the green terminal 3840G of the 2nd endmost terminal group TsB, and the 8th, 10th, and 12th of the 2nd source wirings SLb_8, SLb_10, and SLb_12 are electrically connected to the blue terminal 3840B of the 2nd endmost terminal group TsB.

[0324] The green terminal and the blue terminal of each terminal group Ts other than the 1st endmost terminal group TsA and the 2nd endmost terminal group TsB are not electrically connected to either the 1st source wiring SLa or the 2nd source wiring SLb (i.e., the 3rd source output terminal ot3).

[0325] Even if the configuration shown in FIG. 11A and FIG. 11B is adopted, the same effects as those of the configuration shown in FIG. 7A and FIG. 7B can be obtained.

[0326] [Another example of the configuration of the gate line drive circuit 15]

[0327] An example of another configuration of the gate line drive circuit 15 is shown in FIG. 12 . In the example shown in FIG. 12 , a plurality of gate drivers GD' are monolithically (integrally) formed on the TFT substrate 210 of the back panel 200. The gate driver circuit formed monolithically is sometimes referred to as a GDM (Gate Driver Monolithic) circuit.

[0328] In the configuration in which the gate driver GD' is a GDM circuit, the same effects can be obtained.

[0329] [Another example of the connection method using the buffer amplifier 17]

[0330] Another example of the connection method using the buffer amplifier 17 is shown in FIG. 13 . In FIG. 13 , the leftmost source driver (hereinafter referred to as "first source driver") SD1 among a plurality of source drivers SD and a source driver (hereinafter referred to as "second source driver") SD2 different from (adjacent to) the first source driver SD1 are shown. Two buffer amplifiers 17A and 17B are provided in the first source driver SD1, and two buffer amplifiers 17E and 17F are also provided in the second source driver SD2.

[0331] In the example shown in FIG. 13 , the red terminal 0001R (second source output terminal ot2) is electrically connected to the additional source lines (second source lines) SLb_1, SLb_3, and SLb_5 via the buffer amplifier 17B of the first source driver SD1 and the buffer amplifier 17F of the second source driver SD2 (i.e., via two buffer amplifiers 17). In addition, the green terminal 0001G (second source output terminal ot2) is electrically connected to the additional source lines (second source lines) SLb_2, SLb_4, and SLb_6 via the buffer amplifier 17A of the first source driver SD1 and the buffer amplifier 17E of the second source driver SD2 (i.e., via two buffer amplifiers 17).

[0332] Thus, one second source output terminal ot2 is connected to the second source line SLb via two or more (in this case, two) buffer amplifiers 17, so that the signal strength can be further increased.

[0333] In FIG. 14 another example of the connection method using the buffer amplifiers 17 is shown. In FIG. 14 the example shown, the red terminal 0001R (second source output terminal ot2) is electrically connected to the additional source lines (second source lines) SLb_l, SLb_3, SLb_5 via the buffer amplifiers 17E and 17F of the second source driver SD2 (i.e., via two buffer amplifiers 17). Also, the green terminal 0001G (second source output terminal ot2) is electrically connected to the additional source lines (second source lines) SLb_2, SLb_4, SLb_6 via the buffer amplifiers 17A and 17B of the first source driver SDl (i.e., via two buffer amplifiers 17).

[0334] In FIG. 14 the example shown, one second source output terminal ot2 is connected to the second source line SLb via two buffer amplifiers 17, so that the signal strength can be further increased.

[0335] In FIG. 15 another example of the connection method using the buffer amplifiers 17 is shown. In FIG. 15 the example shown, the red terminal 0001R (second source output terminal ot2) is electrically connected to the additional source lines (second source lines) SLb_l, SLb_3, SLb_5 via the buffer amplifier 17B of the first source driver SDl. The green terminal 0001G (second source output terminal ot2) is electrically connected to the additional source lines (second source lines) SLb_2, SLb_4, SLb_6 via the buffer amplifier 17A of the first source driver SDl.

[0336] Also, in FIG. 15 the example shown, the preliminary lines ALl and AL2 are provided which are routed outside the second dimming region CR2. The preliminary lines ALl and AL2 are configured to be electrically connected to any of the source lines SL.

[0337] In FIG. 15An example in which the backup line AL1 is connected to the source line SL in which disconnection has occurred at the disconnection site Di is shown in FIG. 1. Specifically, the portion of the source line SL on the upstream side from the disconnection site Di is connected to the backup line AL1 at the intersection P1 thereof, and the portion of the source line SL on the downstream side from the disconnection site Di is connected to the backup line AL1 at the intersection P2 thereof. The connection of the source line SL to the backup line AL1 can be performed, for example, by fusing the source line SL and the backup line AL1 by laser irradiation to the intersections P1 and P2, respectively.

[0338] By connecting the backup line AL1 to the source line SL in which disconnection has occurred, it is possible to supply the source signal to the portion of the source line SL on the downstream side from the disconnection site Di via the backup line AL1. According to the example shown in FIG. 1, the source signal is supplied to the portion of the source line SL on the downstream side from the disconnection site Di via the backup line AL1 and the buffer amplifier 17F of the second source driver SD2. FIG. 15 It is to be noted that the supply of the source signal via the backup line AL1 is performed via the buffer amplifier 17F of the second source driver SD2. In contrast, in the case where the backup line AL2 is connected to the source line SL in which disconnection has occurred, the supply of the source signal via the backup line AL2 is performed via the buffer amplifier 17E of the second source driver SD2.

[0339] In this way, by using a part of the plurality of buffer amplifiers 17 for supplying the source signal to the additional source line SLb and using another part of the buffer amplifiers 17 for disconnection correction, it is possible to appropriately perform both the input of the source signal to the additional pixel AP and the correction of the disconnection of the source line SL.

[0340] Further, the example in which two backup lines AL1 and AL2 are provided is shown in the drawing, but the number of backup lines is not limited to two. The number of backup lines is, for example, five to ten.

[0341] In FIG. 16 another example of the connection method using the buffer amplifiers 17 is shown in FIG. 2. In FIG. 16 A leftmost source driver (first source driver) SD1 and two source drivers (second source driver and third source driver) SD2 and SD3 different from the first source driver SD1 are shown in FIG. 2. Two buffer amplifiers 17A and 17B are provided in the first source driver SD1. Two buffer amplifiers 17E and 17F are also provided in the second source driver SD2, and two buffer amplifiers 17G and 17H are also provided in the third source driver SD3.

[0342] In FIG. 16In the illustrated example, the red terminal 0001R (2nd source output terminal ot2) is electrically connected to the additional source lines (2nd source lines) SLb_1, SLb_3, SLb_5 via the buffer amplifier 17B of the 1st source driver SD1 and the buffer amplifier 17F of the 2nd source driver SD2 (i.e., via 2 buffer amplifiers 17). In addition, the green terminal 0001G (2nd source output terminal ot2) is electrically connected to the additional source lines (2nd source lines) SLb_2, SLb_4, SLb_6 via the buffer amplifier 17A of the 1st source driver SD1 and the buffer amplifier 17E of the 2nd source driver SD2 (i.e., via 2 buffer amplifiers 17).

[0343] In addition, in FIG. 16 In the illustrated example, the preparatory lines AL1 and AL2 are provided which are routed outside the 2nd light modulation region CR2. The preparatory lines AL1 and AL2 are configured to be electrically connectable to any of the source lines SL.

[0344] According to FIG. 16 It is known that, in the case where the preparatory line AL1 is used for the line break correction of the source line SL, the buffer amplifier 17H of the 3rd source driver SD3 is used. In addition, in the case where the preparatory line AL2 is used for the line break correction of the source line SL, the buffer amplifier 17G of the 3rd source driver SD3 is used. In FIG. 16 Both the input of the source signal to the additional pixel AP and the correction of the line break of the source line SL can also be appropriately performed in the illustrated example.

[0345] [Another configuration of the 2nd light modulation region CR2]

[0346] In the above description, the configuration in which the 2nd light modulation region (additional light modulation region) CR2 is a frame shape that surrounds the 1st light modulation region CR1 is exemplified, but the embodiment of the present application is not limited to this configuration.

[0347] In FIG. 17 Another example of the configuration of the 2nd light modulation region CR2 is shown in FIG. 17. In FIG. 17 In the illustrated example, the 2nd light modulation region CR2 includes the left additional region (1st portion) CR2a and the right additional region (2nd portion) CR2b, but does not include the upper additional region (3rd portion) CR2c and the lower additional region (4th portion) CR2d. In addition, the plurality of gate lines GL includes only the 1st gate line (normal gate line) GLa, but does not include the 2nd gate line (additional gate line) GLb and the 3rd gate line (additional gate line) GLc. For example, since the use of the liquid crystal display device 1000 is different, the image loss in the up-down direction is sometimes not considered a problem, and thus, in this case, the configuration shown in FIG. 17 may also be employed.

[0348] Another example of the configuration of the 2nd light regulating region CR2 is shown in FIG. 18 Another example of the configuration of the 2nd light regulating region CR2 is shown in FIG. 18 In the example shown in FIG. 17, the 2nd light regulating region CR2 includes the upper additional region (3rd portion) CR2c and the lower additional region (4th portion) CR2d, but does not include the left additional region (1st portion) CR2a and the right additional region (2nd portion) CR2b. In addition, the plurality of source lines SL includes only the 1st source line (normal source line) SLa, but does not include the 2nd source line (additional source line) SLb. For example, since the image loss in the left-right direction is not always regarded as a problem depending on the use of the liquid crystal display device 1000, in such a case, the configuration shown in FIG. 17 can also be employed. FIG. 18

[0349] As described above, according to the embodiment of the present application, a liquid crystal display device of a dual cell structure which prevents image loss when viewed from an oblique direction can be provided.

[0350] Further, in the above description, the case where the resolution of the front panel 100 is the same as the resolution of the 1st light regulating region (normal light regulating region) of the rear panel 200 is exemplified, but the embodiment of the present application is not limited thereto. For example, the resolution of the 1st light regulating region (normal light regulating region) of the rear panel 200 can be lower than the resolution of the front panel 100.

[0351] Industrial Applicability

[0352] The liquid crystal display device of the embodiment of the present application is suitable for use in a use (main monitor or the like) which requires display of a high contrast ratio.​

Claims

1. A liquid crystal display device comprising: a first liquid crystal panel having a display region and including a color filter layer; an illuminating device provided on a back surface side of the first liquid crystal panel; and a second liquid crystal panel disposed between the first liquid crystal panel and the illuminating device and not including a color filter layer, wherein the liquid crystal display device is characterized in that the second liquid crystal panel has: a first light regulating region defined by a plurality of pixels arranged in a matrix shape including a plurality of rows and a plurality of columns, and opposed to the display region; and a second light regulating region defined by a plurality of additional pixels each including an opening region not shielded from light, and located outside the first light regulating region, and in that a plurality of source wiring lines extend in a column direction, the second light regulating region includes a first portion and a second portion, the first portion and the second portion extend in the column direction and are disposed in a manner sandwiching the first light regulating region in a row direction, the liquid crystal display device further comprises a source wiring line drive circuit that supplies source signals to the plurality of source wiring lines, the plurality of source wiring lines include a plurality of first source wiring lines provided corresponding to the plurality of pixels, and a plurality of second source wiring lines provided corresponding to additional pixels of the plurality of additional pixels located in the first portion and the second portion of the second light regulating region, the source wiring line drive circuit has a plurality of source output terminals that output the source signals, and the plurality of source output terminals is more than the plurality of source wiring lines, the plurality of source output terminals includes a plurality of first source output terminals electrically connected to the plurality of first source wiring lines, a plurality of second source output terminals electrically connected to the plurality of second source wiring lines, and a plurality of third source output terminals not electrically connected to either the plurality of first source wiring lines or the plurality of second source wiring lines.

2. The liquid crystal display device according to claim 1, wherein when a number of the plurality of first source wiring lines is n, a number of the plurality of source output terminals is 3n.

3. The liquid crystal display device according to claim 1 or 2, wherein the source wiring line drive circuit has a plurality of terminal groups each including three source output terminals of the plurality of source output terminals that are continuously disposed, and the three source output terminals output source signals of the same gray scale.

4. The liquid crystal display device according to claim 3, wherein one of the three source output terminals is the first source output terminal.

5. The liquid crystal display device according to claim 4, wherein when a pixel column of the plurality of pixel columns constituted by the plurality of pixels that is adjacent to the first portion of the second light regulating region is referred to as a first endmost pixel column, and a pixel column that is adjacent to the second portion of the second light regulating region is referred to as a second endmost pixel column, ​ ​ ​ a plurality of gate lines extending in a row direction; ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ When a terminal group including the first source output terminal electrically connected to the first source line provided in correspondence with the first most edge pixel column among the plurality of terminal groups is referred to as a first most edge terminal group, and a terminal group including the first source output terminal electrically connected to the first source line provided in correspondence with the second most edge pixel column is referred to as a second most edge terminal group, One or two of the three source output terminals of each of the first most edge terminal group and the second most edge terminal group are the second source output terminals.

6. The liquid crystal display device according to claim 5, wherein Two of the three source output terminals included in each of the terminal groups other than the first most edge terminal group and the second most edge terminal group among the plurality of terminal groups are the third source output terminals.

7. The liquid crystal display device according to claim 5, wherein The plurality of source output terminals are arranged such that the source output terminals outputting a first polarity source signal and the source output terminals outputting a second polarity source signal opposite to the first polarity are alternately arranged along the row direction in one horizontal scanning period, The plurality of source lines are electrically connected to a part of the plurality of source output terminals so that the second liquid crystal panel is driven by source inversion driving or dot inversion driving.

8. The liquid crystal display device according to claim 7, wherein The additional pixels in each of the first portion and the second portion are arranged in a plurality of columns, The plurality of second source lines include two or more second source lines provided in the first portion and two or more second source lines provided in the second portion, Two of the three source output terminals included in each of the first most edge terminal group and the second most edge terminal group are two second source output terminals outputting source signals of opposite polarities to each other, One of the two or more second source lines provided in the first portion is electrically connected to one of the two second source output terminals of the first most edge terminal group, and the remaining second source line is electrically connected to the other of the two second source output terminals of the first most edge terminal group, One of the two or more second source lines provided in the second portion is electrically connected to one of the two second source output terminals of the second most edge terminal group, and the remaining second source line is electrically connected to the other of the two second source output terminals of the second most edge terminal group.

9. The liquid crystal display device according to claim 1 or 2, wherein a plurality of buffer amplifiers are further provided, each of the plurality of second source output terminals is electrically connected to a corresponding second source line via at least one of the plurality of buffer amplifiers.

10. The liquid crystal display device according to claim 9, wherein Each of the plurality of second source output terminals is electrically connected to a corresponding second source wiring via two or more of the plurality of buffer amplifiers.

11. The liquid crystal display device according to claim 9, wherein The source wiring drive circuit includes the plurality of buffer amplifiers.

12. The liquid crystal display device according to claim 9, wherein The second liquid crystal panel has a connection wiring for electrically connecting each second source output terminal to a corresponding second source wiring via the at least one buffer amplifier.

13. The liquid crystal display device according to claim 1 or 2, wherein The plurality of additional pixels include a plurality of first additional pixels located in the first portion of the second light regulating region and a plurality of second additional pixels located in the second portion of the second light regulating region, When a pixel column adjacent to the first portion of the second light regulating region among the plurality of pixel columns composed of the plurality of pixels is referred to as a first endmost pixel column and a pixel column adjacent to the second portion of the second light regulating region is referred to as a second endmost pixel column, Each of the plurality of first additional pixels exhibits substantially the same luminance as a pixel of the same row of the first endmost pixel column, Each of the plurality of second additional pixels exhibits substantially the same luminance as a pixel of the same row of the second endmost pixel column.

14. The liquid crystal display device according to claim 1 or 2, wherein A width Whr in a row direction of each of the first portion and the second portion of the second light regulating region is 2 mm or less.

15. The liquid crystal display device according to claim 1 or 2, wherein A number Phr of additional pixel columns among each of the first portion and the second portion of the second light regulating region is 25 or less.

16. The liquid crystal display device according to claim 1 or 2, wherein The second light regulating region includes a third portion and a fourth portion, the third portion and the fourth portion extending in a row direction and being arranged in a column direction in a manner sandwiching the first light regulating region.

17. The liquid crystal display device according to claim 16, wherein The plurality of gate wirings include a plurality of first gate wirings provided corresponding to the plurality of pixels, at least one second gate wiring provided corresponding to additional pixels of the plurality of additional pixels located in the third portion of the second light regulating region, and at least one third gate wiring provided corresponding to additional pixels of the plurality of additional pixels located in the fourth portion of the second light regulating region, The at least one second gate wiring is electrically connected to a first gate wiring of the plurality of first gate wirings provided corresponding to a pixel row adjacent to the third portion of the second light regulating region, The at least one third gate wiring is electrically connected to a first gate wiring of the plurality of first gate wirings provided corresponding to a pixel row adjacent to the fourth portion of the second light regulating region.

18. The liquid crystal display device according to claim 16, wherein The plurality of additional pixels includes a plurality of third additional pixels located in the third portion of the second light adjusting region, and a plurality of fourth additional pixels located in the fourth portion of the second light adjusting region, When a pixel row adjacent to the third portion of the second light adjusting region among a plurality of pixel rows composed of the plurality of pixels is referred to as a first endmost pixel row, and a pixel row adjacent to the fourth portion of the second light adjusting region is referred to as a second endmost pixel row, The plurality of third additional pixels each exhibit substantially the same luminance as a pixel of the same column of the first endmost pixel row, The plurality of fourth additional pixels each exhibit substantially the same luminance as a pixel of the same column of the second endmost pixel row.

19. The liquid crystal display device according to claim 16, wherein A width Wvr in a column direction of each of the third portion and the fourth portion of the second light adjusting region is 2 mm or less.

20. The liquid crystal display device according to claim 16, wherein A number Pvr of pixel rows of additional pixels among each of the third portion and the fourth portion of the second light adjusting region is 25 or less.

21. The liquid crystal display device according to claim 1 or 2, wherein The first light adjusting region is rectangular, The second light adjusting region is frame-shaped surrounding the first light adjusting region.

22. The liquid crystal display device according to claim 1 or 2, wherein Display is performed in a horizontal electric field mode.

Images