Electrostatic protection circuits and chips

Abstract

The present invention discloses an electrostatic protection circuit and chip. The electrostatic protection circuit includes: a thyristor rectifier having an anode, a cathode, and an electrostatic discharge path; a first trigger unit connected between the anode and cathode of the thyristor rectifier, for generating a trigger signal when static electricity occurs in the protected chip; a second trigger unit connected to the electrostatic discharge path, and the input end of the second trigger unit is connected to the output end of the first trigger unit, for conducting the electrostatic discharge path to discharge the electrostatic current based on the trigger signal. The present invention does not require acceleration and directly triggers the discharge and conduction of the second trigger unit by outputting a high level through the first trigger unit, thereby conducting the electrostatic discharge path to discharge the electrostatic current. This not only provides electrostatic protection for the protected chip, but also has the advantages of simple structure, small size, and fast triggering speed.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to an electrostatic protection circuit and chip. Background Art

[0002] Modern semiconductor manufacturing processes are becoming increasingly advanced. With ever-shorter channel lengths, shallower junction depths, the use of metal silicides, lightly doped drains (LDDs), and thinner oxide layers, the window for electrostatic discharge (ESD) design is shrinking, and the challenges facing ESD protection design are increasing. Existing ESD protection circuits require an inverter to connect the discharge tube NMOS transistor to the RC circuit, resulting in a slow turn-on speed. An acceleration module is typically required to speed up the turn-on of the discharge tube NMOS transistor, thereby increasing the triggering speed of the ESD protection circuit. However, this results in an increased size of the ESD protection circuit, which not only increases costs but also fails to meet the requirements for use in integrated circuits using current advanced manufacturing processes. Summary of the Invention

[0003] The purpose of the present invention is to provide an electrostatic protection circuit and chip. In order to solve the problem that the existing electrostatic protection circuit uses an acceleration module to speed up the triggering speed, resulting in a large size of the electrostatic protection circuit, the present invention does not require acceleration and directly triggers the second trigger unit to discharge and turn on by outputting a high level through the first trigger unit, thereby turning on the electrostatic discharge path to discharge the electrostatic current. It can not only provide electrostatic protection for the protected chip, but also has the advantages of simple structure, small size and fast triggering speed.

[0004] To solve the above problems, a first aspect of the present invention provides an electrostatic protection circuit, comprising:

[0005] A silicon controlled rectifier having an anode, a cathode and an electrostatic discharge path;

[0006] A first trigger unit is connected between the anode and cathode of the silicon controlled rectifier and is used to generate a high level when static electricity occurs in the protected chip;

[0007] The second trigger unit is connected to the electrostatic discharge path, and the input end of the second trigger unit is connected to the output end of the first trigger unit, and is used to turn on the electrostatic discharge path based on the high level to discharge the electrostatic current.

[0008] In one embodiment, the electrostatic discharge path includes a first transistor, a second transistor, a first resistor and a second resistor, the emitter of the first transistor is the anode of the thyristor rectifier, the base of the first transistor is connected to one end of the first resistor and the collector of the second transistor, the collector of the first transistor is connected to one end of the second resistor and the base of the second transistor, the other end of the second resistor is connected to the other end of the first resistor, and the emitter of the second transistor serves as the cathode of the thyristor rectifier.

[0009] In one embodiment, the first transistor is a PNP transistor, and the second transistor is an NPN transistor.

[0010] In one embodiment, the thyristor rectifier further has an electrostatic discharge trigger path, which includes a first diode and a second diode, the cathode of the first diode is connected to the cathode of the thyristor rectifier, the anode of the first diode is connected to the cathode of the second diode, and the anode of the second diode is connected to the anode of the thyristor rectifier.

[0011] In one embodiment, the silicon controlled rectifier comprises:

[0012] a substrate, wherein a first N-well, a P-well, and a second N-well are formed in the substrate, a first P+ junction and a first N+ junction are formed in the P-well, a second P+ junction and a second N+ junction are formed in the second N-well, and a third P+ junction is further formed in the substrate, the first N+ junction is connected to a cathode and forms a cathode of the thyristor, and the second P+ junction is connected to an anode and forms an anode of the thyristor;

[0013] The second P+ junction, the second N-well and the P-well are equivalent to the first triode, and the first N+ junction, the P-well and the second N-well are equivalent to the second triode;

[0014] The first P+ junction and the first N+ junction are equivalent to the first diode, and the second P+ junction and the second N+ junction are equivalent to the second diode.

[0015] In one embodiment, a deep N-well is further formed in the substrate, and the deep N-well is arranged on the lower surface of the P-well and the lower surfaces of parts of the first N-well and the second N-well.

[0016] In one embodiment, the first trigger unit includes a third resistor and a capacitor, one end of the capacitor is connected to the anode of the thyristor rectifier, the other end of the capacitor is connected to one end of the third resistor and serves as the output end of the first trigger unit, and the other end of the third resistor is connected to the cathode of the thyristor rectifier.

[0017] In one embodiment, the second trigger unit includes an NMOS transistor, the gate of the NMOS transistor serves as an input end and is connected to the output end of the first trigger unit, the source of the NMOS transistor is connected to one end of the second resistor, the collector of the first transistor and the base of the second transistor, and the drain of the NMOS transistor is connected to one end of the first resistor, the base of the first transistor and the collector of the second transistor.

[0018] According to another aspect of the present invention, a chip is provided, comprising a protected circuit and the electrostatic protection circuit as described above.

[0019] The above technical solution of the present invention has the following beneficial technical effects:

[0020] In order to solve the problem that the existing electrostatic protection circuit uses an acceleration module to speed up the triggering speed, resulting in a large size of the electrostatic protection circuit, the present invention does not require acceleration and directly triggers the second trigger unit to discharge and turn on by outputting a high level through the first trigger unit, thereby turning on the electrostatic discharge path to discharge the electrostatic current. It can not only provide electrostatic protection for the protected chip, but also has the advantages of simple structure, small size and fast triggering speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a structural diagram of an ESD electrostatic protection circuit in the prior art;

[0022] Figure 2 is a structural block diagram of an electrostatic protection circuit according to an embodiment of the present invention;

[0023] Figure 3 is an equivalent circuit diagram of an electrostatic protection circuit according to an embodiment of the present invention;

[0024] Figure 4 1 is a schematic structural diagram of an electrostatic protection circuit according to an embodiment of the present invention;

[0025] Figure 5 yes Figure 3 Schematic diagram of the equivalent circuit of the electrostatic discharge trigger path.

[0026] Reference numerals:

[0027] 003, trigger module; 005, three-stage inverter module; 006, MOS feedback module; 007, enhancement trigger module; 100, thyristor rectifier; 110, substrate; 111, third P+ junction; 120, first N-well; 130, P-well; 131, first P+ junction; 132, first N+ junction; 140, second N-well; 141, second P+ junction; 142, second N+ junction; 150, deep N-well; 200, first trigger unit; 300, second trigger unit. DETAILED DESCRIPTION

[0028] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0030] It will be understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor without departing from the scope of this application. The first resistor and the second resistor are both resistors, but they are not the same resistor.

[0031] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if there is transmission of electrical signals or data between the connected circuits, modules, units, etc.

[0032] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Furthermore, the term "and / or" as used in this specification includes any and all combinations of the relevant listed items.

[0033] See also Figure 1 , Figure 1This is a schematic diagram of the structure of an ESD electrostatic protection circuit in the prior art. An ESD electrostatic protection circuit includes a trigger module and a discharge module. The trigger module 003 includes a three-stage inverter module 005, a PMOS feedback module 006, a feedback enhancement trigger module 007, a resistor R, and an NMOS transistor capacitor Mc. Because the gate voltage of the NMOS transistor MESD cannot change suddenly, an inverter must be provided at the input of the NMOS transistor MESD to discharge the NMOS transistor MESD. This results in a slow turn-on speed of the discharge tube NMOS transistor MESD. Therefore, the PMOS feedback module 006 and the feedback enhancement trigger module 007 are required to speed up the turn-on of the NMOS transistor MESD, thereby increasing the trigger speed of the electrostatic protection circuit. However, this results in an increase in the size and specifications of the electrostatic protection circuit, which not only increases the cost but also does not meet the requirements for use in integrated circuits using current advanced processes.

[0034] See also Figure 2 , Figure 2 : It is a structural schematic diagram of the electrostatic protection device of an embodiment of the present invention. An electrostatic protection circuit includes a thyristor rectifier 100, a first trigger unit 200 and a second trigger unit 300. The thyristor rectifier 100 has an anode, a cathode and an electrostatic discharge path. The first trigger unit 200 is connected between the anode and the cathode of the thyristor rectifier 100, and is used to generate a high level when static electricity occurs in the protected chip (not shown in the figure). The second trigger unit 300 is connected to the electrostatic discharge path, and the input end of the second trigger unit 300 is connected to the output end of the first trigger unit 200, and is used to turn on the electrostatic discharge path based on the high level to discharge electrostatic current.

[0035] Specifically, the protected chip can be a logic chip, an analog chip, or a memory chip, etc. When the protected chip is a memory chip, it can be a DRAM chip. The thyristor rectifier 100 is located inside the protected chip and is connected to the protected circuit inside the protected chip. The electrostatic protection circuit of this embodiment introduces a first trigger unit 200 and a second trigger unit 300. It does not require acceleration and directly triggers the second trigger unit 300 to discharge and turn on by outputting a high level through the first trigger unit 200, thereby triggering the electrostatic discharge path to turn on and discharge the electrostatic current. It can not only provide electrostatic protection for the protected chip, but also has the advantages of simple structure, small size, and fast triggering speed.

[0036] In one embodiment, see Figure 3 The electrostatic discharge path includes a first transistor Q1, a second transistor Q2, a first resistor R NW and the second resistor R PWIn this embodiment, the emitter of the first transistor Q1 is the anode of the silicon controlled rectifier 100, and the base of the first transistor Q1 is connected to the first resistor R NW One end of the first transistor Q1 is connected to the collector of the second resistor R PW One end of the second transistor Q2 is connected to the base of the second resistor R PW The other end is connected to the first resistor R NW The other end is connected, and the emitter of the second transistor Q2 serves as the cathode of the thyristor rectifier 100.

[0037] Specifically, the first transistor Q1 is a PNP transistor, and the second transistor Q2 is an NPN transistor.

[0038] In this embodiment, one end of the second trigger unit 300 is connected to the second resistor R PW The first transistor Q1 and the base of the second transistor Q2 are connected, and the other end of the second trigger unit 300 is connected to the first resistor R NW When static electricity occurs in the protected circuit, the anode of the thyristor rectifier outputs a positive pulse, which turns on the first resistor R NW , and outputs a high level to the second trigger unit 300 through the first trigger unit 200, the second trigger unit 300 discharges and turns on, turning on the second resistor R PW , and increases the base voltage of the second transistor Q2, thereby enabling the electrostatic discharge path to discharge the electrostatic current. In addition, the second trigger unit 300 is connected between the first transistor Q1 and the second transistor Q2, which can extend the trigger path, thereby enhancing the holding voltage and avoiding the occurrence of flicker.

[0039] In one embodiment, the thyristor rectifier 100 further has an electrostatic discharge trigger path, which includes a first diode D1 and a second diode D2, wherein the cathode of the first diode D1 is connected to the cathode of the thyristor rectifier 100, the anode of the first diode D1 is connected to the cathode of the second diode D2, and the anode of the second diode D2 is connected to the anode of the thyristor rectifier 100.

[0040] In this embodiment, because the electrostatic discharge trigger path can be equivalent to a diode string, and the second trigger unit 300 is also connected in series in the electrostatic discharge trigger path, when static electricity occurs, since the conduction voltage required for the diode string to be turned on first is relatively low, the second trigger unit 300 triggers the electrostatic discharge trigger path to be turned on first, and then triggers the electrostatic discharge path to be turned on, and then a large current quickly passes through the electrostatic discharge path, so that static electricity can be released at a smaller trigger voltage.

[0041] In one embodiment, the silicon controlled rectifier 100 includes:

[0042] A substrate 110 is formed in which a first N-well 120, a P-well 130 and a second N-well 140 are formed. A first P+ junction 131 and a first N+ junction 132 are formed in the P-well 130. A second P+ junction 141 and a second N+ junction 142 are formed in the second N-well 140. A third P+ junction 111 is also formed in the substrate 110. The first N+ junction 132 is connected to the cathode and forms the cathode of the thyristor 100. The second P+ junction 141 is connected to the anode and forms the anode of the thyristor 100.

[0043] The second P+ junction 141 , the second N-well 140 , and the P-well 130 are equivalent to the first transistor Q1 , and the first N+ junction 132 , the P-well 130 , and the second N-well 140 are equivalent to the second transistor Q2 .

[0044] The first P+ junction 131 and the first N+ junction 132 are equivalent to the first diode D1 , and the second P+ junction 141 and the second N+ junction 142 are equivalent to the second diode D2 .

[0045] In other embodiments, the thyristor rectifier 100 may also be other semiconductor devices known to those skilled in the art that can achieve the above functions.

[0046] In one embodiment, a deep N-well 150 is further formed in the substrate 110. The deep N-well 150 is disposed on the lower surface of the P-well 130 and on the lower surfaces of the first N-well 120 and the second N-well 140. The deep N-well 150 is used to isolate the P-well 130 from the substrate 110, thereby reducing substrate coupling noise.

[0047] In one embodiment, the first trigger unit 200 includes a third resistor R and a capacitor C, one end of the capacitor C is connected to the anode of the thyristor rectifier 100, the other end of the capacitor C is connected to one end of the third resistor R and serves as the output end of the first trigger unit 200, and the other end of the third resistor R is connected to the cathode of the thyristor rectifier 100.

[0048] In this embodiment, since one end of the capacitor C is connected to the anode of the thyristor rectifier 100, the other end of the capacitor C is connected to one end of the third resistor R and serves as the output end of the first trigger unit 200, and the other end of the third resistor R is connected to the cathode of the thyristor rectifier 100, when static electricity occurs in the protected chip, a positive pulse passes through the capacitor C, so that the output end of the first trigger unit 200 is at a high potential, that is, the input end of the second trigger unit 300 can be at a high potential, and the second trigger unit 300 can be directly discharged and turned on. Therefore, it is possible to save an inverter and there is no need for an acceleration module to increase the conduction speed of the second trigger unit 300. While ensuring the electrostatic protection performance, the size of the electrostatic protection circuit can be greatly reduced.

[0049] In one embodiment, the second trigger unit 300 includes an NMOS transistor Mn.

[0050] In this embodiment, the gate of the NMOS transistor Mn serves as an input terminal and is connected to the output terminal of the first trigger unit 200, and the source of the NMOS transistor Mn is connected to the second resistor R PW The collector of the first transistor Q1 and the base of the second transistor Q2 are connected, and the drain of the NMOS tube Mn is connected to the first resistor R NW The first transistor Q1 and the second transistor Q2 are connected to one end of the capacitor C. When static electricity is generated in the protected chip, a positive pulse passes through the capacitor C. Since the output end of the first trigger unit 200 is at a high potential, that is, the gate of the NMOS transistor Mn is at a high potential, the NMOS transistor Mn discharges and sequentially turns on the first transistor Q1 and the second transistor Q2, thereby enabling the electrostatic discharge path to discharge the electrostatic current.

[0051] The present application also provides a chip comprising a protected circuit and the electrostatic protection circuit described above. The electrostatic protection circuit is capable of dissipating static current when static electricity is generated in the chip, thereby protecting the protected circuit from damage. Furthermore, the electrostatic protection circuit has a simple structure, a small size, and a fast triggering speed, meeting the requirements for use in current advanced integrated circuit manufacturing processes.

[0052] Specifically, the electrostatic protection circuit is connected between the power supply terminal and the ground terminal of the protected circuit, between the power supply terminal and the signal transmission terminal, and between the ground terminal and the signal transmission terminal; the electrostatic protection circuit can be specifically connected between the power supply terminal and the input terminal, between the input terminal and the ground terminal, between the power supply terminal and the output terminal, between the output terminal and the ground terminal, and between the power supply terminal and the ground terminal. In addition, the anode and cathode of the electrostatic protection circuit can be reversed to discharge reverse electrostatic current, which can be set according to actual needs. In this embodiment, reverse connection is relative to positive connection. For example, when the positive connection is that the anode of the electrostatic protection circuit is connected to the power supply terminal of the protected circuit and the cathode of the electrostatic protection circuit is connected to the ground terminal of the protected circuit, the reverse connection is that the anode of the electrostatic protection circuit is connected to the ground terminal of the protected circuit and the cathode of the electrostatic protection circuit is connected to the power supply terminal of the protected circuit.

[0053] In one embodiment, the chip may include a logic chip, an analog signal chip, a memory chip, or the like.

[0054] In one embodiment, the chip may include a DRAM chip.

[0055] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Although these terms are used interchangeably throughout this specification, they do not necessarily refer to the same embodiment or example.

[0056] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0057] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. An electrostatic protection circuit, characterized in that: include: A silicon controlled rectifier having an anode, a cathode and an electrostatic discharge path; A first trigger unit is connected between the anode and cathode of the silicon controlled rectifier and is used to generate a high level when static electricity occurs in the protected chip; a second trigger unit, connected to the electrostatic discharge path, and an input end of the second trigger unit is connected to an output end of the first trigger unit, for turning on the electrostatic discharge path based on the high level to discharge electrostatic current; The electrostatic discharge path includes a first transistor, a second transistor, a first resistor and a second resistor, the emitter of the first transistor is the anode of the thyristor rectifier, the base of the first transistor is connected to one end of the first resistor and the collector of the second transistor, the collector of the first transistor is connected to one end of the second resistor and the base of the second transistor, the other end of the second resistor is connected to the other end of the first resistor, and the emitter of the second transistor serves as the cathode of the thyristor rectifier.

2. The electrostatic protection circuit according to claim 1, wherein: The first transistor is a PNP transistor, and the second transistor is an NPN transistor.

3. The electrostatic protection circuit according to claim 1, wherein: The thyristor rectifier also has an electrostatic discharge trigger path, which includes a first diode and a second diode, the cathode of the first diode is connected to the cathode of the thyristor rectifier, the anode of the first diode is connected to the cathode of the second diode, and the anode of the second diode is connected to the anode of the thyristor rectifier.

4. The electrostatic protection circuit according to claim 3, characterized in that: The silicon controlled rectifier comprises: a substrate, wherein a first N-well, a P-well, and a second N-well are formed in the substrate, a first P+ junction and a first N+ junction are formed in the P-well, a second P+ junction and a second N+ junction are formed in the second N-well, and a third P+ junction is further formed in the substrate, the first N+ junction is connected to a cathode and forms a cathode of the thyristor, and the second P+ junction is connected to an anode and forms an anode of the thyristor; The second P+ junction, the second N-well and the P-well are equivalent to the first triode, and the first N+ junction, the P-well and the second N-well are equivalent to the second triode; The first P+ junction and the first N+ junction are equivalent to the first diode, and the second P+ junction and the second N+ junction are equivalent to the second diode.

5. The electrostatic protection circuit according to claim 4, characterized in that: A deep N-well is also formed in the substrate. The deep N-well is arranged on the lower surface of the P-well and on the lower surfaces of parts of the first N-well and the second N-well.

6. The electrostatic protection circuit according to claim 2, wherein: The first trigger unit includes a third resistor and a capacitor, one end of the capacitor is connected to the anode of the thyristor rectifier, the other end of the capacitor is connected to one end of the third resistor and serves as the output end of the first trigger unit, and the other end of the third resistor is connected to the cathode of the thyristor rectifier.

7. The electrostatic protection circuit according to claim 6, wherein: The second trigger unit includes an NMOS transistor, the gate of the NMOS transistor serves as an input end and is connected to the output end of the first trigger unit, the source of the NMOS transistor is connected to one end of the second resistor, the collector of the first transistor and the base of the second transistor, and the drain of the NMOS transistor is connected to one end of the first resistor, the base of the first transistor and the collector of the second transistor.

8. A chip, characterized in that: The invention comprises a protected circuit and an electrostatic protection circuit as claimed in any one of claims 1 to 7.

Images