A pulse width modulation circuit, a quantization circuit, a memory computing circuit, and a chip.

Abstract

This invention belongs to the field of integrated circuit technology, specifically relating to a pulse width modulation circuit, a quantization circuit, a memory-based computing circuit with multiply-accumulate-add operation functions, and the corresponding memory-based computing chip and its applications. The memory-based computing circuit includes a memory array, redundant columns, redundant rows, bit line groups, word line groups, an input circuit, a word line pulse width modulation array, a quantization circuit array, a timing control circuit, a precharge circuit, a word line driving module, a row decoding module, a read / write control circuit, and an output circuit. The word line pulse width modulation circuit includes two inverters IN1 and IN2, an AND gate, two NMOS transistors NM1 and NM2, and a PMOS transistor PM. The quantization circuit includes three switches M1, M2, and M3, two capacitors C1 and C2, and a sensitive amplifier SA. This invention solves the problem that existing in-memory computing technologies have poor processing efficiency for multiply-accumulate-add operations and cannot effectively handle convolutional neural network tasks.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to a pulse width modulation circuit, a quantization circuit, a memory-based computing circuit with multiplication, accumulation, and addition functions using the pulse width modulation circuit and the quantization circuit, as well as the corresponding memory-based computing chip, its quantization method, and its application. Background Technology

[0002] With the rapid development of artificial intelligence, application areas such as machine learning and edge computing have seen rapid growth, placing higher demands on data processing speed. Traditional computers employ the von Neumann architecture, in which the processor is the unit that performs computations, while data is stored in memory; the processor and memory are separate, each performing computational and data storage tasks respectively. Therefore, when the processor performs computation, it reads data from memory, and then writes the data back to memory after processing it.

[0003] Guided by Moore's Law, processor performance has advanced rapidly. However, advancements in memory read / write performance have lagged behind processor performance, leading to a mismatch between memory speed and processor capability. When memory access speeds significantly lag behind processor processing speeds, memory performance becomes a major bottleneck restricting overall computer performance. This bottleneck is particularly pronounced in data processing fields requiring massive computation, such as machine learning and image recognition, especially in algorithms like Convolutional Neural Networks (CNNs). To overcome this bottleneck caused by the mismatch between data read / write and processing performance in traditional von Neumann architecture computers, researchers have proposed the concept of in-memory computation—implementing logical operations within memory. Because Static Random-Access Memory (SRAM) offers fast data access and good compatibility with advanced logic technologies, SRAM-based in-memory computation technology has attracted considerable attention from scholars both domestically and internationally.

[0004] Embedding computation in memory offers two significant advantages. First, since filter weights are not explicitly read, and only the computational output needs to be sent out of memory, in-memory computation greatly reduces the number of times data is passed into and out of memory. Second, considering that the data processing is only interested in the computation results using in-memory data rather than individual storage bits, the massively parallel nature of CNN algorithms can be leveraged to access multiple memory addresses simultaneously. For these reasons, this new computational technique can achieve higher memory bandwidth, overcoming some of the major limitations imposed by the traditional "von Neumann bottleneck."

[0005] Most machine learning algorithms, such as CNNs, require a large number of multiply-accumulate operations; multiply-accumulate operations are the summation and output of the results of multiple multiplication operations. Existing in-memory computing technologies can perform multiplication, addition, Boolean logic operations, and other complex logic operations on the storage cells inside SRAM. However, the processing performance for multiply-accumulate operations is not good. For example, in current technologies, the results of multiply-accumulate operations mostly need to be obtained by quantizing the bit line discharge through an ADC (Analog-to-Digital Converter). Among the various widely used SRAM in-memory computing quantization technologies, whether Flash ADCs, successive approximation ADCs, or digital circuit-assisted ADCs, they all directly quantize the bit line operation results. In order to achieve more accurate quantization output, these quantization circuits require very complex circuit structures and use large-scale sensitive amplifiers and other electronic components, which significantly increases the power consumption and area per unit of the in-memory computing chip. Summary of the Invention

[0006] To address the shortcomings of existing in-memory computing technologies in handling multiplication-accumulation-addition operations, and the lack of in-memory computing chips specifically designed for computational tasks such as convolutional neural networks, this invention provides a pulse width modulation circuit, a quantization circuit, an in-memory computing circuit employing the pulse width modulation circuit and the quantization circuit with multiplication-accumulation-addition operation capabilities, as well as the corresponding in-memory computing chip, its quantization method, and its applications.

[0007] This invention is achieved using the following technical solution:

[0008] The present invention provides a word line pulse width modulation circuit, which generates a corresponding word line signal WL based on the input signal IN, and controls the pulse width of the word line signal WL.

[0009] The word line pulse width modulation (PWM) circuit includes two inverters IN1 and IN2, an AND gate, two NMOS transistors NM1 and NM2, and one PMOS transistor PM. The circuit connection is as follows: Inverters IN1 and IN2 are connected in series. The input of IN1 is connected to the bit line signal DBL. The output of IN2 is connected to one input of the AND gate, and the other input of the AND gate is connected to the precharge signal PRE_A. The gate of NM1 is connected to the output of the AND gate. The drains of NM1 and PM are connected, serving as the overall input (IN) of the PWM circuit. The sources of NM1 and PM are connected and connected to the drain of NM2, serving as the overall output (WL) of the PWM circuit. The gate of PM is connected to the gate of NM2 and receives the inverted signal from the gate of NM1; the source of NM2 is grounded.

[0010] The present invention also includes a quantization circuit, which is used to output the sum of the product results of several memory cells connected on the same set of bit lines BL and BLB in digital form.

[0011] The quantization circuit includes three switches M1, M2, and M3, two capacitors C1 and C2, and a sensitive amplifier SA. The circuit connections are as follows: one end of capacitors C1 and C2 is connected to VSS, and the other end is connected to the two input terminals of the sensitive amplifier SA, respectively. One end of switch M1 is connected to the bit line BL, and the other end is connected to the node where C1 and SA meet. One end of switch M2 is connected to the bit line BLB, and the other end is connected to the node where C2 and SA meet. The two ends of switch M3 are connected to the bit lines BL and BLB, respectively.

[0012] Among them, the on / off states of switches M2 and M3 are synchronized; the on / off states of switch M1 are opposite to those of M2 and M3.

[0013] As a further improvement of this invention, the capacitance of capacitor C2 is twice the capacitance of capacitor C1. Capacitors C1 and C2 serve as the capacitors for caching the analog quantity Vsum of the calculation result and the reference voltage Vrefi, respectively. Since the reference voltage Vrefi needs to decrease sequentially from large to small during the quantization stage, to obtain an accurate Vrefi that can be compared with Vsum, switches M2 and M3 of the quantization circuit must be closed. The principle is: closing M2 connects bit lines BL and BLB together. Even if the stored data Q and QB are unknown, as long as the word line of the current row is open, BL or BLB will discharge, so the voltage on C2 is known. Furthermore, because BL and BLB are connected together at this time, the parasitic capacitance they carry is twice that of a single bit line. Since in addition to the parasitic capacitance of the bit line itself, an additional capacitor C1 is added to BL. Similarly, to ensure comparability, C2 is an additional capacitor added when BL and BLB are connected together; therefore, C2 = 2C1 must be ensured.

[0014] The present invention also includes a memory circuit with multiplication, accumulation and addition functions, the memory circuit comprising: a memory array, redundant columns, redundant rows, bit line groups, word line groups, an input circuit, a word line pulse width modulation array (PWGC), a quantization circuit array, a timing control circuit, a precharge circuit, a word line driving module, a row decoding module, a read / write control circuit, and an output circuit.

[0015] The storage array comprises N 2 An N×N array consisting of identical storage units; each storage unit contains two inverted storage nodes Q and QB, and each storage unit is used to store data or perform multiplication operations.

[0016] A redundant column consists of N identical storage cells arranged in columns on one side of the storage array. Within each storage cell of a redundant column, identical storage nodes store the same data.

[0017] A redundant row consists of at least one and at most n storage cells arranged in rows on one side of the storage array. Each storage cell in the redundant row shares a bit line with all storage cells in the corresponding column of the storage array; and the data stored in the same storage node within each storage cell of the redundant row is the same.

[0018] The bit line group includes N+1 pairs of bit lines, namely N sets of bit lines BL and BLB corresponding to each memory cell in the memory array, and 1 set of bit lines DBL and DBLB corresponding to the redundant columns.

[0019] The word line group consists of 2N+1 word lines, namely: the word line DCWL corresponding to each row of the storage cells in the redundant column, the word line WL corresponding to each row of the storage cells in the storage cell, and the word line DWL corresponding to the redundant row.

[0020] The input circuit is used to generate 2N+1 independent input signals IN when performing logical operations; each input signal is used to control one of the word lines in the word line group.

[0021] The word line pulse width modulation array includes 2N+1 word line pulse width modulation circuits as described above. Each word line pulse width modulation circuit generates a corresponding word line signal WL based on a received input signal IN during logical operations, thereby controlling the on and off of each word line in the word line group.

[0022] The quantization circuit array includes several quantization circuits that correspond one-to-one with each memory cell in the redundant row. The circuit structure of each quantization circuit is as described above. The quantization circuits are connected to the bit lines and are used to output the sum of the multiplication results of each memory cell in the corresponding column.

[0023] The timing control circuit generates the clock signals required by each functional module, thereby enabling the circuit functions to be implemented accurately and orderly. The precharge circuit performs precharge operations on the bit lines BL and BLB connected to each column of memory cells in the memory array, as well as the bit lines DBL and DBLB connected to redundant columns.

[0024] The word line driver module controls the on / off state of the word lines (WL) connecting each memory cell in the memory array during data read / write operations. The row decoding module controls the word line driver module based on the decoding results during data read / write operations. The read / write control circuit controls the data read / write operations of each memory cell in the memory array.

[0025] The output circuit is used to output the digital value of the sum of the multiplication results of each column of storage cells quantized by the quantization circuit.

[0026] As a further improvement of the present invention, the storage array and the redundant rows use the exact same storage cells. In the redundant rows, storage node Q, which is close to and connected to bit line BL, pre-stores data 0, and storage node QB, which is close to and connected to bit line BLB, pre-stores data 1. In the redundant columns, storage node Q, which is close to and connected to bit line DBL, pre-stores data 0, and storage node QB, which is close to and connected to bit line DBLB, pre-stores data 1.

[0027] The in-memory circuit with multiplication, accumulation, and addition operations provided by this invention has both data storage and logical operation functions. Each storage unit in the storage array serves as a basic unit for performing read and write operations when implementing the data storage function.

[0028] In a memory array, any column, the corresponding redundant row's memory cells, the corresponding quantization circuit, the redundant column, and the pulse width modulation array together constitute the basic unit for performing product and accumulation operations. During product and accumulation logic operations, each memory cell performs an independent product operation, and the result of that product operation serves as the operand for the product-accumulation operation. In the memory-based computing circuit, the maximum number of operands for product-accumulation is equal to the number of rows in the memory array.

[0029] As a further improvement of the present invention, among the 2N+1 input signals input to the input circuit, by adjusting the N input signals corresponding to the word line DCWL in the redundant column, in conjunction with the word line pulse width modulation array, the discharge speed of the redundant column bit line DBL can also be controlled, thereby realizing the adjustment of the pulse width of all 2N+1 word line signals.

[0030] This invention also includes a quantization method applied to the aforementioned in-memory circuit with multiplication-accumulation operation function. This quantization method is used to generate the quantized result of the multiplication-accumulation operation according to a preset operation logic. The operation logic of the quantization method is divided into two stages: an operation stage and a quantization stage. In the operation stage, each memory cell in the same column of the memory array performs a multiplication operation, and the product of each memory cell is "accumulated" on the bit line and cached in capacitor C1. In the quantization stage, the voltage value cached in capacitor C1 is "read out" using the quantization circuit and capacitor C2, and the analog voltage is converted into a digital value corresponding to the number of memory cells whose product is 1.

[0031] The detailed operational logic for the two stages is as follows:

[0032] I. Calculation Stage:

[0033] (1) Precharge all bit line voltages of BL and BLB to VDD, and then in the first cycle, control any selected column in the memory array to perform multiplication and accumulation operations and cache the results on capacitor C1.

[0034] During the operation, if the multiplication result of k memory cells in the current column is 1, k≤N, then the bit line discharge is k·Δv, and the bit line voltage is VDD-k·Δv. The bit line voltage at this time is the analog quantity Vsum of the result of the multiplication and accumulation operation.

[0035] II. Quantification Phase:

[0036] (1) Based on the number of rows N in the storage array, the maximum discharge amount of the bit line is N·Δv; the maximum discharge amount N·Δv is divided into M levels.

[0037] Assume the threshold values ​​for each gear are as follows: Where i represents the gear position number, i = 1, 2, ..., M-1, M.

[0038] (2) Starting from the second cycle, different input signals IN are input in each cycle, and then different reference voltages Vref are generated on capacitor C2 in descending order. i :

[0039]

[0040] (3) The reference voltage Vref i The result is buffered on capacitor C2 and compared with the analog quantity Vsum of the calculation result; observe the output of the sensitive amplifier SA in the quantization circuit, and record the gear number p corresponding to the first flip of the SA output, thereby determining the lower limit of the analog quantity Vsum of the calculation result.

[0041] (4) Enable redundant lines in subsequent cycles and make the analog quantity Vsum of the calculation result decrease by Δv every cycle. Record the number of discharge quantity decreases q when the output of the sensitive amplifier SA flips for the second time.

[0042] (5) Based on the two flips, the analog quantity Vsum of the result of the multiplication and accumulation operation is determined as:

[0043]

[0044] Therefore, the output multiplicative quantized digital value is:

[0045] The present invention also includes an in-memory computing chip, which is an integrated circuit packaged from the aforementioned in-memory computing circuit with multiplication, accumulation and addition functions.

[0046] An application of a memory computing chip, wherein the aforementioned memory computing chip is applied to the processing task of a convolutional neural network, the memory computing chip serving as a storage chip for performing data storage and as a logic operation chip for performing multiplication-accumulation-addition operations.

[0047] The technical solution provided by this invention has the following beneficial effects:

[0048] This invention adds redundant rows and columns, as well as a word line pulse width modulation array to control existing and newly added memory cells, to the existing memory circuit, and combines this with a newly designed quantization circuit to obtain a novel in-memory computing circuit. This in-memory computing circuit not only has data storage and data read / write functions, but can also efficiently complete multiply-accumulate logical operations. When performing multiply-accumulate operations, this circuit can achieve multiply-accumulate operations with a maximum number of operands equal to the number of rows in the memory array, and can also perform multi-task synchronous operations with a maximum number of columns in the memory array.

[0049] This invention incorporates a novel word line pulse width modulation array designed during the circuit design process. This circuit not only enables precise control of word line signals in the memory array, redundant rows, and redundant columns, but also allows for dynamic adjustment of the pulse width of the word line signals on each word line as needed. This adapts to the varying requirements of word line pulse width in different task processing cycles, thereby making the multiplication and accumulation operations of the circuit more accurate.

[0050] This invention also presents a completely new design for the quantization circuit in the in-memory computing circuit. Compared with traditional Flash ADCs, successive approximation ADCs, and digital circuit-assisted ADCs, the newly designed quantization circuit has a simpler structure and uses a significantly reduced number of circuit components, thus greatly reducing the power consumption of the quantization process.

[0051] This invention also constructs a novel quantization processing method for the newly designed quantization circuit. This method adopts a segmented processing approach, which can shorten the number of cycles required for the quantization stage and improve the operation speed when processing multiplication and accumulation tasks with large-scale operation results. At the same time, the new quantization method can also effectively reduce the quantization result errors caused by inconsistencies such as bit line discharge nonlinearity and pulse distortion, thereby improving the accuracy of circuit operation results. Attached Figure Description

[0052] Figure 1 This is a circuit diagram of the storage circuit with multiplication, accumulation, and addition functions provided in Embodiment 1 of the present invention.

[0053] Figure 2 for Figure 1The in-memory computing circuit includes a simplified circuit diagram of components such as a storage array, redundant rows, redundant columns, and quantization circuits.

[0054] Figure 3 for Figure 2 A partial partition diagram of the circuit section related to data storage function in a simplified circuit.

[0055] Figure 4 for Figure 2 A partial partition diagram of the circuit section related to the multiplication, accumulation, and addition operations in a simplified circuit.

[0056] Figure 5 This is a circuit connection diagram for the word line pulse width modulation array used in memory computing circuits.

[0057] Figure 6 for Figure 5 The circuit diagram of each word line pulse width modulation circuit in the word line pulse width modulation array.

[0058] Figure 7 This is a circuit connection diagram of the quantization circuit used in the memory computing circuit.

[0059] Figure 8 The circuit schematic for performing a product operation on a 6T SRAM memory cell.

[0060] Figure 9 This is a schematic diagram of the circuit state of the in-memory computing circuit when performing multiplication-accumulation-addition operations.

[0061] Figure 10 This is a waveform diagram of each signal when the in-memory computing circuit performs multiplication-accumulation operations.

[0062] Figure 11 This is a schematic diagram of the circuit state corresponding to the gradation quantization step in the quantization stage of the memory computing circuit.

[0063] Figure 12 This is a waveform diagram of each signal corresponding to the gradation quantization step in the quantization stage of the memory computing circuit.

[0064] Figure 13 This is a waveform diagram of each signal corresponding to the fine quantization step in the quantization stage of the memory computing circuit. Detailed Implementation

[0065] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0066] Example 1

[0067] This embodiment provides a storage circuit with multiplication, accumulation, and addition operations, such as... Figure 1 As shown, the memory computing circuit includes: a memory array, redundant columns, redundant rows, bit line groups, word line groups, input circuits, word line pulse width modulation array (PWGC), quantization circuit array, timing control circuit, precharge circuit, word line driver module, row decoding module, read / write control circuit, and output circuit.

[0068] This in-memory computing circuit is an improvement and design based on traditional memory circuits that only have data storage and read / write functions. Among the modules of the different functional circuits included in the in-memory computing circuit, the word lines that control the memory array in the bit line group, the bit line pairs that connect to the memory array, the timing control circuit, the precharge circuit, the word line driver module, the row decoding module, the read / write control circuit, and the output circuit are all original functional circuits in existing memory circuits.

[0069] The other signal lines included in the bit line group and word line group of the memory circuit, the redundant columns, redundant rows, input circuits, word line pulse width modulation array (PWGC), and quantization circuit array are all additional circuits designed in this embodiment to enable conventional memory circuits to have high-performance multiply-accumulate-add operation functions.

[0070] The storage array comprises N 2 An N×N array consisting of identical storage units; each storage unit contains two inverted storage nodes Q and QB, and each storage unit is used to store data or perform multiplication operations.

[0071] A redundant column consists of N identical storage cells arranged in columns on one side of the storage array. Within each storage cell of a redundant column, identical storage nodes store the same data.

[0072] A redundant row consists of at least one and at most n storage cells arranged in rows on one side of the storage array. Each storage cell in the redundant row shares a bit line with all storage cells in the corresponding column of the storage array; and the data stored in the same storage node within each storage cell of the redundant row is the same.

[0073] The bit line group includes N+1 pairs of bit lines, namely N sets of bit lines BL and BLB corresponding to each memory cell in the memory array, and 1 set of bit lines DBL and DBLB corresponding to the redundant columns.

[0074] The word line group consists of 2N+1 word lines, namely: the word line DCWL corresponding to each row of the storage cells in the redundant column, the word line WL corresponding to each row of the storage cells in the storage cell, and the word line DWL corresponding to the redundant row.

[0075] The input circuit is used to generate 2N+1 independent input signals IN when performing logical operations; each input signal is used to control one of the word lines in the word line group.

[0076] The word line pulse width modulation array includes 2N+1 word line pulse width modulation circuits as described above. Each word line pulse width modulation circuit generates a corresponding word line signal WL based on a received input signal IN during logical operations, thereby controlling the on and off of each word line in the word line group.

[0077] The quantization circuit array includes several quantization circuits that correspond one-to-one with each memory cell in the redundant row. The circuit structure of each quantization circuit is as described above. The quantization circuits are connected to the bit lines and are used to output the sum of the multiplication results of each memory cell in the corresponding column.

[0078] The timing control circuit generates the clock signals required by each functional module, thereby enabling the circuit functions to be implemented accurately and orderly. The precharge circuit performs precharge operations on the bit lines BL and BLB connected to each column of memory cells in the memory array, as well as the bit lines DBL and DBLB connected to redundant columns.

[0079] The word line driver module controls the on / off state of the word lines (WL) connecting each memory cell in the memory array during data read / write operations. The row decoding module controls the word line driver module based on the decoding results during data read / write operations. The read / write control circuit controls the data read / write operations of each memory cell in the memory array.

[0080] The output circuit is used to output the digital value of the sum of the multiplication results of each column of storage cells quantized by the quantization circuit.

[0081] In the solution provided in this embodiment, the in-memory computing circuit has data storage and logical operation functions. For example... Figure 2 As shown, the storage array, with its redundant rows and columns, constitutes an SRAM array. Within the SRAM array, as... Figure 3 As shown, each storage unit in the storage array serves as the basic unit for performing read and write operations when implementing data storage functionality. When performing multiplication-accumulation-addition operations, as... Figure 4 As shown, any column in the storage array, the storage cells in the corresponding redundant row, the quantization circuit corresponding to the column, the redundant column, and the pulse width modulation array together constitute the basic unit for performing multiplication and accumulation operations.

[0082] When performing multiplication and accumulation operations, each memory cell performs an independent multiplication operation, and the result of that multiplication operation serves as the operand for the multiplication-accumulation operation. In in-memory computing circuits, the maximum number of operands for multiplication-accumulation is equal to the number of rows in the memory array. Considering that each column of memory cells within each pair of bit lines constitutes an independent "computation column," the number of columns in the memory array determines the number of multiplication-accumulation operations that the in-memory computing circuit can execute simultaneously.

[0083] In circuit design, the number of storage cells in a redundant column must correspond to the number of rows in the storage array, while this is not the case for redundant rows. This is because each computational column must correspond to a redundant storage cell in a redundant row to complete its task; therefore, the number of storage cells in a redundant row can be designed specifically for different needs. In circuit design and manufacturing, the minimum number of storage cells in a redundant row is one, meaning only one column in the storage array can be used as a computational column. The maximum number is N, meaning all columns in the storage array can be used as independent computational columns.

[0084] It should be noted that the actual circuitry of the storage cells in the SRAM array of this embodiment can adopt various existing storage cell schemes. For example, existing schemes containing different numbers of transistors, such as 6T, 8T, 10T, 14T, etc., can be used. Based on the circuit's operating principle, to improve circuit stability and calculation accuracy, the storage array and redundant rows should use identical storage cell schemes. Redundant columns can use the same storage cells as the storage array, or they can use different circuit schemes. Of course, the most preferred scheme is that all storage cells in the SRAM array use the same circuit design. For example, in the example images given in this embodiment, a 6T storage circuit containing 6 transistors is used as the basic storage cell in the SRAM array for illustration.

[0085] When the memory-based circuit performs multiplication-accumulation operations, all redundant columns and rows are stored as "1" (Q = 0, QB = 1). That is, in a redundant row, the memory node Q, which is close to and connected to bit line BL, stores data 0, and the memory node QB, which is close to and connected to bit line BLB, stores data 1. In a redundant column, the memory node Q, which is close to and connected to bit line DBL, stores data 0, and the memory node QB, which is close to and connected to bit line DBLB, stores data 1.

[0086] The word lines corresponding to redundant rows are all turned off during the calculation process; however, they are turned on as needed during the quantization phase of outputting the calculation results. The word lines of redundant columns are turned on throughout the calculation and quantization process. During logical operations, the calculation array is determined by write operations to write either "0" or "1". The multiplication operation performed on the array is the input multiplied by the weight, where the input is reflected in the word line voltage and pulse width. Before the calculation, the timing control module and the precharge module precharge the two bit lines BL and BLB to a high level VDD; after the word lines are turned on, if Q=0 and QB=1, the bit line BL discharges to the memory cell. The discharge time is determined by the redundant column and the control circuit, and the final bit line voltage after the calculation is stored on one of the capacitors in the two circuits.

[0087] After the multiplication, accumulation, and addition operations are completed, the analog quantity of the calculation result needs to be converted into a digital quantity and output through a quantization circuit. In this embodiment, the quantization circuit compares the calculation result with multiple known reference potentials to determine the final accurate value. The generation logic of the different reference potentials used for comparison during the quantization operation may affect the number of quantization operations, thus affecting the efficiency and accuracy of the quantization output. To address this issue, this embodiment also designs a new, efficient quantization method for the quantization circuit. This quantization method employs a step-by-step quantization approach. Specifically, the possible quantization results are first divided into several voltage levels. The voltage level value is compared with the calculated value, and the level that is smaller than and closest to the calculated value is obtained. This level voltage is stored on another capacitor in the quantization circuit. Next, using only the redundant row, the bit line continues to discharge based on the calculated value. Each discharge is equal to the discharge amount corresponding to one row of the previous two steps, i.e., ΔV, so that the voltage corresponding to the calculated value successively approaches the level voltage. After obtaining the approximate value, the final bit line voltage is converted into the digital output of the sensitive amplifier. The precise operation process of the quantization method will be described in more detail later.

[0088] The word line pulse width modulation array (PWGC) in the memory computing circuit provided in this embodiment functions to generate a corresponding word line signal based on each input signal IN<0:2N>, and to control the pulse width of the word line signal. Specifically, as shown... Figure 5 The word line pulse width modulation array is composed of a series of simple word line pulse width modulation circuits. Each word line pulse width modulation circuit in the array shares a single bit line DBL. Each word line pulse width modulation circuit is connected to 2N+1 independent input signals IN<0:2N>, numbered 0 to 2N, and generates 2N+1 independent word line signals. In this embodiment, IN<0:N-1> is the N input signals used to control N different word lines WL in the memory array; IN <n>It is an input signal used to control the word line DWL in redundant rows; IN<N+1:2N+1> These are the N input signals used to control the DCWL of N different word lines in the redundant column.

[0089] The word line pulse width modulation circuit designed in this embodiment is as follows: Figure 6 As shown, the circuit includes two inverters IN1 and IN2, an AND gate, two NMOS transistors NM1 and NM2, and one PMOS transistor PM. The circuit connection is as follows: Inverters IN1 and IN2 are connected in series. The input of IN1 is connected to the bit line signal DBL. The output of IN2 is connected to one input of the AND gate, and the other input of the AND gate is connected to the precharge signal PRE_A. The gate of NM1 is connected to the output of the AND gate. The drains of NM1 and PM are connected, serving as the overall input (IN) of the pulse width modulation (PWM) circuit. The sources of NM1 and PM are connected and connected to the drain of NM2, serving as the overall output (WL) of the PWM circuit. The gate of PM is connected to the gate of NM2 and to the inverted signal of the gate of NM1; the source of NM2 is grounded.

[0090] Figure 6 The working principle of the pulse width modulation circuit for the middle character line is as follows: First, DBL is precharged to VDD. After passing through inverters IN1 and IN2, the output of DBL is 1. After passing through an AND gate, the INOUT terminal is 1, turning on NM1 and PM, and transmitting external IN to WL. Since WL is turned on, all bit lines begin to discharge, and DBL also discharges. When DBL drops to the threshold voltage of the inverter, the output of DBL after passing through IN1 and IN2 is 0. After passing through the AND gate, INOUT is 0, turning off NM1 and PM, while turning on NM2. WL is then pulled low to VSS by the pull-down transistor.

[0091] The design in this embodiment is as follows Figure 5 In the word line pulse width modulation circuit shown, when the DBL terminal is connected to the corresponding bit line and the PRE_D terminal is connected to the precharge signal, a corresponding word line signal WL can be generated for each input signal IN. Furthermore, it should be particularly emphasized that the circuit provided in this embodiment consists of multiple... Figure 6 The word line pulse width modulation circuit in the middle is composed as follows Figure 5 The word line pulse width modulation array shown also has the function of modulating the pulse width of each word line.

[0092] During the multiplication-accumulation-addition operation and quantization of the result in the storage circuit, the pulse width when the word line is turned on has a significant impact on the accuracy of the final output calculation and quantization result. Since the final output of the quantization circuit is actually the quantized value after the bit line voltage discharges to the corresponding potential, and the discharge rate of the DBL is crucial in determining the time it takes for the word line to turn off, if the pulse width of the word line is too wide, the bit line may over-discharge, resulting in the output quantized value not being equal to the quantized value of the potential corresponding to the actual amount of discharge that should have been completed. Conversely, if the pulse width of the word line is too narrow, the bit line will not discharge sufficiently, and the resulting quantized value may also be inaccurate.

[0093] To address the aforementioned issues, this implementation designs a word line pulse width modulation circuit that adaptively adjusts the word line pulse width according to different input signals. This circuit can control not only the level of the word line signal but also adjust the pulse width of the word line. Specifically, among the 2N+1 input signals input to the input circuit, N input signals corresponding to the word line DCWL in the redundant control column are adjusted, specifically: IN<N+1:2N+1> Combined with the designed word line pulse width modulation array, it can control the discharge rate of redundant column bit lines (DBL), thereby achieving pulse width adjustment for all 2N+1 word line signals. The external input signal IN...<N+1:2N+1> The more word lines DCWL are enabled, the faster the bit line voltage DBL drops, and the narrower the pulse width of the generated word line signal.

[0094] Quantization circuits and quantization circuit arrays are another specially designed functional circuit in this case. The function of quantization circuits is to convert the analog quantities (bit line voltages) calculated in the various calculation columns of the memory circuit into corresponding digital quantities (natural numbers representing the product results).

[0095] In this embodiment, as Figure 7 As shown, the designed quantization circuit includes three switches M1, M2, and M3, two capacitors C1 and C2, and a sensitive amplifier SA. The circuit connections are as follows: one end of capacitors C1 and C2 is connected to VSS, and the other end is connected to the two input terminals of the sensitive amplifier SA, respectively. One end of switch M1 is connected to the bit line BL, and the other end is connected to the node where C1 and SA meet. One end of switch M2 is connected to the bit line BLB, and the other end is connected to the node where C2 and SA meet. The two ends of switch M3 are connected to the bit lines BL and BLB, respectively.

[0096] The quantization circuit works by buffering the analog result Vsum and the reference voltage Vrefi onto different capacitors, and then comparing the two values ​​using a sensitive amplifier. Switches M1 to M3 control the switching states of the two bit line voltages buffered onto their corresponding capacitors during different quantization stages. Specifically, switch M1 controls the switching state of the bit line voltage buffered onto capacitor C1; switches M2 and M3 control the switching state of the bit line voltage buffered onto capacitor C2. Considering that only one bit line voltage can be buffered onto one capacitor per cycle, in this embodiment, the on / off states of switches M2 and M3 are synchronized; the on / off states of switch M1 are inversely related to those of M2 and M3.

[0097] In this embodiment, the capacitance of capacitor C2 is twice the capacitance of capacitor C1. Capacitors C1 and C2 serve as the capacitors for caching the analog quantity Vsum of the calculation result and the reference voltage Vrefi, respectively. Since the reference voltage Vrefi needs to be decreased sequentially from large to small during the quantization stage, switches M2 and M3 of the quantization circuit must be closed to obtain an accurate Vrefi that can be compared with Vsum. The principle is that closing M2 connects bit lines BL and BLB together. Even if the stored data Q and QB are unknown, as long as the word line of the current row is turned on, BL or BLB will discharge, so the voltage on C2 is known. Since BL and BLB are connected together at this time, the parasitic capacitance they carry is twice that of a single bit line. In addition to the parasitic capacitance of the bit line itself, this circuit adds an extra capacitor C1 to BL. According to the formula Q = CV, to ensure comparability, C2 is the additional capacitor added after BL and BLB are connected together, so C2 = 2C1 must be ensured.

[0098] As mentioned earlier, the function of a quantization circuit is to convert analog quantities into digital quantities. This is achieved by using a known digital reference voltage Vref. i The analog quantity Vsum of the calculation result is compared with the digital quantity Vref. If they are the same, the known digital quantity of the reference voltage is considered to be the digital quantity of the calculation result. Therefore, in the circuit implementation process, how to reasonably select the reference voltage Vref is crucial. i This allows for the rapid identification of the matching value. It plays a crucial role in improving the efficiency of quantization circuits and shortening the processing cycle of in-memory computing circuits when handling each multiplication-accumulation logic operation.

[0099] To address this issue, this embodiment also designs a quantization method for the aforementioned in-memory circuit with multiplication-accumulation operation function. This quantization method is used to generate the quantized result of the multiplication-accumulation operation according to a preset operation logic. The operation logic of the quantization method is divided into two stages: an operation stage and a quantization stage. In the operation stage, each memory cell in the same column of the memory array performs a multiplication operation, "accumulating" the product of each memory cell on the bit line and buffering it in capacitor C1. In the quantization stage, the voltage value buffered in capacitor C1 is "read out" using the quantization circuit and capacitor C2, and the analog voltage is converted into a digital value corresponding to the number of memory cells whose product is 1.

[0100] The detailed operational logic for the two stages is as follows:

[0101] I. Calculation Stage:

[0102] (1) Precharge all bit line voltages of BL and BLB to VDD, and then in the first cycle, control any selected column in the memory array to perform multiplication and accumulation operations and cache the results on capacitor C1.

[0103] During the operation, if the multiplication result of k memory cells in the current column is 1, k≤N, then the bit line discharge is k·Δv, and the bit line voltage is VDD-k·Δv. The bit line voltage at this time is the analog quantity Vsum of the result of the multiplication and accumulation operation.

[0104] II. Quantification Phase:

[0105] (1) Based on the number of rows N in the storage array, the maximum discharge amount of the bit line is N·Δv; the maximum discharge amount N·Δv is divided into M levels.

[0106] Assume the threshold values ​​for each gear are as follows: Where i represents the gear position number, i = 1, 2, ..., M-1, M.

[0107] (2) Starting from the second cycle, different input signals IN are input in each cycle, and then different reference voltages Vref are generated on capacitor C2 in descending order. i :

[0108]

[0109] (3) The reference voltage Vref i The result is buffered on capacitor C2 and compared with the analog quantity Vsum of the calculation result; observe the output of the sensitive amplifier SA in the quantization circuit, and record the gear number p corresponding to the first flip of the SA output, thereby determining the lower limit of the analog quantity Vsum of the calculation result.

[0110] (4) Enable redundant lines in subsequent cycles and make the analog quantity Vsum of the calculation result decrease by Δv every cycle. Record the number of discharge quantity decreases q when the output of the sensitive amplifier SA flips for the second time.

[0111] (5) Based on the two flips, the analog quantity Vsum of the result of the multiplication and accumulation operation is determined as:

[0112]

[0113] Therefore, the output multiplicative quantized digital value is:

[0114] In the above operation, step (1) of the quantization stage adopts the idea of ​​average grading, which divides a possible calculation result into a finite number of "equal-width" gradations. Taking a computation column composed of a 64×64 storage array as an example, since there are 64 accumulated operands, the range of the accumulated result is 0 to 64, a total of 65 cases. For this result, assuming it is divided into 8 gradations, then 0-8 belongs to the first gradation, 9-16 belongs to the second gradation, and so on, with 57-64 belonging to the eighth gradation. In the quantization process, the minimum value of each gradation is first used as a reference potential and compared with the calculation result to find the result of the first flip. Then, within the corresponding gradation, the calculation result is gradually reduced to observe the second flip situation, and finally the matching reference potential and the corresponding quantization value are determined.

[0115] The advantages of the quantization method provided in this embodiment are evident in the following analysis: Assuming that traditional quantization schemes involve successive comparisons, while this method uses a two-round comparison with different operands, for a multiplication-accumulation operation with N = A × B operands, according to the "pigeonhole principle," the traditional scheme requires at most A × B operations to obtain an accurate quantized value; that is, the upper limit of the operation cycle is A × B. However, in this method, the result can be divided into A levels, each with a width of B, containing B different values. Therefore, according to the "pigeonhole principle," in this quantization method, the first stage requires at most A operations to determine the level, and the second stage requires at most B operations to determine the precise value. Thus, the upper limit of the operation cycle of this method is A + B. Considering that in integrated circuits, the number of operands is equal to the number of rows in the memory array, under reasonable level division, A × B will always be smaller than A + B. That is, probabilistically, this method can always output an accurate quantized value in fewer cycles.

[0116] It should be noted that the aforementioned division operation in this case is based on an idealized idea of ​​equal distribution. In practical applications, if the number of operands cannot be evenly divided into M divisions, the first M-1 divisions can be evenly divided, with the "width" of the last division being smaller than that of the first M-1 divisions. For example, in a scenario with 63 operands, the width of the first 7 divisions is designed to be 8, and the width of the last division is designed to be 7.

[0117] Of course, in other solutions, the "grading" concept of this implementation can be applied to distribute the width of different grades unevenly, with some grades being wider and others narrower. As long as this grading strategy is beneficial to shortening the quantization processing cycle, it is acceptable.

[0118] The optimal application scenario for uneven gradation strategies is typically when the results of computations are unevenly distributed, with the results more likely to concentrate within a certain interval. According to the Bernoulli distribution, the result of a multiplicative-accumulator operation is more likely to fall within the middle of the interval. For example, for an accumulation operation with 64 operands, the probability of the result being 32 is much higher than the probability of it being 0 or 64. Therefore, in gradation, the intervals closer to the sides can be wider because this result has a lower probability, while the intervals closer to the middle can be narrower because this result has a higher probability. This uneven gradation quantization strategy is, in fact, still a type of gradation quantization operation limited to this case.

[0119] Example 2

[0120] Based on Embodiment 1, this embodiment further provides a memory-based computing chip, which is an integrated circuit product obtained by packaging and testing the memory-based computing circuit with multiplication-accumulation operation function in Embodiment 1. This memory-based computing chip has both conventional data storage functions and strong logic operation functions. In particular, this memory-based computing chip has very efficient processing capabilities for handling large-scale multiplication-accumulation operations, and the quantization accuracy of the operation results is also very high.

[0121] Because it can efficiently handle multiplication-accumulation-addition operations, the in-memory computing chip in this embodiment is very suitable for processing tasks in convolutional neural networks that require frequent multiplication-accumulation-addition operations. This in-memory computing chip serves both as a storage chip for data storage and as a logic chip for performing multiplication-accumulation-addition operations.

[0122] Simulation test

[0123] To more clearly demonstrate the operation process of the memory computing circuit provided in this embodiment during logical operations, this embodiment also builds the circuit on Cadence's Virtuoso platform and simulates it using SMIC 55nm technology. In the simulation experiment, the designed memory computing circuit is based on a 6T SRAM memory cell, and the simplified circuit is roughly as follows. Figure 2 As shown. Combined with Figure 2 It can be seen that the memory array contains 16 memory cells in 4 rows and 4 columns; in addition, the left side of the memory array includes a 4*1 redundant column, and the bottom of the memory array includes a 1*4 redundant row. Each column of memory cells connected to the same alignment line in the memory array constitutes a computation column; the quantization circuit below each computation column includes three switches M1, M2, and M3, two capacitors C1 and C2, and a sensitive amplifier SA; the redundant rows, redundant columns, and word lines of the memory array (such as WCWL1-4, WL1-4, DWL) are managed by a word line pulse width modulation array (PWGC).

[0124] In the simplified circuit, the bit lines of redundant columns are represented by DBL and DBLB, and the word lines by DCWL; the word lines of redundant rows are represented by DWL; the word lines of the memory array are represented by WL; and the redundant rows and array share the bit lines BL and BLB. The two capacitors connected to BL and BLB are represented by C1 and C2, where C1 stores the calculation result VDRAIN1 (corresponding to Vsum mentioned earlier), and C2 stores the reference voltage VDRAIN2 (corresponding to Vref mentioned earlier). i SA is used to compare the sizes of VDRAIN1 and VDRAIN2.

[0125] In this circuit, each storage unit in the computation column is the main body that performs each multiplication operation in the multiplication-product operation. Figure 8 This is a detailed circuit diagram for each 6TSRAM memory cell. Arrow I in the diagram indicates the direction of current flow. Combined with... Figure 8 The circuit function can analyze the potential state of different nodes in the circuit, and thus obtain the following truth table for multiplication:

[0126] Table 1: Truth Table for Multiplication Operations in 6T SRAM Cells

[0127]

[0128] Based on the truth table above, we know that the input is a variable reflected in the level and pulse width of the word line WL. In multiplication, it can be used to represent one of the operands. When the word line is open, WL=1 represents a multiplier of 1, and WL=0 represents a multiplier of 0. One of the memory nodes QB in the memory cell can be considered another operand. Q=0, QB=1 represents a multiplicand of 1, and Q=1, QB=0 represents a multiplicand of 0. Correspondingly, under different stored data and word line voltage states, the bit line voltage state will be either VDD or VDD-ΔV, and these two different levels can be used to represent the corresponding binary product result of 0 or 1.

[0129] For example:

[0130] When WL=1, Q=0, and QB=1, the bit line BL discharges, and the bit line voltage decreases by ΔV depending on the turn-on time of the word line WL and the magnitude of the WL voltage; the bit line voltage is VDD-ΔV, which means the multiplication result is 1. That is: 1×1=1.

[0131] When WL = 0, Q = 1, and QB = 0, the bit line BL does not discharge, and the bit line voltage remains at VDD, indicating that the multiplication result is 0. That is, 0 × 0 = 0.

[0132] When WL=0, Q=0, and QB=1, the bit line BL does not discharge, and the bit line voltage remains at VDD, indicating that the multiplication result is 0. That is, 0×1=0.

[0133] When WL = 1, Q = 1, and QB = 0, the bit line BL does not discharge, and the bit line voltage remains at VDD, indicating that the multiplication result is 0. That is, 1 × 0 = 0.

[0134] The operating principle of the above circuit perfectly matches the actual logic of multiplication. That is, in a 6T SRAM memory cell, the multiplication formula is:

[0135] WL×QB=BL

[0136] (1) Calculation stage:

[0137] Specifically, in this experiment, when the storage circuit performs a multiplication operation, switch M1 is closed, while switches M2 and M3 are open, so that the calculation result can be cached on capacitor C1. The switch states are as follows: Figure 9 As shown. It is particularly important to emphasize that: in Figure 9 In the diagram, the black lines represent the circuits that are actively operating, while the gray lines represent circuits that are not operating in that state. The operation of different circuits in each cycle is regulated by a dedicated control circuit.

[0138] The waveforms of each signal during the calculation phase are roughly as follows: Figure 10 As shown. Figure 10 From the waveform diagram, we can see that the calculation stage is... Figure 10 During the PH1 phase, PRE_D and PRE_A are initially low, pre-charging the redundant column bit lines and array bit lines to VDD. Once PRE_D and PRE_A are high, pre-charging ceases, and some word lines (WL) are opened. DWL remains closed and is 0 throughout PH1. During this time, due to the partial opening of word lines, the bit lines discharge, and the final discharged bit line voltage is stored on capacitor C1. On the waveform diagram, DRAIN1 represents the node on capacitor C1.

[0139] (2) Quantification stage

[0140] The in-memory circuit in this experiment performs two steps when quantizing the result of multiplication: coarse quantization and fine quantization.

[0141] The gradation quantization step involves successively comparing the reference voltage and the calculated voltage to obtain the range of the calculated voltage. During the gradation quantization step, the quantization circuit is connected to bit lines BL and BLB, and C2 = 2C1. Switch M1 is open, and M2 and M3 are closed; the circuit switching states are as follows: Figure 11 As shown. It is particularly important to emphasize that: in Figure 11 In the diagram, the black lines represent the circuits that are actively operating, while the gray lines represent circuits that are not operating in that state. The operation of different circuits in each cycle is regulated by a dedicated control circuit.

[0142] In this state, according to the capacitor capacitance formula Q = C·V, since C2 = 2C1, V1 = 2V2 under the same number of rows discharged. Considering that the result of multiplication and accumulation is different for each column bit line in the first step of calculation, the bit line voltage can be divided into 17 different results from 0 to 16. Here, the reference voltage is divided into four levels, therefore, the level quantization needs to be completed within 4 different cycles. Since the input in the previous example was 16 ones, the four levels are VDD-4ΔV, VDD-8ΔV, VDD-12ΔV, and VDD-16ΔV respectively.

[0143] The results of gradation quantization are reflected in the waveform. Figure 12 In cycles 2-5, the bit lines are pre-charged with a high level VDD, corresponding to the pre-charge signal PRE_A of the memory array. It's clear that the bit lines are only pre-charged once during the quantization phase and then no longer pre-charged; that is, discharge continues based on the level obtained the first time. The level is provided by inputting eight 1s into the array in the second cycle to obtain VDRAIN2 = VDD - 4ΔV, eight 1s in the third cycle to obtain VDRAIN2 = VDD - 8ΔV, eight 1s in the fourth cycle to obtain VDRAIN2 = VDD - 12ΔV, and so on.

[0144] Furthermore, after each cycle word line WL is turned off, the reference voltage VDRAIN2 obtained each time is compared with the calculated voltage VDRAIN1 via SA. If the reference voltage is greater than the calculated voltage, SA outputs 0; if the calculated voltage is greater than the reference voltage, SA outputs 1. When SA outputs 1, it means that a reference voltage less than and closest to the calculated voltage has been found. By turning off M2 and M3 through the control circuit, the lower limit reference voltage of the calculated voltage value can be obtained across capacitor C2.

[0145] Since a reference voltage smaller than and closest to the calculated voltage has already been found in the gradation step, the subsequent refinement step involves successively approximating the reference voltage with the calculated voltage to determine its magnitude.

[0146] During fine-tuning operations, M1 is closed, while M2 and M3 are open, and the circuit switch state will switch back to the previous state. Figure 9 In this state, the calculation steps are the same as before, and the calculated voltage is obtained again, with the calculated value reflected in capacitor C1. Simultaneously, the redundant row begins operation, pre-charging is no longer required, and the pulse width is still controlled by both the redundant column and the input signal. By discharging the calculation result only by opening the redundant row each time, the calculated value is approximated to the reference voltage value fixed on C2. That is, VDRAIN1 is approximated to VDRAIN2.

[0147] The waveforms of each signal during fine quantization are as follows: Figure 13 As shown in the PH3 cycle. PER_A is precharged once during the calculation, and then no more precharge is given to the bit lines. The voltage at DRAIN1 drops by ΔV in each cycle. The output of a total of 8 cycles is counted for the four cycles of SA segmentation and the four cycles of successive approximation. Finally, the SA output SA_OUT is 01110000, thus converting the simulated voltage value on the bit line into a digital value, and finally obtaining the accumulated multiplication result on each column of bit lines.

[0148] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.< / n>

Claims

1. A word line pulse width modulation circuit, used to generate a corresponding word line signal WL based on an input signal IN, and to control the pulse width of the word line signal WL; characterized in that: The word line pulse width modulation circuit includes two inverters IN1 and IN2, an AND gate, two NMOS transistors NM1 and NM2, and a PMOS transistor PM. The circuit connection is as follows: the two inverters IN1 and IN2 are connected in series. The input of IN1 is connected to the bit line signal DBL. The output of IN2 is connected to one of the inputs of AND, and the other input of AND is connected to the precharge signal PRE_A. The gate of NM1 is connected to the output of AND. The drains of NM1 and PM are connected together, serving as the overall input IN of the pulse width modulation circuit. The sources of NM1 and PM are connected together and connected to the drain of NM2, serving as the overall output WL of the pulse width modulation circuit. The gate of PM is connected to the gate of NM2 and to the inverted signal of the gate of NM1. The source of NM2 is grounded.

2. A quantization circuit for outputting, in digital form, the sum of the product results of several memory cells connected to the same set of bit lines BL and BLB, characterized in that, The quantization circuit includes three switches M1, M2, and M3, two capacitors C1 and C2, and a sensitive amplifier SA. The circuit connection is as follows: one end of capacitors C1 and C2 is connected to VSS, and the other end is connected to the two input terminals of the sensitive amplifier SA, respectively; one end of switch M1 is connected to the bit line BL, and the other end is connected to the node where C1 and SA meet; one end of switch M2 is connected to the bit line BLB, and the other end is connected to the node where C2 and SA meet; the two ends of switch M3 are connected to the bit lines BL and BLB, respectively. Among them, the on / off states of switches M2 and M3 are synchronized; the on / off states of switch M1 are opposite to those of M2 and M3.

3. The quantization circuit as described in claim 2, characterized in that: The capacitance of capacitor C2 is twice that of capacitor C1.

4. A storage circuit with multiplication, accumulation, and addition operations, characterized in that, It includes: Storage array, which includes N 2 An N×N array consisting of identical storage units; each storage unit contains two inverted storage nodes Q and QB, and each storage unit is used to store data or perform multiplication operations; A redundant column, consisting of N identical storage cells arranged in columns on one side of the storage array; in each storage cell of the redundant column, the same storage node stores the same data; A redundant row consists of at least one to at most n storage cells arranged in rows on one side of the storage array; each storage cell in the redundant row shares a bit line with all storage cells in the corresponding column of the storage array; and the data stored in the same storage node in each storage cell of the redundant row is the same. The bit line group includes N+1 pairs of bit lines, namely: N sets of bit lines BL and BLB corresponding to each memory cell in the memory array, and 1 set of bit lines DBL and DBLB corresponding to the redundant column. The word line group consists of 2N+1 word lines, namely: the word line DCWL corresponding to each row of the memory cell in the redundant column, the word line WL corresponding to each row of the memory cell, and the word line DWL corresponding to the redundant row. The input circuit generates 2N+1 independent input signals IN when performing logical operations, with each input signal controlling one of the word lines in the word line group. A word line pulse width modulation array, comprising 2N+1 word line pulse width modulation circuits as described in claim 1; each word line pulse width modulation circuit is used to generate a corresponding word line signal WL based on a received input signal IN when performing a logic operation, thereby controlling the opening and closing of each word line in the word line group; A quantization circuit array comprising a plurality of quantization circuits corresponding one-to-one with each memory cell in a redundant row, each quantization circuit being as described in any one of claims 2 or 3; the quantization circuits are connected to bit lines and are used to output the sum of the multiplication results of each memory cell in the corresponding column; Timing control circuits are used to generate the clock signals required by each functional module, thereby enabling the circuit functions to be implemented accurately and in an orderly manner. A pre-charge circuit is used to pre-charge the bit lines BL and BLB connected to each column of memory cells in the memory array, as well as the bit lines DBL and DBLB connected to redundant columns. The word line driver module is used to control the opening or closing of the word lines WL connected to each memory cell in the memory array during data read and write operations. The line decoding module is used to control the word line driving module according to the decoding result when performing data read and write operations; A read / write control circuit, which is used to control the data read / write operations of each storage unit in the storage array; The output circuit is used to output the digital value of the sum of the multiplication results of each column of storage cells quantized by the quantization circuit.

5. The in-memory circuit with multiplication, accumulation, and addition functions as described in claim 4, characterized in that: The storage array and the redundant rows use the exact same storage units; and In the redundant row, the storage node Q, which is close to and connected to the bit line BL, pre-stores data 0, and the storage node QB, which is close to and connected to the bit line BLB, pre-stores data 1. In the redundant column, the storage node Q, which is close to and connected to the bit line DBL, pre-stores data 0, and the storage node QB, which is close to and connected to the bit line DBLB, pre-stores data 1.

6. The in-memory circuit with multiplication, accumulation, and addition functions as described in claim 4, characterized in that: The in-memory computing circuit has data storage and logic operation functions; Each storage unit in the storage array serves as a basic unit for performing read and write operations when implementing data storage functions. Any column in the storage array, the storage cells in the corresponding redundant rows, the quantization circuit corresponding to the column, the redundant column, and the pulse width modulation array together constitute the basic unit for performing multiplication and accumulation operations. When performing logical operations of multiplication and accumulation, each storage cell performs an independent multiplication operation, and the result of the multiplication operation of the storage cell is used as the operand for multiplication and accumulation. In the storage circuit, the maximum number of operands for multiplication and accumulation is the number of rows in the storage array.

7. The storage circuit with multiplication, accumulation, and addition functions as described in claim 4, characterized in that: Among the 2N+1 input signals input to the input circuit, by adjusting the N input signals corresponding to the word line DCWL in the redundant column, in conjunction with the word line pulse width modulation array, the discharge speed of the redundant column bit line DBL can also be controlled, thereby realizing the adjustment of the pulse width of all 2N+1 word line signals.

8. A quantization method applied to an in-memory computing circuit with multiplication, accumulation, and addition functions as described in any one of claims 4-6, characterized in that: The quantization method is used to generate the quantization result of multiplication-accumulation-sum operations according to a preset operation logic; the operation logic of the quantization method is as follows: Operation phase: (1) Precharge all bit line voltages of BL and BLB to VDD, and then in the first cycle, control any column selected in the memory array to perform multiplication and accumulation operation, and cache the operation result on capacitor C1. During the operation, if the multiplication result of k memory cells in the current column is 1, k≤N, then the bit line discharge is k·Δv, and the bit line voltage is VDD-k·Δv. The bit line voltage at this time is the analog quantity Vsum of the result of the multiplication and accumulation operation. Quantification stage: (1) Based on the number of rows N in the storage array, the maximum discharge amount of the bit line is N·Δv; the maximum discharge amount N·Δv is divided into M levels; assuming that the boundary values ​​of each level are as follows: Where i represents the gear position number, i = 1, 2, ..., M-1, M; (2) Starting from the second cycle, different input signals IN are input in each cycle, and then different reference voltages Vref are generated on capacitor C2 in descending order. i : (3) The reference voltage Vref i The result is buffered on capacitor C2 and compared with the analog quantity Vsum of the calculation result; observe the output of the sensitive amplifier SA in the quantization circuit, and record the gear number p corresponding to the first flip of the SA output, thereby determining the lower limit of the analog quantity Vsum of the calculation result. (4) Enable redundant lines in subsequent cycles and make the analog quantity Vsum of the calculation result decrease by Δv every cycle. Record the number of discharge quantity decreases q when the output of the sensitive amplifier SA flips for the second time. (5) Based on the two flips, the analog quantity Vsum of the result of the multiplication and accumulation operation is determined as: Therefore, the output digital value after multiplication, accumulation, and quantization is:

9. A memory computing chip, characterized in that: It is an integrated circuit packaged from a memory circuit having multiplication, accumulation, and addition functions as described in any one of claims 4-6.

10. An application of the in-memory computing chip as described in claim 9, characterized in that: The in-memory computing chip is applied to the processing task of convolutional neural networks. The in-memory computing chip serves as a storage chip for performing data storage and as a logic operation chip for performing multiplication and accumulation operations.

Images