Verification device, verification method, storage medium and chip for memory controller

Abstract

This application discloses a verification apparatus, verification method, storage medium, and chip for a memory controller. The verification apparatus includes: an information extraction module for acquiring memory configuration information based on memory architecture feature data; an information processing module for generating a physical address to be accessed in the memory based on the logical address to be accessed, the memory type, and the memory configuration information; and an access module for accessing the memory via a backdoor based on the physical address to be accessed, to write verification data into the memory, and / or read data to be verified from the memory. The information processing module is further used to generate verification data and / or perform data analysis on the data to be verified to verify the memory controller. This verification apparatus establishes a verification environment for assisting in the verification of the memory controller and facilitates rapid modification of the verification environment.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip design, in particular to a verification device for a memory controller, a verification method, a storage medium and a chip. BACKGROUND

[0002] With the increasing complexity of chip design and the increasing demand in time and cost, the corresponding memory architecture of the chip is also becoming increasingly complex, and the requirement for chip verification is becoming higher and higher.

[0003] At present, chip verification first needs to generate a verification environment, and for different chips, a corresponding verification environment needs to be designed for chip verification. The existing verification method for the memory controller is inefficient and difficult to realize the reuse of the verification environment.

[0004] Therefore, it is desirable to provide a verification device for a memory controller to improve verification efficiency. SUMMARY

[0005] In view of the above problems, the purpose of the present application is to provide a verification device for a memory controller, a verification method, a storage medium and a chip, thereby facilitating fast modification of the verification environment and facilitating reuse of the verification environment.

[0006] According to a first aspect of the present application, a verification device for a memory controller is provided, comprising: an information extraction module configured to obtain memory configuration information based on memory architecture feature data of a memory; an information processing module configured to generate a to-be-accessed physical address of the memory according to a to-be-accessed logical address of the memory, a memory type and the memory configuration information; and an access module configured to backdoor access the memory based on the to-be-accessed physical address to write verification data into the memory and / or read to-be-verified data from the memory, wherein the information processing module is further configured to generate the verification data and / or perform data analysis on the to-be-verified data to verify the memory controller.

[0007] Optionally, the information processing module comprises: a memory selection component configured to determine a memory code based on the to-be-accessed logical address and the memory configuration information; an address mapping component configured to generate the to-be-accessed physical address for accessing the memory according to the to-be-accessed logical address, the memory configuration information and the memory code; and a data processing component configured to generate the verification data according to the to-be-accessed logical address, the memory type and the memory configuration information, and / or receive the to-be-verified data and perform data analysis on the to-be-verified data.

[0008] Optionally, the address mapping component generates the physical address to be accessed based on a mapping processing algorithm, and the information processing module verifies the memory controller based on a data processing algorithm.

[0009] Optionally, it also includes: an algorithm library for storing a variety of preset algorithms, wherein the mapping processing algorithm and the data processing algorithm are selected from one or more of the variety of preset algorithms.

[0010] Optionally, the information extraction module analyzes the memory architecture feature data of the memory to extract the memory configuration information required for the backdoor access to the memory verification environment.

[0011] According to a second aspect of the present invention, a method for verifying a memory controller is provided, comprising: obtaining memory configuration information based on memory architecture feature data of the memory; generating a physical address to be accessed of the memory according to the logical address to be accessed of the memory, the memory type and the memory configuration information; and accessing the memory through a backdoor based on the physical address to be accessed, to write verification data into the memory, and / or read the data to be verified from the memory, to verify the memory controller.

[0012] Optionally, generating the physical address to be accessed for the memory includes: determining a memory code based on the logical address to be accessed and the memory configuration information; and generating the physical address to be accessed for accessing the memory based on the logical address to be accessed, the memory configuration information, and the memory code.

[0013] Optionally, the physical address to be accessed is generated based on a mapping processing algorithm, and the memory controller is verified based on a data processing algorithm.

[0014] Optionally, it may also include: reading the mapping processing algorithm and the data processing algorithm from an algorithm library.

[0015] Optionally, it may also include: generating the verification data based on the logical address to be accessed, the memory type, and the memory configuration information.

[0016] Optionally, it may also include: analyzing the memory architecture feature data of the memory to extract the memory configuration information required for the backdoor access memory verification environment.

[0017] According to a third aspect of the present invention, a computer-readable storage medium is provided, comprising: a computer program stored on the computer-readable storage medium, which, when run on a computer, causes the computer to perform the verification method as described above.

[0018] According to a fourth aspect of the present invention, a chip is provided, comprising: a memory; a memory controller for reading and writing data to the memory; a processing unit for providing instructions and data for reading and writing data to the memory controller; and a verification device as described above, which receives instructions from the processing unit for verifying the memory controller, accesses the memory through a backdoor, writes verification data to the memory, and / or reads data to be verified from the memory to verify the memory controller.

[0019] The present invention provides a verification device, verification method, storage medium, and chip for memory controllers. For different memory architectures, by modifying the memory architecture feature data, the memory configuration information of the backdoor access memory verification environment is generated, thus completing the modification of the backdoor access memory verification environment. This facilitates rapid modification of the verification environment, enables the reuse of the verification environment, and improves verification efficiency.

[0020] In some embodiments, the verification apparatus, verification method, storage medium, and chip for memory controllers of the present invention are easily scalable. When new processing algorithms are needed for the memory address to be accessed, the verification data, and the data to be verified, the algorithm library can be updated to update the backdoor access to the new memory. When the memory architecture changes, a new verification environment can be built by selecting the corresponding new algorithm from the algorithm library based on the configuration file, thus completing the memory verification. Attached Figure Description

[0021] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0022] Figure 1 A block diagram of a memory system according to an embodiment of the present invention is shown;

[0023] Figure 2 A block diagram of a verification apparatus for a memory controller according to an embodiment of the present invention is shown;

[0024] Figure 3 A flowchart of a verification method for a memory controller according to an embodiment of the present invention is shown. Detailed Implementation

[0025] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown in the drawings.

[0026] Many specific details of the invention, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without following these specific details.

[0027] It should be understood that the connection / coupling of A and B in the embodiments of this application means that A and B can be connected in series or in parallel, or A and B can be connected through other devices. The embodiments of this application do not limit this.

[0028] With the continuous advancement of integrated circuit processes and manufacturing technologies, integrated circuits are becoming increasingly functional, structurally complex, and highly integrated. Therefore, conducting different tests at different stages of integrated circuit chip development has become essential. For chip design, verification testing is indispensable in order to confirm the correctness of the circuit design.

[0029] For chips with memory, the memory uses mixed-signal digital logic to control an analog array. Memory testing mainly focuses on testing the memory cell array. The most basic verification test can be completed by correctly reading the timing sequences for reading, programming, and erasing from the chip pin inputs. Complex tests require the development of complex timing stimuli based on this.

[0030] Currently, chip verification first requires generating a verification environment and transmitting input parameters to it. Then, corresponding parsing code is written in the build program to parse the input parameters, configuring the verification environment to match the specified values. However, this verification method is inefficient.

[0031] Therefore, this application provides an improved verification apparatus, verification method, computer-readable storage medium, and chip for memory controllers to improve verification efficiency, enable rapid modification of the verification environment, and facilitate the reuse and scalability of the verification environment.

[0032] Figure 1 A block diagram of a memory system according to an embodiment of the present invention is shown.

[0033] like Figure 1 As shown, the memory system 100 includes a memory 110, a memory controller 120, a verification device 130, and a processing unit 140. The memory system 100 can be applied to any type of chip to provide storage functionality, and the memory system 100 can be used to build a verification environment, which facilitates the simple and rapid verification of the memory controller's functionality.

[0034] The memory system 100 may be a storage system configured within a computer platform, or in one configuration, the memory system 100 itself may function as a computer platform. The memory system 100 may perform functional verification on the memory 120. The computer platform may be, for example, a desktop computer, a portable computer (such as a laptop or handheld device, e.g., a tablet, a personal digital assistant (PDA), a smartphone, a messaging device, a digital music player, a digital camera, etc.), or other such computer platforms used for data storage, processing, transmission, reception, and / or other similar functions.

[0035] In this embodiment of the invention, the processing unit 140 is used to determine the logical address to be accessed and the memory type of the memory 120, for example, by determining the logical address to be accessed and the memory type according to an instruction sent by the host. It should be understood that, in order to achieve comprehensive memory verification, there may be multiple logical addresses to be accessed.

[0036] In some embodiments, processing unit 140 has one or more processor cores running software (e.g., an operating system on which one or more applications are implemented). For example, processing unit 140 may include a central processing unit (CPU), a dedicated instruction set processor (ASIP), or another processor that runs one or more of operating system instructions, boot software instructions, optional ROM instructions, firmware interface instructions, and / or the like. In an illustrative but not limiting manner, the processor of processing unit 140 may run Basic Input / Output System (BIOS) code, Extensible Firmware Interface (EFI) code such as Unified Extensible Firmware Interface (UEFI) code, and / or other firmware interface instructions. Any of various types of firmware interface code, operating system code, application code, etc. (according to the techniques discussed herein) may be run by processing unit 140.

[0037] In this embodiment, the memory system 100 may include (e.g., via memory controller 110) a memory 120 coupled to the processing unit 140, wherein the memory 120 stores instructions or other data to support the execution of software by the processing unit 140. The memory 120 may, for example, include any of various combinations of one or more volatile storage devices. In an illustrative but not limiting manner, the memory 120 may include one or more of random access memory (RAM), such as dynamic random access memory (DRAM), static random access memory (SRAM), such as double data rate (DDR) synchronous dynamic random access memory (SDRAM), etc. The memory 120 may, for example, include one or more dual-inline-memory-modules (DIMM) devices; it should be understood that the invention is not limited thereto.

[0038] In one embodiment, memory 120 includes a plurality of physical addresses for storing information (e.g., instructions, data, address information, and / or etc.) for access by a verification device 130 of the memory controller to generate a verification environment, thereby facilitating the verification of the memory controller. The physical addresses may, for example, be configured to store information representing the state of one or more software processes to be executed by processing unit 140.

[0039] Some or all of the physical addresses may include or otherwise correspond to corresponding error correction locations in memory 120. These error correction locations may be used to store a corresponding error correction code (ECC) or other error correction value for information stored in the corresponding physical address, such as a parity bit, checksum, hash value, and / or the like. It should be understood that memory 120 may include... Figure 1 Any of the various additional or alternative physical addresses (and / or error correction locations) not shown in the diagram.

[0040] In this embodiment of the invention, the memory system 100 further includes a verification device 130 for the memory controller. The verification device 130 includes logic for performing memory verification for some or all physical addresses. Specifically, the verification device 130 obtains memory configuration information based on memory architecture feature data of the memory 120, generates a physical address to be accessed for the memory 120 according to the logical address to be accessed, memory type, and memory configuration information of the memory 120 provided by the processing unit 120, and accesses the memory 120 based on the physical address to be accessed to write verification data to the memory 120 and / or read verification data from the memory 120 to assist in verifying the memory controller 110. For example, if the result of writing verification data to the memory 120 and / or reading verification data is as expected, then the memory controller 110 can be verified to successfully complete data read and write; if the result of writing verification data to the memory 120 and / or reading verification data is not as expected, then the memory controller 110 is faulty and needs to be modified.

[0041] As an example, the verification device 130 may be located outside the processing unit 140. It should be understood that the invention is not limited thereto, and the verification device 130 may be located within the memory controller 110. In some embodiments, the verification device 130 and / or the memory controller 110 may be located within the integrated circuit (IC) package or other component device (e.g., a system-on-chip (SoC) device) of the memory system 100 including the processing unit 140.

[0042] As an example, verification device 130 includes any of various combinations of hardware, software, and / or firmware to perform one or more writes and / or reads for each physical address. For example, verification device 130 may include a state machine or other hardware engine to generate multiple write commands and verification data for writing to a corresponding location in memory 120 and writing the verification data to memory 120, or to generate multiple read commands for reading to a corresponding location in memory 120 to read data to be verified from memory 120. Alternatively or additionally, verification device 130 may include a coprocessor, microcontroller, or other agent to generate such write commands.

[0043] In some embodiments, the verification device 130 may perform memory verification only in response to communications from the processing unit 140, wherein any such communications are applicable to all physical addresses. For example, memory verification may be independent of any such communications that provide information (address, data, instructions, etc.) specific to a particular physical address.

[0044] It should be understood that the verification device 130 can be set up independently and can be used in a variety of different memories to verify various memories. The verification device 130 sets up a verification environment that requires backdoor access to memory, which greatly simplifies the entire setup process, improves the reusability of the verification environment, reduces the time required for verification personnel to set up and debug such verification environments, and improves verification efficiency.

[0045] The following is combined Figure 2 The verification device 130 of the present invention will be described in detail. Figure 2 A block diagram of a verification apparatus for a memory controller according to an embodiment of the present invention is shown.

[0046] like Figure 2 As shown, the verification device 130 for the memory controller includes an information extraction module 131, an information processing module 132, and an access module 133. The verification device 130 can generate memory instructions for controlling data writing / reading based on the memory architecture feature data of the memory and the host instructions (including instruction code, logical address to be accessed, and memory type) provided by the processing unit 140. Then, the memory instructions (including instruction code and physical address to be accessed) are sent to the memory 120 to perform data reading and writing. The memory verification is completed based on the storage result after the verification data is written to the memory 120 and / or the data to be verified read from the memory 120.

[0047] The information extraction module 131 obtains memory configuration information based on memory architecture feature data. The information extraction module 131 includes, for example, an analysis component that analyzes the memory architecture feature data of the memory to extract the memory configuration information required for backdoor access to the memory verification environment.

[0048] The information processing module 132 is connected to the information extraction module 131 to receive memory configuration information and to the processing unit 140 to receive the logical address to be accessed and the memory type. The information processing module 132 is used to generate the physical address to be accessed for the memory based on the logical address to be accessed, the memory type, and the memory configuration information. In an optional embodiment, the information processing module 132 is also used to generate verification data so that the access module 133 can write the verification data into the memory.

[0049] As an example, the information processing module 132 includes a memory selection component 1321, an address mapping component 1322, and a data processing component 1323. Specifically, the memory selection component 1321 is connected to both the information extraction module 131 and the processing unit 140, and is used to determine the memory code based on the logical address to be accessed and memory configuration information. The address mapping component 1322 is connected to both the information extraction module 131 and the memory selection component 1321, and is used to generate a physical address to be accessed for accessing the memory based on the logical address to be accessed, memory configuration information, and memory code. The data processing component 1323 is connected to both the information extraction module 131 and the address mapping component 1322, and is used to generate verification data based on the logical address to be accessed, memory type, and memory configuration information, and / or receive the data to be verified and perform data analysis on the data to be verified. Optionally, after the access module 133 finishes accessing the memory, the data processing component 1323 is also used to perform data analysis on the data to be verified to verify the memory controller.

[0050] In this example, the address mapping component 1322 generates the physical address to be accessed based on a mapping processing algorithm, such as a key XOR algorithm or an address reconstruction algorithm. The data processing component 1323 generates the verification environment based on a data processing algorithm, such as a key XOR algorithm, a data reordering algorithm, or an algorithm encryption algorithm.

[0051] As an example, the verification device 130 also includes an algorithm library 134, connected to the address mapping component 1322 and the data processing component 1323 respectively. The algorithm library 134 stores the algorithms required by the address mapping component 1322 and the data processing component 1323. The algorithm library 134 may store, for example, a variety of preset algorithms, with the mapping processing algorithm and the data processing algorithm selected from one or more of these preset algorithms. The preset algorithms may include, for example, key XOR algorithms, address reconstruction algorithms, data scrambling algorithms, and algorithm encryption algorithms. It should be understood that the invention is not limited to these, and the preset algorithms may also include any other type of address mapping algorithm and data processing algorithm.

[0052] In this example, the scalability of the verification device 130 is improved. When new processing algorithms are needed for the memory access address, verification data, and data to be verified, the algorithm library 134 can be updated to update the backdoor access to the new memory. When the memory architecture changes, a new verification environment can be built by selecting the corresponding new algorithm in the algorithm library 134 based on the configuration file, thus completing the memory verification.

[0053] Access module 133 accesses the memory based on the physical address to be accessed in order to write verification data to the memory and / or read verification data from the memory. After access module 133 finishes accessing the memory, data processing component 1323 performs data analysis on the verification data to verify the memory controller, or verifies the memory controller based on the storage result of the verification data in the memory. This verification process can also be implemented by processing unit 140.

[0054] The verification device 130 provided in this embodiment of the invention can generate memory configuration information for the backdoor access memory verification environment by modifying the memory architecture feature data for different memory architectures. This completes the modification of the backdoor access memory verification environment, which is beneficial for quickly modifying the verification environment, realizing the reuse of the verification environment and improving verification efficiency.

[0055] Figure 3 A flowchart of a verification method for a memory controller according to an embodiment of the present invention is shown.

[0056] like Figure 3 As shown, the verification method for the memory controller includes steps S1 to S3.

[0057] In step S1, memory configuration information is obtained based on the memory architecture feature data. In this step, the memory architecture feature data is analyzed to extract the memory configuration information required for the backdoor access to the memory verification environment.

[0058] In step S2, the physical address of the memory to be accessed is generated based on the logical address of the memory to be accessed, the memory type, and the memory configuration information.

[0059] Optionally, in this step, verification data is also generated based on the logical address to be accessed, the memory type, and the memory configuration information.

[0060] In step S3, the memory is accessed based on the physical address to be accessed in order to write the verification data into the memory and / or read the verification data from the memory in order to verify the memory controller.

[0061] In this step, the memory code is determined based on the logical address to be accessed and the memory configuration information; a physical address to be accessed for accessing the memory is generated based on the logical address to be accessed, the memory configuration information, and the memory code. Optionally, the physical address to be accessed is generated based on a mapping processing algorithm, and the memory controller is verified based on a data processing algorithm. For example, mapping processing algorithms and data processing algorithms can be read from an algorithm library.

[0062] Furthermore, embodiments of the present invention also provide a computer-readable storage medium, comprising: a computer program stored on the computer-readable storage medium, which, when executed on a computer, causes the computer to perform actions such as... Figure 3 The method described.

[0063] In summary, the embodiments of the present invention provide a verification device, verification method, computer-readable storage medium, and chip for a memory controller. For different memory architectures, by modifying the memory architecture feature data, memory configuration information for backdoor access to the memory verification environment is generated, thereby completing the modification of the backdoor access to the memory verification environment. This facilitates rapid modification of the verification environment, enables the reuse of the verification environment, and improves verification efficiency.

[0064] In some embodiments, the verification apparatus, verification method, computer-readable storage medium, and chip of the memory controller of the present invention are easily scalable. When a new processing algorithm is needed for the memory address to be accessed, the verification data, and the data to be verified, the algorithm library can be updated to update the backdoor access to the new memory. When the memory architecture changes, a new verification environment can be built by selecting the corresponding new algorithm from the algorithm library based on the configuration file, and the memory verification can be completed.

[0065] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0066] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. An authentication apparatus for a memory controller, comprising: an information extraction module configured to obtain memory configuration information based on memory architecture feature data of a memory; an information processing module configured to generate a physical address to be accessed of the memory according to a logical address to be accessed of the memory, a memory type, and the memory configuration information; and an access module configured to access the memory based on the physical address to be accessed to write authentication data to the memory and / or read authentication data to be verified from the memory, wherein the information processing module comprises: a memory selection component configured to determine a memory code based on the logical address to be accessed and the memory configuration information; an address mapping component configured to generate the physical address to be accessed for accessing the memory according to the logical address to be accessed, the memory configuration information, and the memory code; and a data processing component configured to generate the authentication data according to the logical address to be accessed, the memory type, and the memory configuration information, and / or receive and perform data analysis on the authentication data to be verified to verify the memory controller. The address mapping component generates the physical address to be accessed based on a mapping processing algorithm, and the information processing module verifies the memory controller based on a data processing algorithm.

2. The authentication apparatus according to claim 1, wherein Further comprising:

3. The authentication apparatus according to claim 2, wherein an algorithm library configured to store a plurality of preset algorithms, the mapping processing algorithm and the data processing algorithm being selected from one or more of the plurality of preset algorithms. The information extraction module analyzes the memory architecture feature data of the memory to extract the memory configuration information required for backdoor access to a memory authentication environment.

4. The authentication apparatus according to claim 1, wherein 5. An authentication method for a memory controller, comprising: obtaining memory configuration information based on memory architecture feature data of a memory; generating a physical address to be accessed of the memory according to a logical address to be accessed of the memory, a memory type, and the memory configuration information; and accessing the memory based on the physical address to be accessed to write authentication data to the memory and / or read authentication data to be verified from the memory to verify the memory controller, wherein generating the physical address to be accessed of the memory comprises: determining a memory code based on the logical address to be accessed and the memory configuration information; and generating the physical address to be accessed for accessing the memory according to the logical address to be accessed, the memory configuration information, and the memory code; and The authentication method further comprises generating the authentication data according to the logical address to be accessed, the memory type, and the memory configuration information. The physical address to be accessed is generated based on a mapping processing algorithm, and the memory controller is verified based on a data processing algorithm. Further comprising: selecting the mapping processing algorithm and the data processing algorithm from an algorithm library, the algorithm library storing a plurality of preset algorithms, the mapping processing algorithm and the data processing algorithm being selected from one or more of the plurality of preset algorithms.

6. The authentication method of claim 5, wherein, ​ 7. The method of verification of claim 6, wherein, ​ 8. The authentication method of claim 5, wherein, Further comprising: analyzing memory architecture feature data of the memory to extract the memory configuration information required for backdoor access memory verification environment.

9. A computer-readable storage medium comprising: The computer readable storage medium stores a computer program, when the computer program runs on the computer, makes the computer execute the verification method as claimed in any one of claims 5-8.

10. A chip comprising: a memory; a memory controller for reading and writing data to the memory; a processing unit for providing instructions and data for reading and writing data to the memory controller; and the verification device as claimed in any one of claims 1-4, receiving the instructions provided by the processing unit for verifying the memory controller, to backdoor access the memory, and write verification data to the memory, and / or read data to be verified from the memory to verify the memory controller.

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