An optoelectronic chip package structure and a packaging method

Abstract

The application relates to an optoelectronic chip packaging structure and a packaging method, which comprises a first carrier plate, a light chip fixed on the first carrier plate, the light chip being provided with a pad; a second carrier plate, the second carrier plate being located on the same side of the first carrier plate as the light chip, the second carrier plate being electrically connected with the first carrier plate, the second carrier plate being provided with an electric transmission line, the electric transmission line and the pad being located in substantially the same plane and being electrically connected with each other; and an electric chip, the electric chip being mounted on the second carrier plate and being electrically connected with the electric transmission line. Since the second carrier plate is arranged on one side of the first carrier plate, the height of the electric transmission line on the second carrier plate can be adjusted, so that the electric transmission line and the pad on the light chip are located in substantially the same plane, the electric chip and the light chip can be electrically connected through the electric transmission line and the pad located in the same plane, and a larger blind groove does not need to be formed on the carrier plate.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a photoelectric chip packaging structure and packaging method. Background Technology

[0002] Currently, with the continuous development of the optoelectronic industry, people have increasingly higher requirements for signal bandwidth and speed, and the demand for lightweight product specifications is also increasing. Therefore, packaging more chips on smaller substrates with lower losses and better heat dissipation performance will be the development trend of the packaging industry.

[0003] In related technologies, current chip packaging mainly includes two methods: upright mounting and flip-chip mounting. For high-frequency signals, due to the need to consider the impedance matching of transmission lines, a large blind slot is usually required in the substrate when the chip is upright mounted so that the connection between the chip pad and the transmission line is as horizontal as possible. However, due to the limitations of the process, a large blind slot may cause the warping of the substrate to be difficult to control, which in turn leads to excessive wire bonding loss between the chip and the substrate.

[0004] Therefore, it is necessary to design a new optoelectronic chip packaging structure and packaging method to overcome the above problems. Summary of the Invention

[0005] This invention provides a photoelectric chip packaging structure and packaging method to solve the problem in related technologies where blind slots cause substrate warping that is difficult to control, leading to excessive wire bonding losses between the chip and the substrate.

[0006] In a first aspect, an optoelectronic chip packaging structure is provided, comprising: a first carrier plate on which an optical chip is fixed, the optical chip having pads; a second carrier plate on which the optical chip is located on the same side as the first carrier plate and electrically connected to the first carrier plate, an electrical transmission line being disposed on the second carrier plate, the electrical transmission line being substantially on the same plane as the pads and electrically connected to the pads; and an electrical chip mounted on the second carrier plate and electrically connected to the electrical transmission line.

[0007] In some embodiments, the electrical transmission line is electrically connected to the pad via an electrical connection.

[0008] In some embodiments, the width of the electrical connection strip is equal to the width of the electrical transmission line.

[0009] In some embodiments, the first carrier board has heat dissipation holes at the bottom corresponding to the optical chip.

[0010] In some embodiments, the first carrier board is provided with a DC control circuit and a monitoring circuit, both of which are electrically connected to the electrical chip through the second carrier board.

[0011] In some embodiments, a heat sink is attached to the surface of the electrical chip, and the heat sink and the second carrier are distributed on opposite sides of the electrical chip.

[0012] In some embodiments, the optical chip is connected to an optical fiber amplifier via an optical fiber.

[0013] In some embodiments, the first carrier board is provided with a surface transmission line, and a plurality of solder balls are arranged between the first carrier board and the second carrier board, the solder balls being electrically connected to the surface transmission line and the solder balls being electrically connected to the second carrier board.

[0014] Secondly, a method for packaging an optoelectronic chip is provided, comprising the following steps: fixing an optoelectronic chip on a first carrier plate; fixing a second carrier plate to the first carrier plate and controlling the height of the second carrier plate so that the electrical transmission lines on the second carrier plate and the pads on the optoelectronic chip are substantially on the same plane; electrically connecting the electrical transmission lines and the pads; mounting an electrical chip to the second carrier plate and electrically connecting the electrical chip and the electrical transmission lines.

[0015] In some embodiments, electrically connecting the electrical transmission line to the pad includes: electrically connecting the electrical transmission line to the pad using an electrical connection strip.

[0016] The beneficial effects of the technical solution provided by this invention include:

[0017] This invention provides a photoelectric chip packaging structure and packaging method. Since a second carrier board is provided on one side of the first carrier board, the height of the electrical transmission line on the second carrier board can be adjusted so that the electrical transmission line and the pad on the optical chip are basically on the same plane. The electrical connection between the electrical chip and the optical chip can be realized through the electrical transmission line and the pad on the same plane. Therefore, it is not necessary to open a large blind slot on the carrier board, which can effectively solve the problem of carrier board warping. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a three-dimensional structural diagram of an optoelectronic chip packaging structure provided in an embodiment of the present invention;

[0020] Figure 2 This is a front view schematic diagram of an optoelectronic chip packaging structure provided in an embodiment of the present invention;

[0021] Figure 3 This is a three-dimensional structural diagram of an optoelectronic chip packaging structure without an installed electrical chip, provided by an embodiment of the present invention.

[0022] Figure 4 A three-dimensional structural diagram of the second carrier plate provided in an embodiment of the present invention;

[0023] Figure 5 This is a cross-sectional schematic diagram of an optoelectronic chip packaging structure provided in an embodiment of the present invention;

[0024] Figure 6 This is a schematic diagram of the simulation results of an optoelectronic chip packaging structure provided in an embodiment of the present invention.

[0025] In the picture:

[0026] 1. First carrier board; 11. Heat dissipation holes; 12. Surface transmission line;

[0027] 2. Optical chip; 21. Solder pad; 3. Second carrier board; 31. Electrical transmission line;

[0028] 4. Electrical chip; 5. Electrical connector; 6. Fiber optic amplifier; 7. Fiber optic cable; 8. Solder ball. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] In related technologies, current chip packaging mainly includes two methods: upright mounting and flip-chip mounting. Usually, when the chip is upright mounted, a large blind slot needs to be opened in the substrate. However, due to the limitations of the process level, a large blind slot may cause the warping of the substrate to be difficult to control, which in turn leads to excessive wire bonding loss between the chip and the substrate.

[0031] The advantages of flip chips lie in their good heat dissipation performance and high reliability, but their application is still limited due to the stringent process requirements, high cost and difficulty.

[0032] Therefore, a multi-chip packaging design that can flexibly utilize both upright and flip-chip packaging can highlight its advantages in terms of reducing costs, reducing losses, and improving heat dissipation performance.

[0033] This invention provides a photoelectric chip packaging structure that can solve the problem in related technologies where blind slots cause substrate warping that is difficult to control, leading to excessive wire bonding losses between the chip and the substrate.

[0034] See Figure 1 and Figure 2 As shown, an optoelectronic chip packaging structure provided by an embodiment of the present invention may include: a first carrier board 1, on which an optical chip 2 may be fixed, the optical chip 2 having pads 21 (i.e., pads), wherein the first carrier board 1 is responsible for fixing a low-power, upright-mounted optical chip 2, the optical chip 2 is typically a PIC, and the pads 21 on the optical chip 2 can be used for electrical signal transmission; a second carrier board 3, the second carrier board 3 may be located on the same side of the first carrier board 1 as the optical chip 2. In this embodiment, the second carrier board 3 and the first carrier board 1 may be arranged vertically, that is, the first carrier board 1 may be arranged on the lower layer and the second carrier board 3 may be arranged on the upper layer. Of course, in other embodiments, the positions of the first carrier board 1 and the second carrier board 3 may be set according to the actual situation. For example, if necessary, the first carrier board 1 and the second carrier board 3 may be arranged in the left-right direction, or the first carrier board 1 may be placed on the upper layer and the second carrier board 3 on the lower layer.

[0035] The second carrier board 3 is electrically connected to the first carrier board 1, enabling electrical signal transmission between them. An electrical transmission line 31 can be provided on the second carrier board 3 for transmitting electrical signals. The electrical transmission line 31 and the pad 21 are essentially on the same plane, meaning the upper surface of the electrical transmission line 31 is essentially flush with the upper surface of the pad 21. The electrical transmission line 31 is electrically connected to the pad 21. This electrical connection can be either direct or indirect, ensuring electrical signal conduction between the electrical transmission line 31 and the pad 21.

[0036] The optoelectronic chip packaging structure may also include an electrical chip 4, which can be mounted on the second carrier board 3 and electrically connected to the electrical transmission line 31, thereby enabling the electrical chip 4 and the optical chip 2 to conduct through the electrical transmission line 31.

[0037] In this embodiment, since a second carrier board 3 is provided on one side of the first carrier board 1, the electrical chip 4 is mounted on the first carrier board 1 through the second carrier board 3. The height of the second carrier board 3 can be controlled, thereby adjusting the height of the electrical transmission line 31 on the second carrier board 3 (of course, the thickness of the electrical transmission line 31 can also be finely adjusted), so that the electrical transmission line 31 and the pad 21 on the optical chip 2 are basically on the same plane. The electrical connection between the electrical chip 4 and the optical chip 2 can be achieved through the electrical transmission line 31 and the pad 21 located on the same plane. Furthermore, since the higher the electrical transmission line 31 and the pad 21 are, the better the impedance matching effect, this embodiment utilizes the surface height difference between the first carrier board 1 and the second carrier board 3 to enable the electrical transmission line 31 and the pad 21 to have a good impedance matching effect, and does not require opening a large blind slot on the carrier board, which can effectively solve the problem of carrier board warping.

[0038] In some embodiments, see Figure 3 As shown, the electrical transmission line 31 and the pad 21 can be electrically connected via an electrical connecting strip 5. The electrical connecting strip 5 can have a certain width, providing a relatively large contact area after connecting to the electrical transmission line 31 and the pad 21, thus improving connection strength and electrical signal transmission performance. Furthermore, the electrical connecting strip 5 can transmit electrical signals. The preferred material for the electrical connecting strip 5 is gold, which offers good electrical transmission performance. Of course, other alternative materials can also be used; any material capable of electrical transmission is acceptable.

[0039] Of course, in some other alternative embodiments, the electrical transmission line 31 can be extended so that the electrical transmission line 31 directly contacts the pad 21 to achieve electrical conduction.

[0040] Further, see Figure 3 and Figure 4 As shown, the width of the electrical connection strip 5 is preferably set to be equal to the width of the electrical transmission line 31. This ensures that the electrical connection strip 5 is completely connected to the electrical transmission line 31 in its width direction, which helps to reduce insertion loss and return loss between the electrical connection strip 5 and the electrical transmission line 31.

[0041] In some embodiments, see Figure 5 As shown, the first carrier board 1 may have a heat dissipation hole 11 at the bottom corresponding to the optical chip 2. The heat dissipation hole 11 is a through hole. By setting the heat dissipation hole 11, the optical chip 2 can be helped to dissipate heat. The power of the optical chip 2 is generally far less than the high power of the electrical chip 4. The through hole at the bottom of the optical chip 2 can achieve a certain heat dissipation effect.

[0042] Furthermore, the bottom of the first carrier plate 1 corresponding to the bottom of the second carrier plate 3 may also be provided with heat dissipation holes 11, which can further dissipate heat from the second carrier plate 3.

[0043] In some optional embodiments, the first carrier board 1 may be provided with a DC control circuit and a monitoring circuit, both of which can be electrically connected to the electrical chip 4 through the second carrier board 3. In this embodiment, by placing the DC control circuit and the monitoring circuit on the first carrier board 1, it is not necessary to place these circuits on the electrical chip 4, which can effectively solve the problem of heat dissipation difficulties caused by the high power of the electrical chip 4. Under the action of the DC control circuit and the monitoring circuit, the power supply can drive the electrical chip 4 to work normally. These circuits can be led out through the pins of the electrical chip 4 and laid on the first carrier board 1 to ensure the normal operation of the electrical chip 4.

[0044] Furthermore, in this embodiment, the electrical chip 4 can be either a conventionally mounted electrical chip 4 or a flip-chip electrical chip 4 (usually a driver), and flip-chip electrical chips 4 with higher power can also improve the overall heat dissipation performance.

[0045] In some embodiments, see Figure 1 As shown, a heat sink can be attached to the surface of the electrical chip 4. In this embodiment, the first carrier plate 1 and the second carrier plate 3 are arranged vertically, the electrical chip 4 is arranged above the second carrier plate 3, and the heat sink can be arranged on the upper surface of the electrical chip 4. That is, the heat sink and the second carrier plate 3 are distributed on opposite sides of the electrical chip 4, one located above and the other below. The heat sink attached to the upper side is conducive to dissipating the heat of the electrical chip 4 from the top.

[0046] In some alternative embodiments, see Figure 1 As shown, the optical chip 2 can be connected to an optical fiber amplifier 6 via an optical fiber 7. In this embodiment, the input port of the optical chip 2 can be connected to the optical fiber 7, and the optical fiber amplifier 6 can provide a reliable optical signal to the optical chip 2.

[0047] In related technologies, creating a large blind slot within the substrate during chip mounting can lead to uncontrollable substrate warping. This not only results in excessive wire bonding losses between the chip and the substrate but also prevents the fiber amplifier 6 from aligning with the optical input port of the optical chip 2, thus preventing the chip from receiving optical signals properly. However, this embodiment addresses this issue by using a second carrier board 3 and controlling its height. This allows the electrical transmission lines 31 of the second carrier board 3 to be on the same plane as the pads 21 of the optical chip 2. This effectively avoids the problem of the fiber amplifier 6 being unable to horizontally align with the optical input port of the optical chip 2 due to carrier board warping caused by the slot.

[0048] In some embodiments, see Figure 1 and Figure 2As shown, the first carrier board 1 may be provided with a surface transmission line 12, and a plurality of solder balls 8 are arranged between the first carrier board 1 and the second carrier board 3. The solder balls 8 are electrically connected to the surface transmission line 12 and the second carrier board 3. That is, the first carrier board 1 and the second carrier board 3 are electrically connected through a ball grid array (BGA). The method of electrical connection between the first carrier board 1 and the second carrier board 3 is not limited to this, and can be set according to specific circumstances in actual applications.

[0049] The output pads and power control pads of the electrical chip 4 can be connected to the first carrier board 1 below through the second carrier board 3 and the BGA connected at the bottom.

[0050] In this embodiment, solder balls 8 are used to connect the first carrier board 1 and the second carrier board 3. The thickness of the second carrier board 3 plus the diameter of the solder balls 8 can ensure that the pads 21 of the optical chip 2 and the electrical transmission lines 31 of the second carrier board 3 are on the same horizontal plane.

[0051] Compared with the packaging design schemes in related technologies, the optoelectronic chip packaging structure provided in this embodiment can have good three-dimensional connection in the frequency range of 0 to 40 GHz, with a simple overall structure, low process requirements, and low loss, high speed and good thermal conductivity.

[0052] Further, see Figure 6 As shown, to illustrate the innovativeness and feasibility of this application, the optoelectronic chip packaging structure of the present invention was fabricated according to the above embodiments and simulation was performed. The parameters involved in this structure are as follows: the line width of the electrical transmission line 31 of the second carrier board 3 is 0.08 mm, multiple electrical transmission lines 31 can be arranged, the spacing between two adjacent lines is 0.1 mm, the copper thickness of the surface layer of the electrical transmission line 31 is 0.02 mm, the thickness of the second carrier board 3 is 350 mm, and the dielectric material selected for the second carrier board 3 is BT972 with a dielectric constant of 3.5 and a dielectric loss of 0.003; the diameter of the solder ball 8 is 0.4 mm, and the ball center spacing is 0.8 mm; the line width of the surface transmission line 12 of the first carrier board 1 is 0.2 mm, the line spacing is 0.09 mm, the copper thickness of the surface layer of the surface transmission line 12 is 0.03 mm, the thickness of the first carrier board 1 is 0.36 mm, and the dielectric material selected for the first carrier board 1 is Rogers RO1200 with a dielectric constant of 3.05 and a dielectric loss of 0.0017. The selected optical chip 2 has a thickness of 750mm and a power of 40mW, while the selected electrical chip 4 has a thickness of 150mm and a power of 800Mw.

[0053] Combined with simulation Figure 6As can be seen, the uppermost curve is S21 (insertion loss curve), including m5 to m8. The general process requirement is that it should be greater than -3dB at a certain frequency. For example, if curve S21 is still greater than -3dB at 40GHz, it indicates that the line meets the 3dB bandwidth requirement for 40G. The lowermost curve is S11 (return loss curve), including m1 to m4. The general process requirement is less than -10dB, but the simulation results represent ideal conditions, so -20dB can be used as a baseline. In conclusion, the optoelectronic chip packaging structure of this embodiment fully meets the 40G bandwidth requirement and can be used for actual chip packaging.

[0054] This invention also provides a method for packaging an optoelectronic chip, which may include the following steps:

[0055] Step 1: Fix the optical chip 2 on the first carrier board 1. That is, a first carrier board 1 and an optical chip 2 need to be provided first, and then the optical chip 2 is fixed on the first carrier board 1. The optical chip 2 is provided with pads 21 for electrical connection.

[0056] Step 2: Fix the second carrier board 3 to the first carrier board 1, and control the height of the second carrier board 3 so that the electrical transmission lines 31 on the second carrier board 3 and the pads 21 on the optical chip 2 are substantially on the same plane. That is, it is necessary to provide a second carrier board 3 and electrically connect the second carrier board 3 to the first carrier board 1. The second carrier board 3 can be electrically connected to the electrical transmission lines 31. At the same time, when designing the second carrier board 3, it is necessary to control the height of the second carrier board 3 so that after the second carrier board 3 is installed on the first carrier board 1, the surface of the electrical transmission lines 31 on the second carrier board 3 and the surface of the pads 21 on the optical chip 2 are substantially on the same plane and kept flush.

[0057] Step 3: Electrically connect the electrical transmission line 31 to the pad 21.

[0058] Step 4: Install the electrical chip 4 onto the second carrier board 3 and electrically connect the electrical chip 4 to the electrical transmission line 31. At this time, the electrical chip 4 can be electrically connected to the optical chip 2 through the electrical transmission line 31.

[0059] Since a second carrier board 3 is set on one side of the first carrier board 1, the height of the electrical transmission line 31 on the second carrier board 3 can be adjusted so that the electrical transmission line 31 and the pad 21 on the optical chip 2 are basically on the same plane. The electrical connection between the electrical chip 4 and the optical chip 2 can be achieved through the electrical transmission line 31 and the pad 21 on the same plane. Therefore, it is not necessary to open a large blind slot on the carrier board, which can effectively solve the problem of carrier board warping.

[0060] Furthermore, the electrical connection between the electrical transmission line 31 and the pad 21 may include using an electrical connection strip 5 to electrically connect the electrical transmission line 31 and the pad 21. The electrical connection strip 5 may have a certain width, providing a relatively large contact area after connecting the electrical transmission line 31 and the pad 21, thereby improving connection strength and electrical signal transmission performance. Moreover, the electrical connection strip 5 is capable of transmitting electrical signals. The preferred material for the electrical connection strip 5 is gold, which has good electrical transmission performance. Of course, other alternative materials can also be used; any material capable of electrical transmission is acceptable.

[0061] Of course, in some other alternative embodiments, the electrical transmission line 31 can be extended so that the electrical transmission line 31 directly contacts the pad 21 to achieve electrical conduction.

[0062] Furthermore, the width of the electrical connection strip 5 is preferably set to be equal to the width of the electrical transmission line 31. This ensures that the electrical connection strip 5 is completely connected to the electrical transmission line 31 in its width direction, which helps to reduce insertion loss and return loss between the electrical connection strip 5 and the electrical transmission line 31.

[0063] In some embodiments, the first carrier board 1 may be provided with heat dissipation holes 11 at the bottom of the optical chip 2. The heat dissipation holes 11 are through holes, and by providing heat dissipation holes 11, the optical chip 2 can be helped to dissipate heat. The power of the optical chip 2 is generally far less than that of the high power of the electrical chip 4, and a certain heat dissipation effect can be achieved by using the through holes at the bottom of the optical chip 2.

[0064] Furthermore, the bottom of the first carrier plate 1 corresponding to the bottom of the second carrier plate 3 may also be provided with heat dissipation holes 11, which can further dissipate heat from the second carrier plate 3.

[0065] In some optional embodiments, the first carrier board 1 may be provided with a DC control circuit and a monitoring circuit, both of which can be electrically connected to the electrical chip 4 through the second carrier board 3. In this embodiment, by placing the DC control circuit and the monitoring circuit on the first carrier board 1, it is not necessary to place these circuits on the electrical chip 4, which can effectively solve the problem of heat dissipation difficulties caused by the high power of the electrical chip 4.

[0066] Furthermore, in this embodiment, the electrical chip 4 can be either a conventionally mounted electrical chip 4 or an inverted electrical chip 4, and the inverted mounting of the electrical chip 4 with higher power can also improve the overall heat dissipation performance.

[0067] In some embodiments, a heat sink may be attached to the surface of the electrical chip 4. In this embodiment, the first carrier plate 1 and the second carrier plate 3 are arranged vertically, the electrical chip 4 is arranged above the second carrier plate 3, and the heat sink may be arranged on the upper surface of the electrical chip 4. That is, the heat sink and the second carrier plate 3 are distributed on opposite sides of the electrical chip 4, one located above and the other below. The heat sink attached to the upper side is beneficial for dissipating the heat of the electrical chip 4 from the top.

[0068] In some optional embodiments, the optical chip 2 can be connected to an optical fiber amplifier 6 via an optical fiber 7. In this embodiment, the input port of the optical chip 2 can be connected to the optical fiber 7, and the optical fiber amplifier 6 can provide a reliable optical signal to the optical chip 2. In this embodiment, by setting a second carrier board 3 and controlling the height of the second carrier board 3, the electrical transmission line 31 of the second carrier board 3 and the pad 21 of the optical chip 2 can be located on the same plane. This method can effectively avoid the problem that the warping of the carrier board caused by the slotting can prevent the optical fiber amplifier 6 from being horizontally aligned with the optical input port of the optical chip 2 and thus from receiving the optical signal normally.

[0069] In some embodiments, the first carrier board 1 may be provided with a surface transmission line 12, and a plurality of solder balls 8 are arranged between the first carrier board 1 and the second carrier board 3. The solder balls 8 are electrically connected to the surface transmission line 12 and to the second carrier board 3. That is, the first carrier board 1 and the second carrier board 3 are electrically connected through a ball grid array (BGA). The method of electrical connection between the first carrier board 1 and the second carrier board 3 is not limited to this, and can be set according to specific circumstances in actual applications.

[0070] In the description of this invention, it should be noted that the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Unless otherwise expressly specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two elements. For those skilled in the art, the specific meaning of the above terms in this invention can be understood according to the specific circumstances.

[0071] It should be noted that in this invention, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0072] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A photoelectric chip packaging structure, characterized in that, It includes: A first carrier board (1) is provided with an optical chip (2) fixed on the first carrier board (1), and the optical chip (2) is provided with a pad (21). The second carrier board (3) and the optical chip (2) are located on the same side of the first carrier board (1). The second carrier board (3) is electrically connected to the first carrier board (1). An electrical transmission line (31) is provided on the second carrier board (3). The electrical transmission line (31) and the pad (21) are basically located on the same plane. The electrical transmission line (31) and the pad (21) are electrically connected through an electrical connection strip (5). An electrical chip (4) is mounted on the second carrier board (3) and is electrically connected to the electrical transmission line (31).

2. The optoelectronic chip packaging structure as described in claim 1, characterized in that: The width of the electrical connection strip (5) is equal to the width of the electrical transmission line (31).

3. The optoelectronic chip packaging structure as described in claim 1, characterized in that: The first carrier board (1) has heat dissipation holes (11) at the bottom corresponding to the optical chip (2).

4. The optoelectronic chip packaging structure as described in claim 1, characterized in that: The first carrier board (1) is provided with a DC control circuit and a monitoring circuit, and the DC control circuit and the monitoring circuit are electrically connected to the electrical chip (4) through the second carrier board (3).

5. The optoelectronic chip packaging structure as described in claim 1, characterized in that: The surface of the electrical chip (4) is covered with a heat sink, and the heat sink and the second carrier plate (3) are distributed on opposite sides of the electrical chip (4).

6. The optoelectronic chip packaging structure as described in claim 1, characterized in that: The optical chip (2) is connected to an optical fiber amplifier (6) via an optical fiber (7).

7. The optoelectronic chip packaging structure as described in claim 1, characterized in that: The first carrier board (1) is provided with a surface transmission line (12), and a plurality of solder balls (8) are arranged between the first carrier board (1) and the second carrier board (3). The solder balls (8) are electrically connected to the surface transmission line (12) and the solder balls (8) are electrically connected to the second carrier board (3).

8. A method for packaging an optoelectronic chip, characterized in that, It includes the following steps: The optical chip (2) is fixed on the first carrier board (1); The second carrier board (3) is fixed to the first carrier board (1), and the height of the second carrier board (3) is controlled so that the electrical transmission line (31) on the second carrier board (3) and the pad (21) on the optical chip (2) are substantially on the same plane; The electrical transmission line (31) is electrically connected to the pad (21) using an electrical connection strip (5). The electrical chip (4) is installed on the second carrier board (3) and the electrical chip (4) is electrically connected to the electrical transmission line (31).

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