Semiconductor quantum well structure for suppressing carrier lateral diffusion and preparation method thereof
By introducing island-shaped and trench-shaped nucleation structures and stacking barrier layers with different bandgap widths in silicon-based quantum well lasers, the problem of lateral carrier diffusion has been solved, improving device lifetime and performance, especially for III-V semiconductor quantum well lasers grown directly on silicon epitaxially.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING UNIV OF POSTS & TELECOMM
- Filing Date
- 2022-10-09
- Publication Date
- 2026-05-29
AI Technical Summary
Traditional silicon-based quantum well lasers suffer from high threshold current, poor high-temperature stability, and short lifetime due to lateral carrier diffusion, and their high penetration dislocation density limits performance improvement.
By employing island-shaped and/or trench-shaped nucleation structures and barrier layers with different band gap widths, semiconductor quantum well structures that suppress the lateral diffusion of charge carriers are formed through metal-organic chemical vapor deposition (MOCVD) and molecular beam epitaxy (MBE), thus restricting the diffusion of charge carriers within the quantum well plane.
Significantly reduces carrier lateral diffusion, lowers the probability of nonradiative recombination, improves the tolerance of quantum well structures to dislocations, and enhances device lifetime and performance, especially for III-V semiconductor quantum well lasers grown directly on silicon via epitaxy.
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Figure CN115663596B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor lasers and optoelectronic integration technology, specifically to a semiconductor quantum well structure and its fabrication method for suppressing lateral carrier diffusion. Background Technology
[0002] In recent years, integrated photonics has been widely used in integrated circuits on commercial integrated platforms due to its advantages in size, capacity, cost, and power consumption. Silicon-based photonics, in particular, can utilize mature CMOS equipment to produce high-quality, low-cost photonic components and provide low-loss, high-refractive-index waveguides for III-V devices. Currently, heterogeneous integration via bonding has become the main technology for obtaining on-chip III-V light sources in silicon-based photonics. However, direct epitaxial growth, as the next-generation heterogeneous integration solution, has gained favor from many electronic chip manufacturers and research institutions worldwide. Direct epitaxial growth of III-V semiconductor device structures on silicon leads to high-density defects due to the crystal differences between silicon and III-V materials. Defects such as thermal cracks, antiphase domains, and through-dislocations significantly degrade the performance of active devices. Although research over the past two decades has largely solved the problems of thermal cracks and antiphase domains, the situation remains complex. 6 / cm 2 The order-of-magnitude penetration dislocation density still limits the development of direct epitaxial III-V group active devices on silicon, especially silicon-based quantum well lasers.
[0003] Because quantum wells have a layered structure, traditional quantum well structures cannot provide three-dimensional confinement of charge carriers in the active region like quantum dot structures. They only have epitaxial confinement without lateral confinement, making it easier for laterally diffused electrons and holes to enter dislocation regions and undergo nonradiative recombination. Consequently, directly epitaxially grown silicon-based quantum well lasers suffer from high threshold current, poor high-temperature stability, and extremely short lifetimes. With techniques for reducing penetrating dislocation density nearing their limits, a novel quantum well structure is urgently needed to suppress lateral carrier diffusion, reduce the probability of charge carriers reaching dislocation regions, and thus decrease the probability of nonradiative recombination in the active region. This would improve the dislocation tolerance of the quantum well structure, thereby enhancing the performance of semiconductor quantum well devices, including silicon-based directly epitaxially grown quantum well lasers. Furthermore, this structure differs from quantum dot structures in that its gain region remains a two-dimensional layered structure, rather than a three-dimensional island structure like quantum dots. Summary of the Invention
[0004] To address the aforementioned technical problems, this invention provides a semiconductor quantum well structure for suppressing lateral carrier diffusion and its fabrication method.
[0005] In a first aspect, the semiconductor quantum well structure for suppressing lateral diffusion of charge carriers provided in the embodiments of the present invention includes a lower barrier layer, a quantum well layer, a nucleation structure, and an upper barrier layer stacked sequentially; wherein the morphology of the nucleation structure is island-shaped and / or trench-shaped, and the nucleation structure does not completely cover the quantum well layer; the band gap width of the nucleation structure is not equal to the band gap width of the upper barrier layer.
[0006] The III-V semiconductor quantum well structure and its epitaxial growth method provided by this invention can significantly reduce the lateral diffusion length of charge carriers in the quantum well plane, suppress lateral diffusion of charge carriers, thereby reducing the probability of nonradiative recombination and improving the tolerance of the quantum well structure to dislocations. This has a significant improvement on the performance of lasers using this quantum well structure as the active region, especially the device lifetime of III-V semiconductor quantum well lasers directly epitaxially grown on silicon. The epitaxial growth method of this structure is simple and does not increase the complexity of post-processing, so it is suitable as the active region of high-performance III-V semiconductor quantum well lasers, especially III-V semiconductor quantum well lasers directly epitaxially grown on silicon.
[0007] Preferably, the nucleation structures are island-shaped and / or trench-shaped and are not completely adjacent to each other, that is, the nucleation structures do not completely cover the quantum well layer.
[0008] Further preferably, the band gap width of the quantum well layer is smaller than the band gap widths of the lower barrier layer, the nucleation structure, and the upper barrier layer. The charge carriers in the quantum well layer are confined by the quantum dots of the lower barrier layer, the nucleation structure, and the upper barrier layer.
[0009] Further preferably, the thickness of the lower barrier layer is 5 nm to 1000 nm; the thickness of the quantum well layer is 2 nm to 30 nm; the height of the nucleation structure is 0.1 nm to 30 nm; and the thickness of the upper barrier layer is 5 nm to 1000 nm. The lower barrier layer, the nucleation structure, and the upper barrier layer together confine the charge carriers in the quantum well layer.
[0010] Further preferably, the semiconductor quantum well structure is a III-V group semiconductor multi-quantum well structure; preferably, in the semiconductor quantum well structure, the lower barrier layer, quantum well layer, nucleation structure, and upper barrier layer are repeated as a whole to form a multi-period quantum well structure, and the stacking order of each repetition is the same: lower barrier layer, quantum well layer, nucleation structure, and upper barrier layer. In each period, the quantum well layer is subject to the quantum confinement effects of the lower barrier layer below it, the nucleation structure above it, and the upper barrier layer above it.
[0011] Preferably, the lower barrier layer, the quantum well layer, the nucleation structure, and the upper barrier layer are all made of III-V group semiconductor materials; the III-V group semiconductor materials include one or more of GaP-based, GaAs-based, InP-based, and GaSb-based materials, preferably GaAs-based or InP-based materials. In this invention, the III-V group semiconductor materials include, but are not limited to, binary compounds such as AlP, GaP, AlAs, GaAs, InP, and GaSb; ternary compounds such as GaAsP, InGaAs, AlGaAs, InGaP, and GaAsSb; and quaternary compounds such as InAlGaAs, AlGaAsP, InGaAsP, and InGaAsSb. The structure of this invention must meet the requirement that the bandgap width of the nucleation structure is not equal to the bandgap width of the upper barrier layer, and the quantum well layer has the smallest bandgap; no specific material type is limited.
[0012] Further preferably, the lateral diffusion of charge carriers in the semiconductor quantum well structure within the quantum well plane is suppressed. According to the present invention, the lateral diffusion of charge carriers in the quantum well structure within the quantum well plane is suppressed, reducing the probability of charge carriers diffusing laterally to dislocation regions, thereby reducing the probability of nonradiative recombination of charge carriers in dislocation regions of the quantum well and improving the tolerance of the quantum well structure to dislocations.
[0013] Secondly, the method for fabricating the semiconductor quantum well structure for suppressing lateral carrier diffusion provided in the embodiments of the present invention, using metal-organic chemical vapor deposition (MOCVD) and / or molecular beam epitaxy (MBE) for growth, includes the following steps:
[0014] A) Growth of the lower barrier layer;
[0015] B) Growth of quantum well layers;
[0016] C) Growth and nucleation structure;
[0017] D) Growth of the upper barrier layer.
[0018] Further preferred, in step C), a nucleation structure is grown on the quantum well (001) plane.
[0019] Preferably, the semiconductor quantum well structure adopts a multi-quantum well structure; preferably, steps A, B, C and D are repeated as a whole, and the order of steps A, B, C and D remains unchanged in each repetition, and the number of repetitions is no more than 10 times, preferably 2 times.
[0020] Preferably, the quantum well structure is grown directly on the substrate, or other structures are grown on the substrate first, and then the quantum well structure is grown; other structures can be grown after the quantum well structure is grown.
[0021] Preferably, the substrate is grown on a Si(001) substrate, a GaAs(001) substrate or an InP(001) substrate, and the epitaxial surface of the substrate is a non-biased (001) crystal plane or a biased (001) crystal plane.
[0022] Further preferably, in step C, the morphology of the grown nucleation structure is island-shaped and / or trench-shaped; preferably, the nucleation structure is a nucleation island and / or a nucleation trench, and each nucleation island and / or nucleation trench is not adjacent to each other; the growth height of the nucleation structure is 0.1 nm to 30 nm, the band gap width of the nucleation structure is not equal to the band gap width of the quantum well layer, and the band gap width of the nucleation structure is not equal to the band gap width of the upper barrier layer.
[0023] Further optimization involves using the III-V group semiconductor quantum well structure as the active region laser, which can reduce the lateral diffusion of charge carriers in the active region plane of the quantum well and reduce the probability of nonradiative recombination of charge carriers in the dislocation region, thereby improving the lasing performance of the device.
[0024] Thirdly, the semiconductor quantum well device provided in the embodiments of the present invention includes the semiconductor quantum well structure for suppressing lateral diffusion of charge carriers or the semiconductor quantum well structure prepared by the method for preparing the semiconductor quantum well structure for suppressing lateral diffusion of charge carriers; the semiconductor quantum well device includes: a quantum well laser, a quantum well superluminescent diode, a quantum well light-emitting diode, a quantum well optical amplifier, and a quantum well photodetector.
[0025] The beneficial effects of this invention are at least as follows: the band gap width of the material in the III-V group nucleation structure is different from that of the material in the upper barrier layer, and the nucleation structure does not completely cover the quantum well layer; that is, the upper barrier layer also contacts the quantum well layer. Therefore, regions with different barrier heights are divided on the quantum well plane. Within these regions, the quantum confinement provided by the barrier differs, meaning the quantum confinement of charge carriers varies. This creates a barrier difference between the different regions within the quantum well, hindering the lateral movement of charge carriers (within the quantum well plane), thus suppressing their movement. When the lateral diffusion of charge carriers within the quantum well is suppressed, the probability of them reaching the dislocation region and undergoing nonradiative recombination decreases. Therefore, compared with the traditional III-V semiconductor quantum well structure, the quantum well structure provided by this invention has a higher tolerance for dislocations. The performance of semiconductor devices using the quantum well structure described in this invention will be significantly improved, especially for heteroepitaxial silicon III-V semiconductor quantum well lasers, whose device lifetime is greatly increased. At the same time, this structure is different from the quantum dot structure. Its gain region is still a two-dimensional layered structure, rather than a three-dimensional island structure like quantum dots. Moreover, the band gap width of the quantum well layer is the smallest in this structure, which is different from the smallest band gap width of the quantum dots in the quantum dot structure. Attached Figure Description
[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to actual scale. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0027] Figure 1 A schematic diagram of a group III-V semiconductor quantum well structure for suppressing lateral carrier diffusion on a GaAs substrate provided in an embodiment of the present invention;
[0028] Figure 2 An atomic force microscope (AFM) scan morphology image of the AlGaAs nucleation structure on the InGaAs quantum well (001) plane provided in an embodiment of the present invention, with a scan size of 1 μm × 1 μm;
[0029] Figure 3 This is a schematic diagram of a silicon heteroepitaxial III-V group semiconductor quantum well laser structure that uses the III-V group semiconductor quantum well structure that suppresses the lateral diffusion of charge carriers as the active region, provided in an embodiment of the present invention. Detailed Implementation
[0030] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.
[0031] Where specific techniques or conditions are not specified in the embodiments, they shall be performed in accordance with the techniques or conditions described in the literature in this field, or in accordance with the product manual. Instruments and other equipment whose manufacturers are not specified are all conventional products that can be purchased through legitimate channels. Unless otherwise specified, the methods described are conventional methods, and the raw materials described are all obtainable from publicly available commercial sources. Where specific techniques or conditions are not specified in the embodiments, they shall be performed in accordance with the techniques or conditions described in the literature in this field, or in accordance with the product manual.
[0032] The following examples are used to illustrate the present invention, but are not intended to limit the scope of the invention.
[0033] In the description of this invention, unless otherwise stated, the terms "upper," "lower," "inner," "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the invention and simplifying the description, and are not intended to indicate or imply that the system or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention.
[0034] Example 1
[0035] This embodiment describes the epitaxial growth of a GaAs buffer layer on a GaAs substrate, followed by the growth of a quantum well structure containing nucleation structures. The growth scheme for group III-V semiconductor quantum well structures on GaAs substrates provided in this embodiment can significantly suppress the lateral diffusion of internal carriers in the quantum well. In this embodiment, a (001) GaAs substrate is used, an MBE epitaxial device is employed, the group III sources are Al, Ga, and In, and the group V source is As.
[0036] like Figure 1 As shown in the figure, this embodiment provides a growth scheme for a group III-V semiconductor quantum well structure on a GaAs substrate, and the specific steps are as follows:
[0037] S101, after heating and degassing, the GaAs substrate is placed in the growth chamber and heated in an As atmosphere to perform deoxidation treatment.
[0038] S102 uses As as a group V source and Ga as a group III source to grow a 300nm GaAs layer, i.e., a GaAs buffer layer.
[0039] S103, using As as a group V source and Al and Ga as group III sources, grows a 50nm AlGaAs lower barrier layer, in which the Al composition is 0.2.
[0040] S104, using As as a group V source and In and Ga as group III sources, grows a 10 nm InGaAs quantum well layer, where the In composition is 0.2;
[0041] S105 uses As as a group V source and Al and Ga as group III sources to grow an AlGaAs nucleation layer with an equivalent thickness of 1 nm, wherein the Al composition is not less than 0.95. Since the nucleation layer does not completely cover the quantum well layer, its height is greater than the equivalent thickness.
[0042] S106, using As as a group V source and Al and Ga as group III sources, grows a 50nm AlGaAs top barrier layer, where the Al composition is 0.2.
[0043] like Figure 2 As shown in the figure, this is a UID-Al grown on the (001) plane of an InGaAs quantum well.0.95 Ga 0.05 As the AFM morphology diagram of the nucleation structure, it can be clearly seen that the island-shaped and groove-shaped nucleation structures are randomly distributed on the plane, and there is no connection between each nucleation island and nucleation groove. This surface morphology can effectively play a regional quantum confinement effect on the quantum well.
[0044] Example 2
[0045] This embodiment describes a silicon-based direct epitaxial growth of a III-V group semiconductor quantum well laser using the aforementioned semiconductor III-V quantum well structure that suppresses lateral carrier diffusion as the active region. A GaAs buffer layer is first epitaxially grown on a pretreated silicon substrate, followed by the sequential growth of an N-type GaAs contact layer, an N-type AlGaAs confinement layer, the semiconductor III-V quantum well structure that suppresses lateral carrier diffusion, a P-type AlGaAs confinement layer, and a P-type GaAs contact layer. This embodiment provides a growth scheme for directly epitaxially growing a III-V group semiconductor quantum well laser structure on silicon, which significantly suppresses lateral carrier diffusion in the active region, thereby improving the performance of the device fabricated accordingly. In this embodiment, a Si(001) substrate with a
[110] orientation offset of 4° is used as the silicon substrate. The epitaxial equipment used is an MBE (Metal-Based Electrode), and the group III sources in the growth chamber are Al, Ga, and In; the group V source is As; and the doping sources are Si and Be.
[0046] like Figure 3 As shown in the figure, this embodiment provides a growth scheme for directly epitaxially growing a group III-V semiconductor quantum well laser structure on silicon. The specific steps are as follows:
[0047] S201: After cleaning and degassing, the silicon substrate is placed in the chamber and subjected to high-temperature deoxidation treatment in an As atmosphere.
[0048] S202 uses As as a group V source and Ga as a group III source to grow a GaAs buffer layer structure on a silicon substrate, including: growing a 30nm GaAs layer at 300℃; growing a 100nm GaAs layer at 350℃; growing a 150nm GaAs layer at 500℃; and growing a 1000nm GaAs layer at 560℃.
[0049] S203, using As as a group V source, Ga as a group III source, and Si as a dopant source, grows a 500 nm N-type GaAs contact layer with a doping concentration of 4 × 10⁻⁶. 18 / cm 3 ;
[0050] S204, using As as a group V source, Al and Ga as group III sources, and Si as a doping source, grows 1500 nm N-type Al. 0.4 Ga0.6 As lower confinement layer, doping concentration is 1×10 18 / cm 3 ;
[0051] S205, using As as a group V source and Al and Ga as group III sources, grows 100nm Al 0.2 Ga 0.8 As the lower barrier layer;
[0052] S206, using As as a group V source and In and Ga as group III sources, grows 10nm In... 0.2 Ga 0.83 As a quantum well;
[0053] S207, using As as a group V source and Al and Ga as group III sources, grows Al with an equivalent thickness of 1 nm. 0.95 Ga 0.05 As nucleation structure;
[0054] S208, using As as a group V source and Al and Ga as group III sources, grows 100nm Al. 0.2 Ga 0.8 As the upper potential barrier layer;
[0055] S209, using As as a group V source, Al and Ga as group III sources, and Be as a doping source, grows 1500 nm p-type Al. 0.4 Ga 0.6 As confinement layer, doping concentration is 1×10⁻⁶ 18 / cm 3 ;
[0056] S210, using As as a group V source, Ga as a group III source, and Be as a dopant source, grows a 200 nm p-type GaAs contact layer with a doping concentration of 2 × 10⁻⁶. 19 / cm 3 .
[0057] Although the present invention has been described in detail above with general descriptions and specific embodiments, modifications or improvements can be made to it, which will be obvious to those skilled in the art. Therefore, all such modifications or improvements made without departing from the spirit of the present invention fall within the scope of protection claimed by the present invention.
Claims
1. A semiconductor quantum well structure for suppressing lateral carrier diffusion, characterized in that, A semiconductor quantum well structure for suppressing lateral carrier diffusion includes a lower barrier layer, a quantum well layer, a nucleation structure, and an upper barrier layer stacked sequentially. The nucleation structure comprises nucleation islands and / or nucleation trenches grown on the quantum well layer, with no adjoining areas between each nucleation island and / or trench. The nucleation structure does not completely cover the quantum well layer. The bandgap width of the nucleation structure is not equal to the bandgap width of the upper barrier layer, and the bandgap width of the quantum well layer is smaller than the bandgap widths of the lower barrier layer, the nucleation structure, and the upper barrier layer. The thickness of the lower barrier layer is 5 nm to 1000 nm. The thickness of the quantum well layer is 2 nm to 30 nm. The height of the nucleation structure is 0.1 nm to 30 nm. The thickness of the upper barrier layer is 5 nm to 1000 nm.
2. The semiconductor quantum well structure for suppressing lateral carrier diffusion according to claim 1, characterized in that, The semiconductor quantum well structure is a III-V group semiconductor multiple quantum well structure.
3. The semiconductor quantum well structure for suppressing lateral carrier diffusion according to claim 2, characterized in that, In the semiconductor quantum well structure, the lower barrier layer, quantum well layer, nucleation structure and upper barrier layer are repeated as a whole to form a multi-period quantum well structure. The stacking order of each repetition is the lower barrier layer, quantum well layer, nucleation structure and upper barrier layer.
4. The semiconductor quantum well structure for suppressing lateral carrier diffusion according to claim 1, characterized in that, The lower barrier layer, the quantum well layer, the nucleation structure, and the upper barrier layer are all made of III-V semiconductor materials; the III-V semiconductor materials include one or more of GaP-based, GaAs-based, InP-based, and GaSb-based materials.
5. The semiconductor quantum well structure for suppressing lateral carrier diffusion according to claim 4, characterized in that, The III-V group semiconductor materials are GaAs-based and InP-based materials.
6. The semiconductor quantum well structure for suppressing lateral carrier diffusion according to any one of claims 1-5, characterized in that, The lateral diffusion of charge carriers in the semiconductor quantum well structure within the quantum well plane is suppressed.
7. A method for preparing a semiconductor quantum well structure for suppressing lateral carrier diffusion as described in any one of claims 1-6, characterized in that, Growth is performed using metal-organic chemical vapor deposition and / or molecular beam epitaxy, including the following steps: A) Growth of the lower barrier layer; B) Growth of quantum well layers; C) Growth and nucleation structure; D) Growth of the upper barrier layer.
8. The method for fabricating a semiconductor quantum well structure for suppressing lateral carrier diffusion according to claim 7, characterized in that, The semiconductor quantum well structure adopts a multi-quantum well structure.
9. The method for fabricating a semiconductor quantum well structure for suppressing lateral carrier diffusion according to claim 8, characterized in that, Repeat steps A), B), C), and D) as a whole, keeping the order of steps A), B), C), and D) unchanged in each repetition, and repeat no more than 10 times.
10. The method for fabricating a semiconductor quantum well structure for suppressing lateral carrier diffusion according to claim 9, characterized in that, The repetition number is 2 times.
11. The method for fabricating a semiconductor quantum well structure for suppressing lateral carrier diffusion according to any one of claims 7-10, characterized in that, The nucleation structure grown in step C) is a nucleation island and / or a nucleation trench, and each nucleation island and / or nucleation trench is not adjacent to each other; the growth height of the nucleation structure is 0.1 nm to 30 nm, the band gap width of the nucleation structure is not equal to the band gap width of the quantum well layer, and the band gap width of the nucleation structure is not equal to the band gap width of the upper barrier layer.
12. A semiconductor quantum well device, characterized in that, The semiconductor quantum well structure comprising the semiconductor quantum well structure for suppressing lateral diffusion of charge carriers as described in any one of claims 1-6 or the semiconductor quantum well structure for suppressing lateral diffusion of charge carriers as described in any one of claims 7-11; The semiconductor quantum well device includes: a quantum well laser, a quantum well superluminescent diode, a quantum well light-emitting diode, a quantum well optical amplifier, and a quantum well photodetector.