An adjustable low-pass filter circuit based on self-biased pseudo-resistor

Abstract

The application discloses a kind of adjustable low-pass filter circuits based on self-bias pseudo resistance, the filter circuit includes: self-bias pseudo resistance circuit, differential source follower circuit and gain compensation circuit.The self-bias pseudo resistance circuit is made of back-to-back PMOS transistor, and its gate-source voltage is controlled by the direct current component of system input signal and output signal, so as to realize the function of adjustable large resistance;The differential source follower circuit uses common-drain amplifier, and converts passive amplifier into active amplifier with large input impedance and medium output impedance, while providing stable adjustable bias for the above-mentioned pseudo resistance;The gain compensation circuit is used to compensate for the gain loss of the common-drain amplifier due to the substrate effect.The low-pass filter circuit of the application can achieve considerable time constant with very small chip area and power consumption, and can be used in wearable physiological signal detection device, with the advantages of low power consumption, small area, high stability and the like.

Description

Technical Field

[0001] This invention relates to the field of filter circuit design technology for wearable physiological signal detection devices, and particularly to an adjustable low-pass filter circuit based on a self-biased pseudo-resistor. Background Technology

[0002] In biomedical applications, long-term stable detection of physiological signals (such as electrocardiogram, electroencephalogram, and electromyography) is of great significance. The vast majority of human physiological signals operate between sub-hertz and kilohertz frequencies. Therefore, when designing wearable on-chip systems for physiological signal detection, filters are often used to remove interference and noise from outside the signal. Furthermore, CMOS instrumentation amplifiers are widely used in the signal acquisition front end. To remove noise (mainly low-frequency flicker noise) and offset from the amplifier circuit itself, designers typically use chopping techniques to shift low-frequency noise generated in the circuit to higher frequencies, thus separating it from the low-frequency physiological signal frequency domain. However, the ripple shifted to higher frequencies, i.e., modulation noise, still requires circuit techniques for removal. Many ripple suppression techniques have been proposed in recent years, but these techniques often consume a large amount of power consumption area and are complex to design. The simplest and most effective way to solve this problem remains the use of low-pass filters.

[0003] Based on the stage of signal processing, filters can be divided into analog filters and digital filters. Analog filters filter signals before they are digitized by an analog-to-digital converter (ADC), processing analog signals and often relying on specific circuit designs for implementation. Digital filters, on the other hand, process signals after they have been digitized by the ADC, processing digital signals and generally using a general-purpose digital signal processor (DSP). To achieve the same filtering effect, digital filters often rely on high-performance ADCs, which significantly increases the overall cost, power consumption, and complexity of the system. Analog filters, because they process signals before the ADC, are not dependent on the ADC's performance. Analog filters can also be divided into passive analog filters and active analog filters based on the electronic components they use. Passive analog filters generally use passive electronic components such as resistors, capacitors, and inductors, while active analog filters, in addition to resistors, capacitors, and inductors, also contain transistors or operational amplifiers and require an independent power supply.

[0004] Due to the low-frequency characteristics of physiological signals, the low-pass filter used requires a large time constant, i.e., a low cutoff frequency. For passive analog low-pass filters, achieving the required cutoff frequency requires large resistors or capacitors, which is difficult to achieve with a small chip area in standard CMOS integrated circuits. Increased chip area means both a larger overall system size and a significant increase in cost. For wearable physiological signal detection devices, the size and power consumption of the filter are crucial.

[0005] Because passive analog low-pass filters require a large chip area, many active analog low-pass filters have been proposed in recent years, including active resistor-capacitor structures, transconductance-capacitor structures, and active field-effect transistor-capacitor structures. The core idea is to achieve a large equivalent resistance through active circuitry, thereby achieving a large time constant. Since capacitors occupy a significant amount of chip area in integrated circuits, the capacitors used in these structures are generally limited to tens of pF or less. When achieving a large time constant, these technologies face similar design challenges: generating extremely low bias currents, typically in the pA range, to achieve extremely low transconductance or extremely high equivalent resistance. This presents significant design difficulties, and circuit stability is often hard to guarantee. Transistors operating in subthreshold states typically have extremely high resistance values ​​and are therefore called pseudo-resistors. Pseudo-resistors consume very little chip area, but due to their nonlinear characteristics, even small voltage fluctuations can cause large resistance changes. Therefore, additional complex bias circuitry is usually required to improve their stability, which in turn increases the overall power consumption and area of ​​the system. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention provides an adjustable low-pass filter circuit based on a self-biased pseudo-resistor. This circuit has a very small integrated footprint and is an active analog low-pass filter circuit with low power consumption and high stability. It aims to solve the problems of large area, high power consumption, and poor stability in current low-pass filter circuits.

[0007] The objective of this invention is achieved through the following technical solution:

[0008] An adjustable low-pass filter circuit based on a self-biased pseudo-resistor includes a circuit input terminal, a self-biased pseudo-resistor circuit, a differential source follower circuit, a gain compensation circuit, a first-stage capacitor, a second-stage capacitor, and a circuit output terminal connected in sequence; wherein, the first-stage capacitor includes a first capacitor and a second capacitor, and the second-stage capacitor is a third capacitor.

[0009] The circuit input terminal is connected to the input terminal of the self-biased pseudo-resistor circuit. The first capacitor and the second capacitor are connected to the intermediate node and the gate of the self-biased pseudo-resistor circuit, respectively. The two ends of the third capacitor are connected to the positive and negative output terminals of the self-biased pseudo-resistor circuit. The input terminal of the differential source follower circuit is connected to the output terminal of the self-biased pseudo-resistor circuit. The input of the gain compensation circuit is connected to the output of the differential source follower circuit. The output terminal of the gain compensation circuit is connected to the circuit output terminal.

[0010] Specifically, the self-biased pseudo-resistor circuit includes: a first P-channel transistor, a second P-channel transistor, a third P-channel transistor, a fourth P-channel transistor, a fifth P-channel transistor, a sixth P-channel transistor, a seventh P-channel transistor, and an eighth P-channel transistor.

[0011] The first P-channel transistor and the second P-channel transistor form a first pseudo-resistor; the third P-channel transistor and the fourth P-channel transistor form a second pseudo-resistor; the fifth P-channel transistor and the sixth P-channel transistor form a third pseudo-resistor; and the seventh P-channel transistor and the eighth P-channel transistor form a fourth pseudo-resistor. One end of the first pseudo-resistor is connected to the positive input terminal of the circuit, and the other end of the first pseudo-resistor is connected to one end of the second pseudo-resistor. The other end of the second pseudo-resistor is connected to one end of the third capacitor and the differential source follower circuit. One end of the third pseudo-resistor is connected to the negative input terminal of the circuit, and the other end of the third pseudo-resistor is connected to one end of the fourth pseudo-resistor. The other end of the fourth pseudo-resistor is connected to the other end of the third capacitor and the differential source follower circuit.

[0012] One end of the first capacitor is connected to the common connection terminal of the first pseudo resistor and the second pseudo resistor, and the other end of the first capacitor is connected to the gate of the first pseudo resistor and the second pseudo resistor; one end of the second capacitor is connected to the common connection terminal of the third pseudo resistor and the fourth pseudo resistor, and the other end of the second capacitor is connected to the gate of the third pseudo resistor and the fourth pseudo resistor.

[0013] Specifically, the differential source follower circuit includes a first N-channel transistor, a second N-channel transistor, a third N-channel transistor, and a fourth N-channel transistor; the gate of the first N-channel transistor is connected to the self-biasing pseudo-resistor, the drain of the first N-channel transistor is connected to the power supply terminal, the source of the first N-channel transistor is connected to the drain of the second N-channel transistor, the gate of the second N-channel transistor is connected to an external voltage bias, the source of the second N-channel transistor is grounded, the source of the third N-channel transistor is grounded, the gate of the third N-channel transistor is connected to an external voltage bias, the drain of the third N-channel transistor is connected to the source of the fourth N-channel transistor, the gate of the fourth N-channel transistor is connected to the self-biasing pseudo-resistor, and the drain of the fourth N-channel transistor is connected to the power supply terminal.

[0014] Specifically, the gain compensation circuit includes a ninth P-channel transistor, a tenth P-channel transistor, and an eleventh P-channel transistor; the source of the ninth P-channel transistor is connected to a power supply, the gate is connected to an external bias voltage, and the drain is connected to the sources of the tenth P-channel transistor and the eleventh P-channel transistor; the gate and drain of the tenth P-channel transistor are connected to the differential source follower circuit, and the gate and drain of the eleventh P-channel transistor are connected to the differential source follower circuit; the sources of the tenth P-channel transistor and the eleventh P-channel transistor are connected to the output terminal of the circuit.

[0015] Furthermore, the self-biased pseudo-resistor circuit is generated by biasing the output of the differential source follower circuit with its input to a pseudo-resistor acted by a transistor. Since the output DC voltage of the differential source follower can be adjusted by its bias current, it has the ability to adjust the bias of the pseudo-resistor. This circuit uses a very small chip area to generate a stable and adjustable ultra-large resistance value, thereby enabling the circuit to have a low-pass filtering function with an adjustable cutoff frequency.

[0016] Furthermore, the differential source follower circuit is a classic common-drain amplifier circuit that buffers the input signal, giving the circuit an input impedance and an appropriate output impedance. At the same time, its output DC voltage can provide voltage bias for the pseudo-resistors acted by transistors.

[0017] Furthermore, the gain compensation circuit compensates the output current by passing the input voltage signal through the transconductance of the P-channel transistor, thereby compensating for the filter gain loss caused by the non-ideal characteristics of the transistor.

[0018] The beneficial effects of this invention are as follows:

[0019] A considerable adjustable time constant can be achieved with an extremely small chip area and power consumption, meaning this low-pass filter can generate an extremely low adjustable cutoff frequency. Since most physiological signals have low-frequency characteristics, this low-pass filter can be used in wearable physiological signal detection devices, offering advantages such as low power consumption, small size, and high stability. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the embodiments will be briefly described below.

[0021] Figure 1 This is a hardware implementation circuit diagram of the adjustable low-pass filter circuit based on a self-biased pseudo-resistor of the present invention.

[0022] Figure 2 This is a schematic diagram of the physiological signal acquisition front end proposed in an embodiment of the present invention.

[0023] Reference numerals: Filter circuit 100, positive signal input terminal 101, negative signal input terminal 102, first P-channel transistor 103, second P-channel transistor 104, third P-channel transistor 105, fourth P-channel transistor 106, fifth P-channel transistor 108, sixth P-channel transistor 109, seventh P-channel transistor 110, eighth P-channel transistor 111, first capacitor 107, second capacitor 112, third capacitor 113, first N-channel transistor 115, second N-channel transistor 116, third N-channel transistor 117, fourth N-channel transistor 118, ground 119, differential source follower circuit power supply 120, differential source follower circuit bias voltage 114 121, 122, 125, 126, 127, 128, 129, 120, 120, 121, 120, 121, 122, 123, 124, 125, 126, 128, 129, 120, 120, 120, 120, 120, 120, 120, 120, 201, 202, 203, 202, 204, 205, 206, 207, 208, 200, 200, 201, 20 ... Detailed Implementation

[0024] The purpose of this invention is to provide an adjustable low-pass filter circuit that features low area cost after integration, low power consumption, and high stability. To make the above-mentioned objectives, features, and advantages of this invention more apparent and understandable, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0025] An adjustable low-pass filter circuit based on a self-biased pseudo-resistor includes a circuit input terminal, a self-biased pseudo-resistor circuit, a differential source follower circuit, a gain compensation circuit, a first-stage capacitor, a second-stage capacitor, and a circuit output terminal connected in sequence; wherein, the first-stage capacitor includes a first capacitor 107 and a second capacitor 112, and the second-stage capacitor is a third capacitor 113.

[0026] The circuit input terminal is connected to the input terminal of the self-biased pseudo-resistor circuit. The first capacitor 107 and the second capacitor 112 are respectively connected to the intermediate node and the gate of the self-biased pseudo-resistor circuit. The two ends of the third capacitor are connected to the positive and negative output terminals of the self-biased pseudo-resistor circuit. The input terminal of the differential source follower circuit is connected to the output terminal of the self-biased pseudo-resistor circuit. The input of the gain compensation circuit is connected to the output of the differential source follower circuit. The output terminal of the gain compensation circuit is connected to the circuit output terminal.

[0027] The self-biased pseudo-resistor circuit includes: a first P-channel transistor 103, a second P-channel transistor 104, a third P-channel transistor 105, a fourth P-channel transistor 106, a fifth P-channel transistor 108, a sixth P-channel transistor 109, a seventh P-channel transistor 110, and an eighth P-channel transistor 111.

[0028] The first P-channel transistor 103 and the second P-channel transistor 104 form a first pseudo-resistor; the third P-channel transistor 105 and the fourth P-channel transistor 106 form a second pseudo-resistor; the fifth P-channel transistor 108 and the sixth P-channel transistor 109 form a third pseudo-resistor; and the seventh P-channel transistor 110 and the eighth P-channel transistor 111 form a fourth pseudo-resistor. One end of the first pseudo-resistor is connected to the positive input terminal of the circuit, and the other end of the first pseudo-resistor is connected to one end of the second pseudo-resistor. The other end of the second pseudo-resistor is connected to one end of the third capacitor and the differential source follower circuit. One end of the third pseudo-resistor is connected to the negative input terminal of the circuit, and the other end of the third pseudo-resistor is connected to one end of the fourth pseudo-resistor. The other end of the fourth pseudo-resistor is connected to the other end of the third capacitor and the differential source follower circuit.

[0029] One end of the first capacitor is connected to the common connection terminal of the first pseudo resistor and the second pseudo resistor, and the other end of the first capacitor is connected to the gate of the first pseudo resistor and the second pseudo resistor; one end of the second capacitor is connected to the common connection terminal of the third pseudo resistor and the fourth pseudo resistor, and the other end of the second capacitor is connected to the gate of the third pseudo resistor and the fourth pseudo resistor.

[0030] The differential source follower circuit includes a first N-channel transistor 115, a second N-channel transistor 116, a third N-channel transistor 117, and a fourth N-channel transistor 118. The gate of the first N-channel transistor 115 is connected to the self-biasing pseudo-resistor, the drain of the first N-channel transistor 115 is connected to the power supply terminal, the source of the first N-channel transistor 115 is connected to the drain of the second N-channel transistor 116, the gate of the second N-channel transistor 116 is biased by an external voltage, the source of the second N-channel transistor is grounded, the source of the third N-channel transistor 117 is grounded, the gate of the third N-channel transistor 117 is biased by an external voltage, the drain of the third N-channel transistor 117 is connected to the source of the fourth N-channel transistor 118, the gate of the fourth N-channel transistor 118 is connected to the self-biasing pseudo-resistor, and the drain of the fourth N-channel transistor 118 is connected to the power supply terminal.

[0031] The gain compensation circuit includes a ninth P-channel transistor 125, a tenth P-channel transistor 121, and an eleventh P-channel transistor 122. The source of the ninth P-channel transistor is connected to a power supply, the gate is connected to an external bias voltage, and the drain is connected to the sources of the tenth and eleventh P-channel transistors. The gate and drain of the tenth P-channel transistor are connected to the differential source follower circuit, and the gate and drain of the eleventh P-channel transistor are also connected to the differential source follower circuit. The sources of the tenth and eleventh P-channel transistors are connected to the output terminal of the circuit.

[0032] Figure 1 This is a hardware implementation circuit diagram of the adjustable low-pass filter based on a self-biased pseudo-resistor according to the present invention. Figure 1As shown in the filter circuit 100, the physiological electrical signal is input to the low-pass filter circuit through the positive input terminal 101 and the negative input terminal 102. The small signal is buffered by the first N-channel transistor 115 and the fourth N-channel transistor 118 and output from the sources of the first N-channel transistor 115 and the fourth N-channel transistor 118. The second N-channel transistor 116 and the third N-channel transistor 117 provide bias current 128 to the first N-channel transistor 115 and the fourth N-channel transistor 118. The first N-channel transistor 115, the second N-channel transistor 116, the third N-channel transistor 117, and the fourth N-channel transistor 118 together constitute a differential source follower circuit. While buffering the input physiological signal, its large output signal is fed back to the gates of the four sets of pseudo-resistors, biasing the four sets of pseudo-resistors. Since the large signal output from the sources of the first N-channel transistor 115 and the fourth N-channel transistor 118 depends on the magnitude of the bias current 128 provided by the second N-channel transistor 116 and the third N-channel transistor 117, the value of the large signal output from the sources of the first N-channel transistor 115 and the fourth N-channel transistor 118 can be controlled by adjusting the bias current 128. This changes the gate voltage of the pseudo-resistors, thus regulating the gate-source voltage of the pseudo-resistors and affecting their resistance value. Therefore, the four sets of pseudo-resistors can be considered as traditional adjustable resistors, and their adjustment is determined by the bias current 128 of the source follower. At this point, the four sets of resistors (first P-channel transistor 103, second P-channel transistor 104, third P-channel transistor 105, fourth P-channel transistor 106, fifth P-channel transistor 108, sixth P-channel transistor 109, seventh P-channel transistor 110, and eighth P-channel transistor 111), capacitors (first capacitor 107, second capacitor 112, and third capacitor 113), and source followers (first N-channel transistor 115, second N-channel transistor 116, third N-channel transistor 117, and fourth N-channel transistor 118) in the diagram form a second-order Sallen-Key filter circuit. Its cutoff frequency depends on the resistance values ​​of the four sets of resistors and the capacitance values ​​of the capacitors. The capacitors in the diagram are fixed capacitors in the integrated circuit, and since the resistance values ​​of the four sets of resistors are adjustable, the cutoff frequency of this filter circuit is adjustable.

[0033] The differential source follower in the figure provides bias to the dummy resistor while buffering the physiological signal, exhibiting high input impedance and low output impedance. However, due to the substrate effect of the first N-channel transistor 115 and the fourth N-channel transistor 118, the voltage gain of the differential source follower is slightly less than 1. Therefore, when it provides feedback bias to the dummy resistor, small signal fluctuations in the physiological signal may cause the dummy resistor value to fluctuate in real time, thus affecting the cutoff frequency. Therefore, this invention further provides a solution by using a gain compensation circuit to compensate for the loss caused by the substrate effect of the first N-channel transistor 115 and the fourth N-channel transistor 118, making the voltage gain of the differential source follower approximately 1. This gain compensation circuit consists of a ninth P-channel transistor 121, a tenth P-channel transistor 122, and an eleventh P-channel transistor 125. The ninth P-channel transistor 121 and the tenth P-channel transistor 122 of the differential pair are cross-connected to the source output of the differential source follower under the bias of the bias current transistor, namely the eleventh P-channel transistor 125. Since an additional transconductance path is provided, a stable unity gain can be obtained by adjusting the bias current, i.e. the magnitude of the gain compensation current 129 of the differential source follower.

[0034] One implementation using TSMC's 40nm process is as follows: the aspect ratios of the first P-channel transistor 103, the second P-channel transistor 104, the third P-channel transistor 105, the fourth P-channel transistor 106, the fifth P-channel transistor 108, the sixth P-channel transistor 109, the seventh P-channel transistor 110, and the eighth P-channel transistor 111 are 10μm / 1μm; the aspect ratios of the first N-channel transistor 115 and the fourth N-channel transistor 118, the source followers, are 6μm / 4μm; the aspect ratios of the differential pair of the gain compensation circuit, the ninth P-channel transistor 121 and the tenth P-channel transistor 122, are 10μm / 4μm; the first capacitor 107 and the second capacitor 112 are 6pF; the third capacitor 113 is 3pF; the power supply 120 of the differential source follower circuit is 0.5V; and the power supply 127 of the gain compensation circuit is 1.2V. At this point, the chip area of ​​this adjustable low-pass filter based on a self-biased pseudo-resistor is only 0.008 mm². 2 When the bias current 128 of the differential source follower is 12nA and the gain compensation current 129 is 1.5nA, a second-order low-pass filter circuit with a cutoff frequency of 80Hz can be implemented, with a power consumption of only 16nW. As the bias current gradually increases, the cutoff frequency also increases approximately linearly. When the bias current 128 of the differential source follower increases to 200nA and the gain compensation current 129 is 55nA, a second-order low-pass filter circuit with a cutoff frequency of 1.1kHz can be implemented, with a power consumption of only 330nW. This achieves extremely small area, extremely low power consumption, and an extremely low cutoff frequency.

[0035] Figure 2 This is a schematic diagram of the physiological signal acquisition front-end implemented using the present invention. The signal in the diagram is represented by single-ended signals, but can actually be converted to differential signals. The low-frequency physiological signal is transmitted to the first-stage chopper modulator 203 through electrodes. The square wave signal 202 driving the chopper modulator is modulated to the chopper frequency (much higher than the physiological signal frequency range). The physiological signal modulated to a high frequency is superimposed on the equivalent input noise 204 (mainly low-frequency flicker noise) generated inside the equivalent input circuit of the circuit device itself. This is amplified by the front-end instrumentation amplifier 206 and then passed through the second-stage chopper modulator 207. At this time, the modulated physiological signal returns to the original low-frequency range after secondary modulation, while the low-frequency flicker noise is modulated to the chopper frequency. Finally, the noise in the chopper frequency range is filtered by the low-pass filter 100, and the amplified, uncontaminated physiological signal 208 is output.

[0036] The self-biased pseudo-resistor circuit is generated by biasing the output of a differential source follower circuit with its input to a pseudo-resistor acted upon by a transistor. Since the output DC voltage of the differential source follower can be adjusted by its bias current, it has adjustable bias capability for the pseudo-resistor. This circuit utilizes a very small chip area to generate a stable and adjustable ultra-large resistance, thus enabling the circuit to perform low-pass filtering with an adjustable cutoff frequency. The differential source follower circuit is a classic common-drain amplifier circuit that buffers the input signal, giving the circuit appropriate input impedance and output impedance. Simultaneously, its output DC voltage provides voltage bias for the pseudo-resistor acted upon by the transistor. The gain compensation circuit compensates for the output current by passing the input voltage signal through the transconductance of a P-channel transistor, compensating for filter gain loss caused by non-ideal transistor characteristics. Therefore, this circuit realizes an integrated, extremely small, low-power, and highly stable active analog low-pass filter circuit.

[0037] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An adjustable low-pass filter circuit based on a self-biased pseudo-resistor, characterized in that, It includes a circuit input terminal, a self-biased pseudo-resistor circuit, a differential source follower circuit, a gain compensation circuit, a first-stage capacitor, a second-stage capacitor, and a circuit output terminal connected in sequence; wherein, the first-stage capacitor includes a first capacitor 107 and a second capacitor 112, and the second-stage capacitor is a third capacitor 113. The self-biased pseudo-resistor circuit includes: a first P-channel transistor 103, a second P-channel transistor 104, a third P-channel transistor 105, a fourth P-channel transistor 106, a fifth P-channel transistor 108, a sixth P-channel transistor 109, a seventh P-channel transistor 110, and an eighth P-channel transistor 111. The first P-channel transistor 103 and the second P-channel transistor 104 form a first pseudo-resistor; the third P-channel transistor 105 and the fourth P-channel transistor 106 form a second pseudo-resistor; the fifth P-channel transistor 108 and the sixth P-channel transistor 109 form a third pseudo-resistor; and the seventh P-channel transistor 110 and the eighth P-channel transistor 111 form a fourth pseudo-resistor. One end of the first pseudo-resistor is connected to the positive input terminal of the circuit, and the other end of the first pseudo-resistor is connected to one end of the second pseudo-resistor. The other end of the second pseudo-resistor is connected to one end of the third capacitor and the differential source follower circuit. One end of the third pseudo-resistor is connected to the negative input terminal of the circuit, and the other end of the third pseudo-resistor is connected to one end of the fourth pseudo-resistor. The other end of the fourth pseudo-resistor is connected to the other end of the third capacitor and the differential source follower circuit. One end of the first capacitor is connected to the common connection terminal of the first pseudo resistor and the second pseudo resistor, and the other end of the first capacitor is connected to the gate of the first pseudo resistor and the second pseudo resistor; one end of the second capacitor is connected to the common connection terminal of the third pseudo resistor and the fourth pseudo resistor, and the other end of the second capacitor is connected to the gate of the third pseudo resistor and the fourth pseudo resistor. The differential source follower circuit includes a first N-channel transistor 115, a second N-channel transistor 116, a third N-channel transistor 117, and a fourth N-channel transistor 118. The gate of the first N-channel transistor 115 is connected to the self-biasing pseudo-resistor, the drain of the first N-channel transistor 115 is connected to the power supply terminal, the source of the first N-channel transistor 115 is connected to the drain of the second N-channel transistor 116, the gate of the second N-channel transistor 116 is biased by an external voltage, the source of the second N-channel transistor is grounded, the source of the third N-channel transistor 117 is grounded, the gate of the third N-channel transistor 117 is biased by an external voltage, the drain of the third N-channel transistor 117 is connected to the source of the fourth N-channel transistor 118, the gate of the fourth N-channel transistor 118 is connected to the self-biasing pseudo-resistor, and the drain of the fourth N-channel transistor 118 is connected to the power supply terminal. The circuit input terminal is connected to the input terminal of the self-biased pseudo-resistor circuit. The first capacitor 107 and the second capacitor 112 are respectively connected to the intermediate node and the gate of the self-biased pseudo-resistor circuit. The two ends of the third capacitor are connected to the positive and negative output terminals of the self-biased pseudo-resistor circuit. The input terminal of the differential source follower circuit is connected to the output terminal of the self-biased pseudo-resistor circuit. The input of the gain compensation circuit is connected to the output of the differential source follower circuit. The output terminal of the gain compensation circuit is connected to the circuit output terminal.

2. The adjustable low-pass filter circuit based on a self-biased pseudo-resistor according to claim 1, characterized in that, The gain compensation circuit includes a ninth P-channel transistor 125, a tenth P-channel transistor 121, and an eleventh P-channel transistor 122. The source of the ninth P-channel transistor is connected to a power supply, the gate is connected to an external bias voltage, and the drain is connected to the sources of the tenth and eleventh P-channel transistors. The gate and drain of the tenth P-channel transistor are connected to the differential source follower circuit, and the gate and drain of the eleventh P-channel transistor are also connected to the differential source follower circuit. The sources of the tenth and eleventh P-channel transistors are connected to the output terminal of the circuit.

3. The adjustable low-pass filter circuit based on a self-biased pseudo-resistor according to claim 1, characterized in that, The self-biased pseudo-resistor circuit is generated by biasing the output of the differential source follower circuit with its input to a pseudo-resistor, which is a transistor. Since the output DC voltage of the differential source follower can be adjusted by its bias current, it has the ability to adjust the bias of the pseudo-resistor. This circuit uses a very small chip area to generate a stable and adjustable ultra-large resistance value, thereby enabling the circuit to have a low-pass filtering function with an adjustable cutoff frequency.

4. The adjustable low-pass filter circuit based on a self-biased pseudo-resistor according to claim 1, characterized in that, The differential source follower circuit is a classic common-drain amplifier circuit that buffers the input signal, giving the circuit an input impedance and an appropriate output impedance. At the same time, its output DC voltage can provide voltage bias for the pseudo-resistors, which are acted by transistors.

5. The adjustable low-pass filter circuit based on a self-biased pseudo-resistor according to claim 1, characterized in that, The gain compensation circuit compensates for the output current by passing the input voltage signal through the transconductance of a P-channel transistor, thereby compensating for the filter gain loss caused by the non-ideal characteristics of the transistor.

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