Linear amplification circuit and acquisition card of OCT (optical coherence tomography) system

Abstract

The utility model provides a linear amplification circuit and an acquisition card of an OCT (optical coherence tomography) system, and the linear amplification circuit comprises an operational amplifier, a peripheral resistance circuit, a filter capacitor circuit and a passive matching circuit. The operational amplifier comprises an input end, an output end, and a power supply positive electrode and a power supply negative electrode for supplying power; the peripheral resistance circuit is arranged at the input end and between the input end and the output end; the filter capacitor circuit comprises a first filter capacitor arranged at the positive electrode of the power supply and a second filter capacitor arranged at the negative electrode of the power supply; the passive matching circuit is arranged between the positive electrode of the power supply and the first filter capacitor, and / or between the negative electrode of the power supply and the second filter capacitor; the passive matching circuit is used for adjusting the slew rate of positive and negative level output to improve the balance of the positive and negative output stages of the operational amplifier, so that the second harmonic of the circuit is reduced, and the spurious-free dynamic range of the circuit is improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a linear amplifier circuit and an acquisition card for an OCT system. Background Technology

[0002] In SS-OCT (Swept-Source Optical Coherence Tomography) systems, the front-end analog circuitry of the acquisition card requires low noise, high bandwidth, high linearity, and stable gain. Especially for SS-OCT systems operating in the frequency domain, they are particularly sensitive to harmonic distortion, thus requiring high linearity across the entire frequency band, i.e., a high SFDR (Spurious-free Dynamic Range). Currently, the following three methods are commonly used to improve front-end linearity:

[0003] 1. Using a differential circuit results in a large circuit size, high power consumption, and a need for switching between balanced and unbalanced inputs for single-ended inputs;

[0004] 2. Using a power back-off circuit results in high power consumption;

[0005] 3. Using pre-distortion compensation circuits results in complex circuitry, high power consumption, and poor stability.

[0006] All of these circuits will introduce additional power consumption and increase circuit complexity. Utility Model Content

[0007] The purpose of this application is to provide a linear amplifier circuit and an acquisition card for an OCT system. In response to the linearity requirements of SS-OCT, a passive matching circuit is set at at least one of the positive and negative power supply terminals of the operational amplifier to compensate for the power supply circuit of the operational amplifier. By improving the balance of the positive and negative output stages of the operational amplifier, the second harmonic of the circuit is reduced, thereby improving the SFDR of the single-ended input-output operational amplifier circuit.

[0008] In a first aspect, this application provides a linear amplifier circuit, comprising: an operational amplifier, an external resistor circuit, a filter capacitor circuit, and a passive matching circuit; the operational amplifier includes an input terminal, an output terminal, and a positive and negative power supply terminal for power supply; the external resistor circuit is disposed at the input terminal and between the input terminal and the output terminal; the filter capacitor circuit includes: a first filter capacitor disposed at the positive power supply terminal and a second filter capacitor disposed at the negative power supply terminal; the passive matching circuit is disposed between the positive power supply terminal and the first filter capacitor, and / or between the negative power supply terminal and the second filter capacitor; the passive matching circuit is used to adjust the slew rate of the positive and negative level outputs to improve the balance of the positive and negative output stages of the operational amplifier, thereby reducing the second harmonic of the circuit and improving the spurious-free dynamic range of the circuit.

[0009] Furthermore, the passive matching circuit described above includes: a first designated inductor; one end of the first designated inductor is connected to the positive terminal of the power supply, and the other end is connected to a first filter capacitor; or, one end of the first designated inductor is connected to the negative terminal of the power supply, and the other end is connected to a second filter capacitor.

[0010] Furthermore, the inductance value of the first specified inductor is 3.3nH, which is the optimal inductance value obtained after testing by the test circuit.

[0011] Furthermore, the passive matching circuit described above includes: a first designated resistor; one end of the first designated resistor is connected to the positive terminal of the power supply, and the other end is connected to a first filter capacitor; or, one end of the first designated resistor is connected to the negative terminal of the power supply, and the other end is connected to a second filter capacitor.

[0012] Furthermore, the resistance value of the first specified resistor is 5.1 ohms.

[0013] Furthermore, the passive matching circuit described above includes: a first designated capacitor and a second designated resistor; one end of the first designated capacitor and the second designated resistor are respectively connected to the positive terminal of the power supply; the other end of the first designated capacitor is grounded; the other end of the second designated resistor is connected to the first filter capacitor; or, one end of the first designated capacitor and the second designated resistor are respectively connected to the negative terminal of the power supply; the other end of the first designated capacitor is grounded; the other end of the second designated resistor is connected to the second filter capacitor.

[0014] Furthermore, the capacitance value of the first specified capacitor is 10pF; the resistance value of the second specified resistor is 5.1 ohms.

[0015] Furthermore, the passive matching circuit described above includes: a second designated inductor and a second designated capacitor; one end of the second designated inductor and the second designated capacitor are respectively connected to the positive terminal of the power supply; the other end of the second designated capacitor is grounded; the other end of the second designated inductor is connected to the first filter capacitor; or, one end of the second designated inductor and the second designated capacitor are respectively connected to the negative terminal of the power supply; the other end of the second designated capacitor is grounded; the other end of the second designated inductor is connected to the second filter capacitor.

[0016] Furthermore, the inductance value of the second specified inductor is 3.3nH; the capacitance value of the second specified capacitor is 5pF.

[0017] Further, the aforementioned passive matching circuit includes: a third designated capacitor, a third designated inductor, and a fourth designated inductor; one end of the third designated inductor and the third designated capacitor are respectively connected to the positive terminal of the amplifier power supply; the other end of the third designated capacitor is grounded; the other end of the third designated inductor is connected to the first filter capacitor; one end of the fourth designated inductor is connected to the negative terminal of the amplifier power supply, and the other end is connected to the second filter capacitor; or, one end of the third designated inductor and the third designated capacitor are respectively connected to the negative terminal of the amplifier power supply; the other end of the third designated capacitor is grounded; the other end of the third designated inductor is connected to the second filter capacitor; one end of the fourth designated inductor is connected to the positive terminal of the amplifier power supply, and the other end is connected to the first filter capacitor.

[0018] Secondly, this application also provides an acquisition card for an OCT system, wherein the input terminal of the acquisition card is connected to the linear amplifier circuit as described in the first aspect.

[0019] In the linear amplifier circuit and OCT system acquisition card provided in this application, to meet the linearity requirements of SS-OCT, a passive matching circuit is directly set at at least one of the positive and negative power supply terminals of the operational amplifier. The passive matching circuit is set between the positive power supply terminal and its corresponding filter capacitor, and / or between the negative power supply terminal and its corresponding filter capacitor. By adjusting the slew rate of the positive and negative level outputs, the balance of the positive and negative output stages of the operational amplifier is improved, thereby reducing the second harmonic of the circuit and improving the spurious-free dynamic range of the circuit. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0021] Figure 1 A graph showing the harmonic distortion vs. frequency response of operational amplifiers in existing technologies;

[0022] Figure 2 This is a simplified structure of an operational amplifier and a schematic diagram of an asymmetric output stage in the prior art.

[0023] Figure 3 This is a schematic diagram of the structure of an operational amplifier in the prior art;

[0024] Figure 4 This is a schematic diagram of a linear amplifier circuit provided in an embodiment of this application;

[0025] Figure 5 A circuit diagram of a linear amplifier circuit provided in an embodiment of this application;

[0026] Figure 6 A partial circuit diagram of a linear amplifier circuit provided in an embodiment of this application;

[0027] Figure 7 A structural block diagram of a test circuit provided in an embodiment of this application;

[0028] Figure 8 A comparison diagram of second harmonic results provided in an embodiment of this application;

[0029] Figure 9 A diagram illustrating the effect of inductance value on the second harmonic is provided in an embodiment of this application.

[0030] Figure 10 A comparison diagram of third harmonic results provided in an embodiment of this application;

[0031] Figure 11 A partial circuit diagram of another linear amplifier circuit provided in the embodiments of this application;

[0032] Figure 12 A partial circuit diagram of another linear amplifier circuit provided in the embodiments of this application;

[0033] Figure 13 A partial circuit diagram of another linear amplifier circuit provided in the embodiments of this application;

[0034] Figure 14 A partial circuit diagram of another linear amplifier circuit provided in an embodiment of this application. Detailed Implementation

[0035] The technical solutions of this application will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0036] Due to slew rate limitations, the linearity of operational amplifiers typically decreases with increasing frequency. For example, the typical wideband op-amp LMH6703 has a large-signal bandwidth of 500MHz. When the frequency exceeds 100MHz, the second harmonics increase rapidly, becoming the main factor contributing to the deterioration of SFDR. Its harmonic distortion vs. frequency curve is shown below. Figure 1 As shown.

[0037] A significant reason for the increased second-order distortion is the nonlinearity of the op-amp output stage. For example, most CMOS op-amp chips use a Class AB amplifier with a PMOS transistor responsible for positive output and an NMOS transistor responsible for negative output. This circuit can achieve high output capability with lower quiescent current, but it introduces distortion, including crossover distortion near the 0-level output and nonlinear distortion during large-signal output. Due to the asymmetry between the PMOS and NMOS transistors, second-order harmonic distortion is usually the largest in amplitude among all harmonic distortions during large-signal output. A simplified op-amp structure and a schematic diagram of an asymmetric output stage are shown below. Figure 2 As shown.

[0038] See Figure 3 The diagram shows a conventional amplifier circuit. The operational amplifier LMH6703 includes input and output terminals, as well as positive and negative power supply terminals. Operational amplifier datasheets typically recommend placing several filter capacitors near the positive and negative power supply pins to reduce power supply noise and source impedance of the power network. However, if the positive and negative output levels of the op-amp's output stage are unbalanced, perfect power supply filtering cannot achieve high linearity. This is more pronounced at high frequencies, and output matching is difficult for broadband circuits that require operation from DC to the highest operating frequency.

[0039] Based on this, embodiments of this application provide a linear amplifier circuit and an acquisition card for an OCT system. To address the linearity requirements of SS-OCT, a passive matching circuit is directly set at at least one of the positive and negative power supply terminals of the operational amplifier to compensate for the power supply circuit of the operational amplifier. By improving the balance of the positive and negative output stages of the operational amplifier, the second harmonic of the circuit is reduced, thereby improving the SFDR of the single-ended input / output operational amplifier circuit.

[0040] To facilitate understanding of this embodiment, a linear amplifier circuit disclosed in this application will first be described in detail.

[0041] See Figure 4 The embodiment of this application shown provides a schematic diagram of a linear amplifier circuit, which includes: an operational amplifier 11, an external resistor circuit 12, a filter capacitor circuit 13, and a passive matching circuit 14.

[0042] Operational amplifier 11 includes an input terminal (including a positive input terminal Vin+ and a negative input terminal Vin-), an output terminal (Vout), and a power supply positive terminal (indicated by +) and a power supply negative terminal (indicated by -). An external resistor circuit 12 is disposed at the input terminal and between the input and output terminals. A filter capacitor circuit 13 includes a first filter capacitor C1 disposed at the positive power supply terminal and a second filter capacitor C2 disposed at the negative power supply terminal. A passive matching circuit 14 is disposed between the positive power supply terminal and the first filter capacitor C1, and / or between the negative power supply terminal and the second filter capacitor C2. The passive matching circuit 14 is used to adjust the slew rate of the positive and negative output levels to improve the balance of the positive and negative output stages of the operational amplifier, thereby reducing the second harmonic of the circuit and improving the spurious-free dynamic range of the circuit.

[0043] The linear amplifier circuit provided in this application, in order to meet the linearity requirements of SS-OCT, directly sets a passive matching circuit at at least one of the positive and negative power supply terminals of the operational amplifier to compensate the power supply circuit of the operational amplifier. By improving the balance of the positive and negative output stages of the operational amplifier, the second harmonic of the circuit is reduced, thereby improving the SFDR of the single-ended input-output operational amplifier circuit.

[0044] In one possible implementation, the passive matching circuit includes: a first designated inductor L11; one end of the first designated inductor L11 is connected to the positive terminal of the amplifier power supply, and the other end is connected to a first filter capacitor C1, such as... Figure 5 As shown; Figure 5 The diagram also shows the specific structure of the peripheral resistor circuit 12, which includes a first resistor R1, a second resistor R2, and a third resistor R3. One end of the first resistor R1 is connected to the output terminal, and the other end is connected to one end of the second resistor R2 and the negative input terminal, respectively. The other end of the second resistor R2 is grounded. One end of the third resistor R3 is connected to the positive input terminal, and the other end is connected to the input signal.

[0045] In this implementation, by connecting a small inductor in series with the positive power supply pin of the op-amp, the speed and slew rate of the positive output can be reduced, improving the symmetry and balance of the positive and negative output stages of the op-amp. Simultaneously, other performance characteristics of the op-amp remain unaffected. This effectively reduces the second harmonic of the circuit and improves or maintains other order harmonics, thereby improving the spurious-free dynamic range of the circuit. This method is also effective for other op-amp circuits with similar harmonic distortion mechanisms.

[0046] In another possible implementation, one end of the first designated inductor L11 is connected to the negative terminal of the power supply, and the other end is connected to the second filter capacitor C2, as shown below. Figure 6 As shown, the Figure 6 The specific structure of the external resistor circuit 12 is not shown in the diagram; the actual connection method is different. Figure 5 Same as in China.

[0047] The inductance value of the first specified inductor L11 mentioned above is 3.3nH, which is sufficient to pass the test circuit (such as...). Figure 7 The optimal inductance value was obtained after testing (as shown). The optimal L11 value was found by trying different inductance values. See [link to relevant documentation]. Figure 8 The comparison chart of the second harmonic results shown below. Figure 9 The effect of the inductance value on the second harmonic is shown. Figure 10 Comparison of the 3rd harmonic results shown Figure 3 The test results show that when L1=3.3nH and the input level is 2000mVpp, compared with the conventional circuit, the output second harmonic is reduced by nearly 15dB, while the third harmonic performance is not deteriorated. This significantly improves the spurious-free dynamic range (SFDR) of the system, thereby reducing artifacts in the output image of the SS-OCT system.

[0048] This method of improving linearity by adding a high-frequency passive matching circuit to the power supply pin of the operational amplifier chip is not limited to adding small inductors to the positive and negative power supply terminals. Depending on the imbalance properties of different operational amplifier chips, capacitors, resistors, inductors or other passive matching circuits can also be added to the positive and negative power supply terminals or both ends.

[0049] In practical applications, when the positive output is faster than the negative output, a small inductor or resistor needs to be connected in series at the positive power supply pin, or a small capacitor needs to be connected in parallel at the negative power supply pin. Conversely, when the negative output is faster than the positive output, a small inductor is connected in series at the negative power supply pin, or a small capacitor is connected in parallel at the positive power supply pin. Typically, a parallel capacitor needs to be followed by an inductor in series. The capacitor and inductor together create LC resonance, which affects the matching bandwidth, making it less straightforward than using a series inductor or resistor. If the operational amplifier chip used has poor balance, or to obtain better performance over a wider frequency range, matching circuits can be added to both the positive and negative power supply pins, or a conventional modulation circuit can be added to the signal output.

[0050] In another optional embodiment, the passive matching circuit includes: a first designated resistor R11; one end of the first designated resistor R11 is connected to the positive terminal of the amplifier power supply, and the other end is connected to a first filter capacitor C1, such as... Figure 11 As shown; or, one end of the first specified resistor R11 is connected to the negative terminal of the amplifier power supply, and the other end is connected to the second filter capacitor C2. Further, the resistance value of the first specified resistor is 5.1 ohms.

[0051] In another optional embodiment, the passive matching circuit includes: a first designated capacitor C11 and a second designated resistor R22; one end of the first designated capacitor C11 and the second designated resistor R22 are respectively connected to the positive terminal of the amplifier power supply; the other end of the first designated capacitor C11 is grounded; the other end of the second designated resistor R22 is connected to the first filter capacitor C1; or, one end of the first designated capacitor C11 and the second designated resistor R22 are respectively connected to the negative terminal of the amplifier power supply; the other end of the first designated capacitor C11 is grounded; the other end of the second designated resistor R22 is connected to the second filter capacitor C2, as shown. Figure 12 As shown.

[0052] Furthermore, the capacitance value of the first specified capacitor C11 is 10pF; the resistance value of the second specified resistor R22 is 5.1 ohms.

[0053] In another optional embodiment, the passive matching circuit includes: a second designated inductor L22 and a second designated capacitor C22; one end of the second designated inductor L22 and the second designated capacitor C22 are respectively connected to the positive terminal of the amplifier power supply; the other end of the second designated capacitor C22 is grounded; the other end of the second designated inductor L22 is connected to the first filter capacitor C1; or, one end of the second designated inductor L22 and the second designated capacitor C22 are respectively connected to the negative terminal of the amplifier power supply; the other end of the second designated capacitor C22 is grounded; the other end of the second designated inductor L22 is connected to the second filter capacitor C2, such as... Figure 13 As shown.

[0054] Furthermore, the inductance value of the second specified inductor L22 is 3.3nH; the capacitance value of the second specified capacitor C22 is 5pF.

[0055] In another optional embodiment, the passive matching circuit includes: a third designated capacitor C33, a third designated inductor L33, and a fourth designated inductor L44; one end of the third designated inductor L33 and the third designated capacitor C33 are respectively connected to the positive terminal of the amplifier power supply; the other end of the third designated capacitor C33 is grounded; the other end of the third designated inductor L33 is connected to the first filter capacitor C1; one end of the fourth designated inductor L44 is connected to the negative terminal of the amplifier power supply, and the other end is connected to the second filter capacitor C2; or, one end of the third designated inductor L33 and the third designated capacitor C33 are respectively connected to the negative terminal of the amplifier power supply; the other end of the third designated capacitor C33 is grounded; the other end of the third designated inductor L33 is connected to the second filter capacitor C2; one end of the fourth designated inductor L44 is connected to the positive terminal of the amplifier power supply, and the other end is connected to the first filter capacitor C1, as shown. Figure 14 As shown.

[0056] It should be noted that the resistance, capacitance, or inductance values ​​in the above embodiments are merely examples, and can be adjusted according to the actual situation in actual circuits.

[0057] In the linear amplifier circuit provided in this application, to meet the linearity requirements of SS-OCT, a passive matching circuit is directly set at at least one of the positive and negative power supply terminals of the operational amplifier. The passive matching circuit is set between the positive power supply terminal and its corresponding filter capacitor, and / or between the negative power supply terminal and its corresponding filter capacitor. By adjusting the slew rate of the positive and negative level outputs, the balance of the positive and negative output stages of the operational amplifier is improved, thereby reducing the second harmonic of the circuit and improving the spurious-free dynamic range of the circuit.

[0058] Based on the above circuit embodiments, this application also provides an acquisition card for an OCT system, wherein the input terminal of the acquisition card is connected to the linear amplifier circuit as described in the aforementioned circuit embodiments.

[0059] The acquisition card provided in this application embodiment has the same implementation principle and technical effect as the aforementioned circuit embodiment. For the sake of brevity, any parts not mentioned in the acquisition card embodiment can be referred to the corresponding content in the aforementioned circuit embodiment.

[0060] The acquisition card of the OCT system provided in this application has a linear amplifier circuit as described in the circuit embodiment connected at the input end. Therefore, when acquiring signals, the balance of the positive and negative output stages of the operational amplifier can be improved by the linear amplifier circuit, thereby reducing the second harmonic of the circuit, improving the spurious-free dynamic range of the circuit, and making the signal acquired by the acquisition card more accurate, thus reducing the artifacts of the output image of the SS-OCT system.

[0061] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0062] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The protection scope of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the technical scope disclosed in this application. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be covered within the protection scope of this application. Therefore, the protection scope of this application should be determined by the protection scope of the claims.

Claims

1. A linear amplifier circuit, characterized in that, The linear amplifier circuit includes an operational amplifier, an external resistor circuit, a filter capacitor circuit, and a passive matching circuit. The operational amplifier includes an input terminal, an output terminal, and a positive and negative power supply terminal for power supply. The external resistor circuit is disposed at the input terminal and between the input terminal and the output terminal. The filter capacitor circuit includes a first filter capacitor disposed at the positive power supply terminal and a second filter capacitor disposed at the negative power supply terminal. The passive matching circuit is disposed between the positive power supply terminal and the first filter capacitor, and / or between the negative power supply terminal and the second filter capacitor. The passive matching circuit is used to adjust the slew rate of the positive and negative output levels to improve the balance of the positive and negative output stages of the operational amplifier, thereby reducing the second harmonic of the circuit and improving the spurious-free dynamic range of the circuit.

2. The linear amplifier circuit according to claim 1, characterized in that, The passive matching circuit includes: a first designated inductor; one end of the first designated inductor is connected to the positive terminal of the power supply, and the other end is connected to the first filter capacitor; or, one end of the first designated inductor is connected to the negative terminal of the power supply, and the other end is connected to the second filter capacitor.

3. The linear amplifier circuit according to claim 2, characterized in that, The inductance value of the first specified inductor is 3.3nH, which is the optimal inductance value obtained after testing by the test circuit.

4. The linear amplifier circuit according to claim 1, characterized in that, The passive matching circuit includes: a first designated resistor; one end of the first designated resistor is connected to the positive terminal of the power supply, and the other end is connected to the first filter capacitor; or, one end of the first designated resistor is connected to the negative terminal of the power supply, and the other end is connected to the second filter capacitor.

5. The linear amplifier circuit according to claim 4, characterized in that, The resistance value of the first specified resistor is 5.1 ohms.

6. The linear amplifier circuit according to claim 1, characterized in that, The passive matching circuit includes: a first designated capacitor and a second designated resistor; one end of the first designated capacitor and the second designated resistor are respectively connected to the positive terminal of the power supply; the other end of the first designated capacitor is grounded; the other end of the second designated resistor is connected to the first filter capacitor. Alternatively, one end of the first designated capacitor and one end of the second designated resistor are respectively connected to the negative terminal of the power supply; the other end of the first designated capacitor is grounded; and the other end of the second designated resistor is connected to the second filter capacitor.

7. The linear amplifier circuit according to claim 1, characterized in that, The passive matching circuit includes: a second designated inductor and a second designated capacitor; One end of the second designated inductor and one end of the second designated capacitor are respectively connected to the positive terminal of the power supply; the other end of the second designated capacitor is grounded; the other end of the second designated inductor is connected to the first filter capacitor. Alternatively, one end of the second designated inductor and one end of the second designated capacitor are respectively connected to the negative terminal of the power supply; the other end of the second designated capacitor is grounded; and the other end of the second designated inductor is connected to the second filter capacitor.

8. The linear amplifier circuit according to claim 7, characterized in that, The inductance value of the second specified inductor is 3.3nH; the capacitance value of the second specified capacitor is 5pF.

9. The linear amplifier circuit according to claim 1, characterized in that, The passive matching circuit includes: a third designated capacitor, a third designated inductor, and a fourth designated inductor; One end of the third designated inductor and one end of the third designated capacitor are respectively connected to the positive terminal of the amplifier power supply; the other end of the third designated capacitor is grounded; the other end of the third designated inductor is connected to the first filter capacitor; one end of the fourth designated inductor is connected to the negative terminal of the amplifier power supply, and the other end is connected to the second filter capacitor; Alternatively, one end of the third designated inductor and one end of the third designated capacitor are respectively connected to the negative terminal of the amplifier power supply; the other end of the third designated capacitor is grounded; the other end of the third designated inductor is connected to the second filter capacitor; one end of the fourth designated inductor is connected to the positive terminal of the amplifier power supply, and the other end is connected to the first filter capacitor.

10. A data acquisition card for an OCT system, characterized in that, The input terminal of the acquisition card is connected to a linear amplifier circuit as described in any one of claims 1-9.

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