Data Transceiving Method, System, Storage Medium and Device Based on ZYNQ Platform

Abstract

The present invention provides a data receiving and transmitting method, system, storage medium and device based on a ZYNQ platform. The method includes: on the processor system side, the ARM processor receives and processes Ethernet data through the UDP protocol to obtain the processed data; the processed data is transferred to the programmable logic side through the logic DMA engine, and the processed data is packetized and encapsulated through the UDP framing module to obtain Ethernet MAC frame data; the Ethernet MAC frame data is framed according to the physical layer frame format through the first MAC on the programmable logic side to obtain the first message; the first message and the second message on the processor system side are arbitrated by an arbiter and then sent to an external network interface chip through the GMII transmission interface. The present invention realizes the functions of UDP data reception, processing and transmission through software and logic collaborative processing, greatly reducing the consumption of CPU resources.

Description

Technical Field

[0001] The present invention relates to the field of information technology, and in particular to a data transceiver method, system, storage medium and device based on a ZYNQ platform. Background Art

[0002] With the continuous improvement of the requirements for computing power and AI performance in fields such as servers, automobiles, artificial intelligence, and edge computing, a single processor can no longer meet the needs of high-performance computing, and heterogeneous computing has become a new development direction; the ZYNQ series is a high-end embedded SoC (System on Chip) launched by Xilinx. It integrates an ARM processor (Advanced RISC Machines, general-purpose processor) and an FPGA (Field Programmable Gate Array) on the chip. Compared with traditional embedded CPUs (Central Process Unit), it has powerful parallel processing capabilities. How to reasonably divide the functions of the ARM and FPGA to give full play to their respective advantages is particularly important during the development process.

[0003] Figure 1 The following is a schematic structural diagram of the traditional UDP data transceiver implementation provided according to the prior art. As Figure 1 shown, the ARM processor receives Ethernet data through the UDP protocol (User Datagram Protocol), processes the data, and then sends Ethernet data through the UDP protocol; among them, DMA (Direct Memory Access) and MAC (Media Access Control) are hardware units, and device drivers, UDP protocol stacks, and data processing are all implemented by ARM software; when receiving data, the software driver layer calls DMA to obtain Ethernet frame data from the MAC and then hands it over to the UDP protocol stack for packet parsing. The user data obtained after parsing is processed by the ARM. After the processing is completed, the processed user data is handed over to the UDP protocol stack for packet encapsulation to form the final Ethernet frame, which is transported by DMA to the MAC and finally sent out through the Ethernet interface. The above processing flow consumes more and more CPU resources as the data volume increases.

[0004] Figure 2 The following is a schematic diagram of the UDP protocol stack packet processing provided according to the prior art. As Figure 2As shown in the figure, in terms of the UDP sending process alone, the software hands over the user data to the transport layer to add the UDP header to form a UDP segment message, and then hands it over to the IP (Internet Protocol) layer to add the IP header to form an IP segment message. Finally, the IP segment message is handed over to the link layer to add the frame header to form the final Ethernet frame, which is the message finally handed over to the MAC layer for sending. In the above process, in addition to adding header information for each layer, it is also necessary to calculate the checksum. Therefore, multiple checksum calculations and memory copies are required during the framing process from user data to the final Ethernet frame, and the resulting CPU resource consumption is particularly significant when dealing with large amounts of data.

[0005] Actual tests on the ZYNQ7000 platform show that when the data volume is about 350Mbps, only the UDP data sending and receiving through the UDP protocol stack accounts for about 50% of the CPU (ARM) utilization rate. Therefore, how to effectively reduce the CPU resource consumption caused by UDP data sending and receiving is of great significance for releasing the CPU for large amounts of data processing. Summary of the Invention

[0006] In view of this, the purpose of the present invention is to propose a data sending and receiving method, system, storage medium and device based on the ZYNQ platform to solve the problem of consuming a large amount of CPU resources caused by UDP protocol-based data sending and receiving on the ZYNQ platform in the prior art.

[0007] Based on the above purpose, the present invention provides a data sending and receiving method based on the ZYNQ platform, including the following steps:

[0008] On the processor system side, the ARM processor receives and processes Ethernet data through the UDP protocol to obtain the processed data;

[0009] The processed data is transported to the programmable logic side through the logic DMA engine, and the processed data is packetized and encapsulated through the UDP framing module to obtain Ethernet MAC frame data;

[0010] The Ethernet MAC frame data is framed according to the physical layer frame format through the first MAC on the programmable logic side to obtain the first message;

[0011] The first message and the second message on the processor system side are arbitrated by the arbiter and sent to the external network interface chip through the GMII sending interface.

[0012] In some embodiments, the method further includes:

[0013] The processor system side accesses and configures the registers of the logic DMA engine, UDP framing module and the first MAC through the APB bus and the APB slave function module respectively.

[0014] In some embodiments, the method further includes:

[0015] The Ethernet MAC frame data adopts the Ethernet frame format;

[0016] The ARM processor configures the source MAC address and type of the frame header required by the Ethernet frame format, as well as all fields in the IP header and UDP header except the checksum through the APB bus;

[0017] The checksum is obtained after being calculated by the UDP framing module according to the configuration information.

[0018] In some embodiments, the method further includes:

[0019] Determine the destination MAC address of the frame header based on the sending mode of the first packet, which further includes:

[0020] In response to the sending mode being multicast, obtain the destination MAC address based on the preset mapping relationship using the destination IP address of the multicast. The preset mapping relationship is the mapping relationship between multiple IP addresses of the multicast and the corresponding MAC addresses;

[0021] In response to the sending mode being unicast, obtain the destination MAC address through the ARP protocol, and the ARP protocol is implemented by the software protocol stack on the processor system side.

[0022] In some embodiments, framing the Ethernet MAC frame data according to the physical layer frame format includes:

[0023] Add a preamble and a start code before the Ethernet MAC frame data, and add a check code after the Ethernet MAC frame data. The check code is generated according to the Ethernet MAC frame data.

[0024] In some embodiments, sending the first packet and the second packet on the processor system side to the external network interface chip through the GMII sending interface after arbitration by the arbiter includes:

[0025] Temporarily store the second packet sent by the second MAC on the processor system side through the buffer on the programmable logic side;

[0026] In response to the second MAC obtaining the arbitration right, send all the second packets in the buffer to the external network interface chip through the GMII sending interface, and release the arbitration right after the sending is completed.

[0027] In some embodiments, transferring the processed data to the programmable logic side through the logical DMA engine includes:

[0028] Use the AXI bus and transfer the processed data to the programmable logic side through the logical DMA engine.

[0029] On the other hand, the present invention also provides a data transceiver system based on the ZYNQ platform, including:

[0030] A processing module, configured to receive and process Ethernet data through the UDP protocol by the ARM processor on the processor system side, and obtain the processed data;

[0031] An encapsulation module, configured to transfer the processed data to the programmable logic side through the logic DMA engine, and perform packet encapsulation on the processed data through the UDP framing module to obtain Ethernet MAC frame data;

[0032] A framing module, configured to frame the Ethernet MAC frame data according to the physical layer frame format through the first MAC on the programmable logic side to obtain the first packet; and

[0033] A sending module, configured to send the first packet and the second packet on the processor system side to an external network interface chip through the GMII sending interface after arbitration by the arbiter.

[0034] In yet another aspect of the present invention, there is also provided a computer-readable storage medium storing computer program instructions, and when the computer program instructions are executed by a processor, the above method is implemented.

[0035] In still another aspect of the present invention, there is also provided a computer device including a memory and a processor, where a computer program is stored in the memory, and when the computer program is executed by the processor, the above method is executed.

[0036] The present invention has at least the following beneficial technical effects:

[0037] In the data transceiver method based on the ZYNQ platform of the present invention, the data reception and data processing parts are still implemented by software on the ARM side. After the data processing is completed, there is no need to perform processing such as UDP packet encapsulation through the protocol stack. A logic DMA engine is implemented by logic on the programmable logic side to transfer the data to be sent to the programmable logic side, and then the data is packet-encapsulated through the UDP framing module. Then, a physical layer protocol frame is formed through the MAC implemented on the programmable logic side. Finally, the sending port of the GMII interface shared by the arbiter and the MAC on the processor system side is used to share the use of the Ethernet interface, thereby realizing the functions of UDP data reception, processing, and sending through software and logic collaborative processing, greatly reducing the CPU resource consumption; avoiding the problem that when using a software protocol stack to send UDP data in the traditional method, as the amount of data increases, the CPU resource consumption becomes larger and larger because both the driver layer and the UDP protocol stack need to be implemented by software. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other embodiments can be obtained based on these drawings.

[0039] Figure 1 It is a schematic structural diagram of the traditional UDP data transceiver implementation provided according to the prior art;

[0040] Figure 2 It is a schematic diagram of the UDP protocol stack message processing provided according to the prior art;

[0041] Figure 3 It is a schematic diagram of the data transceiver method based on the ZYNQ platform provided according to the embodiments of the present invention;

[0042] Figure 4 It is a schematic structural diagram of implementing the data transceiver method based on the ZYNQ platform provided according to the embodiments of the present invention;

[0043] Figure 5 It is a schematic structural diagram of the Ethernet MAC frame format provided according to the embodiments of the present invention;

[0044] Figure 6 It is a schematic structural diagram of the Ethernet physical layer frame format provided according to the embodiments of the present invention;

[0045] Figure 7 It is a comparison schematic diagram between the prior art solution and the data transceiver method based on the ZYNQ platform provided according to the embodiments of the present invention;

[0046] Figure 8 It is a schematic diagram of the data transceiver system based on the ZYNQ platform provided according to the embodiments of the present invention;

[0047] Figure 9 It is a schematic diagram of the computer-readable storage medium for implementing the data transceiver method based on the ZYNQ platform provided according to the embodiments of the present invention;

[0048] Figure 10 It is a schematic hardware structure diagram of the computer device for executing the data transceiver method based on the ZYNQ platform provided according to the embodiments of the present invention. Detailed Embodiments

[0049] To make the objectives, technical solutions, and advantages of the present invention clearer and more understandable, the following further elaborates on the embodiments of the present invention in detail in combination with specific embodiments and with reference to the accompanying drawings.

[0050] It should be noted that in the embodiments of the present invention, all expressions using "first" and "second" are used to distinguish two non-identical entities or non-identical parameters with the same name. It can be seen that "first" and "second" are only for the convenience of expression and should not be construed as a limitation on the embodiments of the present invention. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units inherently includes other steps or units.

[0051] Based on the above objectives, in the first aspect of the embodiments of the present invention, an embodiment of a data transceiver method based on the ZYNQ platform is proposed. Figure 3 The figure shows a schematic diagram of an embodiment of the data transceiver method based on the ZYNQ platform provided by the present invention. As Figure 3 shown, the embodiments of the present invention include the following steps:

[0052] Step S10: On the processor system side, the ARM processor receives and processes Ethernet data through the UDP protocol to obtain the processed data;

[0053] Step S20: Use the logical DMA engine to transfer the processed data to the programmable logic side, and perform packet encapsulation on the processed data through the UDP framing module to obtain Ethernet MAC frame data;

[0054] Step S30: Frame the Ethernet MAC frame data according to the physical layer frame format through the first MAC on the programmable logic side to obtain the first packet;

[0055] Step S40: Arbitrate the first packet and the second packet on the processor system side through the arbiter and send them to the external network interface chip via the GMII transmission interface.

[0056] In the data transceiver method based on the ZYNQ platform in the embodiments of the present invention, the data reception and data processing parts are still implemented by software on the ARM side. After the data processing is completed, there is no need to perform UDP packet encapsulation and other processing through the protocol stack. On the programmable logic side, a DMA engine is implemented logically to transfer the data to be sent to the programmable logic side, and then the data is packet-encapsulated through the UDP framing module. Then, the MAC implemented on the programmable logic side forms a physical layer protocol frame. Finally, the arbiter and the MAC on the processor system side share the same transmission port of the GMII interface to achieve the shared use of the Ethernet interface. Thus, the functions of UDP data reception, processing, and sending are realized through software and logic collaborative processing, greatly reducing the CPU resource consumption; avoiding the problem that when using the software protocol stack to send UDP data in the traditional method, as the amount of data increases, the CPU resource consumption becomes larger and larger because both the driver layer and the UDP protocol stack need to be implemented by software.

[0057] In some embodiments, the method further includes: the processor system side accesses and configures the registers of the logical DMA engine, UDP framing module, and the first MAC respectively through the APB bus and the APB slave function module.

[0058] In some embodiments, the method further includes: the Ethernet MAC frame data adopts the Ethernet frame format; the ARM processor configures the source MAC address and type of the frame header required by the Ethernet frame format, as well as all fields in the IP header and UDP header except the checksum through the APB bus; the checksum is obtained after being calculated by the UDP framing module according to the configuration information.

[0059] In some embodiments, the method further includes: determining the destination MAC address of the frame header based on the sending mode of the first packet, which further includes: in response to the sending mode being multicast sending, obtaining the destination MAC address based on the preset mapping relationship using the destination IP address of the multicast, and the preset mapping relationship is the mapping relationship between multiple IP addresses of the multicast and the corresponding MAC addresses; in response to the sending mode being unicast sending, obtaining the destination MAC address through the ARP protocol, and the ARP protocol is implemented by the software protocol stack on the processor system side.

[0060] In some embodiments, framing the Ethernet MAC frame data according to the physical layer frame format includes: adding a preamble and a start code before the Ethernet MAC frame data, and adding a check code after the Ethernet MAC frame data, and the check code is generated according to the Ethernet MAC frame data.

[0061] In some embodiments, sending the first packet and the second packet on the processor system side to the external network interface chip through the GMII sending interface after arbitration by the arbiter includes: temporarily storing the second packet sent by the second MAC on the programmable logic side in the buffer; in response to the second MAC obtaining the arbitration right, sending all the second packets in the buffer to the external network interface chip through the GMII sending interface, and releasing the arbitration right after the sending is completed.

[0062] In some embodiments, transferring the processed data to the programmable logic side through the logical DMA engine includes: using the AXI bus and transferring the processed data to the programmable logic side through the logical DMA engine.

[0063] The following are specific embodiments of the data sending and receiving method based on the ZYNQ platform of the present invention:

[0064] ZYNQ is a high-end embedded SoC (System on Chip) launched by Xilinx. It integrates an ARM processor (Advanced RISC Machines, a general-purpose processor) and an FPGA (Field Programmable Gate Array) on the chip. Compared with traditional embedded CPUs (Central Process Unit), it has powerful parallel processing capabilities.

[0065] Figure 4 It is a schematic structural diagram of a data transceiver method based on the ZYNQ platform according to an embodiment of the present invention. As Figure 4 shown, the structure includes a typical UDP (User Datagram Protocol) reception and data processing solution implemented on the PS (Processing System, processor system) side (i.e., the ARM side), and a UDP packet assembly and Ethernet interface sharing solution implemented on the PL (Programmable Logic) side. The implementation solution on the PS side is similar to the traditional solution. The following focuses on the implementation solution of UDP data transmission and Ethernet interface sharing on the PL side, which is divided into the following parts:

[0066] I. Data interaction between the PS side and the PL side

[0067] As Figure 4 shown, after the UDP data is received and processed on the ARM (Advanced RISC Machines, a general-purpose processor) side, the processed data needs to be handed over to the PL side logic for processing. In the ZYNQ chip adopted in this solution, the interaction between the two uses the AXI (Advanced Extensible Interface, a high-speed bus protocol) high-speed bus to achieve efficient data transfer; the APB (Advanced Peripheral Bus, a peripheral bus protocol) low-speed bus is used to implement register access configuration for the PL side DMA (Direct Memory Access), UDP Packager (UDP framing module), and PL side MAC (Media Access Control); at the same time, the MAC on the ARM side is connected to the PL logic side through the GMII interface (Gigabit media-independent interface). The interconnection between the PS and the PL is achieved through the above three interfaces.

[0068] When the PS side accesses the PL side registers through the APB bus, it is necessary to implement an APB Slave function module (APB slave function module) on the PL side to convert the APB bus into a register access interface, which are respectively connected to modules such as DMA, UDP Packager, and MAC to achieve the configuration management of the above modules.

[0069] II. DMA Module on the PL Side

[0070] In order to realize the data transfer from the ARM side to the PL logic side, a DMA engine is implemented on the logic side. After the UDP data processing is completed, the ARM configures the DMA registers and then the DMA starts to work. It transfers the data in the memory address on the ARM side to the PL side through the AXI4 bus and hands it over to the UDP Packager for processing. Usually, the DMA registers include configurations such as source address, destination address, length, and start. Here, since the destination address is only the UDP Packager, and the data is sent to the UDP Packager in a streaming manner rather than in an address-aligned manner, the implementation of the DMA is simplified. There is no need for a destination address register, reducing one register access operation of the ARM.

[0071] III. UDP Packager Module

[0072] Figure 5 The figure is a schematic structural diagram of the Ethernet MAC frame format provided according to an embodiment of the present invention. Since the data transferred from the ARM side to the PL side through the DMA is only user data, it is necessary to implement a UDP framing module UDPPackager on the PL side, where Figure 5 The source MAC address and type of the frame header information shown are configured through the APB bus when the ARM on the PS side is initialized. The destination MAC address is divided into two cases:

[0073] 1) When the sending mode is UDP multicast sending, since there is a fixed mapping relationship between the multicast IP address and the MAC address, the software calculates the multicast MAC address according to the fixed mapping relationship based on the multicast destination IP address.

[0074] 2) When the sending mode is UDP unicast sending, the MAC address of the receiving party is obtained through the ARP protocol, and the ARP protocol is implemented by the software protocol stack on the ARM side.

[0075] After obtaining the destination MAC address by the above method, the UDP Packager module is configured through the APB bus.

[0076] All fields in the IP header and UDP header except the checksum are configured by the ARM on the PS side to the UDPPackager module through the APB bus, and the checksum is obtained after being calculated by the UDP Packager module according to the configuration information.

[0077] After the UDP Packager obtains all the above information, it can generate the final Ethernet frame according to Figure 5 the format.

[0078] IV. MAC on the PL side

[0079] Figure 6 It is a schematic structural diagram of the Ethernet physical layer frame format provided according to the embodiments of the present invention. As Figure 6 shown, it is necessary to frame according to the Ethernet physical layer frame format on the basis of the Ethernet MAC frame format generated by the UDP Packager module. Specifically, it is manifested as adding a 7-byte preamble and a 1-byte start code before the Ethernet MAC frame, and adding a 4-byte check code at the end of the frame. The check code is generated according to the data in the Ethernet MAC frame. Since the PL side only needs to implement the transmission of Ethernet data, the PL side MAC only realizes the conversion from the Ethernet frame format to the physical layer frame format, and does not need to implement the conversion from the physical layer frame to the Ethernet frame format in the standard MAC.

[0080] V. Buffer

[0081] Figure 4 The buffer shown is used to temporarily store the data sent by the MAC on the PS side. Since the GMII interface output by the PS side does not have a handshake function, it is necessary to store the data in the buffer first when the PS side sends data, and then read out all the data in the buffer and send it out through the GMII interface on the PL side after obtaining the transmission arbitration right.

[0082] VI. Arbiter

[0083] As Figure 4As shown in the figure, since the MAC on the PS side and the MAC on the PL side need to share the same Ethernet interface to send data, the packets generated by the protocol stack on the PS side are output to the PL side through the GMII interface, and the data to be sent generated by the MAC on the PL side is sent to the external PHY chip (physical layer chip) via the GMII transmit interface after arbitration by the arbiter, realizing the sharing of the transmit path of the Ethernet interface. In the specific implementation, since the MAC on the PS side does not have a handshaking function, the arbitration priority of the MAC on the PS side is the highest. When the arbitration right switches to the MAC on the PS side, it is necessary to send all the buffer data before releasing the arbitration right, so as to ensure that the data of the MAC on the PS side will not be lost; the MAC on the PL side is designed with a handshaking mechanism, and data is sent after obtaining the arbitration right through arbitration when the MAC on the PS side is idle. Since the software protocol stack on the PS side only implements functions such as packet assembly, sending, and response of the IGMP and ARP protocols in the above scenario, and the data volume is small, it does not affect the real-time performance of the data sent on the PL side, thus realizing the shared use of the same Ethernet interface.

[0084] The above solution details the implementation method of sharing the Ethernet interface. In the solution, the transfer of user data, the framing of UDP data into Ethernet frame format, the framing of the physical layer, the arbiter, etc. are all implemented by the logic on the PL side, and there is no need for the software protocol stack on the ARM side to implement the above functions, which greatly reduces the resource consumption of the ARM.

[0085] Figure 7 It is a comparison schematic diagram of the existing technical solution and the data transceiver method based on the ZYNQ platform provided according to the embodiments of the present invention. As Figure 7 shown, based on the actual test results of the ZYNQ7000 platform, when using the traditional solution, when the UDP data volume is 360 Mbps, the CPU resource occupancy rate reaches about 35% ( Figure 7 the upper line in the figure), and when the solution in this embodiment is adopted, when the data volume is 360 Mbps, the CPU occupancy rate is only about 12% ( Figure 7 the lower line in the figure). It can be seen from this that this solution can greatly reduce the CPU resource occupancy rate when sending data through the UDP protocol.

[0086] Table 1

[0087] PL-side module \ Resource type Luts Registers DMA + UDP Packager + MAC + Arbiter 2K 2.5K

[0088] The above Table 1 shows the logical resources consumed by the DMA, UDP Packager, MAC, arbiter, etc. under the ZYNQ platform. Compared with the traditional method of calling the manufacturer's IP core to implement the DMA and MAC, using RTL (Register Transfer Level) to implement the simplified DMA and MAC is of great significance for effectively reducing the occupancy of the logical resources on the PL side.

[0089] In the second aspect of the embodiments of the present invention, a data transceiver system based on the ZYNQ platform is further provided. Figure 8 The figure shows a schematic diagram of an embodiment of the data transceiver system based on the ZYNQ platform provided by the present invention. As Figure 8 shown, a data transceiver system based on the ZYNQ platform includes: a processing module 10 configured to receive and process Ethernet data through the UDP protocol by an ARM processor on the processor system side to obtain processed data; a packaging module 20 configured to transfer the processed data to the programmable logic side through a logical DMA engine and perform packet encapsulation on the processed data through a UDP framing module to obtain Ethernet MAC frame data; a framing module 30 configured to frame the Ethernet MAC frame data according to the physical layer frame format through a first MAC on the programmable logic side to obtain a first message; and a sending module 40 configured to send the first message and a second message on the processor system side to an external network interface chip via a GMII sending interface after arbitration by an arbiter.

[0090] In the third aspect of the embodiments of the present invention, a computer-readable storage medium is further provided. Figure 9 The figure shows a schematic diagram of a computer-readable storage medium for implementing the data transceiver method based on the ZYNQ platform according to the embodiments of the present invention. As Figure 9 shown, the computer-readable storage medium 3 stores computer program instructions 31. When the computer program instructions 31 are executed by a processor, the method of any of the above embodiments is implemented.

[0091] It should be understood that, without conflict, all the embodiments, features, and advantages described above for the data transceiver method based on the ZYNQ platform according to the present invention are equally applicable to the data transceiver system and storage medium based on the ZYNQ platform according to the present invention.

[0092] In the fourth aspect of the embodiments of the present invention, a computer device is further provided, including a memory 402 and a processor 401 as Figure 10 shown. The memory 402 stores a computer program, and when the computer program is executed by the processor 401, the method of any of the above embodiments is implemented.

[0093] As Figure 10 shown, the figure is a schematic hardware structure diagram of an embodiment of a computer device for executing the data transceiver method based on the ZYNQ platform provided by the present invention. Take Figure 10Taking the computer device shown as an example, the computer device includes a processor 401 and a memory 402, and may further include: an input device 403 and an output device 404. The processor 401, the memory 402, the input device 403 and the output device 404 may be connected through a bus or other means. Figure 10 Taking the connection through the bus as an example. The input device 403 can receive input digital or character information, and generate key signal inputs related to user settings and function controls of the data transceiver system based on the ZYNQ platform. The output device 404 may include display devices such as a display screen.

[0094] The memory 402, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the data transceiver method based on the ZYNQ platform in the embodiments of the present application. The memory 402 may include a program storage area and a data storage area. Among them, the program storage area can store an operating system and application programs required for at least one function; the data storage area can store data created for the use of the data transceiver method based on the ZYNQ platform, etc. In addition, the memory 402 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state storage devices. In some embodiments, the memory 402 may optionally include a memory remotely set relative to the processor 401, and these remote memories can be connected to the local module through a network. Examples of the above network include but are not limited to the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0095] The processor 401 executes various functional applications and data processing of the server by running the non-volatile software programs, instructions, and modules stored in the memory 402, that is, implements the data transceiver method based on the ZYNQ platform in the above method embodiments.

[0096] Finally, it should be noted that the computer-readable storage medium (e.g., memory) in this article can be a volatile memory or a non-volatile memory, or can include both volatile memory and non-volatile memory. By way of example and not limitation, non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM), which can serve as an external cache memory. By way of example and not limitation, RAM can be obtained in various forms, such as synchronous RAM (DRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to include, but not be limited to, these and other suitable types of memory.

[0097] Those skilled in the art will also understand that the various exemplary logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability of hardware and software, a general description has been given of the functions of the various illustrative components, blocks, modules, circuits, and steps. Whether this function is implemented as software or hardware depends on the particular application and the design constraints imposed on the overall system. The functions that can be implemented by those skilled in the art in various ways for each particular application, but such implementation decisions should not be construed as causing a departure from the scope of the disclosure of the embodiments of the present invention.

[0098] The above are the exemplary embodiments disclosed by the present invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the disclosure of the embodiments of the present invention defined by the claims. The functions, steps, and / or actions of the method claims according to the disclosed embodiments herein need not be performed in any particular order. In addition, although the elements disclosed in the embodiments of the present invention can be described or claimed in individual form, they can also be understood as plural unless explicitly limited to the singular.

[0099] It should be understood that, as used herein, unless the context clearly supports an exception, the singular form "a" is also intended to include the plural form. It should also be understood that the "and / or" used herein refers to any and all possible combinations of one or more of the associated listed items. The serial numbers of the disclosed embodiments of the present invention above are merely for description and do not represent the superiority or inferiority of the embodiments.

[0100] Those of ordinary skill in the art should understand that any discussion of the above embodiments is only exemplary and is not intended to imply that the scope (including the claims) of the disclosure of the embodiments of the present invention is limited to these examples; under the concept of the embodiments of the present invention, the technical features in the above embodiments or different embodiments can also be combined, and there are many other variations in different aspects of the embodiments of the present invention as above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the embodiments of the present invention shall be included within the protection scope of the embodiments of the present invention.

Claims

1. A data transceiver method based on the ZYNQ platform, characterized in that, It includes the following steps: On the processor system side, the ARM processor receives and processes Ethernet data through the UDP protocol to obtain the processed data; The processed data is transferred to the programmable logic side through the logical DMA engine, and the processed data is packetized and encapsulated through the UDP framing module to obtain Ethernet MAC frame data; The Ethernet MAC frame data is framed according to the physical layer frame format through the first MAC on the programmable logic side to obtain the first packet; The first packet and the second packet on the processor system side are sent to the external network interface chip via the GMII transmission interface after arbitration by the arbiter; Sending the first packet and the second packet on the processor system side to the external network interface chip via the GMII transmission interface after arbitration by the arbiter includes: Temporarily storing the second packet sent by the second MAC on the processor system side in the buffer on the programmable logic side; In response to the second MAC obtaining the arbitration right, all the second packets in the buffer are sent to the external network interface chip through the GMII transmission interface, and the arbitration right is released after the sending is completed.

2. The method according to claim 1, characterized in that, It also includes: The processor system side accesses and configures the registers of the logical DMA engine, the UDP framing module, and the first MAC through the APB bus and the APB slave function module respectively.

3. The method according to claim 2, characterized in that, It also includes: The Ethernet MAC frame data adopts the Ethernet frame format; The ARM processor configures the source MAC address and type of the frame header required by the Ethernet frame format, as well as all fields in the IP header and UDP header except the checksum through the APB bus; The checksum is obtained by the UDP framing module according to the configuration information after calculation.

4. The method according to claim 3, characterized in that, It also includes: Determining the destination MAC address of the frame header based on the sending method of the first packet, which further includes: In response to the sending method being multicast sending, obtaining the destination MAC address based on the preset mapping relationship using the destination IP address of the multicast, and the preset mapping relationship is the mapping relationship between multiple IP addresses of the multicast and the corresponding MAC addresses; In response to the sending method being unicast sending, obtaining the destination MAC address through the ARP protocol, and the ARP protocol is implemented by the software protocol stack on the processor system side.

5. The method according to claim 1, characterized in that, Framing the Ethernet MAC frame data according to the physical layer frame format includes: Adding a preamble and a start code before the Ethernet MAC frame data, and adding a check code after the Ethernet MAC frame data, and the check code is generated according to the Ethernet MAC frame data.

6. The method according to claim 1, characterized in that, Transferring the processed data to the programmable logic side through the logical DMA engine includes: Using the AXI bus and transferring the processed data to the programmable logic side through the logical DMA engine.

7. A data transceiver system based on the ZYNQ platform, characterized in that, It includes: A processing module configured to, on the processor system side, the ARM processor receives and processes Ethernet data through the UDP protocol to obtain the processed data; The encapsulation module is configured to transfer the processed data to the programmable logic side through the logical DMA engine, and packetize and encapsulate the processed data through the UDP framing module to obtain Ethernet MAC frame data; The framing module is configured to frame the Ethernet MAC frame data into a first packet according to the physical layer frame format through the first MAC on the programmable logic side; And The sending module is configured to send the first packet and the second packet on the processor system side to an external network interface chip via the GMII sending interface after arbitration by an arbiter; Sending the first packet and the second packet on the processor system side to an external network interface chip via the GMII sending interface after arbitration by an arbiter includes: temporarily storing the second packet sent by the second MAC on the processor system side in a buffer on the programmable logic side; In response to the second MAC obtaining the arbitration right, sending all the second packets in the buffer to the external network interface chip via the GMII sending interface, and releasing the arbitration right after the sending is completed.

8. A computer-readable storage medium, characterized in that, Stores computer program instructions, and when the computer program instructions are executed by a processor, the method described in any one of claims 1-6 is implemented.

9. A computer device, including a memory and a processor, characterized in that, The memory stores a computer program, and when the computer program is executed by the processor, the method described in any one of claims 1-6 is executed.

Images