A decoding method and apparatus

Abstract

This specification provides a decoding method and apparatus through one or more embodiments, comprising: performing hard-decision decoding on a received sequence to obtain a hard-decision decoded sequence; performing a permutation process on a generator matrix to obtain a permuted generator matrix; and, in response to the failure to meet a preset decoding termination condition, selecting a target error pattern based on a preset set of error patterns, and generating a decoding result corresponding to the current decoding iteration based on the target error pattern, the hard-decision decoded sequence, and the permuted generator matrix. The decoding method of this embodiment can guarantee decoding performance and reduce decoding complexity.

Description

Technical Field

[0001] This specification relates to one or more embodiments in the field of communication technology, and in particular to a decoding method and apparatus. Background Technology

[0002] The 3rd Generation Partnership Project (3GPP) has defined ultra-reliable low-latency communications (URLLC) as a key communication scenario for 5G and 6G networks and above. URLLC requires decoding algorithms to possess both high performance and low complexity. Ordered Statistic Decoding (OSD) has been proposed as a candidate general decoding algorithm for URLLC. Traditional ordered statistical decoding algorithms can achieve maximum likelihood (ML) decoding performance, but their complexity is relatively high. Summary of the Invention

[0003] In view of this, the purpose of one or more embodiments of this specification is to provide a decoding method and apparatus that can improve decoding performance and reduce complexity.

[0004] For the purposes described above, one or more embodiments of this specification provide a decoding method, including:

[0005] Hard-decision decoding is performed on the received sequence to obtain the hard-decision decoded sequence;

[0006] The generating matrix is ​​permuted to obtain the permuted generating matrix;

[0007] In response to the failure to meet the preset decoding termination condition, a target error pattern is selected based on a preset set of error patterns. The decoding result corresponding to the current decoding iteration is generated based on the target error pattern, the hard-decision decoding sequence, and the permuted generator matrix.

[0008] Optionally, hard-decision decoding is performed on the received sequence to obtain a hard-decision decoded sequence, including:

[0009] The received sequence is permuted to obtain the permuted received sequence;

[0010] Hard-decision decoding is performed on the permuted received sequence to obtain the hard-decision decoded sequence.

[0011] Optionally, after selecting the target error pattern, the following may also be included:

[0012] Expand the possible error patterns by adding the expanded error patterns to the error pattern set to form an updated error pattern set.

[0013] Optionally, the selection of the target error pattern includes:

[0014] For each error pattern in the set of error patterns:

[0015] The hard-decision decoding sequence is flipped according to the error pattern to obtain the flipped decoding sequence;

[0016] Calculate the Euclidean distance between the flipped decoded sequence and the permuted received sequence;

[0017] The error pattern with the smallest Euclidean distance is determined as the target error pattern.

[0018] Optionally, the set of initialized error patterns includes initialized error patterns, which are sequences of all zeros;

[0019] The expansion of possible error patterns, which involves adding the expanded error patterns to the error pattern set, includes:

[0020] In response to the error pattern set being an initialized error pattern set, the bit value of the bit with the largest bit sequence number in the initialized error pattern is modified to 1, and the modified error pattern is added to the error pattern set;

[0021] In response to the fact that the error pattern set is an uninitialized error pattern set, the target bit with the smallest bit value of 1 and bit index in the target error pattern is searched. In response to the fact that the index of the target bit is not 1, the bit value of the target bit is modified to 0 to obtain a modified error pattern. Based on the modified error pattern, the bit value of the bit preceding the target bit is modified to 1 to obtain another modified error pattern. The two modified error patterns are added to the error pattern set.

[0022] Optionally, based on the target error pattern, the hard-decision decoding sequence, and the permuted generator matrix, the decoding result corresponding to the current decoding iteration is generated, including:

[0023] The hard-decision decoding sequence is flipped according to the target error pattern to obtain the flipped decoding sequence;

[0024] The flipped decoded sequence is re-encoded using the permuted generator matrix to obtain a candidate sequence;

[0025] In response to the candidate sequence passing the verification of the preset encoding method, the candidate sequence is modulated to obtain a modulated sequence;

[0026] Calculate the Euclidean distance between the modulated sequence and the permuted received sequence;

[0027] In response to the Euclidean distance being less than a preset minimum Euclidean distance, the candidate sequence is subjected to inverse permutation processing to obtain the decoding result.

[0028] Optionally, the method further includes:

[0029] In response to the candidate sequence failing the verification, or the Euclidean distance being greater than the minimum Euclidean distance, the current decoding count is updated;

[0030] In response to the failure to meet the preset decoding termination condition, a new target error pattern is selected. Based on the newly selected target error pattern, the hard-decision decoding sequence, and the permuted generator matrix, an updated decoding result corresponding to the current decoding iteration is generated.

[0031] Optionally, the encoding method is a CRC concatenated polar code; in response to the verification of the candidate sequence through the preset encoding method, the following steps are included:

[0032] The candidate sequence is verified by freezing bit;

[0033] The candidate sequences conform to CRC constraints.

[0034] Alternatively, the encoding method is a linear block code other than CRC-concatenated polar codes; in response to the verification of the candidate sequence through the preset encoding method, the following is included:

[0035] The candidate sequence passes the verification using a preset verification matrix.

[0036] Optionally, the decoding termination condition is that the number of decoding attempts reaches a preset maximum number of decoding attempts, or that the number of decoded sequences that pass verification reaches a predetermined number.

[0037] This application also provides a decoding device, including:

[0038] The received sequence processing module is used to perform hard decision decoding on the received sequence to obtain a hard decision decoded sequence;

[0039] The generation matrix processing module is used to perform permutation processing on the generation matrix to obtain the permuted generation matrix;

[0040] The decoding module is used to respond to the failure to meet the preset decoding termination condition, select a target error pattern based on a preset error pattern set, and generate the decoding result corresponding to the current decoding count according to the target error pattern, the hard-decision decoding sequence, and the permuted generator matrix.

[0041] As can be seen from the above description, the decoding method and apparatus provided in one or more embodiments of this specification perform hard-decision decoding on the received sequence to obtain a hard-decision decoding sequence, perform permutation processing on the generator matrix to obtain a permuted generator matrix, and if the current decoding count has not reached the preset maximum decoding count, select a target error pattern based on a preset error pattern set, and generate the decoding result corresponding to the current decoding count based on the target error pattern, the hard-decision decoding sequence, and the permuted generator matrix. The decoding method of this embodiment can guarantee decoding performance and reduce decoding complexity. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in one or more embodiments of this specification or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only one or more embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is a schematic diagram of the method flow of one or more embodiments of this specification;

[0044] Figure 2 This is a schematic flowchart of a hard-decision decoding method according to one or more embodiments of this specification;

[0045] Figure 3 This is a schematic flowchart of a generation matrix processing method according to one or more embodiments of this specification;

[0046] Figure 4 This is a schematic diagram of a method flow according to another embodiment of this specification;

[0047] Figure 5 This is a schematic diagram of the decoding process for one or more embodiments of this specification;

[0048] Figure 6 This is a schematic diagram of the device structure of one or more embodiments of this specification;

[0049] Figure 7 This is a schematic diagram of the structure of an electronic device according to one or more embodiments of this specification. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0051] It should be noted that, unless otherwise defined, the technical or scientific terms used in one or more embodiments of this specification should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar words used in one or more embodiments of this specification do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0052] As described in the background section, the OSD decoding algorithm, as a candidate general-purpose decoding algorithm for URLLC, can decode any linear block code. The OSD decoding algorithm first performs hard-decision decoding based on a reliability metric, and then reprocesses the decoded codewords obtained from the hard decisions until maximum likelihood performance is achieved. For codes with a length less than 64, the OSD decoding algorithm has low complexity. However, in URLLC communication scenarios, short codes reduce communication reliability, and the complexity of the OSD decoding algorithm increases with higher code rates. Therefore, in URLLC communication scenarios, how to ensure communication performance while reducing decoding complexity is a problem that needs to be solved.

[0053] In view of this, embodiments of this application provide a decoding method that performs hard-decision decoding on the received sequence to obtain a hard-decision decoding sequence, performs permutation processing on the generator matrix to obtain a permuted generator matrix, and then performs decoding with the maximum number of decoding iterations. During the decoding process, target error patterns are selected in an orderly manner, and decoding is performed based on the target error patterns, the hard-decision decoding sequence, and the permuted generator matrix to obtain the decoding result. This application improves the OSD decoding method, which can both guarantee decoding performance and reduce complexity, and is suitable for decoding short and medium-to-long codes.

[0054] The technical solution of this application will be further described in detail below through specific embodiments.

[0055] like Figure 1 As shown in the embodiments of this specification, a decoding method is provided, including:

[0056] S101: Perform hard decision decoding on the received sequence to obtain a hard decision decoded sequence;

[0057] S102: Perform a permutation on the generating matrix to obtain the permuted generating matrix;

[0058] S103: In response to the failure to meet the preset decoding end condition, select the target error pattern based on the preset error pattern set, and generate the decoding result corresponding to the current decoding count according to the target error pattern, the hard-decision decoding sequence and the permuted generator matrix.

[0059] The decoding method provided in this embodiment first performs hard-decision decoding on the received sequence to obtain a hard-decision decoding sequence, and then performs a permutation process on the generator matrix to obtain a permuted generator matrix. Decoding then proceeds. During each decoding iteration, a target error pattern is selected from the set of error patterns. Decoding is then performed based on the target error pattern, the hard-decision decoding sequence, and the permuted generator matrix. When the decoding termination condition is met, the final decoding result is obtained. By selecting the target error pattern in an orderly manner, the correct codeword sequence can be found quickly, improving decoding efficiency, reducing decoding complexity, and ensuring decoding performance.

[0060] In some embodiments, hard-decision decoding is performed on the received sequence to obtain a hard-decision decoded sequence, including:

[0061] The received sequence is permuted to obtain the permuted received sequence;

[0062] Hard-decision decoding is performed on the permuted received sequence to obtain the hard-decision decoded sequence.

[0063] Combination Figure 2 As shown, in this embodiment, the method for hard-decision decoding of the received sequence is to first perform a permutation process on the received sequence, and then perform hard-decision decoding on the permuted received sequence to obtain a hard-decision decoded sequence. The permutation process of the received sequence to obtain the permuted received sequence includes: permuting the received sequence using a first permutation function to obtain a first-permuted received sequence; and permuting the first-permuted received sequence using a second permutation function to obtain a second-permuted received sequence. Based on this, hard-decision decoding is performed on the first K bits of the second-permuted received sequence to obtain a hard-decision decoded sequence.

[0064] Specifically, if the information sequence The generator matrix is ​​G. The information sequence is encoded using the generator matrix to generate the transmission sequence. After the transmitted sequence is transmitted through the channel, the output received sequence is: For a linear block code (N, K), where N is the code length and K is the number of data bits, let... The first permutation function is: λ1 is used to sort the code elements in the sequence from high to low reliability; The second permutation function is: λ2 is used to find K unrelated column vectors starting from the first column on the left, which are used as the first K columns of the permuted matrix. The remaining columns are used as the last NK columns of the permuted matrix in order from left to right.

[0065] For the received sequence The received sequence is permuted using the first permutation function, which arranges the symbols in the sequence from highest to lowest reliability, resulting in the received sequence r1 after the first permutation. N , represented as In the first permutation, the symbol at position i in the received sequence is transformed to position j. 1i In the received sequence r1 after the first permutation N In the equation, |r1|≥|r2|≥…≥|r N |,|r i | is a measure of the reliability of the code element.

[0066] The received sequence r1 after the first permutation is processed using the second permutation function. N Perform a permutation process to obtain the received sequence after the second permutation. Represented as Where, |v1|≥|v2|≥…≥|v K |and|v K+1 |≥|v K+2 |≥…≥|v N |. Then, the received sequence will be... The first K bits are selected as the most reliable K bits for hard-decision decoding, resulting in a hard-decision decoding sequence. Through statistical analysis, hard-decision decoding sequences... It contains only a small number of error information bits, which reduces the number of possible codewords to be tested compared to other decoding algorithms, and the NK bits discarded in hard-decision decoding do not significantly affect decoding performance.

[0067] In some embodiments, the generating matrix is ​​permuted to obtain a permuted generating matrix, including: permuting the generating matrix using a first permutation function to obtain a first-permuted generating matrix; permuting the first-permuted generating matrix using a second permutation function to obtain a second-permuted generating matrix; and performing Gaussian elimination on the second-permuted generating matrix to obtain a permuted generating matrix.

[0068] Combination Figure 3As shown, in this embodiment, for the generating matrix G, the column vectors of the generating matrix are permuted using the first permutation function to obtain the generating matrix G′ after the first permutation, denoted as G′=λ1(G). Based on the generating matrix G′ after the first permutation, K independent and unrelated columns are searched starting from the first column on the left, which are taken as the first K columns of the generating matrix G″ after the second permutation. The remaining columns are taken as the last NK columns of the generating matrix G″ in order from left to right. Then, elementary row operations are performed on the generating matrix G″ to perform Gaussian elimination, transforming the first K columns of the generating matrix G″ into identity matrices, to obtain the generating matrix G1 after Gaussian elimination.

[0069] In some embodiments, after selecting the target error pattern, the method further includes:

[0070] Expand the possible error patterns by adding the expanded error patterns to the error pattern set, forming an updated error pattern set.

[0071] like Figure 4 As shown, in this embodiment, after selecting the target error pattern, the error patterns in the error pattern set are expanded, the error pattern set is updated, and then decoding is performed based on the target error pattern. If the decoding termination condition is not met, a new target error pattern is selected from the updated error pattern set, the error pattern set is expanded again, and the error pattern set is updated. Based on the newly selected target error pattern, the hard-decision decoding sequence, and the permuted generator matrix, the corresponding decoding result is generated. This process of selecting the target error pattern, updating the error pattern set, and decoding is repeated until the decoding termination condition is met, yielding the final decoding result. In this way, by selecting the target error pattern in an orderly manner, the decoding complexity can be reduced and the decoding efficiency improved.

[0072] In some embodiments, selecting the target error pattern includes:

[0073] For each error pattern in the error pattern set:

[0074] The hard-decision decoding sequence is flipped according to the error pattern to obtain the flipped decoding sequence.

[0075] Calculate the Euclidean distance between the flipped decoded sequence and the permuted received sequence;

[0076] The error pattern with the smallest Euclidean distance is identified as the target error pattern.

[0077] This embodiment provides a method for selecting a target error pattern from a set of error patterns. For the nth error pattern in the set... According to the incorrect diagram Hard decision decoding sequence The sequence is flipped to obtain the flipped decoded sequence. Then calculate the first K sequences of the flipped decoded sequence and the permuted received sequence. The Euclidean distance between them is expressed as (Where, 1k represents the K bits of the sequence being 1, and 2 indicates that the demodulation method is BPSK); After calculating the Euclidean distances corresponding to all error patterns, the minimum Euclidean distance is selected, and the error pattern corresponding to the minimum Euclidean distance is taken as the target error pattern. After selecting the target error pattern, delete the target error pattern from the error pattern set.

[0078] In some embodiments, the set of initialized error patterns includes initialized error patterns, which are sequences of all zeros.

[0079] Expand the possible error patterns by adding the expanded error patterns to the error pattern set, including:

[0080] In response to an initialized error pattern set, the bit value of the largest bit in the initial error pattern is modified to 1, and the modified error pattern is added to the error pattern set.

[0081] In response to the error pattern set being an uninitialized error pattern set, the target bit with the smallest bit value of 1 and bit index is found in the target error pattern. In response to the target bit's index not being 1, the bit value of the target bit is modified to 0, resulting in a modified error pattern. Based on this modified error pattern, the bit value of the bit preceding the target bit is modified to 1, resulting in another modified error pattern. The two modified error patterns are then added to the error pattern set.

[0082] In this embodiment, the first decoding selects a target error pattern based on an initialized error pattern set. This set includes initial error patterns with all-zero sequences, and these initial error patterns are used as the target error patterns. Next, the initial error patterns are removed from the error pattern set, and then modified. The modified error patterns are added to the error pattern set as extended error patterns. When modifying an initial error pattern, the rightmost bit is changed from 0 to 1. If the bit numbers are arranged in ascending order from left to right, the bit with the largest bit number is changed to 1, resulting in the extended error pattern.

[0083] After each selection of a target error pattern, the error pattern set is expanded to form an updated error pattern set. Except for the first decoding, each subsequent decoding is based on the updated error pattern set to select a target error pattern. When expanding the error pattern, for each selected target error pattern, the bits with a value of 1 are searched. If multiple bits have a value of 1, the leftmost bit is selected as the target bit, i.e., the bit with the smallest bit index is selected. After determining the target bit, its value is changed from 1 to 0, resulting in a modified error pattern. Based on this modified error pattern, the value of the bit preceding the target bit (the bit with a smaller bit index) is changed from 0 to 1, resulting in another modified error pattern. These two modified error patterns are added to the error pattern set. If the selected bit with the smallest bit index is the first bit, no further expansion of the error pattern is performed. In this embodiment, since the received sequence after permutation is sorted from high to low reliability, when selecting the target error pattern, searching for possible error patterns in reverse order (i.e., from low to high reliability) can find the correct error pattern as quickly as possible, thereby improving decoding efficiency.

[0084] In some embodiments, the decoding result corresponding to the current decoding iteration is generated based on the target error pattern, the hard-decision decoding sequence, and the permuted generator matrix, including:

[0085] The hard-decision decoding sequence is flipped according to the target error pattern to obtain the flipped decoding sequence.

[0086] The flipped decoded sequence is re-encoded using the permuted generator matrix to obtain a candidate sequence;

[0087] In response to the candidate sequence passing the verification by the preset encoding method, the candidate sequence is modulated to obtain the modulated sequence;

[0088] Calculate the Euclidean distance between the modulated sequence and the permuted received sequence;

[0089] In response to the Euclidean distance being less than the preset minimum Euclidean distance, the candidate sequence is subjected to inverse permutation processing to obtain the decoding result.

[0090] like Figure 5 As shown, in this embodiment, after determining the target error pattern, decoding is performed based on the target error pattern, the hard-decision decoding sequence, and the permuted generator matrix. Specifically, decoding is first performed according to the target error pattern. Hard decision decoding sequence The sequence is flipped to obtain the flipped decoded sequence. The reversed decoded sequence is processed using the permuted generator matrix G1. Re-encode to obtain candidate sequences Next, the candidate sequence is validated. If the validation passes, the candidate sequence is modulated (e.g., using BPSK modulation) to obtain the modulated sequence. Calculate the modulated sequence and the permuted received sequence Euclidean distance between Represented as If the Euclidean distance is less than the minimum Euclidean distance Then, the candidate sequence is subjected to an inverse permutation process, which is the opposite of the permutation process. The decoded sequence is obtained after the inverse permutation process. Simultaneously, the calculated Euclidean distance is used as the updated minimum Euclidean distance, which is infinitely large during system initialization. In this embodiment, during the decoding process, candidate sequences are verified. After successful verification, the Euclidean distance is calculated and judged, resulting in more accurate decoding results and improved decoding performance.

[0091] In some methods, inverse permutation processing is performed on the candidate sequence. This includes using a second inverse permutation function to perform inverse permutation processing on the candidate sequence to obtain the candidate sequence after the first inverse permutation processing. Then, the first inverse permutation function is used to perform inverse permutation processing on the candidate sequence after the first inverse permutation processing to obtain the candidate sequence after inverse permutation processing, i.e., the decoded sequence. Here, the first inverse permutation function is the inverse operation function of the first permutation function, and the second inverse permutation function is the inverse operation function of the second permutation function. For example, during the permutation processing, the first permutation function is used to transform the symbol at position i to position j. 1i Using the second permutation function to change position j 1i The symbol transformation to position j 2i During the inverse permutation process, the second inverse permutation function is used to change the position j. 2i The symbol transformation to position j 1i Using the first inverse permutation function, position j 1i The symbol is transformed to position i.

[0092] In some embodiments, the preset decoding termination condition can be reaching a preset maximum decoding count or reaching a predetermined number of verified decoding sequences. In one scenario, if the number of verified decoding sequences has reached the predetermined number before the maximum decoding count is reached, and the expected decoding result is determined, then decoding ends; for example, decoding can stop when the number of verified decoding sequences is 2 or 3. In another scenario, if the maximum decoding count is reached but the number of verified decoding sequences has not reached the predetermined number, then decoding ends. By setting a finite number of decoding counts, decoding complexity can be reduced. Optionally, the maximum decoding count can be set based on the code length N and data bits K of the block code; the specific value is not limited.

[0093] In some embodiments, the decoding method further includes:

[0094] In response to a candidate sequence failing the verification or the Euclidean distance being greater than the minimum Euclidean distance, update the current decoding count;

[0095] In response to the failure to meet the preset decoding termination condition, a new target error pattern is selected. Based on the new target error pattern, the hard-decision decoding sequence, and the permuted generator matrix, an updated decoding result corresponding to the current decoding iteration is generated.

[0096] In this embodiment, if the candidate sequence fails the verification during the decoding process, or if the calculated Euclidean distance is greater than or equal to the minimum Euclidean distance, the target error pattern needs to be reselected, and the decoding is performed again based on the reselected target error pattern, the hard-decision decoding sequence, and the permuted generator matrix.

[0097] In some embodiments, the encoding method is CRC concatenated polar code; in response to the verification of the candidate sequence passing the preset encoding method, the following steps are included:

[0098] Candidate sequences are verified by freezing bit validation;

[0099] The candidate sequence conforms to the CRC constraint relationship.

[0100] In this embodiment, during the decoding process, the candidate sequence is verified according to the encoding method used. For CRC-concatenated polar codes, the candidate sequence is verified using a frozen bit check method (except for the information bits, the remaining NK bits are frozen bits, and their values ​​should be 0. During verification, it is determined whether a 1 appears at the position of the frozen bit; if a 1 appears, it is determined that the frozen bit check has failed). At the same time, it is determined whether the candidate sequence conforms to the CRC constraint relationship (the receiving end calculates the CRC check bit according to a predetermined method, and uses the CRC check bit to determine whether the data transmission is correct and complete). If the candidate sequence passes the frozen bit check and also conforms to the CRC constraint relationship, then the candidate sequence verification is successful.

[0101] In some embodiments, the encoding method is a linear block code other than CRC-concatenated polar codes; in response to the candidate sequence passing the verification of the preset encoding method, the method includes: verifying the candidate sequence using a preset check matrix. That is, for linear block codes other than CRC-concatenated polar codes, the candidate sequence is verified according to a specific check matrix, the candidate sequence is multiplied by the check matrix, and if the calculation result is 0, the candidate matrix verification is passed.

[0102] The improved OSD decoding method provided in this specification performs decoding even when the decoding termination condition is not met. During the decoding process, it predicts possible target error patterns in an orderly manner based on reliability, which can quickly determine the correct codeword sequence, reduce decoding complexity, and improve decoding efficiency. At the same time, by verifying the candidate sequences and further judging the Euclidean distance of the verified sequences, the decoding accuracy can be improved, thereby improving decoding performance. Moreover, this decoding method is applicable to both short and medium-length codes.

[0103] It should be noted that the methods of one or more embodiments of this specification can be executed by a single device, such as a computer or server. The methods of this embodiment can also be applied in a distributed scenario, where multiple devices cooperate to complete the task. In such a distributed scenario, one of these devices may execute only one or more steps of the methods of one or more embodiments of this specification, and the multiple devices will interact with each other to complete the method described.

[0104] It should be noted that the above description describes specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims may be performed in a different order than that shown in the embodiments and still achieve the desired results. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0105] like Figure 6 As shown in the embodiments of this specification, a decoding device is also provided, comprising:

[0106] The received sequence processing module is used to perform hard decision decoding on the received sequence to obtain a hard decision decoded sequence;

[0107] The generation matrix processing module is used to perform permutation processing on the generation matrix to obtain the permuted generation matrix;

[0108] The decoding module is used to respond to the failure to meet the preset decoding termination condition, select the target error pattern based on the preset error pattern set, and generate the decoding result corresponding to the current decoding count according to the target error pattern, the hard-decision decoding sequence and the permuted generator matrix.

[0109] For ease of description, the above apparatus is described in terms of function, divided into various modules. Of course, when implementing one or more embodiments of this specification, the functions of each module can be implemented in one or more software and / or hardware.

[0110] The apparatus described above is used to implement the corresponding methods in the foregoing embodiments and has the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0111] Figure 7 This embodiment illustrates a more specific hardware structure of an electronic device, which may include a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050. The processor 1010, memory 1020, input / output interface 1030, and communication interface 1040 are interconnected internally via the bus 1050.

[0112] The processor 1010 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this specification.

[0113] The memory 1020 can be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 1020 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program code is stored in the memory 1020 and is called and executed by the processor 1010.

[0114] The input / output interface 1030 is used to connect input / output modules to realize information input and output. Input / output modules can be configured as components within the device (not shown in the figure) or externally connected to the device to provide corresponding functions. Input devices may include keyboards, mice, touchscreens, microphones, various sensors, etc., while output devices may include displays, speakers, vibrators, indicator lights, etc.

[0115] The communication interface 1040 is used to connect a communication module (not shown in the figure) to enable communication between this device and other devices. The communication module can communicate via wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0116] Bus 1050 includes a pathway for transmitting information between various components of the device, such as processor 1010, memory 1020, input / output interface 1030, and communication interface 1040.

[0117] It should be noted that although the above-described device only shows the processor 1010, memory 1020, input / output interface 1030, communication interface 1040, and bus 1050, in specific implementations, the device may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above-described device may only include the components necessary for implementing the embodiments of this specification, and not necessarily all the components shown in the figures.

[0118] The electronic devices described above are used to implement the corresponding methods in the foregoing embodiments and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0119] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this disclosure (including the claims) is limited to these examples; within the framework of this disclosure, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of one or more embodiments of this specification as described above, which are not provided in detail for the sake of brevity.

[0120] Additionally, to simplify the description and discussion, and to avoid obscuring one or more embodiments of this specification, well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided drawings. Furthermore, the apparatus may be illustrated in block diagram form to avoid obscuring one or more embodiments of this specification, and this also takes into account the fact that the details of implementation of these block diagram apparatuses are highly dependent on the platform on which one or more embodiments of this specification will be implemented (i.e., these details should be fully understood by those skilled in the art). While specific details (e.g., circuits) have been set forth to describe exemplary embodiments of this disclosure, it will be apparent to those skilled in the art that one or more embodiments of this specification may be implemented without these specific details or with variations thereof. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0121] Although this disclosure has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0122] One or more embodiments of this specification are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be included within the scope of protection of this disclosure.

Claims

1. A decoding method, comprising: The method comprises the following steps: performing hard decision decoding on the received sequence to obtain a hard decision decoding sequence; performing permutation processing on the generator matrix to obtain a permuted generator matrix; in response to a preset decoding end condition not being met, selecting a target error pattern from a preset error pattern set, expanding a possible error pattern, adding the expanded error pattern to the error pattern set to form an updated error pattern set, comprising: in response to the error pattern set being an initialized error pattern set, modifying the bit value of the bit with the largest bit sequence number in the initialized error pattern in the initialized error pattern set to 1, and adding the modified error pattern to the error pattern set; wherein the initialized error pattern is an all-zero sequence; in response to the error pattern set being a non-initialized error pattern set, finding a target bit in the target error pattern with a bit value of 1 and the smallest bit sequence number, in response to the sequence number of the target bit not being 1, modifying the bit value of the target bit to 0 to obtain a modified error pattern, based on the modified error pattern, modifying the bit value of the previous bit of the target bit to 1 to obtain another modified error pattern, and adding the two modified error patterns to the error pattern set; in response to the sequence number of the target bit being 1, no longer expanding the error pattern; generating a decoding result corresponding to the current decoding number according to the target error pattern, the hard decision decoding sequence and the permuted generator matrix.

2. The method of claim 1, wherein, performing hard decision decoding on the received sequence to obtain a hard decision decoding sequence, comprising: performing permutation processing on the received sequence to obtain a permuted received sequence; performing hard decision decoding on the permuted received sequence to obtain the hard decision decoding sequence.

3. The method of claim 1, wherein, The method comprises the following steps: for each error pattern in the error pattern set: flip the hard decision decoding sequence according to the error pattern to obtain a flipped decoding sequence; calculate the Euclidean distance between the flipped decoding sequence and the permuted received sequence; determine the error pattern with the smallest Euclidean distance as the target error pattern.

4. The method of claim 2, wherein, The method comprises the following steps: flip the hard decision decoding sequence according to the target error pattern to obtain a flipped decoding sequence; re-encode the flipped decoding sequence using the permuted generator matrix to obtain a candidate sequence; in response to the candidate sequence passing the preset encoding mode check, modulate the candidate sequence to obtain a modulated sequence; calculate the Euclidean distance between the modulated sequence and the permuted received sequence; in response to the Euclidean distance being less than a preset minimum Euclidean distance, perform inverse permutation processing on the candidate sequence to obtain the decoding result.

5. The method of claim 4, wherein, The method further comprises the following steps: in response to the candidate sequence failing to pass the check or the Euclidean distance being greater than the minimum Euclidean distance, updating the current decoding number; In response to the preset decoding end condition not being met, a target error pattern is reselected, and a decoding result corresponding to the current decoding number is generated according to the reselected target error pattern, the hard decision decoding sequence and the permuted generator matrix.

6. The method of claim 4, wherein, The encoding mode is a CRC concatenated polar code; in response to the candidate sequence passing the check of the preset encoding mode, the method comprises the following steps of: The candidate sequence passes the check of the frozen bit; The candidate sequence meets the CRC constraint relationship; Or, the encoding mode is a linear block code other than the CRC concatenated polar code; in response to the candidate sequence passing the check of the preset encoding mode, the method comprises the following steps of: The candidate sequence passes the check of the preset check matrix.

7. The method of claim 4, wherein, The decoding end condition is that the decoding number reaches a preset maximum decoding number, or the number of decoding sequences passing the check reaches a preset number.

8. A decoding device, comprising: The method comprises the following steps of: A received sequence processing module is configured to perform hard decision decoding on a received sequence to obtain a hard decision decoding sequence; A generator matrix processing module is configured to perform permutation processing on a generator matrix to obtain a permuted generator matrix; A decoding module is configured to, in response to a preset decoding end condition not being met, select a target error pattern based on a preset error pattern set, expand a possible error pattern, add the expanded error pattern to the error pattern set to form an updated error pattern set, and comprise the following steps of: In response to the error pattern set being an initialized error pattern set, the bit value of the bit with the largest bit serial number in the initialized error pattern in the initialized error pattern set is modified to 1, and the modified error pattern is added to the error pattern set; wherein the initialized error pattern is an all-zero sequence; In response to the error pattern set being a non-initialized error pattern set, a target bit with a bit value of 1 and a smallest bit serial number in the target error pattern is found, in response to the serial number of the target bit not being 1, the bit value of the target bit is modified to 0 to obtain a modified error pattern, based on the modified error pattern, the bit value of a previous bit of the target bit is modified to 1 to obtain another modified error pattern, and the two modified error patterns are added to the error pattern set; in response to the serial number of the target bit being 1, the error pattern is not expanded any more; A decoding result corresponding to the current decoding number is generated according to the target error pattern, the hard decision decoding sequence and the permuted generator matrix.

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