An OSD decoding method and system of parallel Gaussian elimination, a terminal and a storage medium

Abstract

The application discloses an OSD decoding method and system based on parallel Gaussian elimination, a terminal and a storage medium. The method comprises the following steps: obtaining a communication decoding task, obtaining an original matrix to be processed and corresponding received symbols according to the communication decoding task, performing Gaussian elimination on the original matrix according to the received symbols to obtain a first matrix and corresponding first received symbols, performing bit flipping on the first received symbols to obtain target received symbols, performing re-encoding on the target received symbols and the first matrix to obtain a plurality of re-encoding results, and performing screening on all the re-encoding results to obtain a decoding result. Each processing unit in the application adopts binary field operation and does not perform approximate processing. The matrix array and the corresponding received symbols are processed in sequence, and only addition and subtraction operations in the same column are involved, so that parallel Gaussian elimination operation is realized, and the decoding efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a parallel Gaussian elimination OSD decoding method, system, terminal, and computer-readable storage medium. Background Technology

[0002] Gaussian elimination is an algorithm that transforms a matrix into an identity matrix through basic operations such as column swapping, column addition / subtraction, row swapping, and row addition / subtraction. It is widely used in solving linear equations and other problems. In communication systems, Gaussian elimination is also frequently used in processes such as channel encoding / decoding and signal equalization. Due to the high real-time requirements of communication systems, parallel Gaussian elimination algorithms are often implemented on FPGAs (Field-Programmable Gate Arrays) to improve computation speed. Parallel Gaussian elimination algorithms have various implementation methods, allowing for row-by-row processing or column-by-column processing.

[0003] Ordered Statistics Decoder (OSD) is a general-purpose decoding algorithm that can decode all linear block codes. Gaussian elimination is an important step in OSD decoding. Due to the limitations of the OSD algorithm, traditional Gaussian elimination modules are not suitable for direct application in OSD decoding. The specific reasons include: (1) Traditional Gaussian elimination modules are designed for real number matrices, which include approximation operations, while the generated matrix of the code is a matrix in the binary field, which cannot be approximated; (2) Traditional Gaussian elimination modules involve column addition and subtraction operations, while in the OSD decoder, each column of the matrix corresponds to a specific symbol of the received signal, and the matrix columns can only be swapped with the corresponding symbols, and column addition and subtraction operations cannot be performed; (3) Traditional Gaussian elimination modules are designed for square matrices with equal number of rows and columns, while the generated matrix of the code is a "fat" matrix with more columns than rows. During the elimination process, there are linearly dependent columns, and it is necessary to select linearly independent columns for elimination.

[0004] Therefore, existing technologies still need to be improved and developed. Summary of the Invention

[0005] The main objective of this invention is to provide a parallel Gaussian elimination OSD decoding method, system, terminal, and storage medium, aiming to solve the problem that existing OSD decoding methods cannot perform parallel Gaussian elimination operations, resulting in slow decoding efficiency.

[0006] To achieve the above objectives, the present invention provides a parallel Gaussian elimination OSD decoding method, which includes the following steps: Obtain a communication decoding task, obtain the original matrix to be processed and the corresponding received symbol according to the communication decoding task, and perform Gaussian elimination on the original matrix according to the received symbol to obtain a first matrix and the corresponding first received symbol. The first received symbol is bit-flipped to obtain the target received symbol. The target received symbol is then recoded with the first matrix to obtain multiple recoding results. All the recoding results are then filtered to obtain the decoding result.

[0007] Optionally, the parallel Gaussian elimination OSD decoding method, wherein obtaining the communication decoding task, obtaining the original matrix to be processed and the corresponding received symbol according to the communication decoding task, and performing Gaussian elimination on the original matrix according to the received symbol to obtain a first matrix and the corresponding first received symbol, specifically includes: Obtain a communication decoding task, obtain the original matrix to be processed and the corresponding received symbol according to the communication decoding task, and combine the matrix columns of the original matrix with the received symbol to obtain multiple input data; Obtain the first full flag cache information of the first arithmetic unit, and determine the processing method based on the first full flag cache information and all the input data to obtain the processing method determination result; Based on the processing method, Gaussian elimination is performed on all the input data to obtain multiple output data, and a first matrix and the corresponding first received symbol are obtained based on all the output data.

[0008] Optionally, in the parallel Gaussian elimination OSD decoding method, the processing mode determination result includes a first processing mode, a second processing mode, and a third processing mode; The step of determining the processing method based on the first full flag cache information and all the input data to obtain the processing method determination result specifically includes: If the first full flag buffer information is a first value, and the bits of the input data are linearly independent, then the corresponding processing method judgment result is the first processing method; If the first full flag cache information is the second value, then the corresponding processing method judgment result is the second processing method; If the first full flag buffer information is the first value, and the bits of the input data are linearly correlated, then the corresponding processing method judgment result is the third processing method.

[0009] Optionally, in the parallel Gaussian elimination OSD decoding method, the output data includes first output data, second output data, and third output data; The step of performing Gaussian elimination on all the input data based on the judgment result of the processing method to obtain multiple output data specifically includes: If the processing method determination result is the first processing method, then the first full flag cache information is set to the second value, and the matrix columns of the input data are checked for serial numbers to obtain the principal element serial number; The bits corresponding to the principal element index are swapped with the preset bits of the matrix column to obtain the swap result. An output column is generated based on the swap result, and the first output data is obtained based on the output column. If the processing method determination result is the second processing method, then the matrix columns of the input data are subjected to row swapping and row addition / subtraction to obtain the second output data; If the processing method determination result is the third processing method, then the input data will be used as the third output data.

[0010] Optionally, in the parallel Gaussian elimination OSD decoding method, the row swapping and row addition / subtraction of the input data matrix columns specifically involves: ; in, The first column of the matrix after row swapping Bit, For XOR operation, The first column of the matrix after row swapping Bit, For operation, For the first in the column cache Bit, This is the sequence number of the first arithmetic unit. represents the index of the bit in the matrix column.

[0011] Optionally, the parallel Gaussian elimination OSD decoding method, wherein bit flipping is performed on the first received symbol to obtain the target received symbol, the target received symbol is recoded with the first matrix to obtain multiple recoding results, and all the recoding results are filtered to obtain the decoding result, specifically includes: The first received symbol is bit-flipped to obtain the target received symbol, and the target received symbol is combined with the matrix columns of the first matrix to obtain multiple target input data. The second full flag cache information of the second arithmetic unit is obtained, and the processing method is determined based on the second full flag cache information and all the target input data to obtain the target processing method determination result, wherein the target processing method determination result includes the fourth processing method and the fifth processing method; Based on the result of the target processing method, all the target input data are re-encoded to obtain multiple re-encoding results. All the re-encoding results are then filtered to obtain the decoding result.

[0012] Optionally, in the parallel Gaussian elimination OSD decoding method, the recoding result includes a first result and a second result; The step of recoding all the target input data according to the judgment result of the target processing method to obtain multiple recoding results specifically includes: If the target processing method is the fourth processing method, then the second full flag cache information is set to the second value, and the first result is obtained according to the target matrix column of the target input data; If the target processing method is the fifth processing method, then the target matrix columns of the target input data are subjected to row addition and subtraction processing to obtain the second result.

[0013] Optionally, the parallel Gaussian elimination OSD decoding method, wherein the parallel Gaussian elimination OSD decoding system comprises: The matrix processing module is used to acquire a communication decoding task, acquire the original matrix to be processed and the corresponding received symbol according to the communication decoding task, and perform Gaussian elimination on the original matrix according to the received symbol to obtain a first matrix and the corresponding first received symbol. The decoding processing module is used to perform bit flipping on the first received symbol to obtain the target received symbol, re-encode the target received symbol with the first matrix to obtain multiple re-encoding results, and filter all the re-encoding results to obtain the decoding result.

[0014] Furthermore, to achieve the above objectives, the present invention also provides a terminal, wherein the terminal includes: a memory, a processor, and a parallel Gaussian elimination OSD decoding program stored in the memory and executable on the processor, wherein when the parallel Gaussian elimination OSD decoding program is executed by the processor, it implements the steps of the parallel Gaussian elimination OSD decoding method as described above.

[0015] Furthermore, to achieve the above objectives, the present invention also provides a computer-readable storage medium, wherein the computer-readable storage medium stores a parallel Gaussian elimination OSD decoding program, which, when executed by a processor, implements the steps of the parallel Gaussian elimination OSD decoding method as described above.

[0016] In this invention, a communication decoding task is acquired. Based on this task, a raw matrix to be processed and its corresponding received symbol are obtained. Gaussian elimination is performed on the raw matrix based on the received symbol to obtain a first matrix and its corresponding first received symbol. Bit flipping is performed on the first received symbol to obtain a target received symbol. The target received symbol and the first matrix are then recoded to obtain multiple recoding results. All recoding results are then filtered to obtain the decoding result. Each processing unit in this invention employs binary field operations without approximation. The matrix columns and their corresponding received symbols are stored together. Each processing unit processes the matrix columns and their corresponding received symbols sequentially, involving only addition and subtraction operations within the same column (i.e., row addition and subtraction), without involving addition and subtraction operations between different columns. When exchanging columns, the corresponding received symbols are also exchanged. The processing unit is divided into an operation unit and a storage unit. Linearly independent columns can remain in the operation unit, while linearly dependent columns are not processed by the operation unit and are finally stored. This achieves parallel Gaussian elimination operations, improving decoding efficiency. Attached Figure Description

[0017] Figure 1 This is a flowchart of a preferred embodiment of the parallel Gaussian elimination OSD decoding method of the present invention; Figure 2 This is a schematic diagram of the overall structure of the Gaussian elimination module in a preferred embodiment of the present invention; Figure 3 This is a schematic diagram of the data organization method in a preferred embodiment of the present invention; Figure 4 This is a schematic diagram of the U-operation unit structure with serial number X in a preferred embodiment of the present invention; Figure 5 This is a schematic diagram of the storage cell structure with serial number X in a preferred embodiment of the present invention; Figure 6 This is a schematic diagram of the D operation unit structure with serial number X in a preferred embodiment of the present invention; Figure 7 This is a structural diagram of a preferred embodiment of the OSD decoding system with parallel Gaussian elimination of the present invention; Figure 8 This is a structural diagram of a preferred embodiment of the terminal of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this invention clearer and more explicit, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0019] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0020] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0021] The OSD decoding method with parallel Gaussian elimination described in the preferred embodiment of the present invention, such as... Figure 1 As shown, the parallel Gaussian elimination OSD decoding method includes the following steps: Step S10: Obtain the communication decoding task. Obtain the original matrix to be processed and the corresponding received symbol according to the communication decoding task. Perform Gaussian elimination on the original matrix according to the received symbol to obtain the first matrix and the corresponding first received symbol.

[0022] Specifically, in this embodiment of the invention, to address the problem that existing OSD decoding methods cannot perform parallel Gaussian elimination, resulting in slow decoding efficiency, this invention proposes a parallel Gaussian elimination OSD decoding method. The decoding process is performed using a designed Gaussian elimination module, which consists of multiple cascaded similar processing units. Each processing unit employs binary field operations without approximation. Matrix columns and their corresponding received symbols are stored together. Each processing unit processes the matrix columns and their corresponding received symbols sequentially, involving only addition and subtraction operations within the same column (i.e., row addition and subtraction), without involving addition and subtraction operations between different columns. When exchanging columns, the corresponding received symbols are also exchanged. Furthermore, the processing unit is divided into an operation unit and a storage unit. Linearly independent columns can remain in the operation unit, while linearly dependent columns are not processed by the operation unit and finally enter the storage unit. This allows for the selection of linearly independent columns during the elimination process, achieving parallel Gaussian elimination and improving decoding efficiency.

[0023] The overall structure of the designed Gaussian elimination module is as follows: Figure 2As shown, the Gaussian elimination module consists of a first array (i.e., the U array), a second array (i.e., the D array), and two shift registers (shift register A and shift register B, respectively). The U array is used to preprocess the generated matrix (i.e., the first matrix). The matrix is ​​transformed into upper triangular form, and the D array is used to transform the upper triangular form of the matrix into upper triangular form. The array is converted into a unit array, with shift registers A and B used for temporary data storage. The U-array is composed of... It consists of several units, of which the first One is a U-operation unit, the remaining ones are... Each of the D arrays is a storage unit, with a unique serial number. Units are connected in ascending order of their serial numbers, and each unit is connected to a register with the same serial number in shift register A. The D array consists of... It consists of several units, of which the first One is a D operation unit, the remaining ones are D operation units. Each array consists of four units: the first three are U-operation units, and the remaining one is a storage unit. Each unit is connected in ascending order of its number, and each unit is connected to a register with the same number in shift register B. Similarly, the D array consists of four units: the first three are D-operation units, and the remaining one is a storage unit. Each unit has a unique number, and the units are connected in ascending order of their numbers, and each unit is connected to a register with the same number in shift register B. Data input is connected to the U-operation unit with number 1, the output of shift register A is connected to the D-operation unit with number 1, and the output of shift register B is connected to the data output. In the Gaussian elimination module, data input, data output, and the data processed, stored, and transferred between the operation units, storage units, and shift registers are all handled using... Figure 3 The structure is organized to include an integer receiving symbol and A matrix of bits.

[0024] Obtain the communication decoding task, and based on the communication decoding task, obtain the original matrix to be processed and the corresponding received symbols. For example, if the channel coding length of the original matrix is ​​4 and the information bit length is 3, then the corresponding original matrix is: ; The corresponding receiving symbol is The columns of the original matrix are combined with the received symbols to obtain multiple sets of input data, including four sets of input data, which are respectively... , , , Before inputting all the input data into the Gaussian elimination module, the Gaussian elimination module needs to be initialized, specifically the U array, D array, shift register A, and shift register B. Then, all the input data is input into the initialized Gaussian elimination module. After receiving all the input data, the initialized Gaussian elimination module assigns a sequence number... The U array starts working, and the working process generates data for the input shift register A.

[0025] The structure of the U-operation unit (i.e., the first operation unit) in the U-array is as follows: Figure 4 As shown, the corresponding processing procedure is as follows: First, the first full flag cache, main index cache, and column index cache of the U operation unit are initialized, that is, the first full flag cache, main index cache, and column index cache of the U operation unit are set to 0; then, the processing mode is determined according to the first full flag cache information and all the input data to obtain the processing mode determination result. The purpose of obtaining the processing mode determination result is to control the on / off state of switches 1, 2, and 3, where each switch represents a processing mode, corresponding to the first processing mode, the second processing mode, and the third processing mode; the specific determination process is as follows: if the first full flag cache information is a first value (e.g., 0), and the bits of the input data are linearly independent (i.e., the first full flag cache is a first value), the processing mode is determined by setting the first full flag cache to ... X Bit to the K If not all bits are 0), select switch 1, which means the corresponding processing method judgment result is the first processing method; if the first full flag buffer information is the second value (for example, 1), regardless of the first bit of the input data... X Bit to the K Whether all bits are 0, switch 2 is selected, meaning the corresponding processing method is the second processing method; if the first full flag buffer information is the first value, and the bits of the input data are linearly correlated (i.e., the first bit of the input data is zero), then switch 2 is selected, meaning the processing method is the second processing method. X Bit to the K (If all bits are 0), select switch 3, which means the result of the corresponding processing method judgment is the third processing method.

[0026] Then, based on the processing method judgment result, Gaussian elimination is performed on all the input data to obtain multiple output data. If the processing method judgment result is the first processing method, i.e., when switch 1 is turned on, the first full flag buffer information is set to the second value (e.g., 1), and the matrix columns of the input data are checked for their indexes to obtain the pivot index. The pivot index is then stored in the pivot index buffer, wherein the pivot index is the index of the matrix column. X Bit to the KThe index of the first non-zero bit in the matrix; the bit corresponding to the pivot index is compared with the preset bit of the matrix column (i.e., the first... X The bits are swapped to obtain the swap result, which is then stored in the column cache. An output column is generated based on the swap result, wherein the sequence number in the output column is set to the nearest integer. The bit matches the input data, and the sequence number is the [number]. Bit set to 1, sequence number greater than the first The bit is set to 0, and the first output data is obtained according to the output column; if the processing method judgment result is the second processing method, that is, when switch 2 is turned on, the matrix columns of the input data are subjected to row swapping and row addition / subtraction to obtain the second output data, that is, the pivot index in the pivot index cache is read, and the first bit of the matrix column is set to 0. The bit and the first Swap the nth bit, then swap the nth bit in the matrix column. Bit to the The expression for row addition and subtraction of bits is: ; in, The first column of the matrix after row swapping Bit, For XOR operation, The first column of the matrix after row swapping Bit, For operation, For the first in the column cache Bit, This is the sequence number of the first arithmetic unit. The input data is the index of the bit in the matrix column. If the processing method determination result is the third processing method, i.e., when switch 3 is turned on, no operation is performed, and the input data is used as the third output data. The first matrix and the corresponding first received symbol are obtained based on all the output data.

[0027] Next, a specific example will be used for illustration: For the first set of 4 sets of input data When input to the U operation unit with sequence number 1, since the full flag of the U operation unit with sequence number 1 is 0, switch 1 is turned on, and the first full flag buffer information is set to 1; since the first bit is non-zero, the pivot sequence number can be determined to be 1, and 1 is stored in the pivot sequence number buffer; the first bit is swapped with the first bit, and the result is still 110, so 110 is stored in the column buffer; the output column is generated, with the first bit being 1 and bits with sequence numbers greater than 1 being 0, resulting in 100. The output data is... It is output to shift register A via port 1.

[0028] For the second set of data When the input is given to the U arithmetic unit with sequence number 1, since the first full flag buffer information of the U arithmetic unit with sequence number 1 has already been set to 1, switch 2 is turned on, and a row swap operation is performed, swapping the first bit with the first bit. After the swap, the result is still 011. Row addition and subtraction operations are then performed, resulting in 011. The output data is... The data is output through port 2 to the U arithmetic unit with sequence number 2. When it is input to the U arithmetic unit with sequence number 2, since the first full flag buffer information of the U arithmetic unit with sequence number 2 is 0, switch 1 is turned on, and the first full flag buffer information of the U arithmetic unit with sequence number 2 is set to 1; since the second bit is non-zero, the pivot sequence number can be determined to be 2, and 2 is stored in the pivot sequence number buffer; the second bit is swapped with the second bit, and after the swap, it is still 011, so 011 is stored in the column buffer; the output column is generated, the first bit is the same as the input, which is 0, the second bit is 1, and the bits with sequence numbers greater than 2 are 0, resulting in 010. The output data is... It is output to shift register A via port 1.

[0029] For the third set of data When the input is given to the U arithmetic unit with sequence number 1, since the first full flag buffer information of the U arithmetic unit with sequence number 1 has been set to 1, switch 2 is turned on, and a row swap operation is performed, swapping the first bit with the first bit. After the swap, the result is still 101. Row addition and subtraction operations are then performed, resulting in 111. The output data is... The data is output through port 2 to the U arithmetic unit with serial number 2. When it is input to the U arithmetic unit with serial number 2, since the first full flag buffer information of the U arithmetic unit with serial number 2 has been set to 1, switch 2 is turned on, and a row swap operation is performed, swapping the second bit with the second bit. After the swap, the result is still 111. Row addition and subtraction operations are then performed, resulting in 110. The output data is... The data is output through port 2 to the U arithmetic unit with serial number 3. When it is input to the U arithmetic unit with serial number 3, since the first full flag buffer information of the U arithmetic unit with serial number 3 is 0 and the third bit of the input column is 0, switch 3 is turned on, so no operation is performed, and the output data is... The data is output through port 2 to memory cell number 4. When it is input to memory cell number 4, since the full flag buffer information corresponding to memory cell number 4 is 0, switch 1 is turned on, thus setting the corresponding full flag buffer information to 1, and the output data is... It is output to shift register A via port 1.

[0030] For the fourth set of data When the input is given to the U arithmetic unit with sequence number 1, since the first full flag buffer information of the U arithmetic unit with sequence number 1 has been set to 1, switch 2 is turned on, and a row swap operation is performed, swapping the first bit with the first bit. After the swap, the result is still 100. Row addition and subtraction operations are then performed, resulting in 110. The output data is... The data is output through port 2 to the U arithmetic unit with serial number 2. When it is input to the U arithmetic unit with serial number 2, since the first full flag buffer information of the U arithmetic unit with serial number 2 has been set to 1, switch 2 is turned on, and a row swap operation is performed, swapping the second bit with the second bit. After the swap, the result is still 110. Row addition and subtraction operations are then performed, resulting in 111. The output data is... The input is output through port 2 to the U arithmetic unit with serial number 3. When it is input to the U arithmetic unit with serial number 3, since the first full flag buffer information of the U arithmetic unit with serial number 3 is 0, switch 1 is turned on, and the first full flag buffer information of the U arithmetic unit with serial number 3 is set to 1; since the third bit is non-zero, the pivot serial number can be determined to be 3, and 3 is stored in the pivot serial number buffer; the third bit is swapped with the third bit, and after the swap, it is still 111, so 111 is stored in the column buffer; the output column is generated, the first and second bits are the same as the input, which is 11, and the third bit is 1, resulting in 111, and the output data is... The data is output to shift register A via port 1. At this point, each cell of the U array has produced an output to shift register A, and the data stored in shift register A at this time is... , , , That is, the corresponding upper triangular matrix (i.e., the first matrix) is: .

[0031] Furthermore, the structure of the storage cells in a U-array is as follows: Figure 5 As shown, the corresponding workflow is as follows: During initialization, the full flag cache information of the U array's storage cells is initialized to 0. After data input, the full flag cache information of the storage cells is first checked, and the on / off state of switches 4 and 5 is controlled based on the result. If the full flag cache information of the storage cells is 0, switch 4 is turned on; otherwise, switch 5 is turned on. When switch 4 is turned on, the full flag cache information of the storage cells is set to 1, and then the input is directly sent as the final result to output port 1 (connected to the register in shift register A or shift register B). When switch 5 is turned on, no operation is performed, and the input is sent as the final result to output port 2 (connected to the register with sequence number...). (storage unit).

[0032] Step S20: Perform bit flipping on the first received symbol to obtain the target received symbol, recode the target received symbol with the first matrix to obtain multiple recoding results, and filter all the recoding results to obtain the decoding result.

[0033] Specifically, after all units of the U array have generated data for input shift register A, shift register A begins to sequentially output its stored content to the D array. That is, after shift register A obtains the first matrix and its corresponding first received symbol, it performs bit flipping on the first received symbol to obtain the target received symbol. The target received symbol is then combined with the matrix columns of the first matrix to obtain multiple target input data, and all of these target input data are input to the D array. After the D array receives the target input data, the D operation unit (i.e., the second operation unit) of the D array begins to operate. The structure of the D operation unit is as follows: Figure 6 As shown, the specific processing procedure is as follows: First, the second full flag cache information and column number cache of the D operation unit are initialized, that is, the second full flag cache information and column number cache are set to 0; when the target input data is input, the target processing method judgment result is obtained according to the second full flag cache information. The target processing method judgment result includes the fourth processing method and the fifth processing method, and the corresponding switches are switch 6 and switch 7. The on and off of switch 6 and switch 7 are controlled according to the target processing method judgment result. If the second full flag cache information of the D operation unit is 0, switch 6 is turned on; otherwise, switch 7 is turned on.

[0034] Subsequently, based on the target processing method judgment result, all the target input data are re-encoded to obtain multiple re-encoded results; if the target processing method is the fourth processing method, i.e., when switch 6 is turned on, the second full flag buffer information is set to the second value (e.g., 1), and the first result is obtained according to the target matrix column of the target input data, i.e., the matrix column is directly stored in the column buffer to generate the target output column, and the first result of the target output column is obtained. Bit 1 is set and the remaining bits are set to 0. The first result is then sent to output port 1 (i.e., connected to the register in shift register B). If the target processing method is the fifth processing method, i.e. when switch 7 is turned on, the target matrix columns of the target input data are subjected to row addition and subtraction to obtain the second result.

[0035] Next, a specific example will be used for illustration: for the first set of target input data When the input is fed into the D operation unit with sequence number 1, since the second full flag buffer information of the D operation unit with sequence number 1 is 0, switch 6 is turned on, the second full flag buffer information is set to 1, and 100 is stored in the column buffer. The target output column is generated, with the first bit being 1 and the remaining bits being 0, resulting in 100. The output result is... It is output to shift register B via port 1.

[0036] For the second set of data When the input is fed into the D arithmetic unit with serial number 1, since the second full flag buffer information of the D arithmetic unit with serial number 1 has been set to 1, switch 7 is turned on, and row addition and subtraction operations are performed. After the operation, 010 is obtained, and the output result is... The input is output through port 2 to the D operation unit with serial number 2. When it is input to the D operation unit with serial number 2, since the second full flag buffer information of the D operation unit with serial number 2 is 0, switch 6 is turned on, so the second full flag buffer information of the D operation unit with serial number 2 is set to 1, 010 is stored in the column buffer, the target output column is generated, the second bit is 1, and the remaining bits are 0, resulting in 010. The output result is... It is output to shift register B via port 1.

[0037] For the third set of data When the input is fed into the D arithmetic unit with serial number 1, since the second full flag buffer information of the D arithmetic unit with serial number 1 has been set to 1, switch 7 is turned on, and row addition and subtraction operations are performed, resulting in 111. The output result is: The input is output through port 2 to the D arithmetic unit with serial number 2. When it is input to the D arithmetic unit with serial number 2, since the second full flag buffer information of the D arithmetic unit with serial number 2 has been set to 1, switch 7 is turned on, and row addition and subtraction operations are performed. After the operation, the result is 111, and the output result is... The input is output through port 2 to the D operation unit with serial number 3. When it is input to the D operation unit with serial number 3, since the second full flag buffer information of the D operation unit with serial number 3 is 0, switch 6 is turned on, so the full flag is set to 1, and 111 is stored in the column buffer; the target output column is generated, with the third bit set to 1 and the remaining bits set to 0, resulting in 001. The output result is... It is output to shift register B via port 1.

[0038] For the fourth set of data When the input is fed into the D arithmetic unit with serial number 1, since the second full flag buffer information of the D arithmetic unit with serial number 1 has been set to 1, switch 7 is turned on, and row addition and subtraction operations are performed, resulting in 111. The output result is: The input is output through port 2 to the D arithmetic unit with serial number 2. When it is input to the D arithmetic unit with serial number 2, since the second full flag buffer information of the D arithmetic unit with serial number 2 has been set to 1, switch 7 is turned on, and row addition and subtraction operations are performed. After the operation, 110 is obtained, and the output result is... The output is via port 2 to the D arithmetic unit with serial number 3. When it is input to the D arithmetic unit with serial number 3, since the second full flag buffer information of the D arithmetic unit with serial number 3 has been set to 1, switch 7 is turned on, and row addition and subtraction operations are performed. After the operation, 110 is obtained, and the output result is... The signal is output through port 2 to memory cell number 4. When it is input to memory cell number 4, since the full flag buffer information of memory cell number 4 is 0, switch 6 is turned on, thus setting the full flag buffer information of memory cell number 4 to 1, and the output result is... It is output to shift register B via port 1.

[0039] At this point, each cell of array D has produced an output (i.e., the decoding result) to shift register B. The data stored in the shift register at this time are... , , , That is, the corresponding matrix is: ; At this point, shift register B outputs the corresponding decoding results sequentially. The left side of the matrix output by shift register B is the identity matrix, meaning that Gaussian elimination of the "fat" matrix has been completed. During Gaussian elimination, no column addition or subtraction operations are involved; only column swapping occurs. Columns 3 and 4 are swapped, and their corresponding received symbols -3 and -4 are also swapped.

[0040] Each processing unit in this invention employs binary field operations, without approximation processing, and stores the matrix columns together with their corresponding received symbols. Each processing unit processes the matrix columns and their corresponding received symbols sequentially, involving only addition and subtraction operations within the same column (i.e., row addition and subtraction), without involving addition and subtraction operations between different columns. When exchanging columns, the corresponding received symbols are also exchanged. Furthermore, the processing unit is divided into an arithmetic unit and a storage unit. Linearly independent columns can remain in the arithmetic unit, while linearly dependent columns are not processed by the arithmetic unit and finally enter the storage unit, thereby realizing parallel Gaussian elimination operations and improving decoding efficiency.

[0041] Furthermore, such as Figure 7 As shown, based on the above-described parallel Gaussian elimination OSD decoding method, this invention also provides a parallel Gaussian elimination OSD decoding system, wherein the parallel Gaussian elimination OSD decoding system includes: Matrix processing module 51 is used to acquire a communication decoding task, acquire the original matrix to be processed and the corresponding received symbol according to the communication decoding task, and perform Gaussian elimination on the original matrix according to the received symbol to obtain a first matrix and the corresponding first received symbol. The decoding processing module 52 is used to perform bit flipping on the first received symbol to obtain the target received symbol, re-encode the target received symbol with the first matrix to obtain multiple re-encoding results, and filter all the re-encoding results to obtain the decoding result.

[0042] Furthermore, such as Figure 8 As shown, based on the above-mentioned parallel Gaussian elimination OSD decoding method, the present invention also provides a terminal, which includes a processor 10, a memory 20 and a display 30. Figure 8 Only some of the terminal components are shown; however, it should be understood that it is not required to implement all of the components shown, and more or fewer components may be implemented instead.

[0043] In some embodiments, the memory 20 may be an internal storage unit of the terminal, such as a hard disk or memory. In other embodiments, the memory 20 may be an external storage device of the terminal, such as a plug-in hard disk, smart media card (SMC), secure digital card (SD), flash card, etc., equipped on the terminal. Further, the memory 20 may include both internal and external storage units of the terminal. The memory 20 is used to store application software and various types of data installed on the terminal, such as the program code installed on the terminal. The memory 20 can also be used to temporarily store data that has been output or will be output. In one embodiment, the memory 20 stores a parallel Gaussian elimination OSD decoding program 40, which can be executed by the processor 10 to implement the parallel Gaussian elimination OSD decoding method of this application.

[0044] In some embodiments, the processor 10 may be a central processing unit (CPU), a microprocessor, or other data processing chip, used to run program code stored in the memory 20 or process data, such as executing the OSD decoding method of parallel Gaussian elimination.

[0045] In some embodiments, the display 30 may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, or an OLED (Organic Light-Emitting Diode) touchscreen, etc. The display 30 is used to display information on the terminal and to display a visual user interface.

[0046] In one embodiment, when the processor 10 executes the OSD decoding program 40 for parallel Gaussian elimination in the memory 20, the following steps are performed: Obtain a communication decoding task, obtain the original matrix to be processed and the corresponding received symbol according to the communication decoding task, and perform Gaussian elimination on the original matrix according to the received symbol to obtain a first matrix and the corresponding first received symbol. The first received symbol is bit-flipped to obtain the target received symbol. The target received symbol is then recoded with the first matrix to obtain multiple recoding results. All the recoding results are then filtered to obtain the decoding result.

[0047] The step of acquiring the communication decoding task involves obtaining the original matrix to be processed and the corresponding received symbol based on the communication decoding task, and performing Gaussian elimination on the original matrix based on the received symbol to obtain a first matrix and the corresponding first received symbol. Specifically, this includes: Obtain a communication decoding task, obtain the original matrix to be processed and the corresponding received symbol according to the communication decoding task, and combine the matrix columns of the original matrix with the received symbol to obtain multiple input data; Obtain the first full flag cache information of the first arithmetic unit, and determine the processing method based on the first full flag cache information and all the input data to obtain the processing method determination result; Based on the processing method, Gaussian elimination is performed on all the input data to obtain multiple output data, and a first matrix and the corresponding first received symbol are obtained based on all the output data.

[0048] The processing method judgment result includes a first processing method, a second processing method, and a third processing method; The step of determining the processing method based on the first full flag cache information and all the input data to obtain the processing method determination result specifically includes: If the first full flag buffer information is a first value, and the bits of the input data are linearly independent, then the corresponding processing method judgment result is the first processing method; If the first full flag cache information is the second value, then the corresponding processing method judgment result is the second processing method; If the first full flag buffer information is the first value, and the bits of the input data are linearly correlated, then the corresponding processing method judgment result is the third processing method.

[0049] The output data includes first output data, second output data, and third output data; The step of performing Gaussian elimination on all the input data based on the judgment result of the processing method to obtain multiple output data specifically includes: If the processing method determination result is the first processing method, then the first full flag cache information is set to the second value, and the matrix columns of the input data are checked for serial numbers to obtain the principal element serial number; The bits corresponding to the principal element index are swapped with the preset bits of the matrix column to obtain the swap result. An output column is generated based on the swap result, and the first output data is obtained based on the output column. If the processing method determination result is the second processing method, then the matrix columns of the input data are subjected to row swapping and row addition / subtraction to obtain the second output data; If the processing method determination result is the third processing method, then the input data will be used as the third output data.

[0050] Specifically, the process of performing row swapping and row addition / subtraction on the matrix columns of the input data involves: ; in, The first column of the matrix after row swapping Bit, For XOR operation, The first column of the matrix after row swapping Bit, For operation, For the first in the column cache Bit, This is the sequence number of the first arithmetic unit. represents the index of the bit in the matrix column.

[0051] Specifically, the process of bit-flipping the first received symbol to obtain the target received symbol, recoding the target received symbol with the first matrix to obtain multiple recoding results, and filtering all the recoding results to obtain the decoding result includes: The first received symbol is bit-flipped to obtain the target received symbol, and the target received symbol is combined with the matrix columns of the first matrix to obtain multiple target input data. The second full flag cache information of the second arithmetic unit is obtained, and the processing method is determined based on the second full flag cache information and all the target input data to obtain the target processing method determination result, wherein the target processing method determination result includes the fourth processing method and the fifth processing method; Based on the result of the target processing method, all the target input data are re-encoded to obtain multiple re-encoding results. All the re-encoding results are then filtered to obtain the decoding result.

[0052] The recoding result includes a first result and a second result; The step of recoding all the target input data according to the judgment result of the target processing method to obtain multiple recoding results specifically includes: If the target processing method is the fourth processing method, then the second full flag cache information is set to the second value, and the first result is obtained according to the target matrix column of the target input data; If the target processing method is the fifth processing method, then the target matrix columns of the target input data are subjected to row addition and subtraction processing to obtain the second result.

[0053] The present invention also provides a computer-readable storage medium, wherein the computer-readable storage medium stores a parallel Gaussian elimination OSD decoding program, which, when executed by a processor, implements the steps of the parallel Gaussian elimination OSD decoding method as described above.

[0054] In summary, this invention provides a parallel Gaussian elimination OSD decoding method, system, terminal, and storage medium. The method includes: acquiring a communication decoding task; acquiring a raw matrix to be processed and a corresponding received symbol according to the communication decoding task; performing Gaussian elimination on the raw matrix according to the received symbol to obtain a first matrix and a corresponding first received symbol; performing bit flipping on the first received symbol to obtain a target received symbol; performing recoding processing on the target received symbol and the first matrix to obtain multiple recoding results; and filtering all the recoding results to obtain a decoding result. Each processing unit in this invention employs binary field operations, without approximation processing, and stores the matrix columns together with their corresponding received symbols. Each processing unit processes the matrix columns and their corresponding received symbols sequentially, involving only addition and subtraction operations within the same column (i.e., row addition and subtraction), without involving addition and subtraction operations between different columns. When exchanging columns, the corresponding received symbols are also exchanged. Furthermore, the processing unit is divided into an arithmetic unit and a storage unit. Linearly independent columns can remain in the arithmetic unit, while linearly dependent columns are not processed by the arithmetic unit and finally enter the storage unit, thereby realizing parallel Gaussian elimination operations and improving decoding efficiency.

[0055] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0056] Of course, those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware (such as a processor, controller, etc.). The program can be stored in a computer-readable storage medium, and when executed, it can include the processes described in the above method embodiments. The computer-readable storage medium can be a memory, magnetic disk, optical disk, etc.

[0057] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A parallel Gaussian elimination OSD decoding method, characterized in that, The parallel Gaussian elimination OSD decoding method includes: Obtain a communication decoding task, obtain the original matrix to be processed and the corresponding received symbol according to the communication decoding task, and perform Gaussian elimination on the original matrix according to the received symbol to obtain a first matrix and the corresponding first received symbol. The first received symbol is bit-flipped to obtain the target received symbol. The target received symbol is then recoded with the first matrix to obtain multiple recoding results. All the recoding results are then filtered to obtain the decoding result.

2. The OSD decoding method using parallel Gaussian elimination according to claim 1, characterized in that, The acquisition of the communication decoding task involves obtaining the original matrix to be processed and the corresponding received symbol based on the communication decoding task, and performing Gaussian elimination on the original matrix based on the received symbol to obtain a first matrix and the corresponding first received symbol. Specifically, this includes: Obtain a communication decoding task, obtain the original matrix to be processed and the corresponding received symbol according to the communication decoding task, and combine the matrix columns of the original matrix with the received symbol to obtain multiple input data; Obtain the first full flag cache information of the first arithmetic unit, and determine the processing method based on the first full flag cache information and all the input data to obtain the processing method determination result; Based on the processing method, Gaussian elimination is performed on all the input data to obtain multiple output data, and a first matrix and the corresponding first received symbol are obtained based on all the output data.

3. The OSD decoding method using parallel Gaussian elimination according to claim 2, characterized in that, The processing method judgment result includes a first processing method, a second processing method, and a third processing method; The step of determining the processing method based on the first full flag cache information and all the input data to obtain the processing method determination result specifically includes: If the first full flag buffer information is a first value, and the bits of the input data are linearly independent, then the corresponding processing method judgment result is the first processing method; If the first full flag cache information is the second value, then the corresponding processing method judgment result is the second processing method; If the first full flag buffer information is the first value, and the bits of the input data are linearly correlated, then the corresponding processing method judgment result is the third processing method.

4. The OSD decoding method using parallel Gaussian elimination according to claim 3, characterized in that, The output data includes first output data, second output data, and third output data; The step of performing Gaussian elimination on all the input data based on the judgment result of the processing method to obtain multiple output data specifically includes: If the processing method determination result is the first processing method, then the first full flag cache information is set to the second value, and the matrix columns of the input data are checked for serial numbers to obtain the principal element serial number; The bits corresponding to the principal element index are swapped with the preset bits of the matrix column to obtain the swap result. An output column is generated based on the swap result, and the first output data is obtained based on the output column. If the processing method determination result is the second processing method, then the matrix columns of the input data are subjected to row swapping and row addition / subtraction to obtain the second output data; If the processing method determination result is the third processing method, then the input data will be used as the third output data.

5. The OSD decoding method using parallel Gaussian elimination according to claim 4, characterized in that, The specific steps of performing row swapping and row addition / subtraction on the matrix columns of the input data are as follows: ； in, The first column of the matrix after row swapping Bit, For XOR operation, The first column of the matrix after row swapping Bit, For operation, For the first in the column cache Bit, This is the sequence number of the first arithmetic unit. represents the index of the bit in the matrix column.

6. The OSD decoding method using parallel Gaussian elimination according to claim 1, characterized in that, The process of bit-flipping the first received symbol to obtain the target received symbol, recoding the target received symbol with the first matrix to obtain multiple recoding results, and filtering all the recoding results to obtain the decoding result specifically includes: The first received symbol is bit-flipped to obtain the target received symbol, and the target received symbol is combined with the matrix columns of the first matrix to obtain multiple target input data. The second full flag cache information of the second arithmetic unit is obtained, and the processing method is determined based on the second full flag cache information and all the target input data to obtain the target processing method determination result, wherein the target processing method determination result includes the fourth processing method and the fifth processing method; Based on the result of the target processing method, all the target input data are re-encoded to obtain multiple re-encoding results. All the re-encoding results are then filtered to obtain the decoding result.

7. The OSD decoding method using parallel Gaussian elimination according to claim 6, characterized in that, The recoding result includes a first result and a second result; The step of recoding all the target input data according to the judgment result of the target processing method to obtain multiple recoding results specifically includes: If the target processing method is the fourth processing method, then the second full flag cache information is set to the second value, and the first result is obtained according to the target matrix column of the target input data; If the target processing method is the fifth processing method, then the target matrix columns of the target input data are subjected to row addition and subtraction processing to obtain the second result.

8. An OSD decoding system with parallel Gaussian elimination, characterized in that, The parallel Gaussian elimination OSD decoding system includes: The matrix processing module is used to acquire a communication decoding task, acquire the original matrix to be processed and the corresponding received symbol according to the communication decoding task, and perform Gaussian elimination on the original matrix according to the received symbol to obtain a first matrix and the corresponding first received symbol. The decoding processing module is used to perform bit flipping on the first received symbol to obtain the target received symbol, re-encode the target received symbol with the first matrix to obtain multiple re-encoding results, and filter all the re-encoding results to obtain the decoding result.

9. A terminal, characterized in that, The terminal includes a memory, a processor, and a program stored in the memory and executable on the processor. When executed by the processor, the program implements the steps of the OSD decoding method for parallel Gaussian elimination as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer-readable storage medium stores a parallel Gaussian elimination OSD decoding program, and the parallel Gaussian elimination OSD decoding program, when executed by a processor, implements the steps of the parallel Gaussian elimination OSD decoding method as described in any one of claims 1-7.

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