Semiconductor structure and method for manufacturing the same

Abstract

An embodiment of the present invention provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a semiconductor substrate, the semiconductor substrate including a logic device region and a memory region; a bit line and an electrical contact layer disposed in the same layer as the bit line, the bit line being located in the memory region, and the electrical contact layer being located in the logic device region; a first semiconductor channel located on a surface of the bit line, a second semiconductor channel disposed in the same layer as the first semiconductor channel and located on the surface of the electrical contact layer; a word line and a gate disposed in the same layer as the word line; a capacitor structure in contact with a second doped region of the first semiconductor channel; an electrical connection structure in contact with a fourth doped region of the second semiconductor channel; and a dielectric layer disposed between the bit line and the word line, and also on a side of the word line away from the semiconductor substrate. The embodiments of the present invention facilitate in-memory computing within the semiconductor structure, thereby improving the operating efficiency and reducing the operating energy consumption of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] In the von Neumann architecture, the logic control device and memory are separate units. The logic control device reads data from the memory, processes it, and then stores it back in the memory. Specifically, data is transferred back and forth between the logic control device and the memory, and the memory and logic control device are located on different chips. This back-and-forth data transfer between different chips leads to high power consumption and low performance.

[0003] Therefore, it is necessary to design a semiconductor device that can realize in-memory computing. Summary of the Invention

[0004] The technical problem solved by the embodiments of the present invention is to provide a semiconductor structure and a manufacturing method thereof, which are conducive to realizing in-memory computing in the semiconductor structure, so as to improve the working efficiency of the semiconductor structure and reduce the working energy consumption of the semiconductor structure.

[0005] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, comprising: a semiconductor substrate, the semiconductor substrate comprising a logic device area and a memory area; a bit line and an electrical contact layer arranged in the same layer as the bit line, the bit line being located on the semiconductor substrate in the memory area, and the electrical contact layer being located on the semiconductor substrate in the logic device area; a first semiconductor channel, the first semiconductor channel being located on the surface of the bit line, and in a direction along the semiconductor substrate pointing to the bit line, the first semiconductor channel comprising a first doped region, a first channel region, and a second doped region arranged in sequence, the first doped region being in contact with the bit line; a second semiconductor channel, the second semiconductor channel being arranged in the same layer as the first semiconductor channel and being located on the surface of the electrical contact layer, and in a direction along the semiconductor substrate pointing to the bit line In the direction in which the substrate points to the electrical contact layer, the second semiconductor channel includes a third doped region, a second channel region, and a fourth doped region arranged in sequence, the third doped region being in contact with the electrical contact layer; a word line and a gate arranged in the same layer as the word line, the word line being arranged around the first channel region, and the gate being arranged around the second channel region; a capacitor structure, the capacitor structure being located on a side of the second doped region away from the first channel region, and the capacitor structure being in contact with the second doped region; an electrical connection structure, the electrical connection structure being located on a side of the fourth doped region away from the second channel region, and the electrical connection structure being in contact with the fourth doped region; and a dielectric layer, the dielectric layer being located between the bit line and the word line, and also located on a side of the word line away from the semiconductor substrate.

[0006] Correspondingly, an embodiment of the present invention further provides a method for manufacturing a semiconductor structure, comprising: providing a semiconductor substrate, the semiconductor substrate comprising a logic device area and a memory area; forming a bit line and an electrical contact layer provided in the same layer as the bit line, the bit line being located on the semiconductor substrate in the memory area, and the electrical contact layer being located on the semiconductor substrate in the logic device area; forming a first semiconductor channel and a second semiconductor channel provided in the same layer as the first semiconductor channel, the first semiconductor channel being located on the surface of the bit line, and in a direction along the semiconductor substrate pointing to the bit line, the first semiconductor channel comprising a first doped region, a first channel region, and a second doped region arranged in sequence, the first doped region being in contact with the bit line, the second semiconductor channel being located on the surface of the electrical contact layer, and in a direction along the semiconductor substrate pointing to the bit line, the first semiconductor channel comprising a first doped region, a first channel region, and a second doped region arranged in sequence, the first doped region being in contact with the bit line, the second semiconductor channel being located on the surface of the electrical contact layer, and in a direction along the semiconductor substrate pointing to the bit line, the first semiconductor channel comprising a first doped region, a first channel region, and a second doped region In the direction in which the substrate points to the electrical contact layer, the second semiconductor channel includes a third doped region, a second channel region, and a fourth doped region arranged in sequence, and the third doped region is in contact with the electrical contact layer; a word line and a gate arranged in the same layer as the word line are formed, the word line is arranged around the first channel region, and the gate is arranged around the second channel region; a capacitor structure is formed, the capacitor structure is located on a side of the second doped region away from the first channel region, and the capacitor structure is in contact with the second doped region; an electrical connection structure is formed, the electrical connection structure is located on a side of the fourth doped region away from the second channel region, and the electrical connection structure is in contact with the fourth doped region; a dielectric layer is formed, the dielectric layer is located between the bit line and the word line, and is also located on a side of the word line away from the semiconductor substrate.

[0007] Compared with related technologies, the technical solution provided by the embodiment of the present invention has the following advantages:

[0008] In the technical solution provided by the embodiments of the present invention, a semiconductor substrate includes a logic device area and a memory area. The structure within the memory area is used to store data, and the structure within the logic device area is used to perform calculations on the data. This allows the same semiconductor structure to contain both a processor and a memory to implement in-memory computing. Specifically, computing functions are integrated into a special memory array (the logic device area) within the semiconductor structure, and storage functions are integrated into another memory array (the memory area). When computing is required, the memory area within the semiconductor structure sends input data to the logic device area, and after several clock cycles, the logic device area returns the calculated results to the memory area. Compared to the traditional von Neumann architecture, in which "the memory and processor chip are two independent units, all data is stored in the memory, the processor chip sends requests to the memory, the memory transmits data to the processor chip, and reads back the calculation results," the processor and memory are integrated into a large memory array. Data input and output, as well as the calculation process, are all performed in different areas of the memory array. This helps shorten the distance between the processor and the memory, thereby improving the efficiency of data transmission and reducing the power consumption required for data transmission, thereby improving the operating efficiency and reducing the operating energy consumption of the semiconductor structure.

[0009] Furthermore, the first semiconductor channel and the second semiconductor channel are disposed perpendicularly to the surface of the semiconductor substrate. This facilitates further increasing the length of the first semiconductor channel and / or the second semiconductor channel while reducing layout space for the first semiconductor channel and / or the second semiconductor channel in a direction parallel to the surface of the semiconductor substrate (typically a horizontal direction), without reducing the size of the first semiconductor channel and / or the second semiconductor channel, thereby increasing the horizontal integration density of the semiconductor structure. Furthermore, the resistivity of the bit line is less than that of the first doped region, which facilitates reducing the contact resistance between the first doped region and the bit line. The resistivity of the electrical contact layer is less than that of the third doped region, which facilitates reducing the contact resistance between the third doped region and the electrical contact layer. Both of these contribute to improving the electrical performance of the semiconductor structure.

[0010] In addition, the first semiconductor channel and the second semiconductor channel are both used to form the channel of a junctionless transistor. The junctionless transistor has no PN junction, a simple preparation process, and superior performance. It enhances the reliability of the device, especially the resistance to hot carrier injection effect and noise tolerance, and is conducive to further improving the electrical performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] One or more embodiments are exemplarily described by the figures in the corresponding drawings. Unless otherwise stated, the figures in the drawings are not limited to scale.

[0012] Figure 1A schematic cross-sectional structural diagram of a semiconductor structure provided in accordance with an embodiment of the present invention;

[0013] Figure 2 for Figure 1 An enlarged structural diagram of a first semiconductor channel and a word line in the semiconductor structure shown;

[0014] Figure 3 for Figure 1 A schematic diagram of an enlarged structure of a second semiconductor channel and a gate in the semiconductor structure shown;

[0015] Figures 4 to 17 A schematic cross-sectional structure diagram corresponding to each step in a method for manufacturing a semiconductor structure provided by another embodiment of the present invention. DETAILED DESCRIPTION

[0016] As can be seen from the background art, in the prior art, the integration density of semiconductor devices needs to be improved while the manufacturing cost needs to be reduced.

[0017] Analysis shows that traditional computers use the von Neumann architecture, in which computing and storage functions are separated. The CPU and memory communicate via a bus. The CPU reads data from the memory, performs calculations, and then writes the results back to the memory. All data is stored in the memory, then transferred to the CPU, where the CPU's calculation results are stored in the memory. This requires frequent reads and writes to the memory. This back-and-forth data movement consumes significant power and reduces device performance.

[0018] To address the above-mentioned issues, embodiments of the present invention provide a semiconductor structure and a method for manufacturing the same. In the semiconductor structure, a semiconductor substrate is designed to include a logic device region and a memory region. The structure within the memory region is used to store data, and the structure within the logic device region is used to perform data calculations. This allows the same semiconductor structure to contain both a processor and a memory to implement in-memory computing. This allows data input and output, as well as computational processes, to be performed in different regions of the semiconductor structure, thereby shortening the distance between the processor and the memory, improving data transmission efficiency, and reducing power consumption required for data transmission. This, in turn, improves the operating efficiency of the semiconductor structure and reduces its operating energy consumption.

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more apparent, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the embodiments of the present invention to help readers better understand the present application. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0020] An embodiment of the present invention provides a semiconductor structure, which will be described in detail below with reference to the accompanying drawings. Figure 1 A schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention is provided. Figure 2 for Figure 1 An enlarged structural diagram of a first semiconductor channel and a word line in the semiconductor structure shown; Figure 3 for Figure 1 Schematic diagram of the enlarged structure of the second semiconductor channel and gate in the semiconductor structure shown.

[0021] refer to Figures 1 to 3The semiconductor structure includes: a semiconductor substrate 100, the semiconductor substrate 100 includes a logic device area I and a memory area II; a bit line 101 and an electrical contact layer 111 arranged on the same layer as the bit line 101, the bit line 101 is located on the semiconductor substrate 100 in the memory area II, and the electrical contact layer 111 is located on the semiconductor substrate 100 in the logic device area I; a first semiconductor channel 102, the first semiconductor channel 102 is located on the surface of the bit line 101, in the direction along the semiconductor substrate 100 pointing to the bit line 101, the first semiconductor channel 102 includes a first doped region a, a first channel region b and a second doped region c arranged in sequence, the first doped region a is in contact with the bit line 101; a second semiconductor channel 112, the second semiconductor channel 112 is arranged on the same layer as the first semiconductor channel 102, and is located on the surface of the electrical contact layer 111, in the direction along the semiconductor substrate 100 pointing to the bit line 101 In the direction toward the electrical contact layer 111, the second semiconductor channel 112 includes a third doped region d, a second channel region e, and a fourth doped region f, arranged in sequence. The third doped region d is in contact with the electrical contact layer 111; a word line 103 and a gate 113 disposed on the same layer as the word line 103. The word line 103 is disposed around the first channel region b, and the gate 113 is disposed around the second channel region e; a capacitor structure 104 is located on a side of the second doped region c away from the first channel region b, and the capacitor structure 104 is in contact with the second doped region c; an electrical connection structure 105 is located on a side of the fourth doped region f away from the second channel region e, and the electrical connection structure 105 is in contact with the fourth doped region f; and a dielectric layer 106 is located between the bit line 101 and the word line 103, and is also located on a side of the word line 103 away from the semiconductor substrate 100. Because the semiconductor structure includes vertical gate-all-around (GAA) transistors, and bit lines 101 are located between the semiconductor substrate 100 and the gate-all-around transistors, a 3D stacked memory device can be formed, which helps to improve the integration density of the semiconductor structure. In addition, the semiconductor substrate 100 includes a logic device region I and a memory region II. The structures in the memory region II are used to store data, and the structures in the logic device region I are used to perform calculations on the data. This allows the same semiconductor structure to contain both a processor and memory to achieve in-memory computing.

[0022] The following will be combined Figures 1 to 3 The semiconductor structure is described in more detail.

[0023] In this embodiment, the material type of the semiconductor substrate 100 can be an elemental semiconductor material or a crystalline inorganic compound semiconductor material. The elemental semiconductor material can be silicon or germanium; the crystalline inorganic compound semiconductor material can be silicon carbide, silicon germanium, gallium arsenide, or indium gallium.

[0024] Specifically, the material type of the first semiconductor channel 102 and the material type of the second semiconductor channel 112 may be the same as the material type of the semiconductor substrate 100 , that is, both are elemental semiconductor materials or crystalline inorganic compound semiconductor materials.

[0025] Furthermore, the bit line 101 and the first semiconductor channel 102 have the same semiconductor element, and the resistivity of the bit line 101 is lower than the resistivity of the first doped region a. The electrical contact layer 111 and the second semiconductor channel 112 have the same semiconductor element, and the resistivity of the electrical contact layer 111 is lower than the resistivity of the third doped region d.

[0026] Since the first semiconductor channel 102 and the bit line 101 have the same semiconductor element, the first semiconductor channel 102 and the bit line 101 are formed using the same film layer structure. The film layer structure is composed of semiconductor elements, so that the bit line 101 and the first semiconductor channel 102 are an integrated structure, thereby improving the interface state defects between the bit line 101 and the first semiconductor channel 102; the electrical contact layer 111 and the second semiconductor channel 112 have the same semiconductor element, and the second semiconductor channel 112 and the electrical contact layer 111 are formed using the same film layer structure. The film layer structure is composed of semiconductor elements, so that the electrical contact layer 111 and the second semiconductor channel 112 are an integrated structure, thereby improving the interface state defects between the electrical contact layer 111 and the second semiconductor channel 112. Both are conducive to improving the performance of the semiconductor structure.

[0027] In this embodiment, the first semiconductor channel 102, the bit line 101, the electrical contact layer 111, and the second semiconductor channel 112 all have the same semiconductor element, that is, the four can be formed using the same film layer, that is, they can all be formed from the same initial semiconductor substrate. Therefore, the bit line 101, the first semiconductor channel 102, the electrical contact layer 111, the second semiconductor channel 112, and the semiconductor substrate 100 form an integrated structure, which is conducive to improving the interface performance between the semiconductor substrate 100 and the bit line 101 and the electrical contact layer 111, between the bit line 101 and the first semiconductor channel 102, and between the electrical contact layer 111 and the second semiconductor channel 112, thereby reducing interface state defects between the four, and further improving the electrical performance of the semiconductor structure.

[0028] In other embodiments, the material of the bit line may also be metal, such as copper, aluminum, or tungsten; the material of the electrical contact layer may also be metal, such as copper, aluminum, or tungsten.

[0029] In this embodiment, the semiconductor base 100 may include: a semiconductor substrate 110; a first semiconductor well layer 120, arranged on the semiconductor substrate 110 of the memory area II, and the bit line 101 is located on the surface of the first semiconductor well layer 120 away from the semiconductor substrate 110; a second semiconductor well layer 130, arranged on the semiconductor substrate 110 of the logic device area I, and the electrical contact layer 111 is located on the surface of the second semiconductor well layer 130 away from the semiconductor substrate 110.

[0030] The first semiconductor well layer 120 located between the bit line 101 and the semiconductor substrate 110 is beneficial for preventing the bit line 101 from leaking. The second semiconductor well layer 130 located between the electrical contact layer 111 and the semiconductor substrate 110 is beneficial for preventing the electrical contact layer 111 from leaking.

[0031] In this embodiment, semiconductor substrate 110 is a silicon substrate, the first type of ions are N-type ions, and the second type of ions are P-type ions. Specifically, the N-type ions are at least one of arsenic ions, phosphorus ions, or antimony ions; and the P-type ions are at least one of boron ions, indium ions, or gallium ions. In other embodiments, the semiconductor substrate is a germanium substrate, a silicon-germanium substrate, or a III-V compound semiconductor substrate, where the material of the III-V compound semiconductor substrate includes at least one of gallium arsenide, indium phosphide, or gallium nitride.

[0032] Furthermore, the orthographic projection of the first semiconductor well layer 120 on the semiconductor substrate 110 can overlap with the orthographic projection of the bit line 101 on the semiconductor substrate 110, which is beneficial to increase the contact area between the first semiconductor well layer 120 and the bit line 101, thereby reducing the contact resistance between the first semiconductor well layer 120 and the bit line 101; in addition, it is also beneficial to increase the volume of the bit line 101, thereby reducing the resistance of the bit line 101, improving the RC delay effect, and increasing the operating speed of the semiconductor structure.

[0033] The logic device corresponding to the logic device area I may include at least one of a digital signal processor (DSP), a field programmable gate array (FPGA), a central processing unit (CPU), a graphics processing unit (GPU), or an embedded neural network processing unit (NPU). The memory corresponding to the memory area II may include at least one of SRAM (Random Access Memory), DRAM (Random Access Memory), RRAM (Static Random Access Memory), MRAM (Magnetoresistive Random Access Memory), or PCRAM (Phase Change Random Access Memory). In this way, the embodiment of the present invention can integrate the logic device and the memory device on the same chip to achieve true in-memory computing.

[0034] In this embodiment, the logic device region I may include an NMOS region and a PMOS region; the semiconductor substrate 100 of the logic device region I also includes: an isolation structure 140, the isolation structure 140 is located between adjacent second semiconductor well layers 130, and is also located between adjacent electrical contact layers 111.

[0035] The isolation structure 140 is located between adjacent second semiconductor well layers 130 and adjacent electrical contact layers 111, insulating adjacent second semiconductor well layers 130 from each other and adjacent electrical contact layers 111 from each other. This helps prevent electrical interference between adjacent second semiconductor well layers 130 and adjacent electrical contact layers 111. Furthermore, the isolation structure 140 is located between the first semiconductor well layer 120 and the second semiconductor well layer 130, insulating the first semiconductor well layer 120 and the second semiconductor well layer 130 from each other. The isolation structure 140 is made of at least one of silicon nitride, silicon carbonitride, or silicon carbon oxynitride.

[0036] Furthermore, the second semiconductor well layer 130 includes a third semiconductor well layer 131 and a fourth semiconductor well layer 132, and the third semiconductor well layer 131 and the fourth semiconductor well layer 132 are spaced apart from each other. The third semiconductor well layer 131 is doped with first-type ions, and the fourth semiconductor well layer 132 is doped with second-type ions, the second-type ions being different from the first-type ions. The first semiconductor well layer 120 is also doped with first-type ions, and both the first-type ions and the second-type ions are either N-type ions or P-type ions. In this embodiment, the first-type ions are N-type ions, the second-type ions are P-type ions, the logic device region I corresponding to the third semiconductor well layer 131 is an NMOS region, and the logic device region I corresponding to the fourth semiconductor well layer 132 is a PMOS region. In other embodiments, the first-type ions may be P-type ions, and the second-type ions may be N-type ions.

[0037] It should be noted that Figure 1 In the example, the second semiconductor well layer 130 includes two third semiconductor well layers 131 and a fourth semiconductor well layer 132 located between the two third semiconductor well layers 131, and the second semiconductor well layer 130 closest to the first semiconductor well layer 120 is a third semiconductor well layer 131. In fact, this embodiment does not limit the number of second semiconductor well layers 130, nor does it limit the type of the second semiconductor well layer 130 closest to the first semiconductor well layer 120. The number of second semiconductor well layers can be reasonably set according to actual electrical requirements, as long as the third semiconductor well layer and the fourth semiconductor well layer are alternately distributed in sequence. In addition, the second semiconductor well layer closest to the first semiconductor well layer can also be the fourth semiconductor well layer.

[0038] The semiconductor substrate 100 may further include a deep well layer 150. The orthographic projection of the second semiconductor well layer 130 on the semiconductor substrate 110 is located within the orthographic projection of the deep well layer 150 on the semiconductor substrate 110. In this embodiment, the deep well layer 150 is doped with first-type ions. In other embodiments, the deep well layer may be doped with second-type ions.

[0039] In other embodiments, the semiconductor substrate may not include the first semiconductor well layer and the second semiconductor well layer, and the bit line and the electrical contact layer are directly located on the semiconductor substrate. The bit line 101, the first semiconductor channel 102, the electrical contact layer 111, and the second semiconductor channel 112 include the same semiconductor element, and the bit line 101, the first semiconductor channel 102, the electrical contact layer 111, and the second semiconductor channel 112 are an integrated structure. In one example, the bit line 101, the first semiconductor channel 102, the electrical contact layer 111, and the second semiconductor channel 112 all include silicon. In other examples, the bit line, the first semiconductor channel, the electrical contact layer, and the second semiconductor channel may all include germanium, or all four include silicon and germanium, or all four include silicon and carbon, or all four include arsenic and gallium, or all four include gallium and indium.

[0040] Specifically, the material of the bit line 101 may include a metal semiconductor compound, which has a relatively small resistivity compared to unmetallized semiconductor materials. Therefore, compared to the first semiconductor channel 102, the resistivity of the bit line 101 is smaller, which is beneficial to reducing the resistance of the bit line 101 and reducing the contact resistance between the bit line 101 and the first doped region a, further improving the electrical performance of the semiconductor structure.

[0041] In addition, the resistivity of the bit line 101 is lower than the resistivity of the first semiconductor well layer 120 . Compared with using semiconductor materials as the material of the bit line 101 , using metal semiconductor compounds as the material of the bit line 101 has a lower resistivity of the bit line 101 , which is beneficial to reducing the resistance of the bit line 101 .

[0042] In some examples, the entire bit line 101 is made of a metal-semiconductor compound. In other examples, the region of the bit line 101 directly below the first doped region a is made of a semiconductor material, and the region of the bit line 101 not covered by the first doped region a is made of a metal-semiconductor compound. It is understood that as device dimensions continue to shrink or manufacturing process parameters are adjusted, the material of the portion of the bit line 101 directly below the first doped region a may be a semiconductor material, and the material of the remaining region of the bit line 101 directly below the first doped region a may also be a metal-semiconductor compound, with the "remaining region" being located outside the "partial region."

[0043] Furthermore, the material of the electrical contact layer 111 is the same as that of the bit line 101. Therefore, compared with the second semiconductor channel 112, the resistivity of the electrical contact layer 111 is smaller, which is beneficial to reducing the resistance of the electrical contact layer 111 and reducing the contact resistance between the electrical contact layer 111 and the third doped region d, further improving the electrical performance of the semiconductor structure.

[0044] In addition, the resistivity of the electrical contact layer 111 is lower than the resistivity of the second semiconductor well layer 130. Compared with using semiconductor materials as the material of the electrical contact layer 111, using metal semiconductor compounds as the material of the electrical contact layer 111 has a lower resistivity of the electrical contact layer 111, which is beneficial to reducing the resistance of the electrical contact layer 111.

[0045] In some examples, the entire electrical contact layer 111 is made of a metal-semiconductor compound. In other examples, the region of the electrical contact layer 111 directly below the third doped region d is made of a semiconductor material, and the region of the electrical contact layer 111 not covered by the third doped region d is made of a metal-semiconductor compound. It is understood that as device dimensions continue to shrink or manufacturing process parameters are adjusted, the material of a portion of the electrical contact layer 111 directly below the third doped region d may be a semiconductor material, and the material of the remaining region of the electrical contact layer 111 directly below the third doped region d may also be a metal-semiconductor compound, with the "remaining region" being located outside the "partial region."

[0046] In other embodiments, the material of the bit line and the material of the electrical contact layer can both be semiconductor materials, then the semiconductor base does not include the first semiconductor well layer and the second semiconductor well layer, and the bit line and the electrical contact layer are both directly located on the semiconductor substrate.

[0047] In other embodiments, the materials of the bit line and / or the electrical contact layer may also be metal materials.

[0048] The semiconductor element may include at least one of silicon, carbon, germanium, arsenic, gallium, and indium. The metal element in the metal semiconductor compound may include at least one of cobalt, nickel, molybdenum, titanium, tungsten, tantalum, and platinum.

[0049] Taking silicon as the semiconductor element as an example, the metal semiconductor compound includes at least one of cobalt silicide, nickel silicide, molybdenum silicide, titanium silicide, tungsten silicide, tantalum silicide, or platinum silicide. In addition, the metal semiconductor compound may also be doped with nitrogen.

[0050] The semiconductor structure may include a plurality of spaced-apart bit lines 101, each bit line 101 may be in contact with at least one first doped region a. Figure 1 In the example, it is taken that each bit line 101 contacts three first doping regions a. The number of first doping regions a contacting each bit line 101 can be reasonably set according to actual electrical requirements.

[0051] The material of the first semiconductor channel 102 and the material of the second semiconductor channel 112 both include elemental semiconductor materials or crystalline inorganic compound semiconductors. In this embodiment, the material of the first semiconductor channel 102 and the material of the second semiconductor channel 112 are both silicon. In other embodiments, the material of the first semiconductor channel and / or the material of the second semiconductor channel may be germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.

[0052] Furthermore, the first semiconductor channel 102 and the bit line 101 contain the same type of dopant ions, which may be N-type ions or P-type ions. The second semiconductor channel 112 includes a third semiconductor channel 122 and a fourth semiconductor channel 142. The third semiconductor channel 122 is located on a side of the third semiconductor well layer 131 away from the semiconductor substrate 110, and the fourth semiconductor channel 142 is located on a side of the fourth semiconductor well layer 132 away from the semiconductor substrate 110. The dopant ion type doped in the third semiconductor channel 122 is different from the dopant ion type doped in the third semiconductor well layer 131, and the dopant ion type doped in the fourth semiconductor channel 142 is different from the dopant ion type doped in the fourth semiconductor well layer 132.

[0053] In this embodiment, the first semiconductor channel 102 and the second semiconductor channel 112 are both cylindrical structures, and the side surfaces of the first semiconductor channel 102 and the second semiconductor channel 112 are both smooth transition surfaces, which is beneficial to avoid the occurrence of tip discharge or leakage in the first semiconductor channel 102 and the second semiconductor channel 112, and further improve the electrical performance of the semiconductor structure. It should be noted that in other embodiments, the first semiconductor channel and / or the second semiconductor channel may also be an elliptical columnar structure, a square columnar structure or other irregular structures. It is understandable that when the first semiconductor channel structure and / or the second semiconductor channel structure is a square columnar structure, the corners formed by the adjacent surfaces of the side walls of the square columnar structure can be rounded corners, which can also avoid the problem of tip discharge. The square columnar structure can be a cubic columnar structure or a rectangular parallelepiped columnar structure.

[0054] The first doped region a constitutes one of the source or drain of the transistor device, and the second doped region c constitutes the other of the source or drain of the transistor device; the third doped region d constitutes one of the source or drain of another transistor device, and the second doped region g constitutes the other of the source or drain of another transistor device.

[0055] Among them, the second doping region c may also include a first metal contact layer 152, and the first metal contact layer 152 is in contact with the capacitor structure 104. The material of the first metal contact layer 152 is also a metal semiconductor compound, that is, the material of the first metal contact layer 152 can be the same as the material of the bit line 101. The resistivity of the first metal contact layer 152 is lower than the resistivity of the second doping region c excluding the first metal contact layer 152, which is beneficial to reducing the resistivity of the second doping region c; in addition, the first metal contact layer 152 is beneficial to reducing the contact resistance between the second doping region c and the capacitor structure 104. It should be noted that the "same material" here is actually the same without considering N-type doping ions or P-type doping ions. For example, the material of the first metal contact layer 152 and the material of the bit line 101 are both nickel silicide.

[0056] The fourth doped region f may also include a second metal contact layer 162, which is co-located with the first metal contact layer 152 and in contact with the electrical connection structure 105. The material of the second metal contact layer 162 is also a metal-semiconductor compound, meaning that the material of the second metal contact layer 162 can be the same as that of the electrical contact layer 111. The resistivity of the second metal contact layer 162 is lower than that of the fourth doped region f excluding the second metal contact layer 162, which helps reduce the resistivity of the fourth doped region f. Furthermore, the second metal contact layer 162 helps reduce the contact resistance between the fourth doped region f and the electrical connection structure 105. It should be noted that the term "same material" here refers to the material being the same regardless of whether it is N-type or P-type dopant ions. For example, the material of the second metal contact layer 162 and the material of the electrical contact layer 111 are both nickel silicide.

[0057] The first semiconductor channel 102 and the second semiconductor channel 112 can both form the channel of a junctionless transistor, i.e., the doping ions in the first doping region a, the first channel region b, and the second doping region c are of the same type, and the doping ions in the third doping region d, the second channel region e, and the fourth doping region f are of the same type, for example, all of the doping ions are N-type ions or all of the doping ions are P-type ions. Furthermore, the doping ions in the first doping region a, the first channel region b, and the second doping region c can be the same, and the doping ions in the third doping region d, the second channel region e, and the fourth doping region f can be the same. Furthermore, the doping ion types in each region of the first semiconductor channel 102 and the second semiconductor channel 112 can be the same, which facilitates forming the first semiconductor channel 102 and the second semiconductor channel 112 through the same process steps.

[0058] The "junction-free" herein refers to the absence of a PN junction, i.e., there is no PN junction in the device formed by the first semiconductor channel 102 and the second semiconductor channel 112. This has the following advantages: on the one hand, there is no need to perform additional doping on the first doping region a, the second doping region c, the third doping region d, and the fourth doping region f, thereby avoiding the problem of difficulty in controlling the doping process of the first doping region a, the second doping region c, the third doping region d, and the fourth doping region f. In particular, as the size of transistors continues to shrink, if the first doping region a, the second doping region c, the third doping region d, and the fourth doping region f are additionally doped, the doping concentration becomes even more difficult to control. On the other hand, since the device is a junction-free transistor, it is advantageous to avoid the use of an ultra-steep source-drain concentration gradient doping process to produce an ultra-steep PN junction in the nanometer range, thereby avoiding the problems of threshold voltage drift and leakage current increase caused by doping mutations, and also helps to suppress the short channel effect. The device can still operate within the scale range of a few nanometers, thereby helping to further improve the integration density and electrical performance of the semiconductor structure. It can be understood that the additional doping here refers to doping performed to make the doping ion type of the first doping region a and the second doping region c different from the doping ion type of the first channel region b, and doping performed to make the doping ion type of the third doping region d and the fourth doping region f different from the doping ion type of the second channel region e.

[0059] The word line 103 includes: a first gate dielectric layer 123, which is arranged around the first channel region b and is located on the sidewall surface of the first semiconductor channel 102 where the first channel region b is located, and is also located on the sidewall surface of the first semiconductor channel 102 where the second doped region c is located; a first gate conductive layer 133, which is arranged around the first channel region b and is located on the sidewall surface of the first gate dielectric layer 123 corresponding to the first channel region b.

[0060] The first gate dielectric layer 123 is used to isolate the first gate conductive layer 133 from the first semiconductor channel 102. Furthermore, the first gate dielectric layer 123 located on the sidewall surfaces of the first semiconductor channel 102 in the second doped region c can protect the surface of the second doped region c, preventing process damage to the surface of the second doped region c during the manufacturing process, thereby further improving the electrical performance of the semiconductor structure. It is understood that in other embodiments, the first gate dielectric layer may be located only on the sidewall surfaces of the first semiconductor channel where the first channel region is located.

[0061] The gate 113 includes: a second gate dielectric layer 143, which is in the same layer as the first gate dielectric layer 123, the second gate dielectric layer 143 is arranged around the second channel region e, and is located on the sidewall surface of the second semiconductor channel 112 where the second channel region e is located, and is also located on the sidewall surface of the second semiconductor channel 112 where the fourth doped region f is located; a second gate conductive layer 153, which is in the same layer as the first gate conductive layer 133, the second gate conductive layer 153 is arranged around the second channel region e, and is located on the sidewall surface of the second gate dielectric layer 143 corresponding to the second channel region e.

[0062] The second gate dielectric layer 143 is used to isolate the second gate conductive layer 153 from the second semiconductor channel 112. Furthermore, the second gate dielectric layer 143 located on the sidewall surfaces of the second semiconductor channel 112 in the fourth doped region f can protect the surface of the fourth doped region f, preventing damage to the surface of the fourth doped region f during the manufacturing process, thereby further improving the electrical performance of the semiconductor structure. It will be appreciated that in other embodiments, the second gate dielectric layer may be located only on the sidewall surfaces of the second semiconductor channel where the second channel region is located.

[0063] The material of the first gate dielectric layer 123 and the material of the second gate dielectric layer 143 both include at least one of silicon oxide, silicon nitride, or silicon oxynitride. The material of the first gate conductive layer 133 and the material of the second gate conductive layer 153 both include at least one of polysilicon, titanium nitride, tantalum nitride, copper, tungsten, or aluminum. In some examples, the material of the first gate dielectric layer 123 and the material of the second gate dielectric layer 143 are the same, which facilitates forming the first gate dielectric layer 123 and the second gate dielectric layer 143 through the same process steps. The material of the first gate conductive layer 133 and the material of the second gate conductive layer 153 are the same, which facilitates forming the first gate conductive layer 133 and the second gate conductive layer 153 through the same process steps.

[0064] In this embodiment, the semiconductor structure includes a plurality of spaced-apart bit lines 101 and a plurality of spaced-apart electrical contact layers 111, each of which extends along a first direction. Accordingly, the semiconductor structure includes a plurality of spaced-apart word lines 103 and a plurality of spaced-apart gates 113, each of which extends along a second direction. The second direction is different from the first direction, for example, the first direction may be perpendicular to the second direction. Furthermore, each word line 103 may be disposed around a first channel region b of at least one first semiconductor channel 102, and each gate 113 may be disposed around a second channel region e of at least one second semiconductor channel 112. The number of first semiconductor channels 102 surrounded by each word line 103 and the number of second semiconductor channels 112 surrounded by each gate 113 may be appropriately determined based on actual electrical requirements.

[0065] It should be noted that Figure 1 The example shows that a second gate conductive layer 153 surrounds both the third semiconductor channel 122 of the NMOS region and the fourth semiconductor channel 142 of the PMOS region adjacent to the NMOS region. In other examples, a second gate conductive layer may only surround the third semiconductor channel of the NMOS region, and another second gate conductive layer may only surround the fourth semiconductor channel of the PMOS region.

[0066] The dielectric layer 106 is used to isolate the bit line 101 from the first gate conductive layer 133, and is also used to isolate the electrical contact layer 111 and the second gate conductive layer 153, and is also used to isolate the adjacent word line 103 and the adjacent gate 113. In other words, the dielectric layer 106 is not only located between the bit line 101 and the word line 103, and in the space between adjacent word lines 103, but is also located between the electrical contact layer 111 and the gate 113, and in the space between adjacent gates 113.

[0067] The dielectric layer 106 may include: a first dielectric layer 116, the first dielectric layer 116 is located between the bit line 101 and the word line 103 and between the electrical contact layer 111 and the gate 113, so as to insulate the bit line 101 from the word line 103 and the electrical contact layer 111 from the gate 113, thereby preventing electrical interference between the bit line 101 and the word line 103 and between the electrical contact layer 111 and the gate 113; a second dielectric layer 126, the second dielectric layer 126 is located between adjacent word lines 103 and adjacent gates 113 and in contact with the first dielectric layer 116, and is used to achieve insulation between adjacent word lines 103 and adjacent gates 113, and prevent electrical interference between adjacent word lines 103 and adjacent gates 113; the second dielectric layer 126 is also located on the surface of the word lines 103 and the gates 113 away from the semiconductor substrate 100, and is used to support other conductive structures located on the surface of the second dielectric layer 126 away from the semiconductor substrate 100, and to achieve insulation between the word lines 103 and the gates 113 and other conductive structures.

[0068] In this embodiment, the material of the first dielectric layer 116 and the material of the second dielectric layer 126 are the same, and both can be at least one of silicon oxide, silicon nitride, silicon oxycarbonitride, or silicon oxynitride. In other embodiments, the material of the first dielectric layer and the material of the second dielectric layer can also be different.

[0069] It is understandable that in other embodiments, the dielectric layer may also be other stacked film layer structures. The specific structure of the stacked film layer structure is related to the manufacturing process steps, and it only needs to ensure that the dielectric layer can achieve the isolation purpose.

[0070] In this embodiment, the memory area II includes a DRAM area, and the capacitor structure 104 of the DRAM area includes: a first conductive structure 114, which is in contact with the second doped area c; a lower electrode layer 124, which is in contact with the first conductive structure 114; a capacitor dielectric layer 134, which is located on the surface of the lower electrode layer 124; and an upper electrode layer 144, which is located on the surface of the capacitor dielectric layer 134.

[0071] Specifically, the first conductive structure 114 includes a first conductive pillar 154 and a first conductive layer 164. In a plane perpendicular to the surface of the semiconductor substrate 100, the cross-section of the first conductive pillar 154 is an inverted trapezoidal shape, wider at the top and narrower at the bottom. The orthographic projection of the first conductive layer 164 on the semiconductor substrate 100 overlaps the orthographic projection of the first conductive pillar 154 on the semiconductor substrate 100. This facilitates increasing the volume of the first conductive structure 114 while ensuring a large contact area between the first conductive pillar 154 and the second doped region c, and between the first conductive layer 164 and the lower electrode layer 124, thereby reducing the resistance of the first conductive structure 114. In some examples, the material of the first conductive pillar 154 and the first conductive layer 164 are the same, and are both made of at least one of a conductive material such as platinum nickel, titanium, tantalum, cobalt, polysilicon, copper, tungsten, tantalum nitride, titanium nitride, or ruthenium. In other embodiments, the material of the first conductive pillar and the material of the first conductive layer may be different.

[0072] The material of the lower electrode layer 124 and the material of the upper electrode layer 144 can be the same. The material of the lower electrode layer 124 and the material of the upper electrode layer 144 can both be at least one of platinum nickel, titanium, tantalum, cobalt, polysilicon, copper, tungsten, tantalum nitride, titanium nitride, or ruthenium. In other embodiments, the material of the lower electrode layer and the material of the upper electrode layer can also be different. The material of the capacitor dielectric layer 134 includes a high dielectric constant material such as silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide, or barium strontium titanate.

[0073] In this embodiment, the cross-section of the lower electrode layer 124 is U-shaped in a plane perpendicular to the surface of the semiconductor substrate 100. The capacitor dielectric layer 134 located on the surface of the lower electrode layer 124 forms a through-hole. The upper electrode layer 144 completely fills the through-hole. The upper electrode layers 144 located in adjacent through-holes are in contact and electrically connected to each other, that is, the upper electrode layers 144 are a single-piece structure. In other embodiments, the upper electrode layers located in adjacent through-holes are spaced apart, allowing adjacent upper electrode layers to be connected to different potentials, thereby facilitating diversified control of adjacent capacitor structures.

[0074] In other embodiments, the capacitor structure can also be a planar capacitor, wherein the lower electrode layer contacts the side of the second doping region away from the first channel region; the capacitor dielectric layer contacts the side of the lower electrode layer away from the second doping region; and the upper electrode layer contacts the side of the capacitor dielectric layer away from the lower electrode layer.

[0075] In this embodiment, the first semiconductor channel 102 is a cylindrical structure. One end surface of the cylindrical structure, namely, the end surface of the first doped region a, contacts the bit line 101, and the other end surface of the cylindrical structure, namely, the second doped region c, contacts the capacitor structure 104. Furthermore, the second doped region c includes a first metal contact layer 152, which contacts the lower electrode layer 124. This helps reduce the contact resistance between the second doped region c and the lower electrode layer 124, thereby improving the electrical performance of the semiconductor structure.

[0076] The electrical connection structure 105 includes: a second conductive structure 115 in the same layer as the first conductive structure 114, the second conductive structure 115 contacts the fourth doping region f; and a third conductive structure 145, the third conductive structure 145 contacts a side of the second conductive structure 115 away from the fourth doping region f.

[0077] Specifically, the second conductive structure 115 includes a second conductive pillar 125 and a second conductive layer 135 . Figure 1 In the example, one second conductive structure 115 may include a second conductive layer 135 and two second conductive pillars 125, the two second conductive pillars 125 respectively contacting two adjacent fourth doping regions f, i.e., one second conductive structure 115 may be electrically connected to two adjacent fourth doping regions f; another second conductive structure 115 may include a second conductive layer 135 and a second conductive pillar 125, the second conductive pillar 125 electrically connected to one fourth doping region f; and yet another second conductive structure 115 may include a second conductive layer 135 and a second conductive pillar 125, the second conductive pillar 125 electrically connected to the second gate conductive layer 153. It should be noted that in this embodiment, the number of second conductive pillars 125 and second conductive layer 135 included in a single second conductive structure 115, as well as the specific electrical connection of the second conductive pillars 125, may be reasonably set according to actual electrical requirements.

[0078] In addition, the morphology characteristics and material properties of the second conductive pillars 125 and the second conductive layer 135 in the second conductive structure 115 may refer to the aforementioned first conductive structure 114 and are not described in detail here.

[0079] The third conductive structure 145 includes at least two third conductive layers 155 and third conductive pillars 165 electrically connecting adjacent third conductive layers 155. The third conductive pillars 165 are also electrically connected to the second conductive structure 115 and the third conductive layer 155 closest to the second conductive structure 115. Figure 1 In the example, the third conductive structure 145 includes two third conductive layers 155 and two third conductive columns 165. In this embodiment, the number of third conductive layers 155 and third conductive columns 165 included in the third conductive structure 145 can be reasonably set according to actual electrical requirements.

[0080] In addition, the morphology characteristics and material properties of the third conductive layer 155 and the third conductive pillars 165 in the third conductive structure 145 may refer to the aforementioned first conductive structure 114 and are not described in detail here.

[0081] In this embodiment, in a direction perpendicular to the surface of the semiconductor substrate 100 , the depth of the lower electrode layer 124 is the same as the depth of the third conductive structure 145 . Figure 1 The example in which the depth of the lower electrode layer 124 penetrates two third conductive layers 155 is taken as an example. It should be noted that the number of third conductive layers 155 that the depth of the lower electrode layer 124 penetrates can be reasonably set according to actual electrical requirements.

[0082] The memory region II may further include an NVM region; the semiconductor structure further includes: a free layer 108, a tunneling layer 118 and a fixed layer 128 stacked on the second doped region c of the NVM region, and the free layer 108 is electrically connected to the second doped region c of the NVM region.

[0083] Specifically, a first conductive structure 114 is provided between the free layer 108 and the second doped region c of the NVM region, and the free layer 108 and the second doped region c are electrically connected via the first conductive structure 114 .

[0084] It should be noted that the various conductive structures located in the NVM area constitute non-volatile memory (NVM), and the various conductive structures located in the DRAM area constitute dynamic random access memory (DRAM). The NVM area and DRAM area constitute memory area II, which is used to store data; the various conductive structures located in the NMOS area and PMOS area of ​​the logic device area I constitute a processor, which is used to perform logical operations on data. In this way, the same semiconductor structure contains both a processor and a memory to implement in-memory computing, allowing data input and output and computing processes to be performed in different areas of the semiconductor structure, which is beneficial for shortening the distance between the processor and the memory, thereby improving the efficiency of data transmission and reducing the power consumption required for data transmission, thereby improving the operating efficiency of the semiconductor structure and reducing the operating energy consumption of the semiconductor structure.

[0085] The semiconductor structure further includes an insulating layer 107 , which is located on the surface of the dielectric layer 106 , and the capacitor structure 104 and the electrical connection structure 105 are located within the insulating layer 107 , and the relative dielectric constant of the insulating layer 107 material is smaller than the relative dielectric constant of the dielectric layer 106 material.

[0086] Specifically, the insulating layer 107 may include multiple interlayer dielectric layers 117 and multiple etch stop layers 127, and the interlayer dielectric layers 117 and the etch stop layers 127 are stacked in sequence. The insulating layer 107 in contact with the surface of the dielectric layer 106 is the interlayer dielectric layer 117. It is understood that in other embodiments, the insulating layer may also be other stacked film layer structures. The specific structure of the stacked film layer structure is related to the manufacturing process steps, and it is sufficient to ensure that the insulating layer can serve the purpose of isolation.

[0087] In this embodiment, the semiconductor structure may further include: a plurality of mutually spaced fourth conductive layers 109 located at the top layer, the fourth conductive layer 109 being configured to electrically connect to corresponding conductive layers or external devices. It should be noted that, while this embodiment uses four conductive layers as an example, the conductive layer may be three, five, or any other number of layers depending on actual circuit requirements.

[0088] To summarize, the semiconductor substrate 100 includes a logic device area I and a memory area II. The structure within the memory area II is used to store data, and the structure within the logic device area I is used to calculate data, so that the same semiconductor structure has both a processor and a memory to realize in-memory calculation, so that data input and output and the calculation process can be performed in different areas of the semiconductor structure, which is beneficial to shortening the distance between the processor and the memory, so as to improve the efficiency of data transmission and reduce the power consumption required for data transmission, thereby improving the working efficiency of the semiconductor structure and reducing the working energy consumption of the semiconductor structure.

[0089] In addition, the semiconductor structure provided in this embodiment can be applied to 4F 2 Memory, F is the feature size, the memory can be DRAM memory or SRAM memory.

[0090] Accordingly, another embodiment of the present invention provides a method for manufacturing a semiconductor structure, which can be used to form the above-mentioned semiconductor structure.

[0091] Figures 4 to 17 A schematic diagram of the cross-sectional structures corresponding to each step in the method for manufacturing a semiconductor structure provided in another embodiment of the present invention is provided. The method for manufacturing the semiconductor structure provided in this embodiment will be described in detail below in conjunction with the accompanying drawings, and the parts that are the same as or corresponding to the above-mentioned embodiments will not be described in detail below.

[0092] refer to Figures 4 to 9 , providing a semiconductor substrate 100, the semiconductor substrate 100 including a logic device area I and a memory area II; forming a bit line 101 and an electrical contact layer 111 provided on the same layer as the bit line 101, the bit line 101 being located on the semiconductor substrate 100 in the memory area II, the electrical contact layer 111 being located on the semiconductor substrate 100 in the logic device area I; forming a first semiconductor channel 102 and a second semiconductor channel 112 provided on the same layer as the first semiconductor channel 102, the first semiconductor channel 102 being located on the surface of the bit line 101, and In the direction from the semiconductor substrate 100 to the bit line 101, the first semiconductor channel 102 includes a first doped region a, a first channel region b, and a second doped region c arranged in sequence, and the first doped region a is in contact with the bit line 101. The second semiconductor channel 112 is located on the surface of the electrical contact layer 111. In the direction from the semiconductor substrate 100 to the electrical contact layer 111, the second semiconductor channel 112 includes a third doped region d, a second channel region e, and a fourth doped region f arranged in sequence, and the third doped region d is in contact with the electrical contact layer 111.

[0093] Specifically, providing the semiconductor substrate 100 and forming the bit line 101, the electrical contact layer 111, the first semiconductor channel 102 and the second semiconductor channel 112 include the following process steps:

[0094] refer to Figure 4 , providing an initial semiconductor substrate 160.

[0095] The initial semiconductor substrate 160 serves as a basis for forming the semiconductor substrate 100 , the bit line 101 , the electrical contact layer 111 , the first semiconductor channel 102 , and the second semiconductor channel 112 .

[0096] In some embodiments, the initial semiconductor base 160 includes a semiconductor substrate 110, an initial first semiconductor well layer 170, and an initial second semiconductor well layer 180. The initial first semiconductor well layer 170 is located on the semiconductor substrate 110 in the memory region II, and the initial second semiconductor well layer 180 is located on the semiconductor substrate 110 in the logic device region I.

[0097] Specifically, the initial first semiconductor well layer 170 is a double-layer structure, and the initial first semiconductor well layer 170 is doped with first type ions. The doping concentration of the first type ions in different layers is different. This embodiment does not limit the size relationship of the doping concentration of the first type ions in different layers.

[0098] The initial second semiconductor well layer 180 also has a double-layer structure, and some areas of the initial second semiconductor well layer 180 located in the same layer are doped with first type ions, and some areas are doped with second type ions, and the areas doped with first type ions and the areas doped with second type ions are staggered. In the direction perpendicular to the surface of the semiconductor substrate 110, the types of doped ions in the initial second semiconductor well layer 180 of adjacent layers are different.

[0099] In addition, the initial semiconductor substrate 160 may further include a deep well layer 150, and the orthographic projection of the initial second semiconductor well layer 180 on the semiconductor substrate 110 is located within the orthographic projection of the deep well layer 150 on the semiconductor substrate 110. In this embodiment, the deep well layer 150 is doped with first-type ions. In other embodiments, the deep well layer may be doped with second-type ions.

[0100] In this embodiment, the semiconductor substrate 110 is a silicon substrate, the first type of ions are N-type ions, and the second type of ions are P-type ions. In other embodiments, the semiconductor substrate may be a germanium substrate, a germanium silicon substrate, or a III-V compound semiconductor substrate, the first type of ions may be P-type ions, and the second type of ions may be N-type ions.

[0101] Combined with reference Figure 4 and Figure 5 Using the mask layer 119 as a mask, a partial thickness of the initial semiconductor substrate 160 is patterned to form the first semiconductor channel 102 and the second semiconductor channel 112 .

[0102] In this embodiment, a partial thickness of the initial first semiconductor well layer 170 and the initial second semiconductor well layer 180 is patterned to form the first semiconductor channel 102 and the second semiconductor channel 112. The remaining partial thickness of the initial first semiconductor well layer 170 is used to subsequently form the bit line 101, and the remaining partial thickness of the initial second semiconductor well layer 180 is used to subsequently form the electrical contact layer 111. The patterning method includes a self-aligned multiple exposure technique or a self-aligned multiple imaging technique.

[0103] refer to Figure 2 , the first semiconductor channel 102 includes a first doping region a, a first channel region b and a second doping region c arranged in sequence; Figure 3 The second semiconductor channel 112 includes a third doping region d, a second channel region e, and a fourth doping region f which are arranged in sequence.

[0104] Among them, the type of doping ions in the first doping region a, the first channel region b and the second doping region c is the same, and the type of doping ions in the third doping region d, the second channel region e and the fourth doping region f is the same. The first semiconductor channel 102 and the second semiconductor channel 112 are both used to form the channel of the junctionless transistor, avoiding problems such as threshold voltage drift and increased leakage current caused by doping mutations, and is also beneficial to suppressing the short channel effect.

[0105] It is understood that, before patterning, the initial semiconductor substrate 160 may be pre-doped in regions, where N-type or P-type ions may be doped. Alternatively, the doping process may be performed after patterning a portion of the initial semiconductor substrate 160 to form the first semiconductor channel 102 and the second semiconductor channel 112 with a suitable ion distribution. In this embodiment, the first semiconductor channel 102 and / or the second semiconductor channel 112 may be corner-rounded by thermal oxidation, etching, and / or hydrogen annealing to form a cylindrical structure of the first semiconductor channel 102 and / or the second semiconductor channel 112. This helps prevent tip discharge or leakage in the first semiconductor channel 102 and / or the second semiconductor channel 112 during operation of the semiconductor structure.

[0106] Continue to refer Figure 5 , for the remaining initial second semiconductor well layer 180 (reference Figure 4 ) is patterned again to form a groove g at the junction of different doping ion types in the initial second semiconductor well layer 180, and the groove g runs through the thickness of the remaining initial second semiconductor well layer 180,

[0107] refer to Figure 6 , in groove g (reference Figure 5) is formed in the isolation structure 140. When a metal contact layer and a second semiconductor well layer are subsequently formed on the remaining initial second semiconductor well layer 180, the isolation structure 140 is conducive to isolating adjacent metal contact layers and isolating adjacent second semiconductor well layers.

[0108] The top surface of the isolation structure 140 may be flush with the top surface of the remaining initial second semiconductor well layer 180 .

[0109] refer to Figures 7 to 9 , for the remaining portion of the thickness of the initial semiconductor substrate 160 (reference Figure 4 ) is metallized to convert a portion of the thickness of the initial semiconductor substrate 160 located below the first semiconductor channel 102 into a bit line 101, and a portion of the thickness of the initial semiconductor substrate 160 located below the second semiconductor channel 112 into an electrical contact layer 111, with the remaining initial semiconductor substrate 160 serving as the semiconductor substrate 100.

[0110] Specifically, a metallization process is performed on the remaining partial thickness of the initial first semiconductor well layer 170 and the initial second semiconductor well layer 180, so as to convert the partial thickness of the initial first semiconductor well layer 170 located below the first semiconductor channel 102 into the bit line 101, and convert the partial thickness of the initial second semiconductor well layer 180 located below the second semiconductor channel 112 into the electrical contact layer 111. After the metallization process, the remaining initial first semiconductor well layer 170 serves as the first semiconductor well layer 120, and the remaining initial second semiconductor well layer 180 serves as the second semiconductor well layer 130.

[0111] In other embodiments, the remaining partial thickness of the initial first semiconductor well layer and the initial second semiconductor well layer are metallized, so that the entire thickness of the initial first semiconductor well layer located below the first semiconductor channel can be converted into a bit line, and the entire thickness of the initial second semiconductor well layer located below the second semiconductor channel can be converted into an electrical contact layer.

[0112] Specifically, the metallization process includes the following steps:

[0113] refer to Figure 7 , forming a barrier layer 129 , which covers the sidewall surfaces of the first semiconductor channel 102 and the second semiconductor channel 112 .

[0114] The barrier layer 129 exposes the surface of the initial first semiconductor well layer 170 except for the portion directly below the first semiconductor channel 102, and exposes the surface of the initial second semiconductor well layer 180 except for the portion directly below the second semiconductor channel 112. In this embodiment, when the first semiconductor channel 102 and the second semiconductor channel 112 are patterned, the mask layer 119 located on the top surfaces of the first semiconductor channel 102 and the second semiconductor channel 112 is not removed. Therefore, the mask layer 119 and the barrier layer 129 can be used together to protect the first semiconductor channel 102 and the second semiconductor channel 112 during a subsequent annealing process, thereby preventing the materials of the first semiconductor channel 102 and the second semiconductor channel 112 from reacting with the metal material.

[0115] In other embodiments, in this step, the mask layer located on the top surfaces of the first semiconductor channel and the second semiconductor channel can be removed to expose the top surfaces of the first semiconductor channel and the second semiconductor channel, so as to facilitate the subsequent step of forming a bit line and an electrical contact layer, forming a first metal contact layer on the end surface of the second doped region away from the semiconductor substrate, and forming a second metal contact layer on the end surface of the fourth doped region away from the semiconductor substrate.

[0116] refer to Figure 8 A metal layer 139 is formed on the surfaces of the initial first semiconductor well layer 170 and the initial second semiconductor well layer 180 .

[0117] The metal layer 139 provides metal elements for the subsequent formation of the bit line 101. The metal layer 139 is located on the surface of the initial first semiconductor well layer 170 except for the area directly below the first semiconductor channel 102, on the surface of the initial second semiconductor well layer 180 except for the area directly below the second semiconductor channel 112, and on the surface of the barrier layer 129. The material of the metal layer 139 includes at least one of cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum.

[0118] In other embodiments, when the mask layer on the top surface of the first semiconductor channel and the second semiconductor channel is removed, the metal layer contacts the exposed end surface of the second doping region c and the exposed end surface of the fourth doping region f, then in the subsequent step of forming a bit line and an electrical contact layer, a first metal contact layer can be simultaneously formed on the end surface of the second doping region away from the semiconductor substrate, and a second metal contact layer can be formed on the end surface of the fourth doping region away from the semiconductor substrate.

[0119] Combined with reference Figure 8 and Figure 9 , an annealing process is performed to convert a portion of the thickness of the initial first semiconductor well layer 170 into the bit line 101 and convert a portion of the thickness of the initial second semiconductor well layer 180 into the electrical contact layer 111.

[0120] In one embodiment, during the annealing process, the metal layer 139 reacts with a portion of the thickness of the initial first semiconductor well layer 170 and a portion of the thickness of the initial second semiconductor well layer 180, thereby converting a portion of the thickness of the initial first semiconductor well layer 170 into a bit line 101 and a portion of the thickness of the initial second semiconductor well layer 180 into an electrical contact layer 111. The remaining initial first semiconductor well layer 170 serves as the first semiconductor well layer 120, and the remaining initial second semiconductor well layer 180 serves as the second semiconductor well layer 130. In another embodiment, the entire thickness of the initial first semiconductor well layer is converted into a bit line, and the entire thickness of the initial second semiconductor well layer is converted into an electrical contact layer.

[0121] Furthermore, the initial first semiconductor well layer 170 directly below the first semiconductor channel 102 can react with the metal layer 139, and the initial second semiconductor well layer 180 directly below the second semiconductor channel 112 can also react with the metal layer 139, so that the material of the bit line 101 directly below the first semiconductor channel 102 is also a metal-semiconductor compound, and the material of the electrical contact layer 111 directly below the second semiconductor channel 112 is also a metal-semiconductor compound. It is understood that in other embodiments, the material of the bit line directly below the first semiconductor channel can also be consistent with the material of the initial first semiconductor well layer, and the material of the electrical contact layer directly below the second semiconductor channel can also be consistent with the material of the initial second semiconductor well layer.

[0122] Specifically, a rapid thermal annealing (RTA) process is employed for annealing. The process parameters for the RTA include: annealing the semiconductor structure in an N2 atmosphere at a temperature of 300°C to 500°C. The moderate annealing temperature facilitates sufficient diffusion of metal elements in the metal layer 139 into the initial first semiconductor well layer 170 and the initial second semiconductor well layer 180, thereby forming the bit line 101 and the electrical contact layer 111, both of which have relatively low resistivity. Furthermore, the moderate annealing temperature facilitates preventing diffusion of metal elements in the metal layer 139 into the first channel region b and the second channel region e.

[0123] In addition, performing the annealing process in an N 2 atmosphere is beneficial to preventing the metal layer 139 , the initial first semiconductor well layer 170 , and the initial second semiconductor well layer 180 from being oxidized.

[0124] After forming the bit line 101 and the electrical contact layer 111, the barrier layer 129 and the remaining metal layer 139 are removed. Rapid thermal annealing (RTA) is again performed. The RTA process parameters include annealing the semiconductor structure in an N2 atmosphere at a temperature of 500°C to 800°C. This facilitates sufficient reaction of the metal elements with the initial first semiconductor well layer 170 and the initial second semiconductor well layer 180, ensuring a low resistivity for the formed bit line 101 and the electrical contact layer 111.

[0125] In other embodiments, after forming a bit line and an electrical contact layer on a semiconductor substrate, a first semiconductor channel can be formed on a surface of the bit line away from the semiconductor substrate, and a second semiconductor channel can be formed on a surface of the electrical contact layer away from the semiconductor substrate, wherein the materials of the bit line and the electrical contact layer can both be metal materials.

[0126] refer to Figure 9 , forming a first dielectric layer 116 , the first dielectric layer 116 is located on a surface of the semiconductor substrate 110 away from the bit line 101 and the electrical contact layer 111 .

[0127] Specifically, the first dielectric layer 116 is located on the surface of the isolation structure 140 and the first doped region a (refer to Figure 2 ) sidewall surface and the third doped region d (reference Figure 3 ) sidewall surfaces are used to isolate the bit line 101 from the subsequently formed word line, and to isolate the electrical contact layer 111 from the subsequently formed gate. The first dielectric layer 116 is a full-surface film structure and is used to prevent electrical interference between the bit line 101 and the subsequently formed word line, and between the electrical contact layer 111 and the subsequently formed gate.

[0128] The step of forming the first dielectric layer 116 includes: forming an initial first dielectric layer on the surface of the bit line 101 and the electrical contact layer 111 away from the semiconductor substrate 110; planarizing and etching back the initial first dielectric layer to a predetermined thickness to form the first dielectric layer 116.

[0129] Continue to refer Figure 9 , forming an initial gate dielectric layer 163, the initial gate dielectric layer 163 covers the surface of the remaining first semiconductor channel 102 and the remaining second semiconductor channel 112, and is also located on the surface of the mask layer 119, the initial gate dielectric layer 163 prepares for the subsequent formation of the first gate dielectric layer and the second gate dielectric layer.

[0130] Subsequent steps include: forming word lines and gates, wherein the word lines are arranged around the first channel region and the gates are arranged around the second channel region. Forming the word lines and gates includes the following steps:

[0131] refer to Figure 10An initial gate conductive layer 173 is formed on the sidewall surfaces of the initial gate dielectric layer 163 corresponding to the first channel region b and the second channel region e, and the initial gate conductive layer 173 is a full-surface film structure.

[0132] Specifically, the method of forming the initial gate conductive layer 173 includes chemical vapor deposition, physical vapor deposition, atomic layer deposition, or metal organic compound chemical vapor deposition.

[0133] Combined with reference Figure 10 and Figure 11 , patterning the initial gate conductive layer 173 to form a first gate conductive layer 133 and a second gate conductive layer 153 spaced apart from each other.

[0134] It should be noted that the first gate conductive layers 133 of different first semiconductor channels 102 on the same bit line 101 can be connected to different potentials, thereby facilitating diversified control of the first semiconductor channels 102 . Figure 11 In the example, a second gate conductive layer 153 is shown, which surrounds the third semiconductor channel 122 of the NMOS region (refer to Figure 1 ) and the fourth semiconductor channel 142 of the PMOS region adjacent to the NMOS region (reference Figure 1 ), in other examples, one second gate conductive layer may surround only the third semiconductor channel of the NMOS region, and another second gate conductive layer may surround only the fourth semiconductor channel of the PMOS region.

[0135] Continue to refer Figure 11 , forming a second dielectric layer 126 , the second dielectric layer 126 is located in the gap between the adjacent first gate conductive layers 133 and also in the gap between the adjacent second gate conductive layers 153 .

[0136] The second dielectric layer 126 is used to prevent electrical interference between adjacent first gate conductive layers 133 and adjacent second gate conductive layers 153. The second dielectric layer 126 is also located on the surface of the first gate conductive layer 133 and the second gate conductive layer 153 away from the semiconductor substrate 110, and is used to support other conductive structures subsequently formed on the surface of the second dielectric layer 126 away from the semiconductor substrate 110, and to achieve insulation between the first gate conductive layer 133 and the second gate conductive layer 153 and other conductive structures.

[0137] Furthermore, after forming the second dielectric layer 126, the second dielectric layer 126 and the initial gate dielectric layer 163 are planarized until the mask layer 119 is exposed, and the remaining initial gate dielectric layer 163 in the memory area II serves as the first gate dielectric layer 123, and the remaining initial gate dielectric layer 163 in the logic device area I serves as the second gate dielectric layer 143.

[0138] The first gate dielectric layer 123 and the first gate conductive layer 133 together constitute the word line 103 , and the second gate dielectric layer 143 and the second gate conductive layer 153 together constitute the gate 113 .

[0139] In this embodiment, the first dielectric layer 116 and the second dielectric layer 126 together constitute the dielectric layer 106, and the first dielectric layer 116 and the second dielectric layer 126 are made of the same material. This helps reduce the types of materials required for the manufacturing process of the semiconductor structure and reduces the manufacturing cost and complexity of the semiconductor structure.

[0140] Combined with reference Figure 11 and Figure 12 , remove the mask layer 119 so that the second dielectric layer 126 exposes the second doped region c (refer to Figure 2 ) and the fourth doping region f (reference Figure 3 ) is away from the end surface of the semiconductor substrate 110.

[0141] Furthermore, the second doping region c is away from the semiconductor substrate 100 (refer to Figure 1 ) and the end surface of the fourth doped region f away from the semiconductor substrate 100 are metallized, and a partial thickness of the second doped region c is converted into a first metal contact layer 152, and a partial thickness of the fourth doped region f is converted into a second metal contact layer 162, and the materials of the first metal contact layer 152 and the second metal contact layer 162 are both metal semiconductor compounds.

[0142] refer to Figure 13 A first interlayer dielectric layer 117a is formed on a surface jointly formed by the top surface of the first metal contact layer 152, the top surface of the second metal contact layer 162, and the top surface of the second dielectric layer 126; the first interlayer dielectric layer 117a is etched to form a plurality of first grooves, and the first grooves are used to form the first conductive structure 114 and the second conductive structure 115.

[0143] In this embodiment, the first groove has a first opening and a second opening. On a plane perpendicular to the surface of the semiconductor substrate 110, the cross-sectional shape of the first opening is an inverted trapezoid that is wide at the top and narrow at the bottom, and the orthographic projection of the second opening on the semiconductor substrate 110 covers the orthographic projection of the second opening on the surface of the semiconductor substrate 110.

[0144] The first groove is filled with conductive material, the first conductive column 154 in the first conductive structure 114 or the second conductive column 125 in the second conductive structure 115 is formed in the first opening, and the first conductive layer 164 in the first conductive structure 114 or the second conductive layer 135 in the second conductive structure 115 is formed in the second opening.

[0145] It should be noted that Figure 13 Example: Memory Area II (reference Figure 1) of the single first opening to expose a second doped region c, the logic device region I (reference Figure 1 ) can expose one or two fourth doped regions f. In this embodiment, the number of second doped regions c exposed by a single first opening in the memory region II and the number of fourth doped regions f exposed by a single first opening in the logic device region I can be reasonably set based on actual electrical requirements.

[0146] Furthermore, a first etch stop layer 127 a is formed on a surface consisting of the top surface of the first conductive structure 114 , the top surface of the second conductive structure 115 , and the top surface of the first interlayer dielectric layer 117 a .

[0147] refer to Figure 14 A second interlayer dielectric layer 117 b is formed on the top surface of the first etch stop layer 127 a ; the second interlayer dielectric layer 117 b is etched to form a second groove, which is used to form the free layer 108 , the tunneling layer 118 and the fixed layer 128 .

[0148] Specifically, the second groove exposes the top surface of the first conductive structure 114 , and the free layer 108 , the tunneling layer 118 and the fixed layer 128 are sequentially stacked in the second groove.

[0149] refer to Figure 15 , the second interlayer dielectric layer 117b is etched again to form multiple third grooves, some of which have third openings and fourth openings. The morphological characteristics of the third openings and the fourth openings can refer to the aforementioned first openings and second openings, and will not be repeated here. Some of the third grooves only have fourth openings, that is, these third grooves will not expose the second conductive structure 115.

[0150] The third groove is filled with a conductive material, a third conductive pillar 165 of the third conductive structure 145 is formed in the third opening, and a third conductive layer 155 of the third conductive structure 145 is formed in the fourth opening.

[0151] Furthermore, a second etch stop layer 127 b is formed on a surface consisting of the top surface of the second interlayer dielectric layer 117 b , the top surface of the fixed layer 128 , and the top surface of the third conductive layer 155 .

[0152] refer to Figure 16 , a third interlayer dielectric layer 117c is formed on the top surface of the second etch barrier layer 127b; the third interlayer dielectric layer 117c is etched to form a plurality of fourth grooves, some of which have fifth and sixth openings. The morphological features of the fifth and sixth openings can refer to the aforementioned first and second openings and are not described in detail here. Some of the fourth grooves only have the sixth opening, that is, these fourth grooves will not expose the third conductive layer 155.

[0153] The fourth groove is filled with conductive material, another third conductive pillar 165 of the third conductive structure 145 is formed in the fifth opening, and another third conductive layer 155 of the third conductive structure 145 is formed in the sixth opening.

[0154] It should be noted that Figure 16 Taking the third conductive structure 145 as an example, which includes two third conductive layers 155 and two third conductive pillars 165, this embodiment can reasonably set the number of third conductive layers 155 and third conductive pillars 165 included in the third conductive structure 145 based on actual electrical requirements. The second conductive structure 115 and the third conductive structure 145 together constitute the electrical connection structure 105.

[0155] Furthermore, a third etch stop layer 127 c is formed on a surface formed by the top surface of the third interlayer dielectric layer 117 c and the top surface of the third conductive layer 155 .

[0156] Combined with reference Figure 16 and Figure 17 , the second interlayer dielectric layer 117 b , the second etch stop layer 127 b , the third interlayer dielectric layer 117 c and the third etch stop layer 127 c are etched to form a fifth groove, where the fifth groove exposes the first conductive structure 114 .

[0157] Furthermore, a lower electrode layer 124 is formed, and the lower electrode layer 124 is located at the bottom and sidewalls of the fifth groove.

[0158] Specifically, when forming the lower electrode layer 124, part of the lower electrode layer 124 will be formed on the surface of the third etch stop layer 127c away from the semiconductor substrate 110, and the lower electrode layer 124 located on the third etch stop layer 127c away from the surface of the semiconductor substrate 110 is removed by planarization treatment or etching process.

[0159] A capacitor dielectric layer 134 is formed to cover the surface of the lower electrode layer 124 and a portion of the third etch stop layer 127 c away from the surface of the semiconductor substrate 110 . The capacitor dielectric layer 134 in the fifth groove forms a through hole.

[0160] An upper electrode layer 144 is formed. The upper electrode layer 144 is located on the surface of the capacitor dielectric layer 134 and fills the through hole.

[0161] In this embodiment, the first conductive structure 114 , the lower electrode layer 124 , the capacitor dielectric layer 134 and the upper electrode layer 144 together constitute the capacitor structure 104 .

[0162] In other embodiments, there is a gap between the upper electrode layers located in adjacent through holes, so that adjacent upper electrode layers can be connected to different potentials, which is conducive to achieving diversified control of adjacent capacitor structures. Alternatively, the capacitor structure can also be a planar capacitor, which is stacked in sequence in the fifth groove to form a lower electrode layer, a capacitor dielectric layer and an upper electrode layer.

[0163] In this embodiment, the semiconductor substrate 100 (reference Figure 1 ) surface direction, the depth of the lower electrode layer 124 is the same as the depth of the third conductive structure 145. Figure 17 The example in which the depth of the lower electrode layer 124 penetrates two third conductive layers 155 is taken as an example. It should be noted that the number of third conductive layers 155 that the depth of the lower electrode layer 124 penetrates can be reasonably set according to actual electrical requirements.

[0164] Combined with reference Figure 17 and Figure 1 A fourth interlayer dielectric layer is formed on the surface formed by the top surface of the third etch stop layer 127 c and the top surface of the upper electrode layer 144 ; the fourth interlayer dielectric layer is etched to form a sixth groove; and the sixth groove is filled with a conductive material to form a fourth conductive layer 109 .

[0165] In this embodiment, the insulating layer 107 includes a first interlayer dielectric layer 117a, a first etch stop layer 127a, a second interlayer dielectric layer 117b, a second etch stop layer 127b, a third interlayer dielectric layer 117c, a third etch stop layer 127c and a fourth interlayer dielectric layer.

[0166] In summary, the manufacturing method of the semiconductor structure provided by the embodiment of the present invention is designed to include a semiconductor substrate 100 including a logic device area I and a memory area II. The structure within the memory area II is used to store data, and the structure within the logic device area I is used to calculate data, so that the same semiconductor structure has both a processor and a memory to realize in-memory calculation, so that data input and output and the calculation process can be performed in different areas of the semiconductor structure, which is beneficial to shortening the distance between the processor and the memory, so as to improve the efficiency of data transmission and reduce the power consumption required for data transmission, thereby improving the working efficiency of the semiconductor structure and reducing the working energy consumption of the semiconductor structure.

[0167] Those skilled in the art will appreciate that the above-described embodiments are specific examples of the present invention, and that in actual applications, various changes in form and detail may be made thereto without departing from the spirit and scope of the present invention. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that include: A semiconductor substrate, comprising a logic device area and a memory area; a bit line and an electrical contact layer provided on the same layer as the bit line, wherein the bit line is located on the semiconductor substrate in the memory area, and the electrical contact layer is located on the semiconductor substrate in the logic device area; a first semiconductor channel, the first semiconductor channel being located on a surface of the bit line and including a first doped region, a first channel region, and a second doped region arranged in sequence in a direction along the semiconductor substrate toward the bit line, wherein the first doped region contacts the bit line; a second semiconductor channel, the second semiconductor channel being disposed in the same layer as the first semiconductor channel and being located on a surface of the electrical contact layer, the second semiconductor channel comprising a third doped region, a second channel region, and a fourth doped region arranged in sequence along a direction pointing from the semiconductor substrate to the electrical contact layer, the third doped region being in contact with the electrical contact layer; A word line and a gate arranged in the same layer as the word line, wherein the word line is arranged around the first channel region, and the gate is arranged around the second channel region; a capacitor structure, the capacitor structure being located on a side of the second doping region away from the first channel region, and the capacitor structure being in contact with the second doping region; an electrical connection structure, the electrical connection structure being located on a side of the fourth doping region away from the second channel region, and the electrical connection structure being in contact with the fourth doping region; a dielectric layer, the dielectric layer being located between the bit line and the word line and also being located on a side of the word line away from the semiconductor substrate; The semiconductor substrate comprises: semiconductor substrates; a first semiconductor well layer, disposed on the semiconductor substrate of the memory region, wherein the bit line is located on a surface of the first semiconductor well layer away from the semiconductor substrate; an orthographic projection of the first semiconductor well layer on the semiconductor substrate coincides with an orthographic projection of the bit line on the semiconductor substrate; A second semiconductor well layer is provided on the semiconductor substrate in the logic device region, and the electrical contact layer is located on a surface of the second semiconductor well layer away from the semiconductor substrate.

2. The semiconductor structure according to claim 1, wherein The logic device region includes an NMOS region and a PMOS region; the semiconductor substrate in the logic device region further includes an isolation structure, which is located between adjacent second semiconductor well layers and also between adjacent electrical contact layers.

3. The semiconductor structure according to claim 1, wherein: The bit line and the first semiconductor channel have the same semiconductor element, the resistivity of the bit line is smaller than the resistivity of the first doped region, and the electrical contact layer and the second semiconductor channel have the same semiconductor element, the resistivity of the electrical contact layer is smaller than the resistivity of the third doped region.

4. The semiconductor structure according to claim 3, wherein: The material of the electrical contact layer is the same as that of the bit line.

5. The semiconductor structure according to claim 4, wherein: The material of the bit line includes a metal semiconductor compound.

6. The semiconductor structure according to claim 5, wherein: The semiconductor element includes at least one of silicon, carbon, germanium, arsenic, gallium, and indium; the metal element in the metal semiconductor compound includes at least one of cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum.

7. The semiconductor structure according to claim 5, wherein: The second doped region includes: a first metal contact layer, the first metal contact layer is in contact with the capacitor structure, and the resistivity of the first metal contact layer is smaller than the resistivity of the second doped region outside the first metal contact layer; The fourth doped region includes: a second metal contact layer in the same layer as the first metal contact layer, the second metal contact layer is in contact with the electrical connection structure, and the resistivity in the second metal contact layer is less than the resistivity of the fourth doped region outside the second doped metal contact layer.

8. The semiconductor structure according to claim 1, wherein: The first semiconductor channel constitutes a channel of a junctionless transistor; the second semiconductor channel constitutes a channel of a junctionless transistor.

9. The semiconductor structure according to claim 8, wherein: The doping ions in the first doping region, the first channel region, and the second doping region are of the same type; the doping ions in the third doping region, the second channel region, and the fourth doping region are of the same type.

10. The semiconductor structure according to claim 1, wherein: The word line includes: a first gate dielectric layer, the first gate dielectric layer being disposed around the first channel region and being located on a sidewall surface of the first semiconductor channel where the first channel region is located, and also being located on a sidewall surface of the first semiconductor channel where the second doped region is located; A first gate conductive layer is disposed around the first channel region and is located on a sidewall surface of the first gate dielectric layer corresponding to the first channel region.

11. The semiconductor structure according to claim 10, wherein: The gate includes: a second gate dielectric layer, being in the same layer as the first gate dielectric layer, and being disposed around the second channel region and located on a sidewall surface of the second semiconductor channel where the second channel region is located, and also located on a sidewall surface of the second semiconductor channel where the third doped region is located; The second gate conductive layer is in the same layer as the first gate conductive layer. The second gate conductive layer is disposed around the second channel region and is located on a sidewall surface of the second gate dielectric layer corresponding to the second channel region.

12. The semiconductor structure according to claim 1, wherein The memory area includes a DRAM area, and the capacitor structure of the DRAM area includes: a first conductive structure in contact with the second doped area; a lower electrode layer in contact with the first conductive structure; a capacitor dielectric layer located on a surface of the lower electrode layer; and an upper electrode layer located on a surface of the capacitor dielectric layer. The electrical connection structure includes: a second conductive structure in the same layer as the first conductive structure, the second conductive structure is in contact with the fourth doping region; and a third conductive structure, the third conductive structure is in contact with a side of the second conductive structure away from the fourth doping region.

13. The semiconductor structure according to claim 12, wherein: In a direction perpendicular to the surface of the semiconductor substrate, a depth of the lower electrode layer is the same as a depth of the third conductive structure.

14. The semiconductor structure according to claim 1, wherein: Also includes: An insulating layer is located on the surface of the dielectric layer, and the capacitor structure and the electrical connection structure are located in the insulating layer, and the relative dielectric constant of the material of the insulating layer is smaller than the relative dielectric constant of the material of the dielectric layer.

15. The semiconductor structure according to claim 1, wherein The memory area further includes an NVM area; the semiconductor structure further includes: a free layer, a tunneling layer, and a fixed layer stacked on the second doping area of ​​the NVM area, and the free layer is electrically connected to the second doping area of ​​the NVM area.

16. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a semiconductor substrate, wherein the semiconductor substrate includes a logic device area and a memory area; forming a bit line and an electrical contact layer provided on the same layer as the bit line, wherein the bit line is located on the semiconductor substrate in the memory area, and the electrical contact layer is located on the semiconductor substrate in the logic device area; forming a first semiconductor channel and a second semiconductor channel provided in the same layer as the first semiconductor channel, wherein the first semiconductor channel is located on the surface of the bit line, and in a direction along the semiconductor substrate pointing to the bit line, the first semiconductor channel includes a first doped region, a first channel region, and a second doped region arranged in sequence, and the first doped region contacts the bit line; and the second semiconductor channel is located on the surface of the electrical contact layer, and in a direction along the semiconductor substrate pointing to the electrical contact layer, the second semiconductor channel includes a third doped region, a second channel region, and a fourth doped region arranged in sequence, and the third doped region contacts the electrical contact layer; forming a word line and a gate disposed in the same layer as the word line, wherein the word line is disposed around the first channel region, and the gate is disposed around the second channel region; forming a capacitor structure, wherein the capacitor structure is located on a side of the second doping region away from the first channel region, and the capacitor structure is in contact with the second doping region; forming an electrical connection structure, wherein the electrical connection structure is located on a side of the fourth doping region away from the second channel region, and the electrical connection structure is in contact with the fourth doping region; forming a dielectric layer, wherein the dielectric layer is located between the bit line and the word line and is also located on a side of the word line away from the semiconductor substrate; The process steps of providing the semiconductor substrate and forming the bit line, the electrical contact layer, the first semiconductor channel and the second semiconductor channel include: providing an initial semiconductor substrate; Performing patterning on a portion of the thickness of the initial semiconductor substrate to form the first semiconductor channel and the second semiconductor channel; Performing a metallization process on the remaining partial thickness of the initial semiconductor substrate to convert the partial thickness of the initial semiconductor substrate located below the first semiconductor channel into the bit line, and convert the partial thickness of the initial semiconductor substrate located below the second semiconductor channel into the electrical contact layer, with the remaining initial semiconductor substrate serving as the semiconductor substrate; The initial semiconductor base comprises a semiconductor substrate, an initial first semiconductor well layer and an initial second semiconductor well layer, wherein the initial first semiconductor well layer is located on the semiconductor substrate in the memory area, and the initial second semiconductor well layer is located on the semiconductor substrate in the logic device area; The patterning of the partial thickness of the initial semiconductor substrate includes: patterning the partial thickness of the initial first semiconductor well layer and the initial second semiconductor well layer to form the first semiconductor channel and the second semiconductor channel; The metallization treatment is performed on the remaining partial thickness of the initial semiconductor substrate, comprising: performing the metallization treatment on the remaining partial thickness of the initial first semiconductor well layer and the initial second semiconductor well layer; The remaining initial first semiconductor well layer serves as a first semiconductor well layer, and the remaining initial second semiconductor well layer serves as a second semiconductor well layer. The orthographic projection of the first semiconductor well layer on the semiconductor substrate coincides with the orthographic projection of the bit line on the semiconductor substrate.

17. The manufacturing method according to claim 16, wherein: The process steps of the metallization treatment include: forming a barrier layer, wherein the barrier layer covers sidewall surfaces of the first semiconductor channel and the second semiconductor channel; forming a metal layer on the surfaces of the initial first semiconductor well layer and the initial second semiconductor well layer; Performing an annealing process to convert a portion of the thickness of the initial first semiconductor well layer into the bit line, and convert a portion of the thickness of the initial second semiconductor well layer into the electrical contact layer; After forming the bit line and the electrical contact layer, the barrier layer and the remaining metal layer are removed.

18. The manufacturing method according to claim 16, wherein: The end surface of the second doped region away from the semiconductor substrate and the end surface of the fourth doped region away from the semiconductor substrate are metallized to convert a partial thickness of the second doped region into a first metal contact layer, and a partial thickness of the fourth doped region into a second metal contact layer, and the materials of the first metal contact layer and the second metal contact layer are both metal semiconductor compounds.

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