Sag nanowire growth using ion implantation

Abstract

The present disclosure relates to a nanowire structure including a substrate having a substrate body and an ion implantation region, a patterned mask having openings over the substrate, and a nanowire. Here, the substrate body is formed of an electrically conductive material, and the ion implantation region is electrically insulating from the top surface of the substrate body extending into the substrate body. Surface portions of the substrate body are exposed through the openings of the patterned mask, while the ion implantation region is completely covered by the patterned mask. The nanowire is formed directly over the exposed surface portions of the substrate body and does not contact the ion implantation region. Further, the nanowire is confined within the ion implantation region such that the ion implantation region is configured to provide an electrically conductive barrier for the nanowire in the substrate.

Description

Technical Field

[0001] This disclosure relates to a selective region growth (SAG) nanowire structure and a process for fabricating the SAG nanowire structure, and particularly to an SAG nanowire structure having an ion-implanted substrate and a process for fabricating an ion-implanted SAG nanowire structure. Background Technology

[0002] Nanowires show great promise for applications in quantum computing. Unfortunately, fabricating high-quality nanowires is challenging. Conventional processes for fabricating nanowires include selective region growth (SAG), where nanowires are selectively grown on a substrate. For proper operation, the nanowires must be conductive semiconductors, while the substrates on which they are grown are typically insulating materials. Therefore, nanowires grown on the same substrate can be isolated from each other. However, the lattice constant of the substrate and the lattice constant of the nanowires to be grown via SAG often differ significantly. This lattice mismatch leads to crystal defects in the nanowires during growth, such as dislocations and stacking faults. These crystal defects can penetrate the nanowires and, in turn, degrade the performance of the resulting nanowires.

[0003] Therefore, there is a need for a nanowire structure that reduces crystal defects and a method for manufacturing such a nanowire structure. Summary of the Invention

[0004] This disclosure relates to nanowire structures and processes for fabricating nanowire structures. The disclosed nanowire structure includes a substrate having a substrate body and an ion-implanted region, a patterned mask with openings on the substrate, and nanowires. Here, the substrate body is formed of a conductive material, while the ion-implanted region extending from the top surface of the substrate body into the substrate body is electrically insulating. A surface portion of the top surface of the substrate body is exposed through openings in the patterned mask, and the ion-implanted region is completely covered by the patterned mask. The nanowires are formed directly on the exposed surface portion of the substrate body through openings in the patterned mask and do not contact the ion-implanted region. Furthermore, the nanowires are confined within the ion-implanted region, such that the ion-implanted region is configured to provide a conductive barrier for the nanowires within the substrate.

[0005] In one embodiment of the nanowire structure, the ion implantation region has a closed-loop shape.

[0006] In one embodiment of the nanowire structure, the substrate body has a thickness between 50 μm and 1000 μm, and the ion implantation region has a depth between 2 nm and 50 μm.

[0007] In one embodiment of the nanowire structure, the substrate is formed of one of indium phosphide, gallium antimonide, and gallium arsenide, and the nanowire is formed of one of indium arsenide, indium antimonide, and indium antimonide arsenide.

[0008] According to another embodiment, the nanowire structure further includes a superconducting layer formed on the nanowire.

[0009] According to another embodiment, the alternative nanowire structure includes a substrate having a substrate body and at least one ion-implanted region, a patterned mask having a first opening and a second opening on the substrate, a first nanowire, and a second nanowire. Here, the substrate body is formed of a conductive material, while the at least one ion-implanted region extending from the top surface of the substrate body into the substrate body is electrically insulating. A first surface portion of the top surface of the substrate body is exposed through the first opening of the patterned mask, a second surface portion of the top surface of the substrate body is exposed through the second opening of the patterned mask, and the at least one ion-implanted region is completely covered by the patterned mask. The first nanowire is formed directly on the exposed first surface portion of the substrate body through the first opening of the patterned mask. The second nanowire is formed directly on the exposed second surface portion of the substrate body through the second opening of the patterned mask. The first and second nanowires do not contact the at least one ion-implanted region. A portion of the at least one ion-implanted region is located between the first and second nanowires to interrupt the conductive path within the substrate between the first and second nanowires.

[0010] In one embodiment of the alternative nanowire structure, at least one ion implantation region includes a first ion implantation region and a second ion implantation region. Here, the first nanowire is confined within the first ion implantation region such that the first ion implantation region is configured to provide a conductive barrier for the first nanowire. A second nanowire is confined within the second ion implantation region such that the second ion implantation region is configured to provide a conductive barrier for the second nanowire. A portion of the first ion implantation region and a portion of the second ion implantation region are located between the first nanowire and the second nanowire.

[0011] In one embodiment of the alternative nanowire structure, the first ion implantation region has a closed-loop shape, and the second ion implantation region has a closed-loop shape.

[0012] In one embodiment of the alternative nanowire structure, the first ion implantation region and the second ion implantation region have different shapes.

[0013] In one embodiment of the alternative nanowire structure, the depths of the first ion implantation region and the second ion implantation region are different.

[0014] According to another embodiment, the alternative nanowire structure further includes a first superconducting layer formed on the first nanowire and a second superconducting layer formed on the second nanowire. Here, the first and second superconducting layers are not connected.

[0015] In one embodiment of the alternative nanowire structure, the substrate body has a thickness between 50 μm and 1000 μm. The first ion implantation region has a thickness between 2 nm and 50 μm, and the second ion implantation region has a depth between 2 nm and 50 μm.

[0016] In one embodiment of the alternative nanowire structure, the substrate body has a thickness between 50 μm and 1000 μm, and at least one ion implantation region has a depth between 2 nm and 50 μm.

[0017] In one embodiment of the alternative nanowire structure, the substrate is formed of one of indium phosphide, gallium antimonide, and gallium arsenide, and at least one nanowire is formed of one of indium arsenide, indium antimonide, and indium antimonide arsenide.

[0018] According to an exemplary process for fabricating nanowire structures, a substrate body formed of a conductive material is first provided. Then, an implantation mask with implantation openings is provided over the substrate body. A processed surface portion of the top surface of the substrate body is exposed through the implantation openings of the implantation mask. Next, ion implantation is applied to the substrate body through the implantation openings, such that a portion of the substrate body extending from the exposed processed surface portion into the substrate body is transformed into an ion-implanted region. The ion-implanted region is electrically insulating. After forming the ion-implanted region, the implantation mask is removed. A patterned mask with nanowire openings is provided over the substrate body and the ion-implanted region. A nanowire surface portion of the top surface of the substrate body is exposed through the nanowire openings of the patterned mask, and the ion-implanted region is completely covered by the patterned mask. Finally, nanowires are formed over the exposed nanowire surface portion of the substrate body through the nanowire openings of the patterned mask. Here, the nanowires do not contact the ion-implanted regions. The nanowires are confined within the ion-implanted regions, such that the ion-implanted regions are configured to provide a conductive barrier for the nanowires within the substrate.

[0019] In one embodiment of the exemplary process, ion implantation is performed by injecting oxygen ions into the substrate body through an implantation opening.

[0020] In one embodiment of the exemplary process, the substrate is formed of one of indium phosphide, gallium antimonide, and gallium arsenide, and the nanowires are formed of one of indium arsenide, indium antimonide, and indium antimonide arsenide.

[0021] In one embodiment of the exemplary process, the substrate body has a thickness between 50 μm and 1000 μm, and the ion implantation region has a depth between 2 nm and 50 μm.

[0022] According to another embodiment, an exemplary process further includes providing a superconducting layer on the nanowire.

[0023] According to another embodiment, the exemplary process further includes planarizing the top surface of the substrate body after removing the injection mask and before providing a patterned mask.

[0024] Those skilled in the art will understand the scope of this disclosure and will become aware of its additional aspects upon reading the following detailed description of preferred embodiments in conjunction with the accompanying drawings. Attached Figure Description

[0025] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0026] Figure 1A and 1B An exemplary nanowire structure according to one embodiment of the present disclosure is shown.

[0027] Figure 2 A flowchart is provided illustrating an exemplary method for fabricating nanowire structures according to an embodiment of the present disclosure.

[0028] Figures 3 to 9 The diagram illustrates the relationship between... Figure 2 The manufacturing process steps provided in the document.

[0029] It will be understood that, for the sake of clarity, Figures 1 to 12 are... Figure 9 It may not be drawn to scale. Detailed Implementation

[0030] The following embodiments present the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. By reading the following description in conjunction with the accompanying drawings, those skilled in the art will understand the concepts of this disclosure and recognize the application of these concepts not specifically mentioned herein. It should be understood that these concepts and applications fall within the scope of this disclosure and the appended claims.

[0031] It will be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items.

[0032] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "on" another element, it can be located directly on or directly extended onto the other element, or there may be intermediate elements. Conversely, when an element is referred to as being "directly on" another element or "directly extending onto" another element, there are no intermediate elements. Similarly, it will be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element or extending "on" another element, it can be directly on or directly on another element, or there may be intermediate elements. Conversely, when an element is referred to as being "directly on" another element or extending "on" another element, there are no intermediate elements. It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intermediate elements.

[0033] In this document, relative terms such as “below” or “above” or “up” or “below” or “horizontal” or “vertical” may be used to describe the relationship between one element, layer, or region and another element, layer, or region, as shown in the figure. It will be understood that, in addition to the orientation shown in the figure, these terms and the terms discussed above are intended to cover different orientations of the device.

[0034] The terminology used herein is for describing particular embodiments only and is not intended to limit this disclosure. The singular forms “a,” “an,” and “the” as used herein are also intended to include the plural forms unless the context clearly indicates otherwise. It should be further understood that when the terms “comprising,” “including,” “containing,” and / or “having” are used herein, they specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0035] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms used herein should be interpreted as having the same meaning as they have in the context of this specification and the relevant technical field, and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0036] This disclosure relates to selective region growth (SAG) nanowire structures with ion-implanted substrates and processes for fabricating SAG nanowire structures. Figure 1A and 1BAn exemplary nanowire structure 10 according to one embodiment of the present disclosure is provided. Figure 1A A top view of the nanowire structure 10 is shown. Figure 1B A cross-sectional view of the nanowire structure 10 along the dashed line A-A' is shown. For the purposes of this illustration, the nanowire structure 10 includes a substrate 12 having a first ion implantation region 14 and a second ion implantation region 16, a first nanowire 18, and a second nanowire 20. The first nanowire 18 and the second nanowire 20 may be confined within the first ion implantation region 14 and the second ion implantation region 16, respectively. In different applications, the nanowire structure 10 may include more nanowires, and the substrate 12 may correspondingly include more ion implantation regions.

[0037] Specifically, the substrate 12 includes a substrate body 22, a first ion implantation region 14, and a second ion implantation region 16. Here, the substrate body 22 may be formed of a conductive material, such as indium arsenide (InAs), indium antimonide (InSb), gallium antimonide (GaSb), and indium gallium arsenide (InGa). 0.8 As 0.2 The first ion implantation region 14 and the second ion implantation region 16 are electrically insulating and extend from the top surface of the substrate body 22 into the substrate body 22 to prevent electron transport through the substrate body 22 (more details below). The substrate body 22 may have a thickness between 50 μm and 1000 μm. Each of the first implantation region 14 and the second ion implantation region 16 may have a depth (in the Z direction) between 2 nm and 50 μm, which extends from the top surface of the substrate body 22 into the substrate body 22.

[0038] A patterned mask 24 having a first nanowire opening 26 and a second nanowire opening 28 is located on the substrate 12 (e.g. Figure 1B As shown, rather than Figure 1A (As shown). Therefore, the first nanowire surface portion 22-1N and the second nanowire surface portion 22-2N of the top surface of the substrate body 22 are exposed through the first nanowire opening 26 and the second nanowire opening 28 of the patterned mask 24, respectively. Note that the patterned mask 24 completely covers the first ion implantation region 14 and the second ion implantation region 16; therefore, the first ion implantation region 14 and the second ion implantation region 16 are not exposed through the first nanowire opening 26 or the second nanowire opening 28 of the patterned mask 24. The patterned mask 24 can be formed of a dielectric material such as silicon dioxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), diamond, etc. The patterned mask 24 can have a thickness between 2 nm and 1000 nm.

[0039] Each nanowire in the first nanowire 18 and the second nanowire 20 has a nanometer-scale width (W). N The nanowires 18 / 20 are elongated members with an aspect ratio of at least 10 or at least 20, and are selectively grown on the substrate body 22 via a patterned mask 24. Non-limiting examples of the nanowires 18 / 20 have an average width (W) in the range of 10 to 1000 nm, optionally 50 to 100 nm, or 75 to 125 nm. NA ). The length of the nanowire 18 / 20 (L) N The nanowires can be on the micrometer scale, for example, at least 1 μm or at least 10 μm. Furthermore, the thickness (T) of the nanowires is 18 / 20. N The nanowires 18 and 20 may be between 20 nm and 300 nm. The first nanowire 18 and the second nanowire 20 may be formed of conductive semiconductors, such as indium arsenide (InAs), indium antimonide (InSb), or indium arsenide antimonide (InAsSb).

[0040] The first nanowire 18 resides directly on the first nanowire surface portion 22-1N of the substrate body 22 through the first nanowire opening 26 of the patterned mask 24. Since both the first nanowire 18 and the substrate body 22 are formed of conductive material, the lattice constant of the substrate body 22 and the first nanowire 18 are likely to be relatively close. Therefore, defects such as mismatched dislocations, slip planes, and stacking faults caused by lattice constant mismatch will be expected to be relatively small. Similarly, the second nanowire 20 resides directly on the second nanowire surface portion 22-2N of the substrate body 22 through the second nanowire opening 28 of the patterned mask 24. Since both the second nanowire 20 and the substrate body 22 are formed of conductive material, the lattice constant of the substrate body 22 and the second nanowire 20 are likely to be relatively close, resulting in acceptable mismatched dislocations, slip planes, and stacking faults. If the substrate body 22 is formed of insulating material, a high lattice constant mismatch may occur between the nanowires 18 / 20 and the substrate body 22. Therefore, the first nanowire 18 and / or the second nanowire 20 may not function properly.

[0041] In quantum computing, nanowires are used to carry and transport quantum states generated by electrons in a structure, and these quantum states need to move uniformly and consistently. Therefore, each surface of the nanowire needs to be smooth. Since the first nanowire 18 is formed directly on the first nanowire surface portion 22-1N of the substrate body 22 and the second nanowire 20 is formed directly on the second nanowire surface portion 22-2N of the substrate body 22, the first nanowire surface portion 22-1N and the second nanowire surface portion 22-2N of the substrate body 22 need to be planarized with a vertical roughness of less than 10 Å.

[0042] Note that the first nanowire 18 and the second nanowire 20 are only in contact with the surface portions 22-1N and 22-2N of the first nanowire, respectively, but not with the first ion implantation region 14 or the second ion implantation region 16 (which are completely covered by the patterned mask 24). Therefore, the lattice constant of the first ion implantation region 14 or the second ion implantation region 16 may be significantly different from the lattice constant of the nanowires 18 / 20, and will not cause growth defects in the nanowires 18 / 20.

[0043] Each ion implantation region in the first ion implantation region 14 and the second ion implantation region 16 can form a closed loop in the XY plane (the X, Y, and Z directions are orthogonal to each other). A first nanowire 18 is confined within the first ion implantation region 14, and a second nanowire 20 is confined within the second ion implantation region 16. Therefore, the first ion implantation region 14 and the second ion implantation region 16 interrupt the conductive path between the first nanowire 18 and the second nanowire 20 within the substrate 12. The first nanowire 18 and the second nanowire 20 are electrically isolated from each other. If the first ion implantation region 14 and the second ion implantation region 16 were not present, a conductive path would exist between the first nanowire 18 and the second nanowire 20 through the substrate body 12 (formed from a conductive material). Therefore, the first nanowire 18 and / or the second nanowire 20 might not function properly. The first ion implantation region 14 and the second ion implantation region 16 can have different shapes when the first nanowire 26 and the second nanowire 28 have different shapes and / or lengths. Furthermore, the first ion implantation region 14 and the second ion implantation region 16 can have different depths.

[0044] Furthermore, the nanowire structure 10 may also include a first superconductor 30 and a second superconductor 32. The first superconductor 30 resides on the first nanowire 18 and optionally on a portion of the patterned mask 24, while the second superconductor 32 resides on the second nanowire 20 and optionally on another portion of the patterned mask 24. The first superconductor 30 and the second superconductor 32 may not be connected. Each of the first superconductor 30 and the second superconductor 32 may be formed of aluminum (Al), lead (Pb), indium niobium (NbIn), tin (Sn), or vanadium (V) and has a thickness between 3 nm and 30 nm.

[0045] Figure 2 A flowchart is provided illustrating a method for manufacturing a nanowire structure 10 according to an embodiment of the present disclosure. Figures 3 to 9 The diagram illustrates the relationship between... Figure 2The manufacturing process steps provided herein are described. While the exemplary steps are illustrated as a series, the exemplary steps are not necessarily dependent on the order. The order of some steps may differ from the presented order. Furthermore, the process within the scope of this disclosure may include steps that are more complex than those described. Figures 3 to 9 The steps shown are fewer or more.

[0046] Initially, such as Figure 3 As shown, a substrate body 22 is provided (step 100). The substrate 22 may be formed of a conductive material, such as InAs, InSb, GaSb, and InGa. 0.8 As 0.2 The substrate body 22 can have a thickness between 50 μm and 1000 μm. For example... Figure 4 As shown, an implantation mask 34 having a first implantation opening 36 and a second implantation opening 38 is provided on the substrate body 22 (step 102). Each of the first implantation opening 36 and the second implantation opening 38 may have a closed-loop shape in the XY plane (not shown). The implantation mask 34 may be formed of a polymer such as photoresist or polymethyl methacrylate (PMMA) with a thickness between 100 nm and 5 μm. Providing the implantation mask 34 on the substrate body 22 may include providing an implantation mask layer on the entire top surface of the substrate body 22 and then patterning the implantation mask layer by any suitable process to provide the implantation mask 34 having the first implantation opening 36 and the second implantation opening 38.

[0047] Here, the first implantation opening 36 and the second implantation opening 38 are designed for the following ion implantation process. A first processed surface portion 22-1P of the substrate body 22 is exposed through the first implantation opening 36, and a second processed surface portion 22-2P of the substrate body 22 is exposed through the second implantation opening 38. Each of the exposed first processed surface portion 22-1P and the exposed second processed surface portion 22-2P of the substrate body 22 may have a closed-loop shape in the XY plane (not shown).

[0048] Next, as Figure 5As shown (step 104), ion implantation is applied to the substrate body 22 to provide a first ion implantation region 14 and a second ion implantation region 16 to the substrate 12. In a non-limiting example, the ion implantation process can be implemented by implanting oxygen ions into the substrate body 22. Oxygen implantation into the conductive substrate body 22 will create electron traps, thereby suppressing local conductivity. Due to the implantation mask 34, the ion implantation process is applied to the substrate body 22 only through the first implantation opening 36 and the second implantation opening 38. Therefore, the portion of the substrate body 22 extending from the exposed first processing surface portion 22-1P into the substrate body 22 is transformed into the first ion implantation region 14 as a conductive barrier. Another portion of the substrate body 22 extending from the exposed second processing surface portion 22-2P into the substrate body 22 is transformed into the second ion implantation region 16 as a conductive barrier. Each of the first ion implantation regions 14 and the second ion implantation region 16 may have a closed-loop shape in the XY plane (not shown). Due to different implantation parameters, such as energy, different ion currents, stoichiometry, and / or different annealing parameters, the depth of each ion implantation region can be controlled at 14 / 16 (in the Z direction), for example, between 2 nm and 50 μm.

[0049] Then remove injection mask 34 (step 106), as follows Figure 6 As shown. Optionally, a polishing process may then be performed to clean the substrate 12 and / or planarize the top surface of the substrate 12 (including the top surface of the substrate body 22 and the top surfaces of the ion implantation regions 14 and 16). A patterned mask 24 with a first nanowire opening 26 and a second nanowire opening 28 is provided on the substrate 12 (step 108), as shown. Figure 7 As shown. The patterned mask 24 can be formed of a dielectric material (e.g., SiO2, SiN, Al2O3, diamond, or any material that inhibits appropriate epitaxial growth and maintains selectivity). The patterned mask 24 can have a thickness between 2 nm and 1000 nm. Providing the patterned mask 24 on the substrate 12 can include providing a mask layer on the entire top surface of the substrate 12, and then patterning the mask layer by any suitable process (such as photolithography) to provide a patterned mask 24 with a first nanowire opening 26 and a second nanowire opening 28.

[0050] Here, the patterned mask 24 is designed for subsequent nanowire growth. The first ion implantation region 14 and the second ion implantation region 16 are not the basis required for nanowire growth because their lattice constants may have a significant mismatch with the lattice constants of the subsequently formed nanowires 18 and 20. Therefore, the patterned mask 24 is designed to completely cover the first ion implantation region 14 and the second ion implantation region 16. Thus, subsequent nanowire growth will not occur directly on the first ion implantation region 14 or the second ion implantation region 16. The first nanowire surface portion 22-1N and the second nanowire surface portion 22-2N of the substrate body 22 are exposed through the first nanowire opening 26 and the second nanowire opening 28 of the patterned mask 24, respectively. The first nanowire opening 26 is designed to be confined within the first ion implantation region 14, such that the nanowires grown on the first nanowire surface portion 22-1N through the first nanowire opening 26 are confined within the first ion implantation region 14. The second nanowire opening 28 is designed to be confined within the second ion implantation region 16, such that the nanowires grown on the second nanowire surface portion 22-2N through the second nanowire opening 28 are confined within the second ion implantation region 16.

[0051] After forming the patterned mask 24, the first nanowire 18 and the second nanowire 20 are formed (step 110), as follows. Figure 8 As shown, a first nanowire 18 is grown on the first nanowire surface portion 22-1N of the substrate body 22 through a first nanowire opening 26, while a second nanowire 20 is grown on the second nanowire surface portion 22-2N of the substrate body 22 through a second nanowire opening 28. Since the first nanowire 18, the second nanowire 20, and the substrate body 22 are formed of a conductive material, the lattice constant mismatch between the substrate body 22 and the first nanowire 18, and between the substrate body 22 and the second nanowire 20, is relatively small. Therefore, defects such as misfit dislocations, slip planes, and stacking faults caused by lattice constant mismatch will be expected to be relatively small.

[0052] Furthermore, since the first nanowire opening 26 is confined within the first ion implantation region 14, the first nanowire 18 grown through the first nanowire opening 26 is also confined within the first nanowire implantation region 14. Similarly, the second nanowire 20 is confined within the second ion implantation region 16. Clearly, a portion of the first ion implantation region 14 and a portion of the second ion implantation region 16 lie between the first nanowire 18 and the second nanowire 20 to interrupt the conductive path through the substrate body 22 between the first nanowire 18 and the second nanowire 20. Therefore, the first nanowire 18 and the second nanowire 20 are electrically isolated from each other.

[0053] Finally, a first superconductor 30 and a second superconductor 32 are provided to complete the nanowire structure 10 (step 112), as follows. Figure 9 As shown. A first superconductor 30 is formed on a first nanowire 18 and optionally on a portion of a patterned mask 24. The first superconductor 30 may not cover the entire first nanowire 18. A second superconductor 32 is formed on a second nanowire 20 and optionally on another portion of the patterned mask 24. The second superconductor 32 may not cover the entire second nanowire 20. The first superconductor 30 and the second superconductor 32 may not be connected. In some applications, the first superconductor 30 and the second superconductor 32 may be continuously formed as a continuous film over the entire patterned mask 24, the first nanowire 18, and the second nanowire 20 (not shown).

[0054] Optionally, the continuous film layer can be patterned to separate the first nanowire 18 and the second nanowire 20 (not shown).

[0055] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of this disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the following claims.

Claims

1. A nanowire structure comprising: The substrate includes the substrate body and the ion implantation region, wherein: The substrate body is formed of a conductive material; and The ion implantation region is electrically insulating and extends from the top surface of the substrate body into the substrate body; A patterned mask disposed on the substrate, wherein: The patterned mask includes an opening through which a surface portion of the top surface of the substrate body is exposed; and The patterned mask completely covers the ion implantation region; and Nanowires are formed directly on the exposed surface portion of the substrate body through the openings of the patterned mask, wherein: The nanowires do not contact the ion implantation region; and The nanowires are confined within the ion implantation region, such that the ion implantation region is configured to provide a conductive barrier for the nanowires within the substrate.

2. The nanowire structure according to claim 1, wherein: The substrate body is formed of one of indium arsenide, indium antimonide, gallium antimonide, and indium gallium arsenide; and The nanowires are formed from one of indium arsenide, indium antimonide, and indium arsenide-antimonide.

3. The nanowire structure according to claim 1, wherein: The substrate body has a thickness between 50 μm and 1000 μm; and The ion implantation region has a depth between 2 nm and 50 μm.

4. The nanowire structure according to claim 1 further includes a superconducting layer formed on the nanowire.

5. The nanowire structure according to claim 1, wherein the ion implantation region has a closed-loop shape.

6. A nanowire structure comprising: The substrate includes a substrate body and at least one ion implantation region, wherein: The substrate body is formed of a conductive material; and The at least one ion implantation region is electrically insulating and extends from the top surface of the substrate body into the substrate body; A patterned mask having a first opening and a second opening is disposed on the substrate, wherein: A first surface portion of the top surface of the substrate body is exposed through the first opening of the patterned mask; A second surface portion of the top surface of the substrate body is exposed through the second opening of the patterned mask; and The patterned mask completely covers the at least one ion implantation region; A first nanowire is formed directly on the exposed first surface portion of the substrate body through the first opening of the patterned mask; and The second nanowire is formed directly on the exposed second surface portion of the substrate body through the second opening of the patterned mask, wherein: The first nanowire and the second nanowire do not contact the at least one ion implantation region; and A portion of the at least one ion-implanted region is located between the first nanowire and the second nanowire to interrupt the conductive path between the first nanowire and the second nanowire within the substrate.

7. The nanowire structure according to claim 6, The substrate body is formed of one of indium arsenide, indium antimonide, gallium antimonide, and indium gallium arsenide; The first nanowire is formed from one of indium arsenide, indium antimonide, and indium arsenide-antimonide; and The second nanowire is formed from one of indium arsenide, indium antimonide, and indium arsenide-antimonide.

8. The nanowire structure according to claim 6, wherein: The substrate body has a thickness between 50 μm and 1000 μm; and The at least one ion implantation region has a depth between 2 nm and 50 μm.

9. The nanowire structure according to claim 6, wherein the at least one ion implantation region comprises a first ion implantation region and a second ion implantation region, wherein: The first nanowire is confined within the first ion implantation region, such that the first ion implantation region is configured to provide a conductive barrier for the first nanowire. The second nanowire is confined within the second ion implantation region, such that the second ion implantation region is configured to provide a conductive barrier for the second nanowire; and A portion of the first ion implantation region and a portion of the second ion implantation region are located between the first nanowire and the second nanowire.

10. The nanowire structure of claim 9 further comprises a first superconducting layer formed on the first nanowire and a second superconducting layer formed on the second nanowire, wherein the first superconducting layer and the second superconducting layer are not connected.

11. The nanowire structure according to claim 9, wherein: The substrate body has a thickness between 50 μm and 1000 μm; The first ion implantation region has a depth between 2 nm and 50 μm; and The second ion implantation region has a depth between 2 nm and 50 μm.

12. The nanowire structure according to claim 9, wherein the first ion implantation region has a closed-loop shape, and the second ion implantation region has a closed-loop shape.

13. The nanowire structure according to claim 9, wherein the depth of the first ion implantation region is different from the depth of the second ion implantation region.

14. The nanowire structure according to claim 9, wherein the first ion implantation region and the second ion implantation region have different shapes.

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