Replacement metal gate integration

Abstract

A method (100) for forming a semiconductor device, the method comprising: providing (110) a substrate having at least one fin (1) or nanowire; forming dummy gates (3, 4); providing (120) spacers (5) on the at least one fin (1) or nanowire and the dummy gates (3, 4); performing (130) a first RMG module, wherein a high-k material (7) is disposed on the at least one fin (1) or nanowire between the spacers (5); one or more annealing steps; providing (132) a sacrificial plug (9) between the spacers (5); epitaxially growing (140) a source (11, 13) and a drain (11, 13) in the at least one fin (1) or nanowire; removing (134) the sacrificial plug (9); performing (136) a second RMG module, wherein a WFM (14) is deposited between at least some of the spacers such that the WFM covers the high-k material of the at least one fin or nanowire.

Description

Technical Field

[0001] This invention relates to the field of methods for forming semiconductor devices. More specifically, it relates to integrating alternative metal gate modules during the formation of semiconductor devices. Background Technology

[0002] Different techniques have been employed to fabricate MOSFET transistors. In gate-first integration, a high-k material and a metal gate are deposited first. Alternatives to the metal gate (RMG) first integration are being investigated to achieve ultra-steep junctions and improve device performance (e.g., for FinFETs / nanofashelves / forksheets). The advantage of implementing RMG first is that it avoids high-temperature steps following epitaxial growth (e.g., reliability annealing at 850°C to 900°C).

[0003] However, in this process, the gate stack undergoes source / drain doping activation annealing. This source / drain activation annealing is performed at temperatures above 550°C, which is detrimental to the metal work function.

[0004] Therefore, in some existing techniques, the RMG module is implemented last. However, in this case, the annealing step is performed after the gate stack is deposited. This is called reliability annealing, which should preferably not be performed after epitaxial growth.

[0005] Given this predicament in terms of thermal budget levels, an improved RMG integration solution is needed. Summary of the Invention

[0006] One object of embodiments of the present invention is to provide a preferred method for forming a semiconductor device, wherein the method includes an alternative metal gate module.

[0007] The above-mentioned objectives are achieved by the method and apparatus described in this invention.

[0008] Embodiments of the present invention relate to a method for forming a semiconductor device. The method includes:

[0009] - Provide a substrate having one or more fins, and form a pseudo gate on one or more fins or on one or more nanowires formed by one or more fins;

[0010] - Provide spacers on one or more fins or nanowires and dummy gates;

[0011] - Implement a first alternative metal gate module, wherein a high-k material is disposed on at least one of one or more fins, or on one or more nanowires formed by one or more fins, between spacers, followed by one or more annealing steps;

[0012] - After implementing the first alternative metal gate module, a sacrificial plug is provided between the spacers;

[0013] - Epitaxially grow source and drain electrodes in one or more fins or one or more nanowires;

[0014] -Remove the sacrificial plug;

[0015] - Implement a second alternative metal gate module, wherein a work function metal is deposited between at least some of the spacers such that the work function metal covers at least some of the high-k material in one or more nanowires or one or more fins.

[0016] In embodiments of the invention, RMG integration is divided into two modules. The first module includes high-temperature steps of the RMG. In embodiments of the invention, this module is performed before epitaxial growth. The second module of the RMG integration is performed after epitaxial growth. The second module includes steps that do not require a high-temperature budget (e.g., temperatures are maintained below 550°C), such as depositing work function metal between spacers. The division of the RMG module into the first and second modules is achieved by providing a sacrificial plug before continuing source and drain epitaxial growth. This sacrificial plug is removed before implementing the second alternative gate module. An advantage of embodiments of the invention is that high-temperature steps (e.g., above 800°C) after epitaxial growth are avoided. This is achieved by implementing the first alternative gate module before epitaxial growth. Furthermore, an advantage of embodiments of the invention is that the (n-type) work function metal of the gate stack is not exposed to temperatures above 550°C. This prevents degradation of the gate stack due to excessive temperature exposure of the thermally unstable (n-type) work function metal. Therefore, an advantage of embodiments of the invention is that a post-epitaxy flow (e.g., epi-last flow) can be implemented without any risk of gate stack degradation. This is achieved by dividing the alternative metal gate module into first and second alternative metal gate modules, wherein materials that may be damaged by high thermal budgets (e.g., above 500°C) are applied only during the step of the second RMG module. Further steps are required for dividing the RMG modules, namely, providing a sacrificial plug before epitaxial growth and removing the sacrificial plug after epitaxial growth and before providing the work function metal.

[0017] FinFETs, horizontal nanowires, vertical FETs (wherein the nanowires are vertically oriented), and complementary FETs (wherein the nFET and pFET lines are stacked on top of each other) can be obtained using methods according to embodiments of the present invention.

[0018] In an embodiment of the present invention, the first alternative metal gate module includes a work function tuned integration scheme.

[0019] In an embodiment of the invention, the first alternative metal gate module includes providing an etch stop layer or a p-type work function metal on a high-k material.

[0020] In an embodiment of the invention, the first alternative metal gate module includes providing TiN on a high-k material.

[0021] TiN can be provided before or after annealing.

[0022] Furthermore, in embodiments of the present invention, the first alternative metal gate module includes pullback of high-k material before providing the sacrificial plug.

[0023] One advantage of this embodiment of the invention is that there is no metal exposure during epitaxial growth. This is achieved by reducing the high-k material before providing a sacrificial plug that protects the high-k material from exposure.

[0024] In embodiments of the invention where an etch stop layer or a p-type work function metal (e.g., TiN) is disposed on a high-k material (e.g., HfO2), the high-k material will also be reduced in this step.

[0025] Furthermore, in an embodiment of the invention, the method includes providing metal contact with the source and drain before removing the sacrificial plug.

[0026] Therefore, the advantage is that if SiN is used as the sacrificial plug material, additional hard mask selectivity can be obtained for self-aligned contact (SAC) ILD0 etching. Alternatively, it can also avoid the need to etch the ILD0 oxide, which will later contact the epitaxial layer, thus preventing epitaxial layer corrosion.

[0027] In an embodiment of the present invention, the deposited work function metal is an n-type work function metal.

[0028] In embodiments of the present invention, the n-type work function metal may include a variety of metals. One advantage of embodiments of the present invention is that a temperature-sensitive metal, such as an aluminum-containing metal (e.g., TiAl or TiAlC), is deposited in the second alternative metal gate module. Other metals (e.g., TiN and TaN) are themselves pWFM. They can be used as a barrier / modulation in NMOS.

[0029] In embodiments of the present invention, the sacrificial plug provided comprises a deposited bilayer plug.

[0030] In embodiments of the present invention, one or more nanowires are horizontal nanowires.

[0031] In an embodiment of the invention, one or more horizontal nanowires are stacked on top of each other.

[0032] In an embodiment of the invention, the stacked horizontal nanowires are nFET and pFET horizontal nanowires, thereby obtaining a complementary FET device.

[0033] In an embodiment of the present invention, one or more nanowires are vertical nanowires.

[0034] Specific and preferred aspects of the invention are set forth in the appended independent and dependent claims. Features in the dependent claims may be appropriately combined with features in the independent and other dependent claims, and are not limited to those expressly stated in the claims.

[0035] These and other aspects of the invention will be disclosed and illustrated with reference to the embodiments described below. Attached Figure Description

[0036] Figures 1 to 27 The diagram shows different stacks obtained when forming a FinFET device using the method according to an embodiment of the present invention.

[0037] Figures 28 to 34 The diagram shows different stacks obtained when forming a CFET device using the method according to an embodiment of the present invention.

[0038] Figure 35 This illustrates a semiconductor device comprising vertical nanowires obtained using a method according to an embodiment of the present invention.

[0039] Figure 36 A flowchart of a method according to an embodiment of the present invention is shown.

[0040] Any reference numerals in the claims should not be construed as limiting the scope of the invention. In different figures, the same reference numerals denote the same or similar elements. Detailed Implementation

[0041] The invention will be described with reference to specific embodiments and certain accompanying drawings, but is not limited thereto, except as defined by the claims. The drawings described are merely illustrative and not restrictive. In the drawings, the dimensions of some elements may be exaggerated and not drawn to scale for illustrative purposes. The dimensions and relative dimensions stated do not correspond to actual reductions in practice.

[0042] Furthermore, in the specification and claims, terms such as "top" and "below" are used for descriptive purposes and not necessarily to describe relative positions. It should be understood that such terms are interchangeable where appropriate, and embodiments of the invention can operate in orientations other than those described or illustrated herein.

[0043] It should be noted that the term "comprising" as used in the claims should not be construed as limiting to the portion listed thereafter, and does not exclude other elements or steps. Therefore, it should be understood as indicating the presence of the stated feature, integration, step, or component, but does not exclude the presence or addition of one or more other features, integrations, steps, or components, or combinations thereof. Thus, the scope of the expression "a device comprising components A and B" should not be limited to the device consisting solely of components A and B. It indicates that, for the present invention, the relevant components of the device are only A and B.

[0044] The phrase "one embodiment" or "an embodiment" as used in the specification refers to a specific feature, structure, or characteristic described in connection with the embodiment, which is included in at least one embodiment of the invention. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing throughout the specification do not necessarily all refer to the same embodiment, but may all refer to the same embodiment. Furthermore, specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments, as will be apparent to those skilled in the art.

[0045] Similarly, it should be understood that in the description of exemplary embodiments of the invention, different features of the invention are sometimes combined into a single embodiment, drawing, or description thereof, in order to simplify the disclosure and aid in understanding one or more different aspects of the invention. However, the methods in this disclosure should not be construed as reflecting an invention, and the claimed invention requires more features than expressly referenced in the claims. Furthermore, as reflected in the appended claims, inventive aspects may include fewer features than all the features of a single embodiment disclosed above. Therefore, the claims following the detailed description are expressly incorporated into this description, and each claim itself represents an independent embodiment of the invention.

[0046] Furthermore, when some embodiments described herein include, but are not included in, other features included in other embodiments, combinations of features from different embodiments are intended to be included within the scope of the invention and to form different embodiments, as will be understood by those skilled in the art. For example, in the following claims, any claimed embodiment may be used in any combination.

[0047] Numerous specific details are set forth in this description. However, it should be understood that embodiments of the invention may be implemented without these specific details. In other instances, well-known methods, structures, and techniques have not been described in detail to avoid obscuring the understanding of this specification.

[0048] In embodiments of the present invention, the term "high-k material" refers to a material with a dielectric constant higher than that of SiO2. The dielectric constant can be, for example, 10 to 50. Known high-k materials used as gate dielectrics are Hf-based materials, such as HfO2, with a k value of approximately 25.

[0049] Embodiments of the present invention relate to a method for forming a semiconductor device.

[0050] The method includes: providing a 110 substrate having one or more fins 1, and forming dummy gates 3, 4 on the one or more fins 1 or on one or more nanowires formed by the one or more fins.

[0051] In addition, the method includes providing spacers 5 on one or more fins 1 or nanowires and dummy gates 3, 4.

[0052] Furthermore, the method includes: implementing a first alternative metal gate module 130, wherein a high-k material 7 is disposed on at least one of one or more fins 1 between spacers 5, or on one or more nanowires formed by one or more fins 1. One or more annealing steps are performed after providing the high-k material and before epitaxial growth of the source and drain electrodes.

[0053] Furthermore, the method includes providing 132 sacrificial plugs 9 between spacers 5 after implementing the first alternative metal gate module.

[0054] In addition, the method includes epitaxially growing source electrodes 140, 13 and drain electrodes 11, 13 in one or more fins 1 or one or more nanowires.

[0055] Furthermore, the method includes: removing the sacrificial plug 9 (134) and implementing a second alternative metal gate module (136), wherein a work function metal 14 is deposited between at least some of the spacers, such that the work function metal covers at least some of the high-k material in one or more fins or nanowires. An exemplary flowchart of the method is shown below. Figure 36 As shown.

[0056] In embodiments of the invention, separate RMG integration is proposed to enable a post-epitaxy (epi-last) growth scheme while avoiding exposure of the work function metal (e.g., nWFM) to high temperatures and thus degradation. In these embodiments, the RMG module is divided into two parts: a first RMG module and a second RMG module. The first RMG module (including all high-temperature steps) is performed before epitaxial growth, while the second RMG module (including work function metal deposition) is performed after epitaxial growth.

[0057] The advantage of this embodiment of the invention is that the partitioning reduces the aspect ratio and complexity of high-k metal gate recesses and metal gate dicing, and provides more options for M0 and epitaxially grown (now sacrificial) gate plugs.

[0058] In embodiments of the present invention, the first RMG module may include providing an etch stop layer or a p-type WFM on a high-k material. For example, the p-type WFM may be TiN.

[0059] In embodiments of the present invention, the material of the sacrificial plug can be selected so that it has no negative impact on the gate stack, is compatible with selective epitaxial growth processes, and can be removed with high selectivity relative to SiO2, spacer materials and TiN.

[0060] In a specific example, this might imply that the sacrificial plug material can withstand high temperatures (e.g., above 800°C) during epitaxial growth. For example, selective etching can be performed using wet etching. This results in high selectivity relative to SiO2 or low-k gate spacers and SiCO during removal. In this specific example, the sacrificial plug material can be selected to be compatible with chemical mechanical polishing and selective stopping, as well as selective stopping on ILD0 SiO2. In certain cases, selection can also be made such that there is no or only limited interaction with TiN or pWFM during deposition or after removal to ensure that Vt does not shift.

[0061] In embodiments of the present invention, the material of the sacrificial plug may be, for example, SiN, SiC, SiCN, or SiOCN.

[0062] In an embodiment of the invention, the 132 sacrificial plug includes a deposited double-layer plug.

[0063] This can be achieved through aSi deposition, followed by chemical mechanical polishing and etch-back, then plug filling and chemical mechanical polishing.

[0064] In embodiments of the invention, the metal is disposed on a high-k material prior to providing the sacrificial plug. An advantage of these embodiments is that the compatibility between the metal and the sacrificial plug can be improved by depositing a double-layer plug. The aSi of the sacrificial plug can, for example, contact the metal, resulting in no degradation during deposition, no degradation after thermal budgeting, and no degradation after etching. By adding aSi, the choice of (top) plug material can be extended to materials that are unstable in contact with the metal and / or cannot be selectively etched relative to the metal.

[0065] In embodiments of the invention, it is not necessary to fill all the spaces between the spacers with a high-k material. Ultimately, at least one layer of high-k material should be formed between the fins or nanowires and the work function metal. In embodiments of the invention, the work function metal should not completely fill the spaces between the spacers. The work function metal should cover at least some of the high-k material in one or more fins or nanowires.

[0066] Typically, in existing gate last flows, a SiO2 / multi-stack body is used for gate etching, followed by the provision of spacers and epitaxial growth, and then an alternative metal gate module is implemented, wherein high-k materials, (multiple) work function metals, and tungsten are provided. Subsequently, a gate plug (e.g., containing SiN) is provided. The advantage of this process is that the gate etching is simple, and the gate stack body experiences only low temperatures. The disadvantage is that the EPi experiences high temperatures from high-k annealing. The advantage is that this can be avoided using the method according to embodiments of the present invention.

[0067] In an exemplary embodiment of the invention, the alternative metal gate module is divided into a first module and a second module. For example, a SiO2 / multi-stack body is used for gate etching, followed by the removal of the dummy gate, and then the first alternative metal gate module is implemented. In this module, a high-k material may be disposed on at least one or more fins, or on one or more nanowires formed by one or more fins. The high-k material is disposed between spacers.

[0068] TiN can then be deposited. This can be done before or after the annealing step. Following this step can be a reduction step, in which the high-k material and possibly any remaining TiN are partially removed so that they are not exposed during epitaxial growth. A sacrificial plug is then provided, and epitaxial growth can then begin, with a metal plug provided. After removing the sacrificial plug, a second alternative metal gate module can be executed. Through this module, (multiple) WFMs can be deposited between the spacers. Tungsten filler can then be applied between the spacers. A gate plug (e.g., for contacts) can then be provided. An advantage of this proposed implementation is that the gate etching is simple. Furthermore, it is advantageous that the high-k material and TiN can be exposed to high temperatures, while the epitaxial growth (epi) and (multiple) WFMs (e.g., nWFMs) are not exposed to high temperatures.

[0069] In the following paragraphs, different stacks obtained using exemplary methods according to embodiments of the present invention are discussed. These stacks of FinFET devices are shown in... Figures 1 to 27 Furthermore, these stacks of CFET devices are shown in Figures 28 to 34Different stacks illustrate detailed implementation steps of the exemplary method of the present invention. Not all method steps in these examples are strictly necessary. The stacks are schematically drawn. First, a substrate is provided having one or more fins 1, and dummy gates 3, 4 are provided on the one or more fins 1. Figure 1 Different cross sections are shown: E-E' between fins, G-G' orthogonal to the fin at the dummy gate, and A-A' orthogonal to the fin and far from the dummy gate. The attached figure shows fin 1, STI oxide 2, polycrystalline Si or amorphous Si 3 for the dummy gate, and the gate hard mask 4 (SiO2 / Si3N4) for the dummy gate.

[0070] Figure 2 A schematic diagram is shown after 120 spacers are provided by gate spacer deposition. The material of the gate spacer 5 can be a low-k material (e.g., SiCO, Si3N4, or both). The dummy oxide on the fin after fin exposure is not shown in these figures.

[0071] Figure 3 The stack containing ILDO oxide 6 is shown after interlayer dielectric (ILD) oxide deposition.

[0072] After chemical mechanical polishing (CMP), the following was obtained Figure 4 Stacked bodies in the middle.

[0073] After opening the gate hard mask 5 and removing the polysilicon Si 3, the following was obtained: Figure 5 Stacked bodies in the middle.

[0074] Next, the first alternative metal gate module 130 is executed. In this module, a high-k material 7 is disposed on the stack. This may be followed by the deposition of pWFM 8. The high-k material 7 can be provided by atomic layer deposition (ALD). For example, HfO2 can be deposited. pWFM 8 can also be provided by ALD. For example, TiN can be deposited. In the presence of pseudo-oxides, they should be removed before depositing the high-k material. These pseudo-oxides are not depicted in the figure.

[0075] In embodiments of the invention, implementing the first alternative metal gate module may include a SoC coating (spin-coated on carbon) and etch-back following the provision of a high-k material (and possibly pWFM). Three layers of 10, SoG (spin-coated on glass) / SoC (spin-coated on carbon), or BARC (bottom anti-reflective coating) may be applied, followed by etch-back. The results are shown in... Figure 8 This allows for the reduction of high-k material 7 (and possibly pWFM 8) in the next step. The results are shown in... Figure 8 middle.

[0076] After implementation, layer 10 (e.g., SoC stripe) is removed. The results are shown in... Figure 9 middle.

[0077] In this embodiment of the invention, after implementing the first alternative metal gate module, a sacrificial plug 9 is provided between the spacers 5. The material of this sacrificial plug can be, for example, Si3N4. The results are shown in... Figure 10 middle.

[0078] After providing 132 sacrificial plugs 9, 140 source and drain electrodes are epitaxially grown in one or more fins 1 or one or more nanowires. Therefore, in Figure 11 In the example, ILD oxide 6 is first removed, followed by nMOS active SoG / SoC or BARC patterning, to obtain Figure 12 Layer 10 in the middle.

[0079] Figure 13 The exemplary stack is obtained after nMOS spacer etching / fin recessing. This step can be followed by a SoC or BARC strip, such as... Figure 14 As shown. Next, the source and drain of the nMOS transistor 11 (Si:P) can be epitaxially grown. The resulting stack is schematically shown. Figure 15 This can then be followed by depositing Si3N4 CESL 12 (contact etch stop layer) on the source and drain 11 of the nMOS.

[0080] Next, the source and drain of the pMOS can be provided. Therefore, active SoG / SoC or BARC patterning of the pMOS can be applied first (see, Figure 17 Layer 10 in the middle). This step can be followed by pMOS spacer etching / fin recess (see layer 10 in the middle). Figure 18 ) and SoC or BARC stripes (see Figure 19 Next, the drain and source of the pMOS are formed by SiGe epitaxial growth. The resulting stack is shown in... Figure 20 In the middle. The drain and source can also be seen in the left E-E' cross-section because the E-E' plane is offset (see the A-A' cross-section, which indicates the position of the E-E' plane). This step can be followed by a Si3N4 CESL deposition step, such as... Figure 21 As shown, CESL is set on the device.

[0081] For example, this step can be followed by an ILD oxide deposition step and a CMP step (see [link]). Figure 22 It shows ILD0 oxide material 6). Next, 134 sacrificial plug 9 was removed.

[0082] Next, a second alternative metal gate module is implemented, wherein work function metal 14 is deposited between at least some of the spacers, such that the work function metal covers at least some of the high-k material in one or more nanowires or one or more fins. In this example, this is achieved by first providing nMOS RMG SoG / SoC or BARC patterning (see, Figure 24 Layer 10 in the middle is used for this purpose. Then, the pWFM is removed. This can be done by etching with a mixture of hydrochloric acid and hydrogen peroxide (HPM) or by etching with a mixture of ammonium hydrogen peroxide (APM). The results are shown in... Figure 25 In this exemplary embodiment of the invention, after completion, the SoC or BARC stripe 10 is removed. The result is shown in... Figure 26 Next, WFM 14 is deposited between the spacers. In this example, the work function metal is nWFM. It includes aluminum-containing metals and may additionally contain other metals such as TiN or TaN, which are pWFM but can be used as barriers / modulations in NMOS.

[0083] In embodiments of the invention, one or more vertical nanowires can be formed from one or more fins. Moreover, in these embodiments, the same strategy can be employed, wherein a first alternative gate module is first performed to provide a high-k material, and possibly also a pWFM. Next, a sacrificial plug is provided to protect the high-k material and, possibly, the pWFM, during epitaxial growth of the source and drain in one or more vertical nanowires. After epitaxial growth of the nMOS and pMOS, the sacrificial plug can be removed, and a second alternative metal gate module can be performed. In this second RMG module, a work function metal is deposited. An example schematic of the cross-section of this semiconductor device is shown in [illustration]. Figure 35 The figure shows a silicon substrate with vertical nanowires, nMOS epitaxial growth 11, pMOS epitaxial growth 13, a first dielectric D1 (e.g., ILD oxide 6), a second dielectric D2, an STI layer, a high-k material 7 (HFO2 in this example), a work function metal 14, and a tungsten contact 15 at the gate. A second electrolyte is present on top of the tungsten contact. In this example, flexibility is maintained by using two different dielectric materials to separate the epitaxial growth region and the metal contact region.

[0084] In embodiments of the invention, one or more horizontal nanowires can be formed from fins. These nanowires can be stacked on top of each other. The stacked horizontal nanowires can be nFET and pFET horizontal nanowires, thereby obtaining complementary FET devices.

[0085] Figure 28The diagram shows a CFET FinFET version with vertical nanosheets and a CFET nanosheet version with horizontal nanosheets, showing the gate after removing polycrystalline Si (e.g.) Figure 5 (middle). The attached figure also shows SiGe epitaxial layer 16. The right figure shows the active portion of the FinFET version and the nanosheet version.

[0086] Figure 29 The results after the nanowires were released are shown.

[0087] Figure 30 The results are shown after deposition of high-k material 7 and possibly pWFM deposition 8.

[0088] Figure 31 The results are shown after deposition of sacrificial plug 9 and CMP.

[0089] Figure 32 The results are shown after epitaxial growth of the source and drain electrodes, and after providing the contacts. This can be achieved by epitaxial growth (for pMOS), followed by providing the contacts, then epitaxial growth (for nMOS), and then providing the contacts again. Figure 32 In this example, sacrificial filler material 9, nMOS epitaxial growth 11, pMOS epitaxial growth 13, nWFM 14, and tungsten contact 15 are shown.

[0090] Next, a second replacement gate module is applied. Figure 33 The results are shown after removing pWFM and after providing a three-layer 10 with SoG / SoC or BARC. Figure 34 The results are shown after providing tungsten contacts 15 and nWFM14 at the gate. Figure 33 The figure also shows the sacrificial filler material 9, nMOS epitaxial growth 11, pMOS epitaxial growth 13, nWFM 14, and tungsten contact 15. The figure also shows a vertical isolation portion 17. This vertical isolation portion may contain Si3N4, SiCO, or SiO2.

[0091] In embodiments of the present invention, the epitaxial growth of pMOS can be performed before the epitaxial growth of nMOS, and vice versa.

[0092] In embodiments of the present invention, the first alternative metal gate module 130 may include a workfunction tuning integration scheme. The workfunction tuning integration scheme provides a way to integrate one or more gate metals and / or gate stacks for the purpose of tuning the effective work function for one or more types of devices based on a threshold voltage target. Workfunction tuning may, for example, be based on a high-temperature diffusion step.

Claims

1. A method (100) for forming a semiconductor device, the method comprising: - Provide a substrate (110) having one or more fins (1) thereon, and form a pseudo gate (3, 4) on one or more fins (1) or on one or more nanowires formed by one or more fins. - Provide (120) spacers (5) on one or more fins (1) or nanowires and dummy gates (3, 4); - After providing spacers, implement (130) a first alternative metal gate module, wherein a high-k material (7) is disposed on at least one of one or more fins (1) between spacers (5) or on one or more nanowires formed by one or more fins (1), followed by one or more annealing steps; - After the first alternative metal gate module is implemented, a sacrificial plug (9) (132) is provided between the spacers (5); - Epitaxially grow (140) source (11, 13) and drain (11, 13) in one or more fins (1) or one or more nanowires. - Remove (134) sacrificial plug (9); - Implement (136) a second alternative metal gate module, wherein work function metal (14) is deposited between at least some of the spacers such that the work function metal covers at least some of the high-k material in one or more nanowires or one or more fins.

2. The method (100) as described in claim 1, wherein, The first alternative metal gate module (130) also includes a work function tuning integration scheme.

3. The method (100) as described in claim 1, wherein, The first alternative metal gate module (130) includes an etch stop layer or a p-type work function (8) metal provided on a high-k material (7).

4. The method (100) as described in claim 1, wherein, The first alternative metal gate module (130) includes TiN (8) provided on a high-k material (7).

5. The method (100) as claimed in claim 1, wherein, The first alternative metal gate module (130) further includes reducing the high-k material (7) before providing the sacrificial plug.

6. The method (100) as claimed in claim 1, wherein, The method further includes contacting the metal with the source (11, 13) and drain (11, 13) before removing the sacrificial plug.

7. The method (100) as claimed in claim 1, wherein, The deposited work function metal (14) is an n-type work function metal.

8. The method (100) as claimed in claim 1, wherein, The (132) sacrificial plugs provided include deposited double-layer plugs.

9. The method (100) as claimed in claim 1, wherein, One or more nanowires are horizontal nanowires.

10. The method (100) of claim 9, wherein, One or more horizontal nanowires are stacked on top of each other.

11. The method (100) of claim 10, wherein, Stacked horizontal nanowires are nFET and pFET horizontal nanowires, thereby obtaining complementary FET devices.

12. The method (100) according to any one of claims 1-8, wherein, One or more nanowires are vertical nanowires.

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