Light emitting diode chip and preparation method thereof

Abstract

The invention relates to the technical field of semiconductor devices, in particular to a light-emitting diode chip which comprises a substrate, and an N-type semiconductor layer, a multi-quantum well layer, a P-type semiconductor layer and a composite passivation layer are sequentially stacked on the substrate. The composite passivation layer comprises a modified h-BN sub layer and an Al2O3 sub layer which are stacked in sequence, and the Al2O3 sub layer is arranged on the modified h-BN sub layer; the modified h-BN sub-layer is subjected to N2O plasma treatment, and the thickness of the modified h-BN sub-layer is 1nm-5nm; the thickness of the Al2O3 sub layer ranges from 10 nm to 100 nm. The chip provided by the invention has the advantages of good water vapor permeation prevention performance, high light extraction rate, low defect density and long device service life.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a light-emitting diode chip and its fabrication method. Background Technology

[0002] Third-generation semiconductors have broad application prospects and possess excellent physical and chemical properties such as high melting point, chemical inertness, high thermal conductivity, high hardness, and high breakdown electric field. They are used to manufacture various LED light-emitting devices, which have advantages such as high stability, long lifespan, and energy saving. However, the existing technology uses a SiO2 passivation layer, which is difficult to simultaneously achieve metal ion barrier, moisture barrier, and light transmittance. In high humidity and high current density scenarios, pinhole defects are prone to occur, leading to metal ion migration in the electrodes and short circuits between the positive and negative electrodes. At the same time, moisture penetration accelerates electrode oxidation, which shortens the lifespan of LED devices and fails to meet the needs of automotive, outdoor lighting, and other scenarios. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of the prior art. This invention provides a light-emitting diode chip and its preparation method. The chip obtained has good water vapor permeability, high light output, low defect density and long device life.

[0004] To address the aforementioned issues, this invention proposes a light-emitting diode chip, comprising a substrate on which an N-type semiconductor layer, a multiple quantum well layer, a P-type semiconductor layer, and a composite passivation layer are sequentially stacked. The composite passivation layer comprises a modified h-BN sublayer and an Al2O3 sublayer stacked sequentially, wherein the Al2O3 sublayer is disposed on the modified h-BN sublayer; The modified h-BN sublayer is treated with N2O plasma and has a thickness of 1nm~5nm; The thickness of the Al2O3 sublayer is 10nm~100nm.

[0005] As an improvement to the above technical solution, the modified h-BN sublayer is prepared by the following method: Borane and ammonia are introduced as precursors to form an h-BN sublayer on the P-type semiconductor layer; After cleaning with a cleaning agent, dry under a nitrogen atmosphere; The dried device is placed in a reaction chamber, and N2O gas is introduced and ionized into plasma. The plasma bombards the surface of the h-BN sublayer, causing dense nucleation sites to form on its surface.

[0006] As an improvement to the above technical solution, the deposition temperature of the h-BN sublayer is 200℃~400℃, and the pressure is 7×10⁻⁶. -6 torr~8torr, RF power is 50W~300W; The cleaning agent is one or more of acetone, anhydrous ethanol, and deionized water; The N2O plasma treatment has a processing power of 100W~150W, an N2O flow rate of 50sccm~100sccm, a processing gas pressure of 5mtorr~10mtorr, a processing temperature of 200℃~400℃, and a processing time of 30s~100s.

[0007] As an improvement to the above technical solution, the Al2O3 sublayer is prepared by the following method: After forming the modified h-BN sublayer, trimethylaluminum and deionized water are used as precursors to deposit the Al2O3 sublayer using an ALD process.

[0008] As an improvement to the above technical solution, the deposition temperature of the Al2O3 sublayer is 200℃~400℃, and the pressure is 0.01 torr~0.3 torr.

[0009] As an improvement to the above technical solution, the Si doping concentration in the N-type semiconductor layer is 5 × 10⁻⁶. 17 atoms / cm 3 ~1×10 19 atoms / cm 3 The growth thickness is 1.0 μm to 3.0 μm; The number of stacking periods of the quantum barrier layer and the quantum well layer in the multi-quantum well layer is ≥8, and the growth thickness of the quantum well layer is 2nm~4nm; the growth thickness of the quantum barrier layer is 8nm~12nm. The p-type semiconductor layer is a Mg-doped GaN layer with a growth thickness of 15nm~20nm and a Mg doping concentration of 5×10⁻⁶. 18 atoms / cm 3 ~5×10 21 atoms / cm 3 .

[0010] Accordingly, the present invention also provides a method for fabricating a light-emitting diode chip, comprising the following steps: Provide substrate; An N-type semiconductor layer is formed on the substrate; A multi-quantum-well layer is formed on the N-type semiconductor layer; A P-type semiconductor layer is formed on the multi-quantum-well layer; The composite passivation layer is deposited on the P-type semiconductor layer; The composite passivation layer comprises a modified h-BN sublayer and an Al2O3 sublayer stacked sequentially, wherein the Al2O3 sublayer is disposed on the h-BN sublayer; The modified h-BN sublayer is treated with N2O plasma and has a thickness of 1nm~5nm; The thickness of the Al2O3 sublayer is 10nm~100nm.

[0011] As an improvement to the above technical solution, the modified h-BN sublayer is prepared by the following method: Borane and ammonia were introduced as precursors; the deposition temperature was 200℃~400℃; the radio frequency power was 50W~300W; and the pressure was 7×10⁻⁶. -6 torr~8torr, the h-BN sublayer is formed on the P-type semiconductor layer; After the h-BN sublayer is deposited, it is cleaned with a cleaning agent and dried under N2 atmosphere; The dried device is placed in a reaction chamber, and N2O gas is introduced. The gas is ionized into plasma at a processing power of 100W~150W. The plasma bombards the surface of the h-BN sublayer. The N2O flow rate is 50sccm~100sccm, the processing pressure is 5mtorr~10mtorr, the processing temperature is 200℃~400℃, and the processing time is 30s~100s.

[0012] As an improvement to the above technical solution, the Al2O3 sublayer is prepared by the following method: After forming the modified h-BN sublayer, trimethylaluminum and deionized water are used as precursors to deposit the Al2O3 sublayer using an ALD process; wherein the deposition temperature of the Al2O3 sublayer is 200℃~400℃ and the pressure is 0.01 torr~0.3 torr.

[0013] As an improvement to the above technical solution, in the deposition of the N-type semiconductor layer, NH3 and TMGa are used as raw materials, SiH4 is used as an N-type dopant, and the growth temperature is 1000℃~1200℃. In the deposition of multiple quantum well layers, the multiple quantum well layers are formed by periodically alternating quantum barrier layers and quantum well layers, with a stacking period number ≥ 8; When depositing the quantum well layer, NH3, TEGa and TMIn are used as raw materials, the growth temperature is 760℃~800℃, and the growth pressure is 150 torr~250 torr. In the deposition of the P-type semiconductor layer, NH3 and TEGa are used as raw materials, CP2Mg is used as a P-type dopant, and deposition is carried out in an H2 atmosphere; wherein the growth temperature is 980°C~1050°C.

[0014] The implementation of this invention has the following beneficial effects: (1) The light-emitting diode chip provided by the present invention has a composite passivation layer comprising a modified h-BN sublayer and an Al2O3 sublayer, wherein the Al2O3 sublayer is disposed above the modified h-BN sublayer; the mechanical support properties of the Al2O3 sublayer enhance the adhesion of the h-BN layer, preventing film cracking, and leveraging the excellent metal ion blocking properties of the h-BN sublayer to effectively block the diffusion path of electrode metals (such as Au and Ni); the Al2O3 sublayer has high density and reduced water vapor permeability, significantly reducing the risk of electrode oxidation; the modified h-BN sublayer and the Al2O3 sublayer are thin and have good light transmittance, effectively ensuring the light output efficiency of the chip and solving the problems of numerous pinhole defects, poor light transmittance, and poor blocking properties of traditional SiO2 passivation layers. Furthermore, the composite passivation layer has a higher refractive index, filling the refractive index difference between the epitaxial layer and air, allowing more photons to escape from the device surface; thus improving both device lifespan and light output efficiency. It meets the application requirements of harsh environments such as automotive and outdoor lighting.

[0015] (2) The modified h-BN sublayer is obtained by treating the h-BN sublayer with N2O plasma. N2O ionizes into plasma to provide O and N active materials, generating -OH and a small amount of -NH2 / BNO on the h-BN surface. x It exhibits strong nucleation, minimal damage, high nucleation density, and the absence of islands and pinholes. The continuous and dense deposition of Al2O3 sublayers on the modified h-BN sublayer further enhances the prevention of leakage current and improves device stability. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of a light-emitting diode chip according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of a light-emitting diode chip according to another embodiment of the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings.

[0018] See Figure 1 As shown, an embodiment of the present invention provides a light-emitting diode chip, including a substrate 100, on which an N-type semiconductor layer 200, a multiple quantum well layer 300, a P-type semiconductor layer 400 and a composite passivation layer 600 are sequentially stacked. Substrate 100 can be made of sapphire, which is currently the most commonly used substrate material. Sapphire substrates have the advantages of mature manufacturing process, low price, easy cleaning and processing, and good stability at high temperature.

[0019] Specifically, the composite passivation layer 600 includes a modified h-BN sublayer 610 and an Al2O3 sublayer 620 stacked sequentially, wherein the Al2O3 sublayer 620 is disposed on the modified h-BN sublayer 610. The modified h-BN sublayer 610 is treated with N2O plasma and has a thickness of 1nm to 5nm. The thickness of the modified h-BN sublayer 610 is exemplarily 1nm, 2nm, 3nm, 4nm, or 5nm, but is not limited thereto.

[0020] The thickness of the Al2O3 sublayer 620 is 10nm~100nm; the thickness of the Al2O3 sublayer 620 is exemplarily 10nm, 20nm, 50nm, 60nm, 70nm, 80nm, 85nm, 90nm, 99nm, but is not limited thereto.

[0021] In some specific embodiments, see Figure 2 As shown, an ITO layer 500 is deposited on the surface of the P-type semiconductor layer 400, followed by mask etching to form a MESA mesa structure. Then, a P-type electrode 700 and an N-type electrode 800 are deposited on the ITO layer 500 to form an intermediate. Finally, the composite passivation layer 600 is deposited on the intermediate, and the P-type electrode 700 and the N-type electrode 800 are exposed through photolithography and ICP processes.

[0022] h-BN has an atomically flat layered structure with few grain boundary defects. It is highly inert and does not easily react with metal ions. It can block the diffusion path of metal ions (Au, Ni, Al) and inhibit electromigration.

[0023] Al2O3 has high density and low water vapor permeability, which can block the penetration of external water vapor and oxygen and prevent electrode oxidation; its interfacial bonding with modified h-BN sublayer 610 is strong and there are no obvious pores, thus avoiding becoming a channel for impurity diffusion.

[0024] The light-emitting diode chip provided by this invention has a composite passivation layer 600 comprising a modified h-BN sublayer 610 and an Al2O3 sublayer 620, wherein the Al2O3 sublayer 620 is disposed above the modified h-BN sublayer 610. The mechanical support of the Al2O3 sublayer 620 enhances the adhesion of the h-BN layer, preventing film cracking and leveraging the excellent metal ion blocking properties of the h-BN sublayer to effectively block the diffusion path of electrode metals (such as Au and Ni). The Al2O3 sublayer 620 has high density and reduced water vapor permeability, significantly reducing the risk of electrode oxidation. The modified h-BN sublayer 610 and the Al2O3 sublayer 620 are thin and have good light transmittance, effectively ensuring the light output rate of the chip and solving the problems of numerous pinhole defects, poor light transmittance, and poor barrier properties of traditional SiO2 passivation layers. Furthermore, the composite passivation layer 600 has a higher refractive index, bridging the refractive index difference between the epitaxial layer and air, allowing more photons to escape from the device surface; this also improves device lifespan and light extraction efficiency, meeting the needs of harsh environments such as automotive and outdoor lighting applications.

[0025] Modified h-BN sublayer 610 is obtained by treating h-BN sublayer with N2O plasma. The N2O plasma provides O and N active species, generating -OH and a small amount of -NH2 / BNO on the h-BN surface. x It exhibits strong nucleation, minimal damage, high nucleation density, and the absence of islands and pinholes. The continuous and dense deposition of Al2O3 sublayer 620 on the modified h-BN sublayer 610 further enhances the prevention of leakage current and improves device stability.

[0026] Preferably, the modified h-BN sublayer 610 is prepared by the following method: Borane and ammonia are introduced as precursors to form an h-BN sublayer on the epitaxial structure around the P-type electrode 700 and the N-type electrode 800. Specifically, during h-BN sublayer deposition, the temperature inside the reaction chamber is controlled at 200℃~400℃, and the pressure is 7×10⁻⁶. - 6 The deposition temperature ranges from 8 torr, with an RF power of 50W to 300W. Exemplary deposition temperatures for the h-BN sublayer are 200℃, 220℃, 270℃, 310℃, 350℃, and 400℃, but are not limited to these. An exemplary deposition pressure for the h-BN sublayer is 7 × 10⁻⁶. -6 torr, 8.8×10 -6 torr, 9.5×10 -6 Examples of torr, 3torr, 5torr, 7torr, and 8torr are available, but not limited to these. Exemplary RF power for h-BN sublayer deposition includes 50W, 70W, 100W, 150W, 200W, 220W, 260W, and 300W, but not limited to these.

[0027] After the h-BN sublayer is deposited, it is cleaned with a cleaning agent and dried under N2 atmosphere; Specifically, the cleaning agent may be one or more of acetone, anhydrous ethanol, and deionized water.

[0028] After cleaning and drying, the device is placed in the reaction chamber, N2O gas is introduced and ionized into plasma, and the plasma bombards the surface of the h-BN sublayer, causing dense nucleation sites to form on its surface. Specifically, the N2O plasma treatment power is 100W~150W, the N2O flow rate is 50sccm~100sccm, the treatment pressure is 5mtorr~10mtorr, the treatment temperature is 200℃~400℃, and the treatment time is 30s~100s. Examples of plasma treatment power include 100W, 110W, 115W, 120W, 130W, 140W, and 150W, but are not limited to these. Examples of N2O flow rates include 50sccm, 70sccm, 80sccm, 85sccm, 90sccm, 95sccm, and 100sccm, but are not limited to these. Examples of plasma treatment pressure include 5mtorr, 5.5mtorr, 6.3mtorr, 7.8mtorr, 8.3mtorr, 9.5mtorr, and 10mtorr, but are not limited to these. Examples of processing temperatures include 200℃, 220℃, 270℃, 300℃, 320℃, 350℃, and 400℃, but are not limited to these. Examples of processing times include 30s, 50s, 60s, 70s, 80s, 85s, 90s, 95s, and 100s, but are not limited to these.

[0029] Preferably, the Al2O3 sublayer 620 is prepared by the following method: After forming the modified h-BN sublayer 610, trimethylaluminum and deionized water are used as precursors to deposit the Al2O3 sublayer 620 through an ALD process.

[0030] It should be noted that ALD (Atomic Deposition) is a thin film preparation technology based on self-limiting surface reactions, which achieves atomic-level precision layer-by-layer growth by alternately introducing different precursors.

[0031] Specifically, the deposition temperature of the Al2O3 sublayer 620 is 200℃~400℃, and the pressure is 0.01 torr~0.3 torr. Examples of deposition temperatures for the Al2O3 sublayer 620 include 200℃, 220℃, 240℃, 270℃, 320℃, 380℃, and 400℃, but are not limited to these. Examples of deposition pressures include 0.01 torr, 0.05 torr, 0.09 torr, 0.17 torr, 0.19 torr, 0.25 torr, and 0.3 torr, but are not limited to these.

[0032] Preferably, the Si doping concentration in the N-type semiconductor layer 200 is 5 × 10⁻⁶. 17 atoms / cm 3 ~1×10 19 atoms / cm 3 The growth thickness is 1.0 μm to 3.0 μm; The exemplary doping concentration of Si is 5.1 × 10⁻⁶. 17 atoms / cm 3 6.3×10 17 atoms / cm 3 7.8×10 17 atoms / cm 3 8.8×10 17 atoms / cm 3 9.1×10 17 atoms / cm 3 1.8×10 18 atoms / cm 3 5.6×10 18 atoms / cm 3 5.8×10 18 atoms / cm 3 However, it is not limited to this. The exemplary growth thickness of the N-type semiconductor layer 200 is 1.0 μm, 1.5 μm, 1.8 μm, 2.1 μm, 2.5 μm, 2.7 μm, 3.0 μm, but it is not limited to this.

[0033] The number of stacking cycles of the quantum barrier layer and the quantum well layer in the multi-quantum well layer 300 is ≥8, and the growth thickness of the quantum well layer is 2nm~4nm; the growth thickness of the quantum barrier layer is 8nm~12nm. Examples of stacking cycles include 8, 9, 10, 11, 12, and 13, but are not limited to these. Examples of quantum well layer growth thickness include 2.2 nm, 2.5 nm, 2.8 nm, 3.4 nm, 3.7 nm, and 3.9 nm, but are not limited to these. Examples of quantum barrier layer growth thickness include 8.5 nm, 8.7 nm, 8.9 nm, 10.1 nm, 10.5 nm, 11.2 nm, and 12 nm, but are not limited to these.

[0034] The p-type semiconductor layer 400 is a Mg-doped GaN layer with a growth thickness of 15nm~20nm and a Mg doping concentration of 5×10⁻⁶. 18 atoms / cm 3 ~5×10 21 atoms / cm 3 ; The exemplary growth thickness of the P-type semiconductor layer 400 is 15nm, 16nm, 18nm, or 20nm, but it is not limited to these. The Mg doping concentration is 5.3 × 10⁻⁶. 18 atoms / cm 3 6.8×10 18 atoms / cm 3 7.7×10 18 atoms / cm 3 8.6×10 18 atoms / cm 3 8.3×10 19 atoms / cm 3 5.6×10 20 atoms / cm 3 5.9×10 20 atoms / cm 3 3.7×10 21 atoms / cm 3 4.9×10 21 atoms / cm 3 However, it is not limited to this.

[0035] This invention also provides a method for fabricating a light-emitting diode chip, comprising the following steps: Substrate 100 is provided; An N-type semiconductor layer 200 is formed on the substrate 100; A multiple quantum well layer 300 is formed on the N-type semiconductor layer 200; A P-type semiconductor layer 400 is formed on the multi-quantum-well layer 300; The composite passivation layer 600 is formed on the P-type semiconductor layer 400; The composite passivation layer 600 includes a modified h-BN sublayer 610 and an Al2O3 sublayer 620 stacked sequentially, wherein the Al2O3 sublayer 620 is disposed on the h-BN sublayer 610. The modified h-BN sublayer 610 is treated with N2O plasma and has a thickness of 1nm~5nm; The thickness of the Al2O3 sublayer 620 is 10nm~100nm.

[0036] Preferably, the modified h-BN sublayer 610 is prepared by the following method: Borane and ammonia were introduced as precursors, and the deposition temperature was 200℃~400℃, with a pressure of 7×10⁻⁶. -6 The torr~8torr, the radio frequency power is 50W~300W, and the h-BN sublayer is formed on the P-type semiconductor layer; After the h-BN sublayer is deposited, it is cleaned with a cleaning agent and dried under N2 atmosphere; The dried device is placed in a reaction chamber, and N2O gas is introduced. The gas is ionized into plasma at a processing power of 100W~150W. The plasma bombards the surface of the h-BN sublayer. The N2O flow rate is 50sccm~100sccm, the processing pressure is 5mtorr~10mtorr, the processing temperature is 200℃~400℃, and the processing time is 30s~100s.

[0037] Preferably, the Al2O3 sublayer 620 is prepared by the following method: After forming the modified h-BN sublayer 610, trimethylaluminum and deionized water are used as precursors to deposit the Al2O3 sublayer using an ALD process; wherein the deposition temperature of the Al2O3 sublayer 620 is 200℃~400℃ and the pressure is 0.01 torr~0.3 torr.

[0038] Preferably, in depositing the N-type semiconductor layer 200, NH3 and TMGa are used as raw materials, SiH4 is used as an N-type dopant, and the growth temperature is 1000℃~1200℃. Specifically, the reaction chamber temperature is raised to 1000℃~1200℃, with NH3 as the nitrogen source, TMGa as the gallium source, and SiH4 as the N-type dopant. Exemplary reaction chamber temperatures for depositing the N-type semiconductor layer 200 are 1000℃, 1100℃, and 1200℃, but are not limited to these.

[0039] In the deposition of the multiple quantum well layer 300, the multiple quantum well layer 300 is formed by periodically alternating growth of quantum barrier layers and quantum well layers, with a stacking period number ≥ 8; When depositing the quantum well layer, NH3, TEGa and TMIn are used as raw materials, the growth temperature is 760℃~800℃, and the growth pressure is 150 torr~250 torr. When depositing the quantum barrier layer, NH3 and TEGa are used as raw materials, the growth temperature is 860°C~900°C, and the growth pressure is 150 torr~250 torr. In the deposition of the P-type semiconductor layer 400, NH3 and TEGa are used as raw materials, CP2Mg is used as a P-type dopant, and deposition is carried out in an H2 atmosphere; wherein, the growth temperature is 980°C~1050°C; the reaction chamber temperature of the P-type semiconductor layer is exemplary, such as 980°C, 1000°C, and 1050°C, but is not limited thereto.

[0040] The technical solution of the present invention will be further described below with reference to specific embodiments and comparative examples.

[0041] Example 1 A method for fabricating a light-emitting diode (LED) chip includes the following steps: Provide a substrate, which is sapphire; An N-type semiconductor layer is deposited on the substrate; Specifically, the deposition process is as follows: the reaction chamber temperature is lowered to 1100℃, NH3 is used as the N (nitrogen) source, TMGa is used as the Ga (gallium) source, and SiH4 is used as the N-type dopant to deposit a Si-doped N-type GaN layer with a Si doping concentration of 5 × 10⁻⁶. 18 atoms / cm 3 The thickness of the deposited N-type GaN layer is controlled to be approximately 2 μm.

[0042] A multi-quantum-well layer is deposited on the N-type semiconductor layer; The specific deposition process is as follows: When growing the quantum well layer, the N (nitrogen) source is NH3, the Ga (gallium) source is TEGa, and the In (indium) source is TMIn. The temperature of the reaction chamber is controlled at 780℃, the pressure at 200 torr, and the thickness of the deposited InGaN quantum well layer is controlled to be approximately 3 nm. When growing the quantum barrier layer, the N (nitrogen) source is NH3, the Ga (gallium) source is TEGa, the temperature of the reaction chamber is controlled at 880℃, the pressure at 200 torr, and the thickness of the deposited GaN quantum barrier layer is controlled to be 10 nm. The quantum well layer and the quantum barrier layer are alternately deposited and stacked 10 times to obtain a multi-quantum well layer.

[0043] A P-type semiconductor layer is deposited on the multi-quantum-well layer; The specific deposition process was as follows: NH3 was used as the N (nitrogen) source, TEGa as the Ga (gallium) source, and CP2Mg as the P-type dopant. The reaction chamber temperature was controlled at 1000℃, and the deposition thickness was controlled under an H2 atmosphere. The deposited P-type low-Mg-doped GaN layer had a thickness of 17 nm, and the Mg doping concentration was 5 × 10⁻⁶. 20 atoms / cm 3 .

[0044] A composite passivation layer is formed on the P-type semiconductor layer; Specifically, the device is placed in a reaction chamber, and borane and ammonia are introduced as precursors. The deposition temperature is 300°C, the pressure is 4 torr, the radio frequency power is 200W, and the growth thickness of the h-BN sublayer is 3.5nm. Cleaning was performed using anhydrous ethanol, followed by drying under a nitrogen atmosphere. The dried chip is placed in a reaction chamber, N2O gas is introduced and ionized into plasma, and the plasma bombards the surface of the h-BN sublayer, causing dense nucleation sites to form on its surface. The N2O plasma treatment has a processing power of 125W, an N2O flow rate of 75sccm, a processing gas pressure of 7.5mtorr, a processing temperature of 300℃, and a processing time of 80s.

[0045] After forming the modified h-BN sublayer, trimethylaluminum and deionized water were used as precursors to deposit the Al2O3 sublayer using an ALD process. The Al2O3 sublayer was deposited at a temperature of 300°C, a pressure of 0.15 torr, and a growth thickness of 55 nm.

[0046] Example 2 The difference from Example 1 is that the growth thickness of the modified h-BN layer is 1 nm.

[0047] Example 3 The difference from Example 1 is that the growth thickness of the modified h-BN layer is 5 nm.

[0048] Example 4 The difference from Example 1 is that the growth thickness of the Al2O3 sublayer is 10 nm.

[0049] Example 5 The difference from Example 1 is that the growth thickness of the Al2O3 sublayer is 100 nm.

[0050] Example 6 The difference from Example 1 is that in the N2O plasma treatment step, the treatment power is 100W, the N2O flow rate is 50sccm, the treatment pressure is 5mtorr, the treatment temperature is 200℃, and the treatment time is 30s.

[0051] Example 7 The difference from Example 1 is that in the N2O plasma treatment step, the treatment power is 150W, the N2O flow rate is 100sccm, the treatment pressure is 10mtorr, the treatment temperature is 400℃, and the treatment time is 100s.

[0052] Comparative Example 1 The difference from Example 1 is that a SiO2 passivation layer is formed on the epitaxial structure around the P-type electrode and the N-type electrode, and the growth thickness of the SiO2 passivation layer is 300 nm.

[0053] Comparative Example 2 The difference from Example 1 is that the h-BN sublayer was not treated with N2O plasma.

[0054] Comparative Example 3 The difference from Example 1 is that its passivation layer consists only of a modified h-BN sublayer.

[0055] Performance testing: The epitaxial structures obtained in the examples and comparative examples were fabricated into 3mil × 5mil chips using the same chip fabrication conditions. Their photoelectric performance was tested under a 2mA operating current using the same LED spot tester. The luminous efficacy improvement was calculated based on Comparative Example 1.

[0056] Table 1 Performance test results of each embodiment and comparative example

[0057] As can be seen from the above results, the composite passivation layer of the present invention comprises a modified h-BN sublayer and an Al2O3 sublayer stacked sequentially. The Al2O3 sublayer is disposed on the modified h-BN sublayer, effectively ensuring the light extraction efficiency of the chip and solving the problems of numerous pinhole defects, poor light transmittance, and poor barrier properties of traditional SiO2 passivation layers. Furthermore, the composite passivation layer has a higher refractive index, bridging the refractive index difference between the epitaxial layer and air, allowing more photons to escape from the device surface; thus improving both device lifespan and light extraction efficiency. This meets the application requirements of harsh environments such as automotive and outdoor lighting. In addition, the modified h-BN sublayer is obtained through N2O plasma treatment, resulting in strong nucleation, minimal damage, high nucleation density, and the absence of islands and pinholes; the continuous and dense deposition of the Al2O3 sublayer on the modified h-BN sublayer further enhances the prevention of leakage current and improves device stability.

[0058] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A light-emitting diode chip, characterized in that, Includes a substrate, on which an N-type semiconductor layer, a multiple quantum well layer, a P-type semiconductor layer and a composite passivation layer are sequentially stacked; The composite passivation layer comprises a modified h-BN sublayer and an Al2O3 sublayer stacked sequentially, wherein the Al2O3 sublayer is disposed on the modified h-BN sublayer; The modified h-BN sublayer is treated with N2O plasma and has a thickness of 1nm~5nm; The thickness of the Al2O3 sublayer is 10nm~100nm.

2. The light-emitting diode chip as described in claim 1, characterized in that, The modified h-BN sublayer was prepared by the following method: Borane and ammonia are introduced as precursors to form an h-BN sublayer on the P-type semiconductor layer; After cleaning with a cleaning agent, dry under a nitrogen atmosphere; The dried device is placed in a reaction chamber, and N2O gas is introduced and ionized into plasma. The plasma bombards the surface of the h-BN sublayer, causing dense nucleation sites to form on its surface.

3. The light-emitting diode chip as described in claim 2, characterized in that, The deposition temperature of the h-BN sublayer is 200℃~400℃, and the pressure is 7×10⁻⁶. -6 torr~8torr, RF power is 50W~300W; The cleaning agent is one or more of acetone, anhydrous ethanol, and deionized water; The N2O plasma treatment has a processing power of 100W~150W, an N2O flow rate of 50sccm~100sccm, a processing gas pressure of 5mtorr~10mtorr, a processing temperature of 200℃~400℃, and a processing time of 30s~100s.

4. The light-emitting diode chip as described in claim 1, characterized in that, The Al2O3 sublayer was prepared by the following method: After forming the modified h-BN sublayer, trimethylaluminum and deionized water are used as precursors to deposit the Al2O3 sublayer using an ALD process.

5. The light-emitting diode chip as described in claim 4, characterized in that, The deposition temperature of the Al2O3 sublayer is 200℃~400℃, and the pressure is 0.01 torr~0.3 torr.

6. The light-emitting diode chip as described in claim 1, characterized in that, The Si doping concentration in the N-type semiconductor layer is 5 × 10⁻⁶. 17 atoms / cm 3 ~1×10 19 atoms / cm 3 The growth thickness is 1.0 μm to 3.0 μm; The number of stacking periods of the quantum barrier layer and the quantum well layer in the multi-quantum well layer is ≥8, and the growth thickness of the quantum well layer is 2nm~4nm; the growth thickness of the quantum barrier layer is 8nm~12nm. The p-type semiconductor layer is a Mg-doped GaN layer with a growth thickness of 15nm~20nm and a Mg doping concentration of 5×10⁻⁶. 18 atoms / cm 3 ~5×10 21 atoms / cm 3 .

7. A method for fabricating a light-emitting diode chip as described in any one of claims 1 to 6, characterized in that, Includes the following steps: Provide substrate; An N-type semiconductor layer is formed on the substrate; A multi-quantum-well layer is formed on the N-type semiconductor layer; A P-type semiconductor layer is formed on the multi-quantum-well layer; The composite passivation layer is deposited on the P-type semiconductor layer; The composite passivation layer comprises a modified h-BN sublayer and an Al2O3 sublayer stacked sequentially, wherein the Al2O3 sublayer is disposed on the h-BN sublayer; The modified h-BN sublayer is treated with N2O plasma and has a thickness of 1nm~5nm; The thickness of the Al2O3 sublayer is 10nm~100nm.

8. The method for fabricating a light-emitting diode chip as described in claim 7, characterized in that, The modified h-BN sublayer was prepared by the following method: Borane and ammonia were introduced as precursors; the deposition temperature was 200℃~400℃; the radio frequency power was 50W~300W; and the pressure was 7×10⁻⁶. -6 torr~8torr, the h-BN sublayer is formed on the P-type semiconductor layer; After the h-BN sublayer is deposited, it is cleaned with a cleaning agent and dried under N2 atmosphere; The dried device is placed in a reaction chamber, and N2O gas is introduced. The gas is ionized into plasma at a processing power of 100W~150W. The plasma bombards the surface of the h-BN sublayer. The N2O flow rate is 50sccm~100sccm, the processing pressure is 5mtorr~10mtorr, the processing temperature is 200℃~400℃, and the processing time is 30s~100s.

9. The method for fabricating a light-emitting diode chip as described in claim 7, characterized in that, The Al2O3 sublayer was prepared by the following method: After forming the modified h-BN sublayer, trimethylaluminum and deionized water are used as precursors to deposit the Al2O3 sublayer using an ALD process; wherein the deposition temperature of the Al2O3 sublayer is 200℃~400℃ and the pressure is 0.01 torr~0.3 torr.

10. The method for fabricating a light-emitting diode chip as described in claim 7, characterized in that, In the deposition of the N-type semiconductor layer, NH3 and TMGa are used as raw materials, SiH4 is used as N-type dopant, and the growth temperature is 1000℃~1200℃. In the deposition of multiple quantum well layers, the multiple quantum well layers are formed by periodically alternating quantum barrier layers and quantum well layers, with a stacking period number ≥ 8; When depositing the quantum well layer, NH3, TEGa and TMIn are used as raw materials, the growth temperature is 760℃~800℃, and the growth pressure is 150 torr~250 torr. In the deposition of the P-type semiconductor layer, NH3 and TEGa are used as raw materials, CP2Mg is used as a P-type dopant, and deposition is carried out in an H2 atmosphere; wherein the growth temperature is 980°C~1050°C.

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