Wireless receiving circuit

Abstract

In the wireless receiving circuit (1), the input signal is amplified by the LNA (2), and the output of the LNA (2) is mixed with the local signal (L01) by the mixer (3) and then output. The output of the mixer (3) is filtered by the first filter circuit (4), and the signal strength is detected by the first signal strength detection circuit (5). In addition, the output of the mixer (3) is filtered by the second filter circuit (7) via the attenuator (6), and the signal strength is detected by the second signal strength detection circuit (8). Then, the signal strength of the input signal is obtained by adding the signal strength detected by the first signal strength detection circuit (5) and the signal strength detected by the second signal strength detection circuit (8).

Description

Technical Field

[0001] This invention relates to a wireless receiving circuit. Background Technology

[0002] In wireless communication systems, such as the ETC (Electronic Toll Collection) system (DSRC), digital modulation methods like ASK (Amplitude Shift Keying) are used. The receiver in such a system performs carrier sense, searching for the presence of a target communication partner within the communication area. If the receiver receives a signal from the target partner within the communication area, it uses an internal demodulator to detect amplitude changes, demodulates the ASK signal, and if the signal matches the specified pattern, communication begins.

[0003] In typical wireless communication systems, signals from other channels within the same system and signals from other wireless systems coexist in adjacent frequency bands. These signals are unnecessary for the desired signal and degrade the communication quality. Therefore, filters or similar devices are needed to remove these unnecessary signals.

[0004] In Non-Patent Document 1, a wireless receiving circuit is disclosed with the following structure: a wireless signal is received by an antenna and amplified by an LNA (Low Noise Amplifier); the signal is then converted into a low-frequency signal by a mixer; and finally, unwanted signals are removed by a filter to detect the signal strength. In the prior art, an external SAW filter is used to remove unwanted signals before detecting the signal strength. RSSI (Received Signal Strength Indication) is used for signal strength detection. SAW filters have high Q values; for example, a filter with a Q value of around 10 is used in the receiver.

[0005] Non-licensed document 1: N. Sasho, et al., "Single-Chip 5.8GHz DSRC Transceiver with Dual-Mode of ASK and Pi / 4-QPSK", 2008 IEEE Radio and Wireless Symposium, pp. 799-802, January 2008 Summary of the Invention

[0006] -The technical problem the invention aims to solve-

[0007] However, SAW filters are expensive and large, hindering miniaturization and cost reduction of the module. Therefore, an active circuit filter within the LSI is considered as a replacement for the SAW filter. However, active circuits have issues with linearity and noise characteristics, and cannot achieve the necessary dynamic range while ensuring reception performance. For example, with an active circuit filter, filter saturation occurs when the input signal level increases. If the filter saturates, the RSSI output signal will also saturate, making it impossible to detect changes in signal level and potentially leading to incorrect demodulation of the modulated signal. Furthermore, if the RSSI output signal saturates, demodulation may also fail correctly in other digital modulation methods.

[0008] This disclosure was made to solve the aforementioned technical problems, and its purpose is to integrate filters on semiconductor integrated circuits in order to achieve miniaturization and low cost in wireless receiving circuits, thereby enabling high-speed and wide dynamic range signal strength detection.

[0009] -Technical solutions for solving technical problems-

[0010] A wireless receiving circuit according to one aspect of this disclosure is configured to include: a low-noise amplifier (LNA) that amplifies an input signal; a first mixer that receives the output of the LNA and mixes the output of the LNA with a first local oscillator signal before outputting it; a first filter circuit that filters the output of the first mixer; a first signal strength detection circuit that receives the output of the first filter circuit and detects the signal strength; an attenuator that receives the output of the first mixer and attenuates the output of the first mixer before outputting it; a second filter circuit that filters the output of the attenuator; and a second signal strength detection circuit that receives the output of the second filter circuit and detects the signal strength, thereby obtaining the signal strength of the input signal by adding the signal strength detected by the first signal strength detection circuit to the signal strength detected by the second signal strength detection circuit.

[0011] Based on the above aspects, a first signal strength detection circuit is provided to detect the signal strength based on the output of the first mixer, and a second signal strength detection circuit is provided to attenuate the output of the first mixer using an attenuator and detect the signal strength based on the attenuated signal. The signal strength of the input signal is obtained by adding the signal strength detected by the first signal strength detection circuit and the signal strength detected by the second signal strength detection circuit. With this structure, even in the saturated region of the first filter circuit, the second filter circuit can operate without saturation, thereby expanding the range of linear output relative to the input signal. In this way, the filter is integrated on a semiconductor integrated circuit for miniaturization and low cost, enabling high-speed and wide dynamic range signal strength detection.

[0012] A wireless receiving circuit according to one aspect of this disclosure is configured to include: a low-noise amplifier (LNA) that amplifies an input signal; a first mixer that receives the output of the LNA and mixes the output of the LNA with a local oscillator signal before outputting it; an amplifier circuit that receives the output of the first mixer and amplifies the output of the first mixer before outputting it; a first filter circuit that filters the output of the amplifier circuit; a first signal strength detection circuit that receives the output of the first filter circuit and detects the signal strength; a second filter circuit that filters the output of the first mixer; and a second signal strength detection circuit that receives the output of the second filter circuit and detects the signal strength, thereby obtaining the signal strength of the input signal by adding the signal strength detected by the first signal strength detection circuit to the signal strength detected by the second signal strength detection circuit.

[0013] Based on the above aspects, a first signal strength detection circuit is provided that amplifies the output of the first mixer using an amplifier and detects the signal strength based on the amplified signal, and a second signal strength detection circuit is provided that detects the signal strength based on the output of the mixer. The signal strength of the input signal is obtained by adding the signal strength detected by the first signal strength detection circuit to the signal strength detected by the second signal strength detection circuit. With this structure, even in the saturated region of the first filter circuit, the second filter circuit can operate without saturation, thereby expanding the range of linear output relative to the input signal. In this way, the filter is integrated onto a semiconductor integrated circuit for miniaturization and low cost, enabling high-speed signal strength detection over a wide dynamic range.

[0014] -The Effects of the Invention-

[0015] The wireless receiving circuit disclosed herein integrates a filter on a semiconductor integrated circuit to achieve miniaturization and low cost, thereby enabling high-speed and wide dynamic range signal strength detection. Attached Figure Description

[0016] Figure 1 This is a block diagram illustrating the structure of the wireless receiving circuit according to an embodiment;

[0017] Figure 2 This is a circuit diagram showing an example of the structure of a filter circuit;

[0018] Figure 3 This is a circuit diagram showing an example of the attenuator's structure;

[0019] Figure 4 This is a circuit diagram showing other structural examples of attenuators;

[0020] Figure 5 This is a block diagram illustrating an example of the structure of a signal strength detection circuit;

[0021] Figure 6 This is a circuit diagram showing an example of the structure of a limiting amplifier;

[0022] Figure 7 This is a diagram illustrating an example of the input / output characteristics of a wireless receiver circuit;

[0023] Figure 8 This is a diagram showing the simulation results of the input and output characteristics of the wireless receiver circuit;

[0024] Figure 9 This is a block diagram showing the structure of the wireless receiving circuit of Modified Example 1;

[0025] Figure 10 This is a block diagram showing the structure of the wireless receiving circuit in Modified Example 2;

[0026] Figure 11 This is a block diagram showing the structure of the wireless receiving circuit of Modified Example 3. Detailed Implementation

[0027] The embodiments will now be described in detail with reference to the accompanying drawings. It should be noted that the specific numerical values ​​shown in the following embodiments are merely examples to facilitate understanding of the invention and are not intended to limit the scope of the invention.

[0028] Figure 1 This is a block diagram showing a structural example of the wireless receiving circuit 1 according to this embodiment.

[0029] The wireless receiving circuit 1 described in this embodiment is, for example, integrated into the receiver (not shown) of a wireless communication system such as a narrow-area communication system (DSRC) like the ETC system. The receiver performs carrier sensing to search for other devices (hereinafter referred to as the communication counterpart) located within its communication area. If the receiver receives a signal from the communication counterpart within the communication area, the wireless receiving circuit 1 detects changes in amplitude, demodulates the ASK signal, and if the signal conforms to a predetermined pattern, communication with the communication counterpart begins. It should be noted that the application of the wireless receiving circuit 1 in this embodiment is not limited to ETC systems; for example, it can be widely used in wireless systems that detect the signal level of received signals and perform AGC control, and in demodulate ASK modulated signals.

[0030] like Figure 1 As shown, the wireless receiving circuit 1 includes: a low-noise amplifier circuit 2 (hereinafter referred to as LNA2), a mixer 3 (equivalent to a first mixer), a first filter circuit 4, a first signal strength detection circuit 5, an attenuator 6, a second filter circuit 7, a second signal strength detection circuit 8, and an adder circuit 85.

[0031] LNA2 amplifies the high-frequency signal RFIN received by the antenna (not shown) with low noise and outputs the amplified signal as amplified signal S2. The high-frequency signal RFIN is, for example, a signal in the GHz band. When the wireless receiving circuit 1 of this embodiment is applied to an ETC system, for example, the frequency of the high-frequency signal RFIN is 5795 [MHz], and the frequency of the local oscillator signal L01 (described later) is 5835 [MHz]. In addition, the signal level of the high-frequency signal RFIN received by the ETC system is, for example, -20 [dBm] to -80 [dBm]. However, the frequency and signal level of the high-frequency signal RFIN received by the wireless receiving circuit 1, as well as the frequency of the local oscillator signal L01 input to the mixer 3, are not limited to the above.

[0032] Mixer 3 receives the amplified signal S2 output from LNA2, mixes the amplified signal S2 with the local oscillator signal LO1, and outputs an IF signal S3 relating to the frequency difference between the two signals. The frequency of the IF signal S3 is, for example, the frequency difference between the high-frequency signal RFIN and the local oscillator signal LO1. In an ETC system, for example, the frequency of the IF signal S3 is 40 [MHz], and the sum of the gains of LNA2 and mixer 3 is 30 [dB].

[0033] The first filter circuit 4 receives the IF signal S3 output from the mixer 3, filters it, and outputs the filtered signal as the first filtered signal S4 to the first signal strength detection circuit 5. Figure 2In the diagram, as an example of the first filter circuit 4, a dual second-order bandpass filter combining an operational amplifier and RC components is shown. The first filter circuit 4, for example, sets its center frequency to 40 [MHz], corresponding to the frequency of the IF signal S3, and sets its signal bandwidth to 4 [MHz]. The first filter circuit 4, for example, has the characteristic of saturating at -40 [dBm] for the high-frequency signal RFIN. As described above, when the sum of the gains of LNA2 and mixer 3 is set to 30 [dB], the first filter itself saturates at -10 [dBm]. It should be noted that the first filter circuit 4 can also be configured as a multi-stage bandpass filter depending on the required attenuation, which is not shown. Furthermore, the first filter circuit 4 can be a multiple feedback type, or a combination of a low-pass filter and a high-pass filter. Additionally, when the frequency of the high-frequency signal RFIN is the same as the frequency of the local oscillator signal L01 (Direct-Conversion reception mode), the first filter circuit 4 can also be constructed using a low-pass filter.

[0034] Attenuator 6 receives the IF signal S3 output from the mixer, attenuates the signal level, and outputs the attenuated signal as the attenuated signal S6. Figure 3 An example circuit structure of attenuator 6, configured such that the attenuation is determined by the resistance ratio, is shown. Figure 3 In the case of the circuit, the attenuation A is

[0035] A=-20×log(R62 / (2×R61+R62))……(1)

[0036] In equation (1) above, R61 is Figure 3 The resistance value of resistor R61, and the resistance value of R62 are... Figure 3 The resistance value of resistor R62. And, for example, when R61 = 9 [kΩ] and R62 = 2 [kΩ], Figure 3 The attenuation A of the circuit is A = 20 [dB].

[0037] It should be noted that attenuator 6 is not limited to Figure 3 The structure can be either or other structures. For example, Figure 4 An example of using an operational amplifier to construct attenuator 6 is shown. Figure 4 In the case of the circuit, the attenuation A is

[0038] A=-20×log(R64 / R63)……(2)

[0039] In equation (2) above, R63 is Figure 4 The resistance value of resistor R63, and the resistance value of R64. Figure 4The resistance value of resistor R64. And, for example, when R63 = 50 kΩ and R64 = 5 kΩ, Figure 4 The attenuation A of the circuit is A = 20 [dB].

[0040] The second filter circuit 7 receives the attenuated signal S6 output from the attenuator 6, filters the attenuated signal S6, and outputs the filtered signal as the second filtered signal S7 to the second signal strength detection circuit 8. It should be noted that since the second filter circuit 7 can also use the same circuitry as the first filter circuit 4, the description of the structure of the second filter circuit 7 is omitted here. Here, the IF signal S3 output from the mixer 3 is attenuated by 20 dB by the attenuator 6 before being input to the second filter circuit 7. Therefore, even though, like the first filter circuit 4, the second filter circuit 7 has the characteristic that the filter itself saturates at -10 dBm, the second filter circuit 7 will not saturate until the high-frequency signal RFIN reaches -20 dBm.

[0041] like Figure 5 As shown, the first signal strength detection circuit 5 includes a first limiting amplifier group 50 and a first adder 52 (equivalent to a first detection circuit), wherein the first limiting amplifier group 50 is composed of multiple stages of first limiting amplifiers 51 connected together. In this embodiment, an example is shown where the first limiting amplifier group 50 is composed of five stages of first limiting amplifiers 51. It should be noted that in the following description, when distinguishing the first limiting amplifiers 51 (five stages), sometimes the first limiting amplifiers 51 (five stages) are described with the symbols 511 to 515 in the order of the first stage to the fifth stage receiving the first filtered signal S4.

[0042] Figure 6 An example of a first limiting amplifier 51 constructed using a differential operational amplifier 51a (equivalent to a first amplifier circuit) is shown. Figure 6 In the structure, the gain of the first limiting amplifier 51 is determined by the ratio of the input resistance to the output resistance connected to the operational amplifier 51a. For example, in Figure 6In the circuit, when the input resistor R51 has a resistance of 10 kΩ and the output resistor R52 has a resistance of 32 kΩ, the gain of each stage of the first limiting amplifier 51 is 10 dB. In each of the first limiting amplifiers 51, the rectifier 51b (equivalent to a first converter) extracts the amplitude information from the output of the operational amplifier 51a and outputs it to the first adder 52. That is, the rectifier 51b outputs a current signal with an amplitude equivalent to the output signal of the operational amplifier 51a. Then, in the first adder 52, the first current signals S5x (x is an integer from 1 to 5 in this embodiment) received from the rectifier 51b of each stage of the first limiting amplifier 51 are added together, and the summed signal is output as the first current signal S5. It should be noted that the first limiting amplifier 51 is not limited to a differential configuration; for example, it can also be a single-ended configuration.

[0043] return Figure 1 The second signal strength detection circuit 8 includes a second limiting amplifier group 80 and a second adder 82 (equivalent to a second detection circuit), wherein the second limiting amplifier group 80 is composed of multiple stages of second limiting amplifiers 81 connected together. In this embodiment, an example is shown where the second limiting amplifier group 80 is composed of two stages of second limiting amplifiers 81. It should be noted that in the following description, when distinguishing between the two stages of the second limiting amplifiers 81, the notation 811 is sometimes added to the first stage second limiting amplifier that receives the second filtered signal S7, and the notation 812 is sometimes added to the second stage second limiting amplifier. The second limiting amplifier 81 can use the same structure as the first limiting amplifier 51. That is, in Figure 6 In this circuit, operational amplifier 51a is an example of the second amplification circuit of the second limiting amplifier 81, and rectifier 51b is an example of the second converter of the second limiting amplifier 81. For example, it is possible to use... Figure 6 The structure serves as the structure of the second limiting amplifier 81, where the gain of each stage of the second limiting amplifier 81 is 10 dB. Then, in the second adder 82, the second current signals S81 and S82 received from the rectifiers (equivalent to the second converters) in each stage of the second limiting amplifier 81 are added together, and the added signal is output as the second current signal S8. It should be noted that a single-ended structure can also be used in the second limiting amplifier 81.

[0044] The adder circuit 85 adds the first current signal S5 and the second current signal S8, converts them into a voltage signal, and outputs it as the RSSI output signal ROUT to the subsequent ADC91. In the ADC91, the RSSI output signal ROUT is converted into a digital signal.

[0045] By adopting the structure described above. Figure 1The wireless receiving circuit 1 can obtain an output that linearly changes when the signal level of the high-frequency signal RFIN is between -90 [dBm] and -20 [dBm] as the RSSI output signal ROUT.

[0046] [Example of wireless receiver circuit operation]

[0047] The operation of the wireless receiving circuit 1 when a signal with a signal level of -90 dBm to -20 dBm is input as a high-frequency signal RFIN is described in detail below. Here, as mentioned above, the gain of each of the first limiting amplifiers 51 (511 to 515) and each of the second limiting amplifiers 81 (811, 812) is set to 10 dB. In addition, the first filter circuit 4 is set to saturate at an input signal (IF signal S3) of -10 dBm. Similarly, the second filter circuit 7 is set to saturate at an input signal (attenuation signal S6) of -10 dBm. In addition, the first limiting amplifier 51 and the second limiting amplifier 81 are set to saturate at an output level of 0 dBm.

[0048] -Regarding interval (i)-

[0049] exist Figure 7In interval (i), the high-frequency signal RFIN varies within the range of -90 [dBm] to -80 [dBm]. At this time, the output of the first limiting amplifier 515 of the fifth stage changes linearly relative to the rise of the high-frequency signal RFIN, and the result is reflected in the RSSI output signal ROUT. Specifically, when the high-frequency signal RFIN is within the range of -90 [dBm] to -80 [dBm], the signal level of the IF signal S3 after passing through LNA2 and mixer 3 is -60 [dBm] to -50 [dBm]. Therefore, a first filtered signal S4 with a signal level of -60 [dBm] to -50 [dBm] is input to the first limiting amplifier 511 of the first stage, and the first limiting amplifier 511 of the first stage outputs a signal with a signal level of -50 [dBm] to -40 [dBm]. The output signal of the first-stage first-limiter amplifier 511 is input to the first-stage first-limiter amplifier 512 of the second stage, and the output signal level of the first-stage first-limiter amplifier 512 is -40 [dBm] to -30 [dBm]. The output signal of the second-stage first-limiter amplifier 512 is input to the first-stage first-limiter amplifier 513 of the third stage, and the output signal level of the first-stage first-limiter amplifier 513 is -30 [dBm] to -20 [dBm]. The output signal of the third-stage first-limiter amplifier 513 is input to the first-stage first-limiter amplifier 514 of the fourth stage, and the output signal level of the first-stage first-limiter amplifier 514 is -20 [dBm] to -10 [dBm]. The output signal of the fourth-stage first-limiter amplifier 514 is input to the first-stage first-limiter amplifier 515 of the fifth stage, and the output signal level of the first-stage first-limiter amplifier 515 is -10 [dBm] to 0 [dBm]. Here, because the outputs of the first limiting amplifier 511 in the first stage to the first limiting amplifier 514 in the fourth stage are small, the current signals S51 to S54 are also small, thus their influence on the RSSI output signal ROUT can be ignored. Furthermore, in the second limiting amplifier group 80, because the IF signal S3 is attenuated by 20 dB by the attenuator 6, the outputs of the second limiting amplifiers 811 and 812 are small, so the current signals S81 and S82 are also small, thus their influence on the RSSI output signal ROUT can be ignored. The same applies to intervals (ii) to (v) described later. Therefore, as described above, the linear change in the output of the first limiting amplifier 515 in the fifth stage of the first signal strength detection circuit 5 relative to the rise of the high-frequency signal RFIN, and the linear change in the current output S55, are reflected in the RSSI output signal ROUT.

[0050] -Regarding interval (ii)-

[0051] exist Figure 7In interval (ii), the high-frequency signal RFIN varies within the range of -80 [dBm] to -70 [dBm]. At this time, the output of the first limiting amplifier 514 of the fourth stage changes linearly relative to the rise of the high-frequency signal RFIN, and the result is reflected in the RSSI output signal ROUT. Specifically, in the description of interval (i) above, the input and output signals from the first limiting amplifier 511 of the first stage to the first limiting amplifier 514 of the fourth stage all rise by 10 [dB]. Here, since the first limiting amplifier 515 of the fifth stage saturates at an output level of 0 [dBm], the current signal S55 remains constant (refer to...). Figure 7 (The dashed line extending between (i) and (ii)). Therefore, from the signal level of the high-frequency signal RFIN being -80 [dBm], its output signal level does not substantially change. In addition, since the outputs of the first limiting amplifier 511 of the first stage to the first limiting amplifier 513 of the third stage and the second limiting amplifiers 811 and 812 are small, the current signals S51 to S53 and the current signals S81 and S82 are also small, thus the influence on the RSSI output signal ROUT can be ignored. Therefore, the output of the sum of the outputs of the first limiting amplifier 514 of the fourth stage and the first limiting amplifier 515 of the fifth stage is reflected in the RSSI output signal ROUT. In addition, the result that the output of the first limiting amplifier 514 of the fourth stage in the first signal strength detection circuit 5 changes linearly with respect to the rise of the high-frequency signal RFIN and the current output S54 also changes linearly is reflected in the RSSI output signal ROUT.

[0052] Regarding interval (iii)-

[0053] exist Figure 7 In interval (iii), the high-frequency signal RFIN varies within the range of -70 [dBm] to -60 [dBm]. At this time, the output of the first limiting amplifier 513 of the third stage changes linearly relative to the rise of the high-frequency signal RFIN, and the result is reflected in the RSSI output signal ROUT. Specifically, in the description of interval (ii) above, the input and output signals from the first limiting amplifier 511 of the first stage to the first limiting amplifier 513 of the third stage all rise by 10 [dB]. Here, the first limiting amplifier 514 of the fourth stage saturates at an output level of 0 [dBm], therefore the current signal S54 remains constant. Therefore, from the signal level of the high-frequency signal RFIN when it reaches -70 [dBm], the output signal levels of the first limiting amplifier 514 of the fourth stage and the first limiting amplifier 515 of the fifth stage do not substantially change (refer to...). Figure 7(The dashed line extending between (ii) and (iii)). Furthermore, since the outputs of the first limiting amplifier 511 of the first stage, the first limiting amplifier 512 of the second stage, and the second limiting amplifiers 811 and 812 are small, the current signals S51, S52, and S81 and S82 are also small, thus their influence on the RSSI output signal ROUT can be ignored. Therefore, the sum of the outputs of the first limiting amplifiers 513 of the third stage to the first limiting amplifiers 515 of the fifth stage is reflected in the RSSI output signal ROUT. Additionally, the linear change in the output of the first limiting amplifier 513 of the third stage in the first signal strength detection circuit 5 relative to the rise of the high-frequency signal RFIN, and the linear change in the current output S53, are also reflected in the RSSI output signal ROUT.

[0054] -Regarding interval (iv)-

[0055] exist Figure 7 In interval (iv), the high-frequency signal RFIN varies within the range of -60 [dBm] to -50 [dBm]. At this time, the output of the first limiting amplifier 512 of the second stage changes linearly relative to the rise of the high-frequency signal RFIN, and the result is reflected in the RSSI output signal ROUT. Specifically, in the above description, the input and output signals of the first limiting amplifier 511 of the first stage and the first limiting amplifier 512 of the second stage both rise by 10 [dB]. Here, the first limiting amplifier 513 of the third stage saturates at an output level of 0 [dBm], therefore the current signal S53 remains constant. Therefore, from the signal level of the high-frequency signal RFIN when it reaches -60 [dBm], the output signal levels of the first limiting amplifier 513 of the third stage to the first limiting amplifier 515 of the fifth stage do not substantially change (refer to...). Figure 7 (The dashed line extending between (iii) and (iv)). Furthermore, since the outputs of the first limiting amplifier 511 and the second limiting amplifiers 811 and 812 in the first stage are small, the current signals S51 and S81 and S82 are also small, thus their influence on the RSSI output signal ROUT can be ignored. Therefore, the sum of the outputs of the first limiting amplifier 512 in the second stage to the first limiting amplifier 515 in the fifth stage is reflected in the RSSI output signal ROUT. Additionally, the linear change in the output of the first limiting amplifier 512 in the second stage of the first signal strength detection circuit 5 relative to the rise of the high-frequency signal RFIN, and the linear change in the current output S52, are also reflected in the RSSI output signal ROUT.

[0056] -Regarding the interval (v)-

[0057] exist Figure 7Within the interval (v), the high-frequency signal RFIN varies within the range of -50 [dBm] to -40 [dBm]. At this time, the output of the first limiting amplifier 511 of the first stage changes linearly relative to the rise of the high-frequency signal RFIN, and the result is reflected in the RSSI output signal ROUT. Specifically, as described in the above paragraph, the input and output signals of the first limiting amplifier 511 of the first stage rise by 10 [dB]. Here, the first limiting amplifier 512 of the second stage saturates at an output level of 0 [dBm], therefore the current signal S52 remains constant. Therefore, from the signal level of the high-frequency signal RFIN when it reaches -50 [dBm], the output signal levels of the first limiting amplifier 512 of the second stage to the first limiting amplifier 515 of the fifth stage do not substantially change (refer to...). Figure 7 (The dashed line extending between (iv) and (v). Furthermore, since the outputs of the second limiting amplifiers 811 and 812 are small, the current signals S81 and S82 are also small, thus their influence on the RSSI output signal ROUT can be ignored. Therefore, the sum of the outputs of the first limiting amplifier 511 of the first stage to the first limiting amplifier 515 of the fifth stage is reflected in the RSSI output signal ROUT. Additionally, the linear change in the output of the first limiting amplifier 511 of the first stage in the first signal strength detection circuit 5 relative to the rise of the high-frequency signal RFIN, and the linear change in the current output S51, are also reflected in the RSSI output signal ROUT.

[0058] -Regarding the interval (vi)-

[0059] exist Figure 7 Within the interval (vi), the high-frequency signal RFIN varies within the range of -40 [dBm] to -30 [dBm]. As described above, the first filter circuit 4 saturates when the IF signal S3 becomes -10 [dBm], that is, it saturates when the high-frequency signal RFIN becomes -40 [dBm]. Therefore, from the point when the signal level of the high-frequency signal RFIN is -40 [dBm], the output signal levels of the first limiting amplifier 511 of the first stage to the first limiting amplifier 515 of the fifth stage do not substantially change.

[0060] On the other hand, a signal attenuated by 20 dB compared to the IF signal S3 is input to the second filter circuit 7. Therefore, the second filter circuit 7 is not saturated, and instead outputs the second filtered signal S7 with a signal level of -30 dBm to -20 dBm to the second signal strength detection circuit 8. In the second signal strength detection circuit 8, the first-stage second limiting amplifier 811 receives the second filtered signal S7, and outputs a signal with a signal level of -20 dBm to -10 dBm. The output signal of the first-stage second limiting amplifier 811 is input to the second-stage second limiting amplifier 812, and outputs a signal with a signal level of -10 dBm to -0 dBm. Here, because the output of the first-stage second limiting amplifier 811 is small, the current signal S81 is also small, thus its influence on the RSSI output signal ROUT can be ignored. Therefore, the output of the sum of the outputs of the second limiting amplifier 812 in the second stage of the second signal strength detection circuit 8 and the first limiting amplifiers 511 through 515 in the first stage of the first signal strength detection circuit 5 is reflected in the RSSI output signal ROUT. Furthermore, the linear change in the output of the second limiting amplifier 812 in the second stage of the second signal strength detection circuit 8 relative to the rise of the high-frequency signal RFIN, and the linear change in the current output S82, are also reflected in the RSSI output signal ROUT.

[0061] -Regarding interval (vii)-

[0062] exist Figure 7 In interval (vii), the high-frequency signal RFIN varies within the range of -30 [dBm] to -20 [dBm]. Figure 7 The interval (vi) is the same. Since the first filter circuit 4 is saturated, the output signal level of the first limiting amplifier 511 of the first stage to the first limiting amplifier 515 of the fifth stage does not change substantially from the signal level of the high-frequency signal RFIN when it is -30 [dBm].

[0063] On the other hand, the second filter circuit 7 is not saturated, but instead outputs the second filtered signal S7 with a signal level of -20 [dBm] to -10 [dBm] to the second signal strength detection circuit 8. As a result, the input and output signals of the first-stage second limiting amplifier 811 rise by 10 [dB]. Therefore, the second-stage second limiting amplifier 812 saturates at an output level of 0 [dBm], and thus the current signal S82 remains constant. Thus, from the point when the high-frequency signal RFIN has a signal level of -30 [dBm], the output signal level of the second-stage second limiting amplifier 812 does not substantially change (refer to...). Figure 7(The dashed line extending between (vi) and (vii). Therefore, the output of the summation of the outputs of the second limiting amplifier 811 of the first stage, the second limiting amplifier 812 of the second stage in the second signal strength detection circuit 8, and the first limiting amplifiers 511 to 515 of the first stage in the first signal strength detection circuit 5 is reflected in the RSSI output signal ROUT. In addition, the linear change in the output of the second limiting amplifier 811 of the first stage in the second signal strength detection circuit 8 relative to the rise of the high-frequency signal RFIN, and the linear change in the current output S81, are also reflected in the RSSI output signal ROUT.

[0064] [Comparison with comparative examples]

[0065] exist Figure 7 In the comparison example shown by the thin solid line, the following is illustrated: Figure 1 An example of a wireless receiving circuit where the second limiting amplifier group 80 is not included, and only the first limiting amplifier group 50 constitutes the wireless receiving circuit. For example... Figure 7 As shown in intervals (i) to (v), by adding current signals equivalent to the signal amplitudes of the first limiting amplifier 511 from the first stage to the first limiting amplifier 515 from the fifth stage, a pseudo-logarithmic RSSI output signal ROUT can be obtained relative to the signal level of the high-frequency signal RFIN. That is, in the wireless receiving circuit of the comparative example, the signal level of the high-frequency signal RFIN changes linearly during the period of variation in the range of -90 [dBm] to -40 [dBm], but if the signal level of the high-frequency signal RFIN is in the range of -40 [dBm] to -20 [dBm], then all of the first limiting amplifiers 511 to 515 are saturated, and thus the RSSI output signal ROUT will also be saturated. In contrast, as described above, the wireless receiving circuit 1 according to this embodiment can obtain an output that changes linearly relative to the signal level of the high-frequency signal RFIN in the range of -90 [dBm] to -20 [dBm].

[0066] Figure 8 In the wireless receiving circuit 1 of the above embodiment ( Figure 1 Simulation results regarding the input-output characteristics of the wireless receiving circuit in the structure of the present embodiment and the structure of the comparative example (structure without the second limiting amplifier group 80). According to the simulation results, in the comparative example, saturation occurs at a signal level of -40 [dBm] for the high-frequency signal RFIN, but by adopting the structure of this embodiment, the dynamic range is expanded by about 20 [dB], and good linearity characteristics can be confirmed.

[0067] Furthermore, in the above embodiment, the gain of the second limiting amplifier group 80 (second limiting amplifier 81 × second stage) and the attenuation of the attenuator 6 are made equal, both being 20 [dB]. This enables signal strength detection where the signal strength detection circuits do not overlap.

[0068] <Variation Example 1>

[0069] Figure 9 This is a block diagram showing the structure of the wireless receiving circuit of Modified Example 1. Here, it is used in conjunction with... Figure 1 The explanation focuses on the differences between them, sometimes omitting the differences between them. Figure 1 Explanation of the common structure.

[0070] exist Figure 9 In the middle, amplifier 12 (equivalent to an amplifier circuit) is set to replace Figure 1 Attenuator 6. Specifically, in Figure 9 In the first signal strength detection circuit, the second filter circuit 7 receives the IF signal S3 output from the mixer 3, filters the IF signal S3, and outputs the filtered signal as the second filtered signal S7 to the second signal strength detection circuit 8. The amplifier 12 receives the IF signal S3 output from the mixer 3 and amplifies it, outputting the amplified signal as the amplified signal S12. The first filter circuit 4 filters the amplified signal S12 output from the amplifier 12, outputting the filtered signal as the first filtered signal S4 to the first signal strength detection circuit 5. Furthermore, when set to be... Figure 1 Under the condition of common characteristics, the sum of the gains of LNA2 and mixer 3 is set to 10 [dB], and the gain of amplifier 12 is set to 20 [dB]. Thus, the same operation as shown in the "Operating Example of Wireless Receiver Circuit" described above can be achieved. Specifically, when the high-frequency signal RFIN varies within the range of -90 [dBm] to -80 [dBm], the signal level of the first filter signal S4 is -60 [dBm] to -50 [dBm]. Furthermore, when the high-frequency signal RFIN reaches -40 [dBm], the first filter circuit 4 is saturated, but the second filter circuit 7 is not saturated. And when the high-frequency signal RFIN varies within the range of -40 [dBm] to -30 [dBm], the signal level of the second filter signal S7 is -30 [dBm] to -20 [dBm].

[0071] As described above, in this modified example 1, the same operation as in the above-described embodiment can also be achieved, thereby obtaining the same effect. Furthermore, by adopting Figure 9 The structure allows the amplifier 12 to improve the noise characteristics of the first filter circuit 4.

[0072] <Variation Example 2>

[0073] Although the above embodiments illustrate an example of a wireless receiving circuit 1 in a wireless system for demodulating ASK modulated signals, the application of the technology disclosed herein is not limited thereto. For example, the wireless receiving circuit 1 can also be used in a wireless system for demodulating QPSK (Quadrature Phase Shift Keying) modulated signals.

[0074] Figure 10 This is a block diagram showing the structure of the wireless receiving circuit in Modified Example 2. Here, it is used in conjunction with... Figure 1 The explanation focuses on the differences between them, sometimes omitting the differences between them. Figure 1 Explanation of the common structure.

[0075] exist Figure 10 In the structure, besides Figure 1 In addition to the structure, it also includes a selector 93 and a DSP (Digital Signal Processor) 92 as a control circuit. The selector 93 accepts the output signal (equivalent to an amplified signal) of the first limiting amplifier 515 of the fifth (final) stage of the first signal strength detection circuit 5 and the output signal (equivalent to an amplified signal) of the second limiting amplifier 812 of the second (final) stage of the second signal strength detection circuit 8, and selects one of them to output. Hereinafter, the output signal of the first limiting amplifier 515 is referred to as the amplified output signal of the first signal strength detection circuit 5, and the output signal of the second limiting amplifier 812 is referred to as the amplified output signal of the second signal strength detection circuit 8.

[0076] DSP92 receives the RSSI output signal ROUT after digital conversion by ADC91 and detects its signal level. Then, based on the signal level of RSSI output signal ROUT, DSP92 controls selector 93 to output the unsaturated amplified output signal from the amplified output signal of the first signal strength detection circuit 5 and the amplified output signal of the second signal strength detection circuit 8. The output signal of selector 93 is converted into a digital signal by ADC94 and demodulated by demodulator 95.

[0077] For example, in the case of QPSK modulation, if the input signal to demodulator 95 is saturated, the signal quality deteriorates, therefore the input signal level needs to be adjusted appropriately. Figure 10 As shown in the structure, based on the RSSI output signal ROUT, the unsaturated amplified output signal is selected from the amplified output signal of the first signal strength detection circuit 5 and the amplified output signal of the second signal strength detection circuit 8, thereby enabling the unsaturated signal with good S / N characteristics to be transmitted to the demodulator 95.

[0078] For example, in the wireless receiving circuit 1, there is Figure 7 Under the condition of the RSSI output signal ROUT, when the signal level is 0.5 [V], the amplified output signal of the second signal strength detection circuit 8 is selected, and when the signal level is below 0.5 [V], the amplified output signal of the first signal strength detection circuit 5 is selected.

[0079] Furthermore, in this modified example, the output signal of the first limiting amplifier 515, the final stage of the first signal strength detection circuit 5, and the output signal of the second limiting amplifier 812, the final stage of the second signal strength detection circuit 8, are selected by the selector, but this configuration is not limited to this. For example, the output signals of unsaturated limiting amplifiers in the first limiting amplifier group 50 and the second limiting amplifier group 80 can also be output from the selector. In this case, based on the RSSI output signal ROUT, the output signal of the appropriate unsaturated limiting amplifier from the plurality of first limiting amplifiers 51 and the plurality of second limiting amplifiers 81 is selected, thereby enabling the transmission of an unsaturated signal with good S / N characteristics to the demodulator. For example, in the wireless receiving circuit 1 having Figure 7 Under the condition of the RSSI output signal ROUT signal level being 0.5 [V], the output of the first limiting amplifier 512 in the second stage of the first limiting amplifier group 50 can be selected.

[0080] <Variation Example 3>

[0081] Figure 11 This is a block diagram showing the structure of the wireless receiving circuit in Modified Example 3. Here, it is used in conjunction with... Figure 10 The explanation focuses on the differences between them, sometimes omitting the differences between them. Figure 10 Explanation of the common structure.

[0082] Figure 11 The structure is in Figure 10 Based on the existing structure, a mixer 98 (equivalent to a second mixer) is included between selector 93 and ADC 94. Mixer 98 receives the output of selector 93 and mixes it with the second local oscillator signal L02 before outputting the result. For example, if the second local oscillator signal L02 is set to approximately 33 [MHz], the output frequency of mixer 98 will be approximately 7 [MHz]. By employing... Figure 11 Such a structure can reduce the signal frequency of the input ADC 94 and demodulator 95, thereby making subsequent signal processing easier.

[0083] -Industry Applicability-

[0084] According to this disclosure, signal strength can be detected at high speed and over a wide dynamic range, and therefore it is useful as a wireless receiving circuit for wireless communication systems such as ETC systems.

[0085] -Symbol Explanation-

[0086] 1. Wireless receiving circuit

[0087] 2 LNA

[0088] 3. Mixer (First Mixer)

[0089] 4 First Filter Circuit

[0090] 5 First signal strength detection circuit

[0091] 50 First Limiting Amplifier Group

[0092] 51 First Limiting Amplifier

[0093] 51A Operational Amplifier (First Amplifier Circuit)

[0094] 52 First Adder (First Detection Circuit)

[0095] 511 Primary First Limiting Amplifier

[0096] 6 Attenuators

[0097] 7 Second Filter Circuit

[0098] 8 Second signal strength detection circuit

[0099] 80 Second Limiting Amplifier Group

[0100] 81 Second Limiting Amplifier

[0101] 82 Second Adder (Second Detection Circuit)

[0102] 811 Primary Secondary Limiting Amplifier

[0103] 12 Amplifier Circuit

[0104] 93 Selector

[0105] 98 Mixer (Second Mixer)

Claims

1. A wireless receiving circuit, characterized in that: include: A low-noise amplifier (LNA) amplifies the input signal; The first mixer receives the output of the low-noise amplifier circuit and mixes the output of the low-noise amplifier circuit with the first local oscillator signal before outputting the result. A first filtering circuit filters the output of the first mixer; A first signal strength detection circuit receives the output of the first filter circuit and detects the signal strength. An attenuator that receives the output of the first mixer and attenuates the output of the first mixer before outputting it; The second filtering circuit filters the output of the attenuator; as well as The second signal strength detection circuit receives the output of the second filtering circuit and detects the signal strength. The signal strength of the input signal is obtained by adding the signal strength detected by the first signal strength detection circuit to the signal strength detected by the second signal strength detection circuit.

2. The wireless receiving circuit according to claim 1, characterized in that: The first signal strength detection circuit includes: A first limiting amplifier group, comprising cascaded first limiting amplifiers whose output amplitude signal is equivalent to the signal amplitude of the input signal, wherein the primary first limiting amplifier receives the output of the first filtering circuit; and A first detection circuit detects the signal strength by summing the amplitude signals output from each of the first limiting amplifiers. The second signal strength detection circuit includes: The second limiting amplifier group is formed by cascading second limiting amplifiers whose output amplitude signal is equivalent to the signal amplitude of the input signal, and the primary second limiting amplifier receives the output of the second filter circuit; and The second detection circuit detects the signal strength by adding the amplitude signals output from each of the second limiting amplifiers.

3. The wireless receiving circuit according to claim 2, characterized in that: The first limiting amplifier includes: A first amplification circuit amplifies the input signal and outputs the amplified signal as a first amplified output signal; and A first converter converts the amplitude of the first amplified output signal into a current and outputs it as the amplitude signal. The second limiting amplifier includes: A second amplifier circuit amplifies the input signal and outputs the amplified signal as a second amplified output signal; and The second converter converts the amplitude of the second amplified output signal into current and outputs it as the amplitude signal.

4. The wireless receiving circuit according to claim 3, characterized in that: The wireless receiving circuit includes a selector that, based on the signal strength detected by the first signal strength detection circuit and the signal strength detected by the second signal strength detection circuit, selects and outputs an unsaturated amplified output signal from the first amplified output signal output from the first limiting amplifier in the final stage of the first limiting amplifier group and the second amplified output signal output from the second limiting amplifier in the final stage of the second limiting amplifier group.

5. The wireless receiving circuit according to claim 3, characterized in that: The wireless receiving circuit includes a selector that, based on the signal strength detected by the first signal strength detection circuit and the signal strength detected by the second signal strength detection circuit, selects and outputs an amplified output signal from an unsaturated limiting amplifier from among the first amplified output signals output from each of the first limiting amplifiers in the first limiting amplifier group and the second amplified output signals output from each of the second limiting amplifiers in the second limiting amplifier group.

6. The wireless receiving circuit according to claim 4, characterized in that: The wireless receiving circuit includes a second mixer, which receives the output of the selector and mixes the output of the selector with a second local oscillator signal before outputting it.

7. The wireless receiving circuit according to claim 2, characterized in that: The gain of the second limiting amplifier group is equal to the attenuation of the attenuator.

8. A wireless receiving circuit, characterized in that: include: A low-noise amplifier (LNA) amplifies the input signal; A first mixer receives the output of the low-noise amplifier circuit and mixes the output of the low-noise amplifier circuit with the local oscillator signal before outputting the result. An amplifier circuit that receives the output of the first mixer and amplifies the output of the first mixer before outputting it; A first filtering circuit filters the output of the amplifier circuit. A first signal strength detection circuit receives the output of the first filter circuit and detects the signal strength. The second filtering circuit filters the output of the first mixer. as well as The second signal strength detection circuit receives the output of the second filtering circuit and detects the signal strength. The signal strength of the input signal is obtained by adding the signal strength detected by the first signal strength detection circuit to the signal strength detected by the second signal strength detection circuit.

9. The wireless receiving circuit according to claim 8, characterized in that: The first signal strength detection circuit includes: A first limiting amplifier group, comprising cascaded first limiting amplifiers whose output amplitude signal is equivalent to the signal amplitude of the input signal, wherein the primary first limiting amplifier receives the output of the first filtering circuit; and A first detection circuit detects the signal strength by summing the amplitude signals output from each of the first limiting amplifiers. The second signal strength detection circuit includes: The second limiting amplifier group is formed by cascading second limiting amplifiers whose output amplitude signal is equivalent to the signal amplitude of the input signal, and the primary second limiting amplifier receives the output of the second filter circuit; and The second detection circuit detects the signal strength by adding the amplitude signals output from each of the second limiting amplifiers.

10. The wireless receiving circuit according to claim 9, characterized in that: The first limiting amplifier includes: A first amplification circuit amplifies the input signal and outputs the amplified signal as a first amplified output signal; and A first converter converts the amplitude of the first amplified output signal into a current and outputs it as the amplitude signal. The second limiting amplifier includes: A second amplifier circuit amplifies the input signal and outputs the amplified signal as a second amplified output signal; and The second converter converts the amplitude of the second amplified output signal into current and outputs it as the amplitude signal.

11. The wireless receiving circuit according to claim 10, characterized in that: The wireless receiving circuit includes a selector that, based on the signal strength detected by the first signal strength detection circuit and the signal strength detected by the second signal strength detection circuit, selects and outputs an unsaturated amplified output signal from the first amplified output signal output from the first limiting amplifier in the final stage of the first limiting amplifier group and the second amplified output signal output from the second limiting amplifier in the final stage of the second limiting amplifier group.

12. The wireless receiving circuit according to claim 10, characterized in that: The wireless receiving circuit includes a selector that, based on the signal strength detected by the first signal strength detection circuit and the signal strength detected by the second signal strength detection circuit, selects and outputs an amplified output signal from an unsaturated limiting amplifier from among the first amplified output signals output from each of the first limiting amplifiers in the first limiting amplifier group and the second amplified output signals output from each of the second limiting amplifiers in the second limiting amplifier group.

13. The wireless receiving circuit according to claim 11, characterized in that: The wireless receiving circuit includes a second mixer, which receives the output of the selector and mixes the output of the selector with a second local oscillator signal before outputting it.

14. The wireless receiving circuit according to claim 9, characterized in that: The gain of the second limiting amplifier group is equal to the gain of the amplifier circuit.

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