Ultrasonic signal sampling circuit, ultrasonic signal sampling method and ultrasonic diagnostic instrument

Abstract

The present application relates to the technical field of ultrasonic signal processing, and discloses an ultrasonic signal sampling circuit, an ultrasonic signal sampling method, and an ultrasonic diagnostic instrument. A signal demodulation module is used to demodulate an ultrasonic echo signal to obtain an orthogonal first-channel ultrasonic signal and a second-channel ultrasonic signal. A voltage regulation module is used to output an adjustable first voltage to a first ADC sampling module, and an adjustable second voltage to a second ADC sampling module, so that the first ADC sampling module samples the first ultrasonic channel signal based on the first voltage to obtain a digital signal of the first channel ultrasonic signal, and the second ADC sampling module samples the second ultrasonic channel signal based on the second voltage to obtain a digital signal of the second channel ultrasonic signal, thereby solving the problem of mirroring in ultrasonic images generated in related technologies.

Description

Technical Field

[0001] The present application relates to the technical field of ultrasonic signal processing, and in particular to an ultrasonic signal sampling circuit, an ultrasonic signal sampling method and an ultrasonic diagnostic instrument. Background Art

[0002] In related technologies, after demodulating the ultrasonic echo signal, I / Q (In-Phase / Quadrature) channel signals reflecting Doppler frequency deviation information are obtained. These I / Q channel signals are then sampled and processed through analog-to-digital conversion. The processed digital signals are then sent to a host computer, where they are calculated and generated into the corresponding ultrasonic image. The input voltage of the analog-to-digital conversion device is a fixed voltage.

[0003] Typically, a host computer uses the I- and Q-channel signals to obtain the echo amplitude and frequency deviation of an ultrasonic echo signal. For example, when examining a patient's cardiac blood flow using an ultrasound diagnostic device, the velocity and intensity of the blood flow can be determined based on these echo amplitude and frequency deviation information. However, the ultrasound images produced by these technologies suffer from image artifacts, hindering doctors' ability to accurately determine the patient's true blood flow status. Summary of the Invention

[0004] The embodiments of the present application provide an ultrasonic signal sampling circuit, an ultrasonic signal sampling method, and an ultrasonic diagnostic instrument, thereby solving the problem of mirror images in ultrasonic images generated in the related art.

[0005] In a first aspect, an embodiment of the present application provides an ultrasonic signal sampling circuit, comprising: a signal demodulation module, a first analog-to-digital conversion ADC sampling module, a second analog-to-digital conversion ADC sampling module, and a voltage regulation module;

[0006] The signal demodulation module is used to demodulate the ultrasonic echo signal to obtain an orthogonal first channel ultrasonic signal and a second channel ultrasonic signal;

[0007] The voltage regulating module is configured to output an adjustable first voltage to the first ADC sampling module, and output an adjustable second voltage to the second ADC sampling module;

[0008] The first ADC sampling module is configured to sample the first channel ultrasonic signal based on the first voltage to obtain a digital signal of the first channel ultrasonic signal;

[0009] The second ADC sampling module is used to sample the second channel ultrasonic signal based on the second voltage to obtain a digital signal of the second channel ultrasonic signal.

[0010] In some possible embodiments, the voltage regulating module includes: a first voltage regulating unit and a second voltage regulating unit;

[0011] The first voltage regulating unit is configured to output the adjustable first voltage to the first ADC sampling module;

[0012] The second voltage regulating unit is configured to output the adjustable second voltage to the second ADC sampling module.

[0013] In some possible embodiments, the first voltage regulating unit includes: a first digital-to-analog conversion DAC unit and a first low-noise operational amplifier unit;

[0014] The first DAC unit is used to output a first analog signal to the first low-noise operational amplifier unit;

[0015] The first low-noise operational amplifier unit is configured to output the first voltage by utilizing a proportional relationship between the first analog signal and the first voltage;

[0016] The second voltage regulating unit includes: a second digital-to-analog conversion DAC unit and a second low-noise operational amplifier unit;

[0017] The second DAC unit is used to output a second analog signal to the second low-noise operational amplifier unit;

[0018] The second low-noise operational amplifier unit is configured to output the second voltage by utilizing a proportional relationship between the second analog signal and the second voltage.

[0019] In some possible embodiments, the first DAC unit is a current-mode DAC chip or a voltage-mode DAC chip, and the second DAC unit is a current-mode DAC chip or a voltage-mode DAC chip.

[0020] In some possible embodiments, the circuit further includes a memory for storing a first preset logic control word corresponding to the first voltage and a second preset logic control word corresponding to the second voltage;

[0021] The voltage regulation module is specifically configured to read the first preset logic control word and the second preset logic control word from the memory, and output the first voltage to the first ADC sampling module based on the first preset logic control word, and output the second voltage to the second ADC sampling module based on the second preset logic control word.

[0022] In a second aspect, an embodiment of the present application provides an ultrasonic signal sampling method, the method comprising:

[0023] Demodulating the ultrasonic echo signal to obtain an orthogonal first channel ultrasonic signal and a second channel ultrasonic signal;

[0024] Based on an adjustable first voltage, the first channel ultrasonic signal is analog-to-digital converted to obtain a digital signal of the first channel ultrasonic signal; and based on an adjustable second voltage, the second channel ultrasonic signal is analog-to-digital converted to obtain a digital signal of the second channel ultrasonic signal.

[0025] In some possible embodiments, determining the first voltage includes:

[0026] Performing analog-to-digital conversion on the first channel ultrasonic signal using a first initial voltage to obtain a first test value;

[0027] Adjusting the first initial voltage until the difference between the first test value and the first preset digital signal is within a preset threshold range, thereby obtaining the first voltage;

[0028] Determining the second voltage includes:

[0029] Performing analog-to-digital conversion on the second channel ultrasonic signal using a second initial voltage to obtain a second test value;

[0030] The second initial voltage is adjusted until the difference between the second test value and the second preset digital signal is within the preset threshold range, thereby obtaining the second voltage.

[0031] In some possible embodiments, adjusting the first initial voltage includes:

[0032] If the first test value is greater than the first preset digital signal, increasing the first initial voltage;

[0033] If the first test value is less than the first preset digital signal, reducing the first initial voltage;

[0034] The adjusting the second initial voltage includes:

[0035] If the second test value is greater than the second preset digital signal, increasing the second initial voltage;

[0036] If the second test value is smaller than the second preset digital signal, the second initial voltage is reduced.

[0037] In some possible embodiments, the first initial voltage is increased or decreased by the following method:

[0038] increasing the first initial voltage by increasing the first preset logic control word bit by bit;

[0039] reducing the first initial voltage by decreasing the first preset logic control word bit by bit;

[0040] Increase or decrease the second initial voltage by:

[0041] increasing the second initial voltage by increasing the second preset logic control word bit by bit;

[0042] The second initial voltage is reduced by decreasing the second preset logic control word bit by bit.

[0043] In some possible embodiments, adjusting the first initial voltage includes: adjusting the first initial voltage using a dichotomy method;

[0044] The adjusting the second initial voltage includes: adjusting the second initial voltage by adopting a dichotomy method.

[0045] In a third aspect, an embodiment of the present application provides an ultrasonic diagnostic apparatus, comprising: a probe, a display unit, a processor, and an ultrasonic signal sampling circuit as described in any one of the first aspects;

[0046] The probe is used to transmit ultrasonic beams and receive ultrasonic echo signals;

[0047] The processor is configured to send a digital signal to a host computer and receive an ultrasonic image sent by the host computer; the digital signal is obtained by the ultrasonic signal sampling circuit;

[0048] The display unit is used to display the ultrasound image.

[0049] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, which, when the instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to execute any of the methods provided in the second aspect of the present application.

[0050] In a fifth aspect, an embodiment of the present application provides a computer program product, comprising a computer program / instruction, which, when executed by a processor, implements any of the methods provided in the second aspect of the present application.

[0051] The technical solutions provided by the embodiments of this application bring at least the following beneficial effects:

[0052] The present application proposes an ultrasonic signal sampling circuit, which demodulates an ultrasonic echo signal through a signal demodulation module to obtain an orthogonal first-channel ultrasonic signal and a second-channel ultrasonic signal, and uses a voltage regulation module to output an adjustable first voltage to a first ADC sampling module, and outputs an adjustable second voltage to a second ADC sampling module, so that the first ADC sampling module samples the first ultrasonic channel signal based on the first voltage to obtain a digital signal of the first channel ultrasonic signal, and the second ADC sampling module samples the second ultrasonic channel signal based on the second voltage to obtain a digital signal of the second channel ultrasonic signal.

[0053] The present application outputs an adjustable first voltage and an adjustable second voltage through a voltage regulation module, and then samples the first channel ultrasonic signal and the second channel ultrasonic signal based on the adjusted first voltage and second voltage, thereby reducing the problem of different ultrasonic echo amplitudes caused by the discreteness of device parameters, and thus solving the problem of mirror images in ultrasonic images.

[0054] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. The purposes and other advantages of the present application can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. Obviously, the drawings introduced below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0056] Figure 1 A schematic diagram of transmitting an ultrasonic beam to blood flowing in a blood vessel according to an embodiment of the present application;

[0057] Figure 2 A schematic diagram of an ultrasonic signal sampling circuit in the related art provided in one embodiment of the present application;

[0058] Figure 3 A schematic diagram of an ultrasonic signal sampling circuit in the related art provided in one embodiment of the present application;

[0059] Figure 4 A schematic diagram of a composite signal provided by an embodiment of the present application in which the relative amplitude error of two-channel ultrasonic signals is small and the image frequency is not obvious;

[0060] Figure 5A schematic diagram of an ultrasound image provided by an embodiment of the present application in which the relative amplitude error of the two-channel ultrasound signals is small and the mirror image frequency is not obvious;

[0061] Figure 6 A schematic diagram of a composite signal provided by an embodiment of the present application in which the relative amplitude error of two-channel ultrasonic signals is large and the image frequency is obvious;

[0062] Figure 7 A schematic diagram of an ultrasound image provided by an embodiment of the present application in which the relative amplitude error of the two-channel ultrasound signals is large and the mirror image frequency is obvious;

[0063] Figure 8 A schematic diagram of an ultrasonic signal sampling circuit provided in one embodiment of the present application;

[0064] Figure 9 A schematic diagram of the internal structure of a first ADC sampling module provided in one embodiment of the present application;

[0065] Figure 10 The analog voltage value difference provided by an embodiment of the present application is 2 N Schematic diagram of the corresponding relationship between voltage values;

[0066] Figure 11 A schematic diagram of the connection relationship between a current-mode DAC chip and a low-noise operational amplifier chip provided in one embodiment of the present application;

[0067] Figure 12 A flowchart of a first voltage calibration provided in an embodiment of the present application;

[0068] Figure 13 A hardware configuration block diagram of an ultrasonic diagnostic instrument provided in one embodiment of the present application;

[0069] Figure 14 A schematic diagram of the application principle provided in one embodiment of the present application. DETAILED DESCRIPTION

[0070] The following will clearly and thoroughly describe the technical solutions in the embodiments of the present application in conjunction with the accompanying drawings. In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in the text is only a description of the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, "multiple" means two or more than two.

[0071] In the description of the embodiments of the present application, unless otherwise specified, the term "multiple" refers to two or more, and other quantifiers should be understood similarly. The preferred embodiments described herein are only used to illustrate and explain the present application and are not used to limit the present application. In addition, the embodiments of the present application and the features in the embodiments may be combined with each other if there is no conflict.

[0072] All other embodiments derived by persons of ordinary skill in the art based on the exemplary embodiments described herein without inventive effort are within the scope of protection of the claims appended hereto. Furthermore, although the disclosure herein is presented based on one or more exemplary embodiments, it should be understood that each aspect of the disclosure may constitute a complete embodiment on its own.

[0073] It should be noted that the brief descriptions of terms in this application are only for the purpose of facilitating the understanding of the embodiments described below, and are not intended to limit the embodiments of this application. Unless otherwise specified, these terms should be understood according to their ordinary and usual meanings.

[0074] In the specification and claims of this application and the drawings, the terms "first," "second," "third," etc. are used to distinguish similar or similar objects or entities, and are not necessarily intended to limit a particular order or precedence, unless otherwise indicated. It should be understood that the terms used in this manner are interchangeable under appropriate circumstances, for example, the embodiments of this application can be implemented in an order other than those shown or described in the drawings.

[0075] In addition, the terms "comprises" and "comprising" and any variations thereof are intended to cover but not exclude inclusion, for example, a product or device comprising a list of components is not necessarily limited to those components expressly listed but may include other components not expressly listed or inherent to such product or device.

[0076] To further illustrate the technical solutions provided by the embodiments of the present application, this is described in detail below in conjunction with the accompanying drawings and specific implementation methods. Although the embodiments of the present application provide the method operation steps as shown in the following embodiments or drawings, more or fewer operation steps may be included in the method based on routine or no creative labor. In steps where there is no necessary causal relationship logically, the execution order of these steps is not limited to the execution order provided by the embodiments of the present application. During the actual processing process or when the control device is executed, the method can be executed in the order of the methods shown in the embodiments or drawings or in parallel.

[0077] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. The purposes and other advantages of the present application can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings.

[0078] In the specific practice, the working principle of using ultrasound diagnostic equipment to check the patient's heart blood flow status is as follows: Figure 1 As shown in the figure, a schematic diagram of the probe transmitting an ultrasonic beam to the blood flowing in the blood vessel is shown. Assume that the signal frequency of the ultrasonic beam transmitted by the probe is F0, and the signal frequency of the ultrasonic echo signal is F0+F d , the blood velocity flowing in the blood vessels is V, and the angle between the ultrasonic beam and the blood velocity is θ. According to the Doppler principle, the blood flow velocity V can be expressed by formula 1.

[0079] V=(C*F d )(2 F0*cosθ) Formula 1

[0080] Where C represents the transmission speed of the ultrasonic beam in the human body, which is 1540 m / s, and F0 is a known value. θ can be measured in the ultrasound image. If F is determined, d The blood flow velocity can be calculated according to Formula 1.

[0081] In related technologies, such as Figure 2 As shown, the ultrasonic echo signal is demodulated by the signal demodulation module 101. During the demodulation process, the Doppler principle is used to demodulate the Doppler frequency deviation signal carrying blood flow velocity information, namely the first channel ultrasonic signal (I channel signal) and the second channel ultrasonic signal (Q channel signal), which are orthogonal in a mathematical sense. The first channel ultrasonic signal is then output to the first gain module 102, where signal filtering and gain amplification processing are performed. The processed first channel ultrasonic signal is then output to the first ADC (Analog-to-Digital Converter) sampling module 103. The second channel ultrasonic signal is output to the second gain module 104, where signal filtering and gain amplification processing are performed. The processed second channel ultrasonic signal is then output to the second ADC sampling module 105.

[0082] In the first ADC sampling module 103, the processed first-channel ultrasound signal is sampled based on the input first fixed voltage to obtain a digital signal of the first-channel ultrasound signal. In the second ADC sampling module 105, the processed second-channel ultrasound signal is sampled based on the input second fixed voltage to obtain a digital signal of the second-channel ultrasound signal. Here, the first fixed voltage and the second fixed voltage may or may not share the same voltage source, and this is not limited here.

[0083] The digital signal of the first channel ultrasound signal and the digital signal of the second channel ultrasound signal are output to the host computer 106 , and the host computer 106 calculates the patient's blood flow velocity and intensity according to the digital signals.

[0084] Among them, Figure 3 As shown, the signal demodulation module 101 may also include low-noise amplifiers 1, ..., low-noise amplifiers n, voltage-current converters 1, ..., voltage-current converter n, mixers 1, mixers 2, ..., mixers 2n, summing amplifiers 1, summing amplifiers 2, and a clock distribution circuit 1. Each ultrasonic echo signal corresponds to one low-noise amplifier, one voltage-current converter, two mixers, and two clock control signals. After passing through the clock distribution circuit 1, clock 1 distributes clock 1a to mixer 1 and clock 1b to mixer 2. Mixer 1 receives the first channel ultrasonic signal, while mixer 2 receives the second channel ultrasonic signal.

[0085] The first gain module 102 may further include a first signal filtering unit 1021 and a first gain amplification unit 1022. The first signal filtering unit 1021 is configured to perform signal filtering on the first channel ultrasonic signal and output the filtered signal to the first gain amplification unit 1022; the first gain amplification unit 1022 is configured to perform gain amplification processing on the filtered first channel ultrasonic signal.

[0086] The second gain module 104 may further include a second signal filtering unit 1041 and a second gain amplifying unit 1042. The second signal filtering unit 1041 is configured to perform signal filtering on the second channel ultrasonic signal and output the filtered signal to the second gain amplifying unit 1042. The second gain amplifying unit 1042 is configured to perform gain amplification processing on the filtered second channel ultrasonic signal.

[0087] Generally, the Doppler frequency deviation signal (i.e., the patient's blood flow velocity and intensity) is reflected by the two parameters of the phase and relative amplitude (i.e., the difference between the amplitudes of the two ultrasonic signals) of the first channel ultrasonic signal and the second channel ultrasonic signal. Since the actual parameters of the devices used in the above-mentioned modules deviate from the standard parameters of the devices, that is, there is a problem of parameter discreteness, the calculated phase and relative amplitude of the first channel ultrasonic signal and the second channel ultrasonic signal respectively have errors with their corresponding standard values. When the error is large, it will cause a mirror image problem in the ultrasonic image generated by the host computer 106, thereby affecting the doctor's judgment of the patient's true blood flow condition based on the ultrasonic image.

[0088] For example, assuming that the relative amplitude error between the first channel ultrasonic signal and the second channel ultrasonic signal is K, the amplitude I(t) of the first channel ultrasonic signal is expressed by Formula 2, the amplitude Q(t) of the second channel ultrasonic signal is expressed by Formula 3, and the amplitude X(t) of the composite signal of the first channel ultrasonic signal and the second channel ultrasonic signal in the host computer 106 is expressed by Formula 4.

[0089] I(t)=cos(ωt) Formula 2

[0090] Q(t)=(1+K)sin(ωt) Formula 3

[0091] X(t)=I(t)+Q(t)=cos(ωt)+j(1+K)sin(ωt)=(1+K / 2)e jωt -(K / 2)e j(-ω)t Formula 4

[0092] Wherein, ω represents angular frequency, t represents time, cos(ωt) represents cosine, sin(ωt) represents sine, j represents a complex number, and e represents the base of natural logarithm.

[0093] It can be seen from the above formula 4 that due to the relative amplitude error between the first channel ultrasonic signal and the second channel ultrasonic signal, the image frequency -ω is generated. If the relative amplitude error K between the first channel ultrasonic signal and the second channel ultrasonic signal is 0, no image frequency is generated.

[0094] like Figure 4 The figure shows a schematic diagram of a composite signal where the relative amplitude error between the first-channel and second-channel ultrasonic signals is small and the image frequency is not noticeable. The vertical axis represents the blood flow velocity in centimeters per second (cm / s), and the positive and negative half-axes represent the direction of blood flow. For example, when the probe transmits an ultrasonic beam toward blood flowing in a blood vessel, the direction toward the probe is defined as the positive half-axis, while the direction away from the probe is defined as the negative half-axis. This is merely an example and can be adjusted based on actual application.

[0095] Figure 5 The figure shows a schematic diagram of an ultrasound image in which the relative amplitude error between the first channel ultrasound signal and the second channel ultrasound signal is small and the mirror image frequency is not obvious. The figure is a normal ultrasound image of the mitral valve blood flow. Figure 4 The same, no longer repeated here.

[0096] When image frequencies are generated, the generated ultrasound image will be distorted. Figure 6 As shown, it shows a schematic diagram of a composite signal when the relative amplitude error between the first channel ultrasonic signal and the second channel ultrasonic signal is large and the mirror image frequency is obvious. Figure 4 It can be seen that Figure 6 The closed curve in the figure is the error composite signal generated by the mirror frequency. Figure 4 The same, no longer repeated here.

[0097] Figure 7 The figure shows a schematic diagram of an ultrasound image when the relative amplitude error between the first channel ultrasound signal and the second channel ultrasound signal is large and the mirror image frequency is obvious. The figure shows the ultrasound image of the mitral valve blood flow when the mirror image frequency is obvious, and the positive and negative semi-axes relative to the vertical coordinate are symmetrical. Figure 4 The same, no longer repeated here.

[0098] In summary, due to the discrete nature of the parameters of each component, the phase and relative amplitude of the first-channel and second-channel ultrasound signals may differ from their respective standard values. This in turn generates image frequencies, distorting the ultrasound image and affecting the doctor's understanding of the patient's true condition. However, phase error is primarily determined by the design of the mixer in the signal demodulation module and is a circuit performance issue within the module. The currently used signal demodulation module can keep the phase error within a specified error range.

[0099] Since the relative amplitude error is related to the link design of the first channel ultrasonic signal and the second channel ultrasonic signal, even if the related art uses a device with high discrete precision to reduce the relative amplitude error, Figure 6 As shown, the composite signal generated by the mirror frequency still exists objectively. Therefore, the present application provides an ultrasonic signal sampling circuit, which reduces the relative amplitude error, improves the accuracy of signal sampling, and thus solves the problem of mirror images in the ultrasonic images generated in the related art.

[0100] like Figure 8 As shown, an ultrasonic signal sampling circuit provided by the present application is shown. Figure 3Based on the circuit structure shown, the circuit further includes a voltage regulation module 107, which is configured to output an adjustable first voltage to the first ADC sampling module 103, and output an adjustable second voltage to the second ADC sampling module 105. The first ADC sampling module 103 is configured to sample the first channel ultrasound signal based on the first voltage to obtain a digital signal of the first channel ultrasound signal; and the second ADC sampling module 105 is configured to sample the second channel ultrasound signal based on the second voltage to obtain a digital signal of the second channel ultrasound signal.

[0101] By adding the voltage regulation module 107, the first ADC sampling module 103 and the second ADC sampling module 105 can more accurately sample the signal based on the adjustable voltage output by the voltage regulation module 107, thereby obtaining a more accurate digital signal. When the digital signal is output to the host computer, the ultrasound image generated by the present application avoids the mirroring problem compared to the related art in which the digital signal is generated based on fixed voltage sampling and output to the host computer.

[0102] The voltage regulating module 107 may further include: a first voltage regulating unit 1071 and a second voltage regulating unit 1072. The first voltage regulating unit 1071 is configured to output an adjustable first voltage to the first ADC sampling module 103; the second voltage regulating unit 1072 is configured to output an adjustable second voltage to the second ADC sampling module 105.

[0103] Because the first channel ultrasonic signal and the second channel ultrasonic signal are two parallel independent channel signals, voltage adjustment of the two channels can be performed separately to achieve more accurate adjustment. That is, the first voltage adjustment unit 1071 is used to determine the adjustable first voltage, and the second voltage adjustment unit 1072 is used to determine the adjustable second voltage. By adjusting the first voltage and the second voltage separately, more accurate first and second voltages can be obtained.

[0104] In addition, the first voltage regulating unit 1071 may further include: a first digital-to-analog converter (DAC) unit 10711 and a first low-noise operational amplifier unit 10712. The first DAC unit 10711 is configured to output a first analog signal to the first low-noise operational amplifier unit 10712; the first low-noise operational amplifier unit 10712 is configured to output the first voltage based on the proportional relationship between the first analog signal and the first voltage.

[0105] Similarly, the second voltage regulating unit 1072 may further include a second digital-to-analog converter (DAC) unit 10721 and a second low-noise operational amplifier (OPA) unit 10722. The second DAC unit 10721 is configured to output a second analog signal to the second low-noise operational amplifier 10722; the second low-noise operational amplifier 10722 is configured to output the second voltage based on the proportional relationship between the second analog signal and the second voltage.

[0106] The specific device models of the first digital-to-analog conversion DAC unit 10711 , the first low-noise operational amplifier unit 10712 , the second digital-to-analog conversion DAC unit 10721 , and the second low-noise operational amplifier unit 10722 are not limited here and can be adjusted according to actual applications.

[0107] By processing the first analog signal by first digital-to-analog converter DAC unit 10711 and first low-noise operational amplifier unit 10712, a more accurate first voltage can be obtained. By processing the second analog signal by second digital-to-analog converter DAC unit 10721 and second low-noise operational amplifier unit 10722, a more accurate second voltage can be obtained. Furthermore, first low-noise operational amplifier unit 10712 and second low-noise operational amplifier unit 10722 can effectively drive a load, making the output first and second voltages more stable and reducing electrical noise.

[0108] Here, the first DAC unit 10711 is a current-mode DAC chip or a voltage-mode DAC chip, and the second DAC unit 10721 is a current-mode DAC chip or a voltage-mode DAC chip. The specific chip model is not limited here and can be adjusted according to actual application. By setting the specific device composition of the first DAC unit 10711 and the second DAC unit 10721, the first analog signal and the second analog signal can be more accurately processed.

[0109] The circuit also includes a memory 108 for storing a first preset logic control word corresponding to the first voltage and a second preset logic control word corresponding to the second voltage. The voltage adjustment module 107 reads the first preset logic control word and the second preset logic control word from the memory 108 and outputs the first voltage to the first ADC sampling module 103 based on the first preset logic control word and outputs the second voltage to the second ADC sampling module 105 based on the second preset logic control word. The memory 108 may be a rewritable memory.

[0110] By setting the memory 108 to store the adjusted first preset logic control word and the second preset logic control word, the first preset logic control word and the second preset logic control word can be directly obtained when the ultrasonic echo signal is processed again, without the need to adjust the first voltage and the second voltage again, thereby reducing the amount of calculation.

[0111] After introducing the circuit connection structure of the ultrasonic signal sampling circuit, the ultrasonic signal sampling method is introduced next, which specifically includes the following steps:

[0112] A1, performing signal demodulation on the ultrasonic echo signal to obtain an orthogonal first channel ultrasonic signal and a second channel ultrasonic signal;

[0113] A2, based on the adjustable first voltage, performs analog-to-digital conversion on the first channel ultrasonic signal to obtain a digital signal of the first channel ultrasonic signal; and, based on the adjustable second voltage, performs analog-to-digital conversion on the second channel ultrasonic signal to obtain a digital signal of the second channel ultrasonic signal.

[0114] By sampling the first channel ultrasonic signal and the second channel ultrasonic signal separately based on an adjustable first voltage and an adjustable second voltage, compared with the prior art in which the first channel ultrasonic signal and the second channel ultrasonic signal can only be sampled separately by a fixed voltage, the error caused by the discreteness of the device can be reduced, thereby obtaining a more accurate digital signal.

[0115] Next, the above-mentioned ultrasonic signal sampling method is introduced in three parts, including: 1. Determining a first preset digital signal and a second preset digital signal, 2. Determining a first voltage and a second voltage, 3. Calibrating the first preset digital signal and the first test value, and calibrating the second preset digital signal and the second test value.

[0116] 1. Determine the first preset digital signal and the second preset digital signal

[0117] Describe the ultrasonic echo signal in the frequency domain. Assume that the ultrasonic echo signal is expressed as A*sin[(ω0+ω d )*t], where A represents the signal amplitude, ω0 represents the angular frequency of the carrier, and ω d Represents the angular frequency of the Doppler shift. If (4 / π)*sin(ω0t) and (4 / π)*cos(ω0t) are multiplied by the expression for the ultrasonic echo signal, the following equations 5 and 6 are obtained.

[0118] A*sin[(ω0+ω d )*t]*(4 / π)*sin(ω0t)=(2 / π)A[cos(ω d t)-cos(2ω0+ω d )]Formula 5

[0119] A*sin[(ω0+ω d )*t]*(4 / π)*cos(ω0t)=(2 / π)A[sin(ω d t)+sin(2ω0+ω d )]Formula 6

[0120] After the signals in Formula 5 and Formula 6 are input to the low-pass filter, the high-frequency signal part 2ω0+ω in Formula 5 and Formula 6 is filtered out. d , we get the Doppler frequency deviation ω d The low-frequency signal part of the first channel ultrasonic signal and the second channel ultrasonic signal. d Then, in the host computer 106, the above formula 1 and F d =2πω d You can know the speed of blood flow.

[0121] The first channel ultrasonic signal and the second channel ultrasonic signal are output to the first ADC sampling module 103 and the second ADC sampling module 105 respectively, to obtain a first preset digital signal output by the first ADC sampling module 103 and a second preset digital signal output by the second ADC sampling module 105.

[0122] The process of the first ADC sampling module 103 outputting the first preset digital signal is taken as an example for description:

[0123] Assume that the internal structure of the first ADC sampling module 103 is as follows Figure 9 As shown, the first channel ultrasonic signal is divided in frequency by the first gain amplifier unit 1022 to generate a third channel ultrasonic signal and a fourth channel ultrasonic signal. Therefore, one of the third channel ultrasonic signal and the fourth channel ultrasonic signal is input to pin 9, and the other is input to pin 10. Furthermore, the input voltage value corresponding to the first ADC sampling module 103 is input to pin 3. The corresponding first preset digital signal is output via pins 19 and 20.

[0124] Figure 9Pin 1 represents the conversion start flag CONVST, pin 2 represents the chip register reset signal RST, pin 3 represents the reference voltage input REFIN, pin 4 represents the reference voltage "ground" REFM-4, pin 5 represents the chip internal reference voltage REFBUFOUT, pin 6 represents no connection NC, pin 7 represents the chip internal reference voltage REFP, pin 8 represents the reference voltage "ground" REFM-8, pin 9 represents the analog input signal AINP, pin 10 represents the analog input signal AINM, pin 11 represents the chip power supply "ground" GND-11, pin 12 represents the analog power supply RVDD, pin 13 represents the chip power supply Electrical filter DECAP-13, pin 14 represents the chip power supply filter DECAP-14, pin 15 represents the chip power supply "ground" GND-15, pin 16 represents the chip digital interface power supply DVDD, pin 17 represents the conversion data output 3 SDO-3, pin 18 represents the conversion data output 2 SDO-2, pin 19 represents the conversion data output 1 SDO-1, pin 20 represents the conversion data output 0 SDO-0, pin 21 represents the multi-function digital output RVS, pin 22 represents the serial port data input SDI, pin 23 represents the serial port clock input SCLK, pin 24 represents the chip enable chip select signal CS, pin 25 represents no connection EP.

[0125] Assuming that the number of bits of resolution in the first ADC sampling module 103 is N, where N is a positive integer, the analog voltage difference between the third channel ultrasonic signal and the fourth channel ultrasonic signal is U, and the input voltage value corresponding to the first ADC sampling module 103 is V_REF, the converted first preset digital signal is obtained by Formula 7:

[0126] First preset digital signal = U*2 N-1 / V_REF Formula 7

[0127] Specifically, (-V_REF, V_REF) is divided into 2 N Equal parts, such as Figure 10 As shown, the analog voltage difference U and 2 N The voltage values are compared and the closest voltage value is selected as the output digital signal. Figure 10 The vertical axis represents 2 N Voltage value, that is (-2 N-1 , 2 N-1 ), the horizontal axis represents the analog voltage difference U, and its unit is LSB, for example -2 N-1 The corresponding U is 1-V_REF, 2 N-1 The corresponding U is -1+V_REF.

[0128] The process of the second ADC sampling module 105 outputting the second preset digital signal may refer to the process of the first ADC sampling module 103 outputting the first preset digital signal, which will not be described in detail here.

[0129] 2. Determine the first voltage and the second voltage

[0130] Taking the first DAC unit 10711 as a current-mode DAC chip as an example, the first voltage is determined by the following steps:

[0131] B1, performing analog-to-digital conversion on the first channel ultrasonic signal using a first initial voltage to obtain a first test value;

[0132] B2. Adjust the first initial voltage until the difference between the first test value and the first preset digital signal is within a preset threshold range, thereby obtaining a first voltage.

[0133] For example, since the input voltage value corresponding to the first ADC sampling module 103 is within a specified voltage value range, a voltage within the specified voltage value range is selected as the first initial voltage, such as Figure 11 Figure 1 shows a schematic diagram of the connection between a current-mode DAC chip and a low-noise op amp chip. By writing any logic control input bit to the current-mode DAC chip, the output voltage corresponding to that logic control input bit can be obtained. Therefore, after determining the first initial voltage, the logic control input bit corresponding to the first initial voltage can be determined by calculation. The first initial voltage can then be adjusted by adjusting the logic control input bit.

[0134] Specifically, pins 1 to 10 of the current mode DAC chip are logic control input bits, and pin 22 is the current value I output by the current mode DAC chip. OUT1 , when the current flows through the resistor R1, the output voltage V +IN At the same time, the voltage V +IN As the input of pin 4 of the low noise operational amplifier chip, the low noise operational amplifier chip forms a common-mode proportional amplifier circuit through resistors R2 and R3. Therefore, pin 6 of the low noise operational amplifier chip, that is, the output first voltage and the voltage V of pin 4 +IN The input relationship is expressed by formula 8. Again, V +IN =I OUT1* R1, the first voltage and V +IN The input relationship can also be expressed by Formula 9.

[0135] First voltage = ((R2+R3) / R2)*V +IN Formula 8

[0136] First voltage = ((R2+R3) / R2)*I OUT1* R1 Formula 9

[0137] Figure 11 Pin 1 of the medium current DAC chip represents D9, which is the 9th bit of the logic control input bit. Pin 2 represents D8, which is the 8th bit of the logic control input bit. Pin 3 represents D7, which is the 7th bit of the logic control input bit. Pin 4 represents D6, which is the 6th bit of the logic control input bit. Pin 5 represents D5, which is the 5th bit of the logic control input bit. Pin 6 represents D4, which is the 4th bit of the logic control input bit. Pin 7 represents D3, which is the 3rd bit of the logic control input bit. Pin 8 represents D2, which is the 2nd bit of the logic control input bit. Pin 9 represents D1, which is the 1st bit of the logic control input bit. Pin 10 represents D0, which is the 0th bit of the logic control input bit. Pin 11 represents no connection NC-11. Pin 12 represents no connection NC-12. Pin 13 represents no connection NC-13. Pin 14 represents There is no connection NC-14, pin 15 represents the chip sleep control SLEEP, pin 16 represents the internal "reference ground" of the chip EXTLO, pin 17 represents the external reference input EXTIO, pin 18 represents the full-scale output current bias BIASJ, pin 19 represents the internal decoupling COMP1 of the chip, pin 20 represents the chip analog "ground" AGND, pin 21 represents the DAC output port 2 IOUT2, pin 22 represents the DAC output port 1 IOUT1, pin 23 represents the internal decoupling COMP2 of the chip, pin 24 represents the chip analog power input AVDD, pin 25 represents the timing mode selection MODE, pin 26 represents the chip digital "ground" DGND, pin 27 represents the chip digital power input DVDD, pin 28 represents the conversion reference clock input CLK.

[0138] Pin 1 of the low-noise op amp chip indicates no connection NC1, pin 2 indicates the inverting input -IN, pin 3 indicates the non-inverting input, i.e. +IN, pin 4 indicates the chip power supply -, i.e. V-, pin 5 indicates no connection NC5, pin 6 indicates the low-noise amplifier output OUT, pin 7 indicates the chip power supply +, i.e. V+, and pin 8 indicates no connection NC8.

[0139] Similarly, the second voltage is determined specifically by the following steps:

[0140] C1, performing analog-to-digital conversion on the second channel ultrasonic signal using the second initial voltage to obtain a second test value;

[0141] C2, adjust the second initial voltage until the difference between the second test value and the second preset digital signal is within a preset threshold range, thereby obtaining a second voltage.

[0142] The specific execution process of determining the second voltage may refer to the execution process of determining the first voltage, which will not be repeated here.

[0143] By adjusting the first initial voltage and the second initial voltage, the final first voltage and the second voltage are determined, so that the signal can be sampled more accurately based on the final first voltage and the second voltage, thereby obtaining a more accurate digital signal.

[0144] 3. Calibrate the First Preset Digital Signal and the First Test Value, and Calibrate the Second Preset Digital Signal and the Second Test Value

[0145] After determining the first preset digital signal, the second preset digital signal, the first voltage, and the second voltage, and using the first voltage and the second voltage to obtain the first test value and the second test value, if the first test value is greater than the first preset digital signal, the first initial voltage is increased; if the first test value is less than the first preset digital signal, the first initial voltage is reduced.

[0146] Likewise, if the second test value is greater than the second preset digital signal, the second initial voltage is increased; if the second test value is less than the second preset digital signal, the second initial voltage is decreased.

[0147] By comparing the first preset digital signal with the first test value determined according to the first initial voltage, and comparing the second preset digital signal with the second test value determined according to the second initial voltage, the first initial voltage and the second initial voltage are adjusted more accurately, and finally more accurate first voltage and second voltage are obtained.

[0148] In one embodiment of the present application, the first initial voltage is increased or decreased by the following method:

[0149] The first initial voltage is increased by increasing the first preset logic control word bit by bit; and the first initial voltage is decreased by decreasing the first preset logic control word bit by bit.

[0150] For example, the first preset logic control word corresponding to the current first initial voltage is 0000001000. If the current first initial voltage needs to be increased, the first preset logic control word is increased bit by bit, that is, the first preset logic control word becomes 0000010000 at this time. If the current first initial voltage needs to be reduced, the first preset logic control word is reduced bit by bit, that is, the first preset logic control word becomes 0000000100 at this time.

[0151] In one embodiment of the present application, the second initial voltage is increased or decreased by the following method:

[0152] The second initial voltage is increased by increasing the second preset logic control word bit by bit; and the second initial voltage is decreased by decreasing the second preset logic control word bit by bit.

[0153] By increasing or decreasing the first preset logic control word or the second preset logic control word bit by bit, the first preset logic control word or the second preset logic control word is precisely adjusted to more accurately adjust the first initial voltage and the second initial voltage, and ultimately obtain more accurate first voltage and second voltage.

[0154] In one embodiment of the present application, a binary method may be used to adjust the first initial voltage, and a binary method may be used to adjust the second initial voltage.

[0155] For example, assuming the first preset logic control word can be any one of 0000, 0001, 0010, 0100, and 1000, the logic control word is divided into two parts, the first part being 0000, 0001, and 0010, and the second part being 0100 and 1000. When initially determining the magnitude of the first test value and the first preset digital signal, a maximum or minimum control word can be determined from the first or second part as the first preset logic control word, generating a first initial voltage, and then generating a first test value based on the first initial voltage for adjustment. For example, determining the maximum control word from the first part as the first preset logic control word, i.e., using 0010 as the first preset logic control word, if the first preset digital signal is less than the first test value, the first preset logic control word needs to be increased, and then a control word is selected from the second part to generate a corresponding first preset digital signal for comparison with the first test value. If the first preset digital signal is greater than the first test value, the first preset logic control word needs to be decreased, and then a control word is selected from the first part to generate a corresponding first preset digital signal for comparison with the first test value. The first initial voltage and the second initial voltage are finally adjusted by cyclic comparison according to the above process.

[0156] For another example, the logic control word corresponding to the initial voltage A is selected as the first preset logic control word, the first initial voltage is generated according to the logic control word corresponding to the initial voltage A, and the first test value is generated based on the first initial voltage. If the first test value is less than the first preset digital signal at this time, it is determined that the input voltage needs to be increased, and the logic control word corresponding to the initial voltage A is adjusted to the logic control word corresponding to voltage B, and then the logic control word corresponding to voltage B is used to adjust the first initial voltage, and the first test value is generated based on the adjusted first initial voltage. If the first test value is greater than the first preset digital signal at this time, it is determined that the input voltage needs to be reduced, so the reasonable voltage should be between the initial voltage A and the voltage B, and then the logic control word corresponding to a voltage C between the initial voltage A and the voltage B can be selected to control the input voltage.

[0157] Continue to use the logic control word corresponding to voltage C to adjust the first initial voltage, and generate a first test value based on the adjusted first initial voltage. If the first test value is less than the first preset digital signal at this time, it is determined that the input voltage needs to be increased, which means that the expected voltage should be between voltage C and voltage B. Therefore, a voltage D can be found between voltage C and voltage B. If it is determined again that the input voltage needs to be reduced, the expected voltage should be between voltage C and voltage D. Similarly, the voltage value range can be gradually narrowed to obtain a reasonable voltage.

[0158] By using the binary method to adjust the first initial voltage and the second initial voltage, the amount of calculation can be reduced and the search speed can be accelerated.

[0159] like Figure 12 , a flow chart of a first voltage calibration is shown, comprising the following steps:

[0160] S1201 , performing analog-to-digital conversion on a first channel ultrasonic signal using a first initial voltage to obtain a first test value; and determining a first preset logic control word corresponding to the first initial voltage.

[0161] S1202, determining whether the difference between the first test value and the first preset digital signal is less than a preset threshold, if not, executing step S1203, and if so, executing step S1204.

[0162] S1203 , increasing the first preset logic control word bit by bit to increase the first initial voltage.

[0163] S1204 , reducing the first preset logic control word bit by bit to reduce the first initial voltage.

[0164] S1205 , storing the first preset logic control word corresponding to the final first voltage.

[0165] Figure 13 FIG1 shows a schematic diagram of the structure of an ultrasonic diagnostic apparatus 1300 provided in one embodiment of the present application. The following embodiment is specifically described using the ultrasonic diagnostic apparatus 1300 as an example. It should be understood that Figure 13 The ultrasonic diagnostic apparatus 1300 shown is only an example, and the ultrasonic diagnostic apparatus 1300 may have more Figure 13 The more or less components shown in the figure can be combined with two or more components, or can have different component configurations. The various components shown in the figure can be implemented in hardware, software, or a combination of hardware and software including one or more signal processing and / or application specific integrated circuits.

[0166] Figure 13 exemplarily shows a hardware configuration block diagram of an ultrasonic diagnostic apparatus 1300 according to an exemplary embodiment.

[0167] like Figure 13 As shown, the ultrasonic diagnostic apparatus 1300 may include: a processor 110, a memory 120, a display unit 130, a probe 140, and the ultrasonic signal sampling circuit 150 mentioned above; wherein,

[0168] The probe 140 is used to transmit ultrasonic beams and receive ultrasonic echo signals;

[0169] A display unit 130 is used to display ultrasound images;

[0170] The memory 120 is configured to store data required for ultrasound images, which may include software programs, application interface data, etc.

[0171] The processor 110 is configured to send digital signals to the host computer 106 and receive ultrasound images sent by the host computer 106 ; the digital signals are obtained through the ultrasound signal sampling circuit 150 .

[0172] Figure 14 Schematic diagram of the application principle according to an embodiment of the present application. Figure 13 The implementation of some modules or functional components of the ultrasonic diagnostic instrument shown in the figure will only be described in terms of the main components, while other components, such as memory, controller, control circuit, etc., will not be described in detail here.

[0173] like Figure 14 As shown, the application environment may include a user interface 310 , a display unit 320 for displaying the user interface, and a processor 330 .

[0174] The display unit 320 may include a display panel 321 and a backlight assembly 322. The display panel 321 is configured to display ultrasound images, and the backlight assembly 322 is located behind the display panel 321. The backlight assembly 322 may include a plurality of backlight sub-areas (not shown in the figure), each of which may emit light to illuminate the display panel 321.

[0175] The processor 330 may be configured to control the brightness of the backlight source of each backlight partition in the backlight assembly 322 , and control the probe to transmit a wide beam and receive an echo signal.

[0176] The processor 330 may include a focusing processing unit 331, a beamforming unit 332, and a spectrum generation unit 333. The focusing processing unit 331 may be configured to perform focusing processing on the current frame ultrasound image. The focusing processing includes: using a designated position in the current frame ultrasound image as the focus position of the wide beam, transmitting a wide beam to the target detection area according to the transmission coefficient of the designated position; and receiving the echo signal fed back from the designated position. The beamforming unit 332 is configured to, after completing the focusing processing on the target detection area, perform beamforming on the echo signal fed back from the designated position to obtain scanning information. The spectrum generation unit 333 is configured to perform Doppler imaging based on the scanning information of each designated position.

[0177] Those skilled in the art will appreciate that various aspects of the present application can be implemented as systems, methods, or program products. Therefore, various aspects of the present application can be specifically implemented in the following forms: a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or an implementation that combines hardware and software aspects, which may be collectively referred to herein as a "circuit," "module," or "system."

[0178] In an exemplary embodiment, various aspects of an ultrasonic signal sampling method provided by the present application can also be implemented in the form of a program product, which includes program code. When the program product is run on a computer device, the program code is used to enable the computer device to execute the steps of the ultrasonic signal sampling method according to various exemplary embodiments of the present application described above in this specification.

[0179] The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or component, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0180] The program product for ultrasonic signal sampling of the embodiments of the present application can be a portable compact disc read-only memory (CD-ROM) and include program code, and can be run on an ultrasonic device. However, the program product of the present application is not limited thereto. In this document, a readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0181] A readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries readable program code. Such propagated data signals may take a variety of forms, including, but not limited to, electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium that can transmit, propagate, or transfer a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0182] Program code embodied on a readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0183] The program code for performing the operations of the present application can be written in any combination of one or more programming languages, including object-oriented programming languages such as Java, C++, etc., and conventional procedural programming languages such as "C" language or similar programming languages. The program code can be executed entirely on the user ultrasound device, partially on the user device, as a separate software package, partially on the user ultrasound diagnostic instrument, partially on the remote ultrasound diagnostic instrument, or entirely on the remote ultrasound diagnostic instrument or server. In the case of a remote ultrasound diagnostic instrument, the remote ultrasound diagnostic instrument can be connected to the user ultrasound diagnostic instrument through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external ultrasound diagnostic instrument (for example, using an Internet service provider to connect via the Internet).

[0184] It should be noted that although several units or subunits of the device are mentioned in the detailed description above, this division is merely exemplary and not mandatory. In fact, depending on the embodiment of the application, the features and functions of two or more units described above can be embodied in a single unit. Conversely, the features and functions of a single unit described above can be further divided and embodied by multiple units.

[0185] Furthermore, although the operations of the method of the present application are described in a particular order in the accompanying drawings, this does not require or imply that the operations must be performed in this particular order, or that all illustrated operations must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

[0186] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0187] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable image scaling device to produce a machine, so that the instructions executed by the processor of the computer or other programmable ultrasound signal sampling device generate instructions for implementing the process in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0188] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable ultrasonic signal sampling device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, the instruction device being implemented in the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0189] These computer program instructions can also be loaded onto a computer or other programmable ultrasonic signal sampling device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable device to implement the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0190] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0191] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. An ultrasonic signal sampling circuit, characterized in that: include: A signal demodulation module, a first analog-to-digital conversion (ADC) sampling module, a second analog-to-digital conversion (ADC) sampling module, and a voltage regulation module; The voltage regulating module includes: a first voltage regulating unit and a second voltage regulating unit, the first voltage regulating unit includes: a first digital-to-analog conversion DAC unit and a first low-noise operational amplifier unit, the second voltage regulating unit includes: a second digital-to-analog conversion DAC unit and a second low-noise operational amplifier unit; The signal demodulation module is used to demodulate the ultrasonic echo signal to obtain an orthogonal first channel ultrasonic signal and a second channel ultrasonic signal; The first digital-to-analog conversion DAC unit is used to output a first analog signal to the first low-noise operational amplifier unit; The first low-noise operational amplifier unit is configured to output an adjustable first voltage to the first analog-to-digital conversion ADC sampling module using a proportional relationship between the first analog signal and the first voltage. The second digital-to-analog conversion DAC unit is used to output a second analog signal to the second low-noise operational amplifier unit; The second low-noise operational amplifier unit is configured to output an adjustable second voltage to the second analog-to-digital conversion (ADC) sampling module by utilizing a proportional relationship between the second analog signal and the second voltage; The first analog-to-digital conversion (ADC) sampling module is configured to sample the first channel ultrasonic signal based on the first voltage to obtain a digital signal of the first channel ultrasonic signal; The second analog-to-digital conversion (ADC) sampling module is configured to sample the second channel ultrasonic signal based on the second voltage to obtain a digital signal of the second channel ultrasonic signal.

2. The circuit according to claim 1, wherein: The first digital-to-analog conversion DAC unit is a current-mode DAC chip or a voltage-mode DAC chip, and the second digital-to-analog conversion DAC unit is a current-mode DAC chip or a voltage-mode DAC chip.

3. The circuit according to claim 1, wherein: The circuit further includes a memory for storing a first preset logic control word corresponding to the first voltage and a second preset logic control word corresponding to the second voltage; The voltage regulation module is specifically used to read the first preset logic control word and the second preset logic control word from the memory, and output the first voltage to the first analog-to-digital conversion ADC sampling module based on the first preset logic control word, and output the second voltage to the second analog-to-digital conversion ADC sampling module based on the second preset logic control word.

4. A method for sampling an ultrasonic signal, characterized in that: The method comprises: Demodulating the ultrasonic echo signal to obtain an orthogonal first channel ultrasonic signal and a second channel ultrasonic signal; Performing analog-to-digital conversion on the first channel ultrasonic signal based on an adjustable first voltage to obtain a digital signal of the first channel ultrasonic signal; and performing analog-to-digital conversion on the second channel ultrasonic signal based on an adjustable second voltage to obtain a digital signal of the second channel ultrasonic signal; in, Determining the first voltage includes: Performing analog-to-digital conversion on the first channel ultrasonic signal using a first initial voltage to obtain a first test value; Adjusting the first initial voltage until the difference between the first test value and the first preset digital signal is within a preset threshold range, thereby obtaining the first voltage; Determining the second voltage includes: Performing analog-to-digital conversion on the second channel ultrasonic signal using a second initial voltage to obtain a second test value; The second initial voltage is adjusted until the difference between the second test value and the second preset digital signal is within the preset threshold range, thereby obtaining the second voltage.

5. The method according to claim 4, characterized in that The adjusting the first initial voltage includes: If the first test value is greater than the first preset digital signal, increasing the first initial voltage; If the first test value is less than the first preset digital signal, reducing the first initial voltage; The adjusting the second initial voltage includes: If the second test value is greater than the second preset digital signal, increasing the second initial voltage; If the second test value is smaller than the second preset digital signal, the second initial voltage is reduced.

6. The method according to claim 5, characterized in that Increase or decrease the first initial voltage by: increasing the first initial voltage by increasing the first preset logic control word bit by bit; reducing the first initial voltage by decreasing the first preset logic control word bit by bit; Increase or decrease the second initial voltage by: increasing the second initial voltage by increasing the second preset logic control word bit by bit; The second initial voltage is reduced by decreasing the second preset logic control word bit by bit.

7. An ultrasonic diagnostic apparatus, characterized in that: include: A probe, a display unit, a processor, and an ultrasonic signal sampling circuit as described in any one of claims 1 to 3; The probe is used to transmit ultrasonic beams and receive ultrasonic echo signals; The processor is configured to send a digital signal to a host computer and receive an ultrasonic image sent by the host computer; the digital signal is obtained by the ultrasonic signal sampling circuit; The display unit is used to display the ultrasound image.

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