Package structure and method of forming the same

Abstract

The present invention relates to a packaging structure and a method of forming the same. The packaging structure includes a substrate, an optical integrated circuit located above the substrate, the optical integrated circuit having an optical guide on an upper surface thereof, and an optical fiber array located above the optical guide of the optical integrated circuit, the optical guide of the optical fiber array being optically coupled to the optical guide of the optical integrated circuit.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a packaging structure and a method for forming the same. Background Technology

[0002] In a conventional optical integrated circuit unit (PIC unit), multiple wave guides (WGs) correspond to and pass through the corresponding fibers in the fiber array (FAU), and can transmit the modulated laser source signal using edge coupling.

[0003] like FIG. 1A As shown, the optical engine (OE) is a unit containing a PIC 12 / EIC 14. To reduce the overall width of the OE, the FAU 16 can be recessed between the PIC 12 and EIC 14, as shown. FIG. 1B As shown. However, in order to accommodate the FAU, an additional high-conductivity pillar 22 must be used between the PIC and EIC. FIG. 1A and FIG. 1B The connection between PIC 12 and EIC 14 is made by electricity. This structure will increase the overall thickness of the OE. Therefore, a design that can take into account both the overall width and thickness of the OE is required. Summary of the Invention

[0004] To address the aforementioned problems in related technologies, this invention proposes a packaging structure and its formation method.

[0005] An embodiment of the present invention provides a packaging structure, comprising: a substrate; an optical integrated circuit located above the substrate, the upper surface of the optical integrated circuit having a light guide; and an optical fiber array located above the light guide of the optical integrated circuit, wherein the light guide of the optical fiber array is optically coupled to the light guide of the optical integrated circuit.

[0006] In some embodiments, the packaging structure further includes an insulating layer located between the optical integrated circuit and the fiber array and having a cavity that accommodates the light guide of the optical integrated circuit.

[0007] In some embodiments, the insulating layer has a through-hole located above the cavity, through which the optical fiber array passes into the cavity.

[0008] In some embodiments, at least the optical guide of the fiber array within the cavity extends in a different direction than the optical guide of the fiber array above the insulating layer.

[0009] In some embodiments, the package structure further comprises an underfill between the optical integrated circuit and the fiber array, and surrounding the optical guides of the partial fiber array.

[0010] In some embodiments, the package structure further comprises an electrical integrated circuit. The electrical integrated circuit is above the optical integrated circuit. In some embodiments, the electrical integrated circuit is spaced apart from the optical integrated circuit above the substrate.

[0011] In some embodiments, the package structure further comprises a routing layer between the electrical integrated circuit and the optical integrated circuit. The electrical integrated circuit is electrically connected to the optical integrated circuit through the routing layer.

[0012] In some embodiments, the routing layer exposed by the upper surface of the insulating layer is electrically connected to the substrate through a lead.

[0013] In some embodiments, the lead is coated by a protective layer, and the protective layer covers the sidewall of the insulating layer and the optical integrated circuit.

[0014] Embodiments of the present application also provide a method of forming a package structure, comprising: forming an optical integrated circuit on a substrate, wherein the optical integrated circuit has optical guides on a surface opposite to the substrate; forming a fiber array on the side of the optical integrated circuit opposite to the substrate, and connecting the optical guides of the fiber array to the optical guides of the optical integrated circuit.

[0015] In some embodiments, the method of forming a package structure further comprises: forming an insulating layer with a cavity on a carrier; bonding the insulating layer to the optical integrated circuit, and, after the bonding, removing the carrier with the optical guides of the optical integrated circuit accommodated in the cavity.

[0016] In some embodiments, the forming of the fiber array comprises: connecting the optical guides of the fiber array to the optical guides of the optical integrated circuit through the insulating layer into the cavity, and the extending direction of the optical guides of the fiber array into the cavity is different from the extending direction of the optical guides of the fiber array not entering the insulating layer.

[0017] In some embodiments, the formed insulating layer further has a via above the cavity, and the forming of the fiber array comprises: connecting the optical guides of the fiber array to the optical guides of the optical integrated circuit through the via into the cavity.

[0018] In some embodiments, the method of forming a package structure further comprises, after the forming of the fiber array: forming a protective layer between the optical integrated circuit and the fiber array, wherein the protective layer surrounds the optical guides of the partial fiber array.

[0019] In some embodiments, the method of forming a package structure further comprises, after the forming of the optical integrated circuit: forming an electrical integrated circuit above the optical integrated circuit.

[0020] In some embodiments, further comprising, before forming the electrical integrated circuit, forming a wiring layer on the carrier, bonding the wiring layer on the side of the optical integrated circuit opposite the substrate, and removing the carrier, wherein the electrical integrated circuit is formed on the wiring layer after removing the carrier.

[0021] In some embodiments, further comprising, after bonding the wiring layer with the optical integrated circuit, forming a lead connecting the wiring layer exposed by the upper surface of the insulating layer and the wiring layer of the substrate.

[0022] In some embodiments, a protective layer is formed covering the lead, and the protective layer covers the insulating layer and the sidewall of the optical integrated circuit.

[0023] In some embodiments, further comprising, after forming the optical integrated circuit, forming an electrical integrated circuit on the same side of the substrate as the optical integrated circuit. BRIEF DESCRIPTION OF DRAWINGS

[0024] Various aspects of the application can be best understood from the following detailed description when read with the accompanying drawings in which: It should be noted that the various components are not necessarily drawn to scale. Indeed, the dimensions of the various components can be arbitrarily increased or decreased for clarity sake.

[0025] FIG. 1A and FIG. 1B is a schematic diagram of a prior art optical engine package structure.

[0026] FIG. 2A is a schematic diagram of a package structure according to an embodiment of the application.

[0027] FIG. 2B is FIG. 2A a top view of the package structure of

[0028] FIG. 3A , FIG. 3B and FIG. 3C show a perspective view, a top view and a side view of the light guide, respectively.

[0029] FIG. 4 is FIG. 2A an enlarged view of a portion of the package structure shown in

[0030] FIG. 5 to FIG. 7B are schematic diagrams of package structures according to other embodiments of the application.

[0031] FIG. 8A to FIG. 8Q show schematic diagrams of various stages of a method of package structure according to an embodiment of the application. DETAILED DESCRIPTION

[0032] The following disclosure provides many different embodiments, or examples, for implementing various aspects of the provided subject matter. Although each of the various embodiments of the present application can represent a pioneering advancement in the field of the art, they are described in sufficient detail to enable one skilled in the art to make and use the application. The elements in which each of the various embodiments of the present application are used will be described, from time to time, in the following description with reference to the associated drawings in which like reference numbers are used to refer to like elements throughout. It is to be noted that the use of certain of the terms, such as "top," "bottom," "front," "back," "leading," "trailing," etc., are used in the descriptions intended to orient the reader with respect to the material being discussed. Such terms can differ from the actual physical orientation of a device, material, etc. described and / or shown in the figures. It is therefore, to be understood that the embodiments can be carried out in other embodiments and its

[0033] According to embodiments of the present application, a packaging structure is provided. FIG. 2A is a schematic view of a packaging structure 200 according to embodiments of the present application. FIG. 2B is a top view of the packaging structure 200 of FIG. 2A is a top view of the packaging structure 200 of FIG. 2A and FIG. 2B As shown in FIGS. 1 and 2, the packaging structure 200 provided by the present application includes a substrate 202, a PIC 210 and a FAU 220. The PIC 210 is disposed above the substrate 202. In some embodiments, the PIC 210 can be a silicon photonic integrated circuit (Si-Ph IC). In some embodiments, the PIC 210 can be bonded to the substrate 202 by an adhesive layer 205. The PIC 210 has a light guide 215 disposed on its upper surface. The FAU 220 is disposed above the light guide 215 of the PIC 210 (rather than being placed at the side of the PIC 210 in the prior art structure), and the FAU 220 has a plurality of light guides 225 at its surface facing the PIC 210. The light guides 225 of the FAU 220 are optically coupled to the light guide 215 of the PIC 210 for optical coupling between the FAU 220 and the PIC 210.

[0034] In some embodiments, the width of the substrate 202 defines the width X of the packaging structure 200. The width X of the packaging structure 200 can be in the range of tens of mm to hundreds of mm, for example, can be in the range of 10 mm to 900 mm. The distance from the bottom surface of the substrate 202 to the top surface of the FAU 220 defines the thickness Y of the packaging structure 200. In some embodiments, the thickness Y of the packaging structure 200 can be in the range of a few mm to tens of mm, for example, can be in the range of 1 mm to 90 mm.

[0035] The above technical solution of the present application, by the optical coupling mode of the FAU 220 and the PIC 210, can provide a larger area for the FAU 220 above the PIC 210 in structure, which is suitable for a large-area FAU 220 and does not limit the thickness of the FAU 220. In addition, the PIC 210 is directly arranged on the surface of the substrate 202, which can be beneficial to the heat dissipation performance of the PIC 210.

[0036] In order to facilitate the understanding of the present application, FIG. 3A A perspective view of the light guide is shown. FIG. 3B A top view of the light guide is shown. FIG. 3C A side view of the light guide is shown. As FIG. 3A to FIG. 3C shown, the light guide 215 of the PIC 210 can include a light guide part 2151 and a cladding 2152. A plurality of rasters 2154 are arranged at the end of the light guide part 2151, and the raster 2154 is used to receive light from the FAU 255 and transmit the light to the laser diode 2155. In some embodiments, the pitch P between the light guides 215 of the PIC 210 can be in the range of 50 μm to 500 μm.

[0037] As FIG. 2A shown, the packaging structure 200 of the present application further includes an insulating layer 232 between the PIC 210 and the FAU 220. In some embodiments, the insulating layer can also be referred to as a dielectric layer. The material of the insulating layer 232 can include polyimide (PI), epoxy, insulating dielectric adhesive film (ABF), polypropylene (PP) or / and acrylic, organic photosensitive, non-photosensitive liquid or / and dry film material. And, the insulating layer 232 has a cavity 235 therein, which is used to accommodate the light guide 215 of the PIC. The insulating layer 232 also has a plurality of through holes 236 arranged above the cavity 235. The light guide 225 of the FAU 220 can pass through the through hole 236 into the cavity 235. By arranging the through hole 236 and the cavity 235, a good performance of the PIC 210 packaging application can be provided.

[0038] Because the FAU 220 in the package structure 200 of the present application is aligned and coupled with the light guide 215 of the PIC 210 using the light guide 225, but the precision of the bond head used in the process is not high, it is possible that the FAU 220 and the light guide 215 of the PIC 210 are not aligned. In some embodiments of the present application, the extension direction of the light guide 225 of the FAU 220 in the cavity 235 is different from the extension direction of the light guide 225 of the FAU 220 above the insulating layer. Because the light guide 225 of the FAU 220 passes through the via hole 236 and the cavity 235, the distance between the side walls of the via hole 236 provides a light guide with precision and a turning angle, and when the light guide contacts the via hole wall, it will rotate an included angle, so that the FAU 220 can be automatically aligned through the via hole 236 and the cavity 235 after the bond head is pressed down.

[0039] FIG. 4 is FIG. 2A an enlarged view of a portion of the package structure shown in FIG. 2A and FIG. 4 As shown in , the angle θ formed by the light guide 225 of the FAU 220 inserted into the cavity 235 is in the range of 0°-45°. The number of insulating layers 232 can be multiple, and the via hole 236 can be formed in at least two insulating layers 232. The side walls of the via hole 236 located in at least two insulating layers 232 form an acute angle with the horizontal direction, such as αb, αm, αt. In some embodiments, each of αb, αm, αt is in the range of 10°-85°. The size (maximum width) of the via hole 236 can be in the range of 80μm to 200μm. In other embodiments, the light guide 225 of the FAU 220 can also be inserted vertically into the cavity 235 and coupled vertically to the light guide 215 of the PIC 210.

[0040] With continued reference to FIG. 2A , the underfill 260 is disposed between the PIC 210 and the FAU 220, and the underfill 260 surrounds the light guide 225 of the portion of the FAU 220. The underfill 260 can also fill the via hole 236 of the uppermost insulating layer 232 to secure the FAU 220. In some embodiments, the material of the underfill 260 can include polyimide (PI), epoxy, ABF, polypropylene (PP), or / and acrylic, organic photosensitive, non-photosensitive liquid, or / and dry film material. The underfill 260 can be used to secure the FAU 220 and ensure the alignment of the PIC 210 and the FAU 220.

[0041] An EIC 280 is also disposed above the PIC 210. The EIC 280 and FAU 220 are spaced apart laterally. In some embodiments, the width of the PIC 210 can be in the range of 20 μm to 100 μm. The width of the EIC 280 can also be in the range of 20 μm to 100 μm. A line 234 is disposed within the insulating layer 232 below the EIC 280; therefore, the insulating layer 232 and the line 234 within the insulating layer 232 are collectively referred to as the circuit layer 230. The circuit layer 230 is located between the EIC 280 and the PIC 210. In some embodiments, the line width / line spacing value of the line 234 in the circuit layer 230 is in the range of 1 μm to 30 μm / 1 μm to 30 μm, and the pitch of the line 234 in the circuit layer 230 is in the range of 2 μm to 60 μm. In some embodiments, the circuit layer 230 is bonded to the PIC 210 by an adhesive layer 228. The thickness of the adhesive layer 228 can be, for example, in the range of 20 μm to 80 μm. The material of the adhesive layer 228 can be an insulating material. The adhesive layer 228 can also be referred to as an insulating layer.

[0042] The circuit layer 230 is electrically connected to the PIC 210. The lead 238 is electrically connected to the substrate 202. In some embodiments, the diameter of the lead 238 can be in the range of 10 μm to 100 μm. The lead 238 can be covered by an underfill 260 (protective layer), and the underfill 260 covers the insulating layer 232 and the sidewalls of the PIC 210.

[0043] FIG. 5 A schematic diagram of a packaging structure 500 according to another embodiment of the present invention is shown. FIG. 5 As shown, with FIG. 2A The difference between the package structure 200 shown is that the EIC 280 and PIC 210 are spaced apart and located above the substrate 202. The EIC 280 can be electrically connected to the PIC 210 via leads 238 and a circuit layer 230. FIG. 5 Other aspects of the package structure 500 shown can be compared with FIG. 2A The packaging structure shown is similar to 200, and will not be described in detail here.

[0044] FIG. 6 A schematic diagram of a packaging structure 600 according to another embodiment of the present invention is shown. FIG. 6 As shown, instead FIG. 2A In this embodiment, the PIC 210 may have an interposer 219 that passes through the PIC 210, and the line 234 in the line layer 230 may be electrically connected to the solder ball 218 on the opposite side of the PIC 210 through the interposer 219. FIG. 6 Other aspects of the package structure 600 shown can be compared withFIG. 2A The packaging structure shown is similar to 200, and will not be described in detail here.

[0045] FIG. 7A and FIG. 7B Side and top views of a packaging structure 700 according to another embodiment of the present invention are shown respectively. FIG. 7A and FIG. 7B As shown, the number of EIC 280s can also be multiple, such as two. In this embodiment, the number of FAU 220s can be four. The four FAU 220s are arranged adjacently and located between the two EIC 280s. It should be understood that FIG. 7A and FIG. 7B The number of FAU 220s, the number of EIC 280s, and the layout of FAU 220s and EIC 280s shown are merely examples, and the number of FAU 220s, the number of EIC 280s, and the layout of FAU 220s and EIC 280s can be any other suitable configuration.

[0046] This invention also provides a method for forming an encapsulation structure. FIG. 8A to FIG. 8Q Schematic diagrams of various stages of the method for packaging structure according to embodiments of the present invention are shown.

[0047] First, such as FIG. 8A As shown, a first adhesive layer 802, a first seed layer 811 on the first adhesive layer 802, and a first photoresist layer 821 on the first seed layer 811 are formed on the first carrier 801. The first photoresist layer 821 is exposed and developed, and a plurality of first openings 831 are formed in the first photoresist layer 821, such as... FIG. 8B As shown. Electroplating of metal material 840 is performed in the first opening 831.

[0048] Then, remove the first photoresist layer 821, as follows: FIG. 8C As shown, a dielectric layer 232 is covered on the first seed layer 811 and the metal material 840. The dielectric layer 232 is patterned, and cavities 235 and second openings 832 are formed in the dielectric layer 232, as shown. FIG. 8D As shown. Cavity 235 can expose the first seed layer 811 beneath dielectric layer 232. Second opening 832 is located above metal material 840 and can expose metal material 840 through second opening 832. Second seed layer is formed within cavity 235, within second opening 832, and on dielectric layer 232. Since cavity 235 exposes the first seed layer 811 beneath dielectric layer 232, and second opening 832 exposes metal material 840, second seed layer 812 is in contact with the first seed layer 811 beneath cavity 235 and second opening 832.

[0049] like FIG. 8EAs shown, a second photoresist layer 822 is formed on the dielectric layer 232, the cavity 235, and the second opening 832. The second photoresist layer 822 is then exposed and developed to form a third opening 833 located above the second opening 832. A metal material 840 is then filled into the second opening 832 via the third opening 833. Furthermore, the metal material 840 is also formed at the bottom of the third opening 833. FIG. 8F As shown, the second seed layer 812 covered by the second photoresist layer 822 is removed, and the second photoresist layer 822 is also removed. The second seed layer 812 and metal material 840 above the formed dielectric layer 232, as well as the metal material 840 formed on the first seed layer 811 in the dielectric layer 232, can be used as the subsequent circuit layer 230. FIG. 8G The trace 2301 in the dielectric layer 232, the second seed layer 812 and the metal material 840 formed between the trace 2301 can be used as vias 2302 in the circuit layer, and the vias 2302 are used to interconnect adjacent traces 2301.

[0050] Can be repeated FIG. 8C to FIG. 8F The steps shown are used to form the circuit layer 230, as follows. FIG. 8G As shown. The circuit layer 230 can be, for example, a fanout circuit layer. The circuit layer 230 includes traces 2301 having a desired number of layers formed in respective dielectric layers 232, and vias 2302 for interconnecting the traces 2301. The traces 2301 and vias 2302 can be collectively referred to as lines 234 in the circuit layer 230. Additionally, a plurality of vias 236 communicating with the cavity 235 are formed in the dielectric layer 232 above the cavity 235. In some embodiments, the width of the vias 236 in the uppermost dielectric layer is greater than the width of the vias 236 in the other dielectric layers 232.

[0051] like FIG. 8H As shown, FIG. 8G The resulting structure is inverted and bonded to the second carrier 804 via the second adhesive layer 806. The first adhesive layer 802 and the first carrier 801 are then removed. Then, as... FIG. 8I As shown, for example, the exposed first seed layer 811 is removed by an etching process.

[0052] like FIG. 8J As shown, a third adhesive layer 228 is applied above the circuit layer 230 (i.e., FIG. 2A The material of the adhesive layer 228 is used to pick up and place the PIC 210 onto the material of the circuit layer 230 and the third adhesive layer 228 using a bonding head 910. The PIC 210 has a light guide 215 and an electrical connector 216 on its surface facing the circuit layer 230. After the PIC 210 is bonded to the circuit layer 230, as...FIG. 8K As shown, electrical connections 216 of PIC 210 can be electrically connected to lines 234 in line layer 230. PIC 210 is bonded to line layer 230 by adhesive layer 228. Locations corresponding to cavities 235 are free of adhesive layer 228, so cavities 235 also extend into adhesive layer 228. Light guide 215 of PIC 210 is housed in cavity 235. Subsequently, a dicing process can be performed along the dashed lines in FIG. 8K

[0053] The diced PIC 210 is picked up and placed by bonding head 910 on top of EIC 280, which is on top of line layer 230, as shown in FIG. 8K FIG. 8L The structure in FIG. 8M is shown on substrate 202, as shown in FIG. 8N In some embodiments, the exposed surface of substrate 202 can have conductive lines 2021. Second carrier 804 and second adhesive layer 806 above line layer 230 are removed, as shown in

[0054] As shown in FIG. 8O EIC 280 is picked up and placed by bonding head 910 on top of line layer 230, with EIC 280 electrically connected to lines 234 on the surface of line layer 230 by electrical connections 286.

[0055] As shown in FIG. 8P Bottom fill 260 is formed. Bottom fill 260 can surround light guide 225 of FAU 220, lower portions of EIC 280, and leads 238 above line layer. Bottom fill 260 can also fill within via 236 of topmost dielectric layer 232 of line layer 230 to secure FAU 220. In some embodiments, bottom fill 260 that encapsulates leads 238 can be formed by a separate process. In other words, bottom fill 260 that encapsulates leads 238 can be formed by a different process than bottom fill 260 under FAU 220 and EIC 280, and bottom fill 260 that encapsulates leads 238 can be a different material than bottom fill 260 under FAU 220 and EIC 280.​​

[0056] Then, as shown in FIG. 8Q , the structure obtained in FIG. 8P is inverted and solder balls 209 are formed on pads 208 of substrate 202. A dicing process is performed along the dashed line in FIG. 8Q , and then the diced structure is inverted to obtain the package structure shown in FIG. 2A .

[0057] The above method of forming a package structure of the present application first fabricates a circuit layer 230 on a first carrier 801, and also fabricates a cavity 235 and a via 236 in circuit layer 230. Then, circuit layer 230 is bonded with a PIC 210 and an EIC 280. Next, a FAU 220 is inserted into via 236 and cavity 235 to optically couple with PIC 210. In addition, FAU 220 can be secured in via 236 within the uppermost surface of circuit layer 230 by a bottom fill 260. Structurally, the package structure formed can provide a larger area for FAU 220 above PIC 210, suitable for a large-area FAU 220, and does not impose a limitation on the thickness of FAU 220.

[0058] The above summary of features of several embodiments enables those skilled in the art to better understand the various aspects of the present disclosure. Those skilled in the art should understand that other processes and structures can be easily designed or altered using the present application as a basis to achieve the same purpose and / or achieve the same advantages as the embodiments described in the present application. Those skilled in the art should also realize that these equivalent structures do not deviate from the spirit and scope of the present application, and that various changes, substitutions and alterations can be made without deviating from the spirit and scope of the present application.

Claims

1. A package structure, characterized by, Comprising: a substrate; an optical integrated circuit above the substrate, the optical integrated circuit having an optical guide on an upper surface thereof; an optical fiber array above the optical guide of the optical integrated circuit, and the optical guides of the optical fiber array are optically coupled to the optical guide of the optical integrated circuit; an insulating layer between the optical integrated circuit and the optical fiber array and having a cavity, the cavity accommodating the optical guide of the optical integrated circuit; an underfill between the optical integrated circuit and the optical fiber array, and surrounding the optical guides of part of the optical fiber array to secure the optical fiber array; an electrical integrated circuit above the optical integrated circuit; and a wiring layer between the electrical integrated circuit and the optical integrated circuit, wherein the electrical integrated circuit is electrically connected to the optical integrated circuit through the wiring layer, wherein the insulating layer has a through hole above the cavity, and the optical guides of the optical fiber array pass through the through hole into the cavity. The extension direction of the optical guides of the optical fiber array within at least the cavity is different from the extension direction of the optical guides of the optical fiber array above the insulating layer.

2. The package structure of claim 1, wherein, The wiring layer exposed by the upper surface of the insulating layer is electrically connected to the substrate through a lead.

3. The package structure of claim 1, wherein, The lead is covered by a protective layer, and the protective layer covers the sidewalls of the insulating layer and the optical integrated circuit.

4. The package structure of claim 3, wherein, The electrical integrated circuit is spaced apart from the optical integrated circuit above the substrate.

5. The package structure of claim 1, wherein, ​

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