Display device and data driving circuit

Abstract

The present invention provides a display device and a data driving circuit. The display device may include: a data driving circuit, the data driving circuit includes k sensing terminals and a switch part, the switch part includes a switch element located between the outermost sensing terminal of the k sensing terminals and a constant voltage supply terminal, wherein k is a positive integer greater than or equal to 2; and a display panel, the display panel includes a plurality of sub-pixels and a plurality of sensing lines electrically connected to the plurality of sub-pixels, wherein the plurality of sensing lines are electrically connected to n sensing terminals of the k sensing terminals provided in the data driving circuit, wherein n is a positive integer less than or equal to k, and n is greater than or equal to 1.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2021-0100665 filed in Korea on Jul. 30, 2021, the entire contents of which are hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0003] Embodiments of the present disclosure relate to a display device and a data driving circuit. Background Art

[0004] As the information society further develops, various demands on display devices for displaying images are increasing, and various types of display devices, such as liquid crystal displays (LCDs) and organic light emitting diode (OLED) displays, are used.

[0005] Such a display device may include different types of display panels having various specifications.

[0006] The data driving circuit may be designed and manufactured according to display panels having various specifications. Therefore, there is a need for a data driving circuit that can be commonly used in different types of display panels having various specifications. Summary of the invention

[0007] Embodiments of the present disclosure may provide a data driving circuit that may be generally applied to different types of display panels having various specifications, and a display device including the data driving circuit.

[0008] Embodiments of the present disclosure may provide a display device and a data driving circuit capable of compensating for a change in a characteristic value of an analog-to-digital converter in real time.

[0009] According to an embodiment of the present disclosure, a display device may be provided, comprising: a data driving circuit, the data driving circuit comprising k (k ≥ 2) sensing terminals and a switching part, the switching part comprising a switching element located between an outermost sensing terminal among the k sensing terminals and a constant voltage supply terminal; and a display panel, the display panel having a plurality of sub-pixels and a plurality of sensing lines electrically connected to the plurality of sub-pixels, wherein the plurality of sensing lines are electrically connected to n (1 ≤ n ≤ k) sensing terminals among the k sensing terminals arranged in the data driving circuit, wherein k is a positive integer.

[0010] According to an embodiment of the present disclosure, a data driving circuit may be provided, the data driving circuit comprising: k (k ≥ 2) sensing terminals; a constant voltage supply terminal, which supplies a constant voltage to a constant voltage supply line; a sensing part, which receives an analog voltage from each of the k sensing terminals; and a switching part, which comprises a switching element located between an outermost sensing terminal among the k sensing terminals and the constant voltage supply line.

[0011] Effects of the Invention

[0012] According to an embodiment of the present disclosure, a data driving circuit that can be generally applied to different types of display panels having various specifications and a display device including the data driving circuit can be provided.

[0013] According to an embodiment of the present disclosure, a display device and a data driving circuit capable of compensating for a change in a characteristic value of an analog-to-digital converter in real time may be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other objects, features and advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0015] Figure 1 is a view showing a display device according to an embodiment of the present disclosure;

[0016] Figure 2 is a view schematically showing a display device according to an embodiment of the present disclosure;

[0017] Figure 3 is a view schematically illustrating an equivalent circuit of a sub-pixel SP and a configuration for compensating a characteristic value of the sub-pixel SP according to an embodiment of the present disclosure;

[0018] Figure 4 is a view showing a data driving circuit of a display device according to an embodiment of the present disclosure;

[0019] Figure 5 is a view showing a connection relationship among a sensing terminal, an output terminal, a sensing line, and a data line of a display device according to an embodiment of the present disclosure;

[0020] Figure 6 is a view showing an example of a sensing terminal floating problem caused by common use of a data driving circuit;

[0021] Figure 7 is a view showing a data driving circuit and a display panel according to an embodiment of the present disclosure;

[0022] Figure 8 The present invention is a diagram showing an embodiment of the present invention. Figure 7 a view of a data driving circuit for one or more switching elements;

[0023] Fig. 9 This is an example of an embodiment according to the disclosure Figure 7 A diagram of operation of one or more switching elements in a case where all sensing terminals of a data driving circuit in a display device are connected to sensing lines;

[0024] Fig.10 This is an example of an embodiment according to the disclosure Figure 7 A view of the operation of one or more switching elements in a case where some sensing terminals of a data driving circuit in a display device are not electrically connected to sensing lines;

[0025] Fig.11 This is an example of an embodiment according to the disclosure Figure 7 A view of the operation of one or more switching elements in another case where some sensing terminals of a data driving circuit in a display device are not electrically connected to sensing lines;

[0026] Fig.12 This is an example of an embodiment according to the disclosure Figure 7 A diagram showing operations of various circuit elements disposed in a first sensing terminal region and a second sensing terminal region in a display device and voltages applied to specific nodes;

[0027] Fig.13 is a view showing a first sensing terminal region, a second sensing terminal region, and a dummy region in a display device according to an embodiment of the disclosure;

[0028] Fig.14 is a view showing a display device according to an embodiment of the present disclosure;

[0029] Fig.15 is a diagram showing an embodiment according to the present disclosure Fig.14 a view of a data driving circuit;

[0030] Fig.16 is a diagram showing an embodiment according to the present disclosure Fig.14 a diagram of operations of circuit elements disposed in a first sensing terminal region and a second sensing terminal region and voltages at specific nodes;

[0031] Fig.17 is a view showing common use of a data driving circuit according to an embodiment of the present disclosure;

[0032] Fig.18is a diagram schematically showing an input / output correspondence relationship of an analog-to-digital converter according to an embodiment of the disclosure;

[0033] Fig.19 is a diagram showing an example of an initial input / output function of an analog-to-digital converter according to an embodiment of the present disclosure and an input / output function of an analog-to-digital converter in which an input / output deviation occurs;

[0034] Fig. 20 is a view showing an example of performing ADC input / output compensation by averaging two or more ADC compensation sensing voltages according to an embodiment of the disclosure;

[0035] Fig.21 is a view schematically illustrating a compensation process of the display device 100 according to an embodiment of the disclosure; and

[0036] Fig. 22 is a view showing a driving timing of a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] In the following description of examples or embodiments of the present invention, reference will be made to the accompanying drawings, in which specific examples or embodiments that can be implemented are shown by way of illustration, and in the accompanying drawings, the same reference numerals and symbols may be used to represent the same or similar components, even if they are shown in different drawings from each other. In addition, in the following description of examples or embodiments of the present invention, detailed descriptions of well-known functions and components incorporated herein will be omitted when it is determined that the description may make the subject matter in some embodiments of the present invention quite unclear. Terms such as "including", "having", "comprising", "consisting of", "composed of", and "formed by..." used herein are generally intended to allow the addition of other components unless the term is used together with the term "only". As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0038] Terms such as "first", "second", "A", "B", "(A)" or "(B)" may be used herein to describe elements of the present invention. Each of these terms is not used to limit the nature, order, sequence or number of elements, etc., but is only used to distinguish the corresponding element from other elements.

[0039] When it is mentioned that a first element is "connected or coupled to", "contacts or overlaps", etc. a second element, it should be understood that not only the first element can be "directly connected or coupled to" or "directly contact or overlaps" the second element, but also a third element can be "inserted" between the first element and the second element, or the first element and the second element can be "connected or coupled to", "contacts or overlaps", etc. each other via a fourth element. Here, the second element can be included in at least one of the two or more elements that are "connected or coupled to", "contacts or overlaps", etc. each other.

[0040] When time-related terms such as “after,” “subsequently,” “next,” “before,” etc. are used to describe a process or operation of an element or configuration, or a flow or step in an operation, process, or manufacturing method, these terms may be used to describe non-sequential or non-sequential processes or operations unless the terms “directly” or “immediately” are used together.

[0041] In addition, when referring to any dimension, relative size, etc., it should be considered that the numerical value of the element or feature, or the corresponding information (e.g., level, range, etc.) includes the tolerance or error range that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no relevant description is specified. In addition, the term "can" fully includes all meanings of the term "may".

[0042] Hereinafter, various embodiments of the present disclosure are described in detail with reference to the accompanying drawings.

[0043] Figure 1 is a view showing a display device 100 according to an embodiment of the present disclosure.

[0044] Reference Figure 1 , a display device 100 according to an embodiment of the present disclosure may include: a display panel 110 ; a data driving unit 120 and a gate driving unit 130 for driving the display panel 110 ; and a controller 140 for controlling the data driving unit 120 and the gate driving unit 130 .

[0045] In the display panel 110, signal lines such as a plurality of data lines DL and a plurality of gate lines GL may be disposed on a substrate. In the display panel 110, a plurality of sub-pixels SP connected to the plurality of data lines DL and the gate lines GL may be disposed.

[0046] The display panel 110 may include a display area AA where an image is displayed and a non-display area NA where no image is displayed. In the display panel 110, a plurality of sub-pixels SP for displaying an image may be provided in the display area AA, and a data driving unit 120 and a gate driving unit 130 may be installed in the non-display area NA, or a pad unit connected to the data driving unit 120 or the gate driving unit 130 may be provided.

[0047] The data driving unit 120 is a circuit for driving a plurality of data lines DL, and may supply data voltages to the plurality of data lines DL. The gate driving unit 130 is a circuit for driving a plurality of gate lines GL, and may supply gate signals to the plurality of gate lines GL. The controller 140 may supply a data driving timing control signal DCS to the data driving unit 120 to control the operation timing of the data driving unit 120. The controller 140 may supply a gate driving timing control signal GCS to the gate driving unit 130 for controlling the operation timing of the gate driving unit 130.

[0048] The controller 140 can start scanning according to the timing implemented in each frame, convert the input image data input from the outside into image data DATA in a data signal format suitable for use in the data driving unit 120, supply the image data DATA to the data driving unit 120, and control the data drive at an appropriate time suitable for scanning.

[0049] The controller 140 receives various timing signals including a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, an input data enable signal DE, and a clock signal, and input image data from the outside (eg, a host system).

[0050] In order to control the data driving unit 120 and the gate driving unit 130, the controller 140 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, an input data enable signal DE, and a clock signal CLK, generates various control signals DCS and GCS, and outputs the control signals to the data driving unit 120 and the gate driving unit 130.

[0051] In order to control the gate driving unit 130 , the controller 140 outputs various gate driving timing control signals GCS including a gate start pulse GSP, a gate shift clock GSC, and a gate output enable signal GOE.

[0052] In order to control the data driving unit 140 , the controller 140 outputs various data driving timing control signals DCS including, for example, a source start pulse SSP and a source sampling clock.

[0053] The data driving unit 120 receives image data DATA from the controller 140 and drives a plurality of data lines DL.

[0054] The data driving unit 120 may include one or more source driver integrated circuits (SDICs).

[0055] Each source driver integrated circuit (SDIC) can be connected to the display panel 110 through a tape automated bonding (TAB) method, or connected to a bonding pad of the display panel 110 through a chip on glass (COG) method, or can be implemented through a chip on film (COF) method and connected to the display panel 110.

[0056] The gate driving unit 130 may output a gate signal of an on-level voltage or a gate signal of an off-level voltage according to the control of the controller 140. The gate driving unit 130 may drive the plurality of gate lines GL by supplying the gate signal of an on-level voltage to the plurality of gate lines GL.

[0057] The gate driving unit 130 may be connected to the display panel 110 through a tape automated bonding (TAB) method, or connected to a bonding pad of the self-luminous display panel 110 through a COG or chip on panel (COP) method, or may be connected to the display panel 110 according to a COF method.

[0058] The gate driving unit 130 may be formed in a gate-in-panel (GIP) type in the non-display area NA of the display panel 110. The gate driving unit 110 may be disposed on a substrate of the display panel 110 or may be connected to the substrate of the display panel 110. The gate driving unit 130 as a GIP type may be disposed in the non-display area NA of the substrate. The gate driving unit 130 as a chip-on-glass (COG) type or a chip-on-film (COF) type may be connected to the substrate of the display panel 110.

[0059] When a specific gate line GL is turned on by the gate driving circuit 130 , the data driving unit 120 may convert the image data DATA received from the controller 140 into an analog data voltage and supply the analog data voltage to the plurality of data lines DL.

[0060] The data driving unit 120 may be connected to one side (e.g., the upper side or the lower side) of the display panel 110. Depending on a driving scheme or a panel design scheme, the data driving unit 120 may be connected to both sides (e.g., the upper side and the lower side) of the self-luminous display panel 110, or to two or more of the four sides of the self-luminous display panel 110.

[0061] The gate driving unit 130 may be connected to one side (e.g., the left side or the right side) of the display panel 110. Depending on a driving scheme or a panel design scheme, the gate driving unit 130 may be connected to both sides (e.g., the left side and the right side) of the display panel 110, or to two or more of the four sides of the display panel 110.

[0062] The controller 140 may be a timing controller used in display technology, a control device that may perform other control functions as well as the functions of the timing controller, or a control device other than the timing controller, or may be a circuit in the control device. The controller 140 may be implemented as various circuits or electronic components, such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a processor.

[0063] The controller 140 may be mounted on a printed circuit board or a flexible printed circuit, and may be electrically connected to the data driving unit 120 and the gate driving unit 130 through the printed circuit board or the flexible printed circuit.

[0064] The controller 140 may transmit / receive signals to / from the data driving unit 120 according to one or more predetermined interfaces. The interface may include, for example, a low voltage differential signaling (LVDS) interface, an EPI interface, and a serial peripheral interface (SPI).

[0065] The controller 140 may include a storage medium, such as one or more registers.

[0066] The display device 100 according to an embodiment of the present disclosure may be a display including a backlight unit, such as a liquid crystal display, or may be a self-luminous display, such as an organic light emitting diode (OLED) display, a quantum dot display, or a micro light emitting diode (LED) display.

[0067] According to an embodiment, when the display device 100 is an OLED display, each sub-pixel SP may include a self-luminous organic light emitting diode (OLED) as a light emitting element. According to an embodiment, when the display device 100 is a quantum dot display, each sub-pixel SP may include a light emitting element formed of a quantum dot as a self-luminous semiconductor crystal. According to an embodiment, when the display device 100 is a micro LED display, each sub-pixel SP may include a self-luminous micro light emitting diode formed of an inorganic material as a light emitting element.

[0068] Figure 2 is a view schematically showing a display device 100 according to an embodiment of the present disclosure.

[0069] Figure 2An example is shown in which the data driving unit 120 in the display device 100 according to an embodiment of the present disclosure is implemented in a chip on film (COF) scheme among various schemes such as TAB, COG, or COF.

[0070] The data driving unit 120 may include one or more data driving circuits 200. The data driving circuit 200 may be implemented as a source driver integrated circuit (SDIC). When the data driving unit 120 is implemented in a chip on film (COF) scheme, the data driving circuit 200 may be mounted on a source circuit film (SF).

[0071] One side of the source circuit film (SF) may be electrically connected to the display panel 110. Lines for electrically connecting the source driving integrated circuit (SDIC) and the display panel 110 may be disposed on the source circuit film (SF).

[0072] The display device 100 according to an embodiment of the present disclosure may include: at least one source printed circuit board SPCB for circuit connection between one or more data driving circuits 200 and other devices; and a control printed circuit board CPCB.

[0073] The other side of the source circuit film (SF) may be electrically connected to the source printed circuit board SPCB.

[0074] Figure 2 An example is shown in which the gate driving unit 130 in the display device 100 according to the embodiment of the present disclosure is implemented in a chip on film (COF) scheme among various schemes such as TAB, COG, COF, or GIP.

[0075] The gate driving unit 130 may include a gate driving integrated circuit (GDIC). When the gate driving unit 130 is implemented in a chip on film (COF) scheme, the gate driving integrated circuit (GDIC) may be mounted on a gate circuit film (GF).

[0076] One side of the gate circuit film (GF) may be electrically connected to the display panel 110. A line for electrically connecting the gate driving integrated circuit (GDIC) and the display panel 110 may be disposed on the gate circuit film (GF).

[0077] The controller 140 and a power management integrated circuit (PMIC) 240 may be mounted on the control printed circuit board CPCB. The controller 140 may control the data driving unit 120 and the gate driving unit 130. The power management integrated circuit 240 may supply driving voltage or current to the display panel 110, the data driving unit 120, and the gate driving unit 130.

[0078] At least one source printed circuit board SPCB and the control printed circuit board CPCB may be circuit-connected by at least one connecting member. The connecting member may be, for example, a flexible printed circuit (FPC) or a flexible flat cable (FFC).

[0079] At least one source printed circuit board SPCB and a control printed circuit board CPCB may be integrated into one printed circuit board.

[0080] The display device 100 according to an embodiment of the present disclosure may further include a setting board 210 electrically connected to the control printed circuit board CPCB. A main power management circuit 220 for managing the overall power of the display device 100 may be provided on the setting board 210. The main power management circuit 220 may interact with the power management integrated circuit 240.

[0081] The driving voltage generated by the setting board 210 is transmitted to the power management integrated circuit 240 in the control printed circuit board (CPCB). The power management integrated circuit 240 transmits the driving voltage required for driving the display device 100 or sensing the characteristic value (for example, sensing the characteristic value of the sub-pixel or sensing the input / output deviation of the analog-to-digital converter) to the source printed circuit board SPCB through the connection member. The power management integrated circuit 240 can supply the driving voltage to the data driving unit 120, the gate driving unit 130 or the display panel 110.

[0082] Figure 3 is a view schematically illustrating an equivalent circuit of a sub-pixel SP and a configuration for compensating a characteristic value of the sub-pixel SP according to an embodiment of the present disclosure.

[0083] Reference Figure 3 , each of a plurality of sub-pixels SP provided on the display panel 110 of the display device 100 according to an embodiment of the present disclosure may include a light emitting element ED, a driving transistor DRT, a scanning transistor TSC, and a storage capacitor Cst.

[0084] The light emitting element ED may include a pixel electrode PE and a common electrode CE, and may include a light emitting layer EL between the pixel electrode PE and the common electrode CE.

[0085] The pixel electrode PE of the light emitting element ED may be an electrode provided in each sub-pixel SP, and the common electrode CE may be an electrode provided in common in all sub-pixels SP. Here, the pixel electrode PE may be an anode electrode, and the common electrode CE may be a cathode electrode. Conversely, the pixel electrode PE may be a cathode electrode, and the common electrode CE may be an anode electrode.

[0086] For example, the light emitting element ED may be an organic light emitting diode (OLED), a light emitting diode (LED), or a quantum dot light emitting element.

[0087] The driving transistor DRT is a transistor for driving the light emitting element ED, and may include a first node N1, a second node N2, and a third node N3.

[0088] The first node N1 of the driving transistor DRT may be a gate node of the driving transistor DRT and may be electrically connected to a source node or a drain node of the scanning transistor SCT. The second node N2 of the driving transistor DRT may be a source node or a drain node of the driving transistor DRT and may be electrically connected to a source node or a drain node of the sensing transistor SENT and may also be electrically connected to a pixel electrode PE of the light emitting element ED. The third node N3 of the driving transistor DRT may be electrically connected to a driving voltage line DVL supplying a driving voltage EVDD.

[0089] The scanning transistor SCT may be controlled by a scanning pulse SCAN as a gate signal and may be connected between the first node N1 of the driving transistor DRT and the data line DL. In other words, the scanning transistor SCT may be turned on or off according to the scanning pulse SCAN supplied from the scanning line SCL as a gate line GL, thereby controlling the connection between the data line DL and the first node N1 of the driving transistor DRT.

[0090] The scan transistor SCT may be turned on by a scan pulse SCAN having an on-level voltage and transmit the data signal Vdata supplied from the data line DL to the first node N1 of the driving transistor DRT.

[0091] If the scan transistor SCT is an n-type transistor, the on-level voltage of the scan pulse SCAN may be a high-level voltage. If the scan transistor SCT is a p-type transistor, the on-level voltage of the scan pulse SCAN may be a low-level voltage.

[0092] The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2 of the driving transistor DRT. The storage capacitor Cst is charged with an amount of charge corresponding to the voltage difference between its two ends and is used to maintain the voltage difference between the two ends during a predetermined frame time. Therefore, during the predetermined frame time, the corresponding sub-pixel SP may emit light.

[0093] Reference Figure 3 , each of the plurality of sub-pixels SP disposed on the display panel 110 of the display device 100 may further include a sensing transistor SENT.

[0094] The sensing transistor SENT may be controlled by a sensing pulse SENSE as a gate signal and may be connected between the second node N2 of the driving transistor DRT and the sensing line SL. In other words, the sensing transistor SENT may be turned on or off according to the sensing pulse SENSE supplied from the sensing line SENL as another gate line GL, thereby controlling the connection between the sensing line SL and the second node N2 of the driving transistor DRT.

[0095] The sensing transistor SENT may be turned on by a sensing pulse SENSE having an on-level voltage and transmit a reference voltage Vref supplied from the sensing line SL to the second node N2 of the driving transistor DRT. The sensing line SL is also referred to as a reference voltage line.

[0096] The reference voltage Vref may be applied to the sensing line SL through the reference voltage switch SPRE. One end of the reference voltage supply switch SPRE may be electrically connected to the sensing line SL, and the other end thereof may be electrically connected to a reference voltage supply node Nref to which the reference voltage Vref is supplied.

[0097] The sensing transistor SENT may be turned on by the sensing pulse SENSE having an on-level voltage and transmit the voltage of the second node N2 of the driving transistor DRT to the sensing line SL.

[0098] If the sensing transistor SENT is an n-type transistor, the on-level voltage of the sensing pulse SENSE may be a high-level voltage. If the sensing transistor SENT is a p-type transistor, the on-level voltage of the sensing pulse SENSE may be a low-level voltage.

[0099] The function in which the sensing transistor SENT transmits the voltage of the second node N2 of the driving transistor DRT to the sensing line SL can be used when driving to sense the characteristic value of the sub-pixel SP. In this case, the voltage transmitted to the sensing line SL can be a voltage for calculating the characteristic value of the sub-pixel SP or a voltage reflecting the characteristic value of the sub-pixel SP.

[0100] Each of the driving transistor DRT, the scanning transistor SCT and the sensing transistor SENT may be an n-type transistor or a p-type transistor. In an embodiment of the present disclosure, for ease of description, each of the driving transistor DRT, the scanning transistor SCT and the sensing transistor SENT is an n-type transistor.

[0101] The storage capacitor Cst is not a parasitic capacitor (eg, Cgs or Cgd) as an internal capacitor existing between the gate node and the source node (or drain node) of the driving transistor DRT, but may be an external capacitor intentionally designed outside the driving transistor DRT.

[0102] The scan line SCL and the sensing line SENL may be different gate lines GL. In this case, the scan pulse SCAN and the sensing pulse SENSE may be separate gate signals, and the on-off timing of the scan transistor SCT and the on-off timing of the sensing transistor SENT in one sub-pixel SP may be independent. In other words, the on-off timing of the scan transistor SCT and the on-off timing of the sensing transistor SENT in one sub-pixel SP may be the same or different.

[0103] Alternatively, the scan line SCL and the sensing line SENL may be the same gate line GL. In other words, the gate node of the scan transistor SCT and the gate node of the sensing transistor SENT in one sub-pixel SP may be connected to one gate line GL. In this case, the scan pulse SCAN and the sensing pulse SENSE may be the same gate signal, and the on-off timing of the scan transistor SCT and the on-off timing of the sensing transistor SENT in one sub-pixel SP may be the same.

[0104] Figure 3 The structure of the subpixel SP shown is merely an example, and various changes may be made thereto, such as including one or more transistors or one or more capacitors, for example.

[0105] Although it is assumed that the display device 100 is a self-luminous display device, referring to Figure 3 The structure of the sub-pixel is described, but if the display device 100 is a liquid crystal display, each sub-pixel SP may include a transistor and a pixel electrode.

[0106] Reference Figure 3 , the display device 100 according to an embodiment of the present disclosure may include a line capacitor Cline. The line capacitor Cline may be a capacitor element having one end electrically connected to the sensing line SL, or may be a parasitic capacitor formed on the sensing line SL.

[0107] The sensing line SL may be electrically connected to a sensing unit 330 included in the data driving circuit 200. The sensing unit 330 may sense a voltage of the sensing line SL. The voltage sensed by the sensing unit 330 may be a voltage reflecting a characteristic value of the sub-pixel SP. Here, the sensing unit 330 is a portion that senses a voltage of a characteristic value of the sub-pixel SP through the sensing line SL and may be referred to as a sensing portion or a sensing circuit.

[0108] In the disclosure, the characteristic value of the subpixel SP may be a characteristic value of the driving transistor DRT or the light emitting element ED. The characteristic value of the driving transistor DRT may include a threshold voltage and mobility of the driving transistor DRT. The characteristic value of the light emitting element ED may include a threshold voltage of the light emitting element ED.

[0109] The sensing unit 330 may further include a sampling switch and an analog-to-digital converter. In this case, the sensing unit 330 may receive an analog voltage, convert the analog voltage into a digital value, and output the digital value to the controller 140.

[0110] The controller 140 may include a storage unit 310 that stores characteristic value information about the sub-pixel SP and a compensation circuit that performs calculation for compensating for a variation in the characteristic value of the sub-pixel SP based on the information stored in the storage unit 310 .

[0111] The storage unit 310 may store information for compensating characteristic values ​​of the subpixels SP. For example, the storage unit 310 may store information about the threshold voltage and mobility of the driving transistor DRT of each of the plurality of subpixels SP and information about the threshold voltage of the light emitting element ED included in the subpixel SP.

[0112] The compensation circuit 320 calculates the variation degree of the characteristic value of the corresponding subpixel SP based on the characteristic value information about the subpixel SP stored in the storage unit 310 and the digital value received from the sensing unit 330. The compensation circuit 320 updates the characteristic value of the subpixel SP stored in the storage unit 310.

[0113] The controller 140 compensates for the image data by applying the characteristic value variation of the sub-pixel SP calculated by the compensation circuit 320 , thereby driving the data driving unit 120 .

[0114] The data voltage Vdata reflecting the change of the characteristic value of the sub-pixel SP may be output to the data line DL through the digital-to-analog converter DAC.

[0115] The process of sensing the characteristic value change of the sub-pixel SP and compensating for it is referred to as a “sub-pixel characteristic value compensation process”.

[0116] Figure 4 is a view showing a data driving circuit 200 of the display device 100 according to an embodiment of the present disclosure.

[0117] Reference Figure 4 The data driving circuit 200 may include a shift register unit 410 , a latch unit 420 , a digital-to-analog conversion unit 430 , an output buffer unit 440 , a data receiving unit 450 , and a sensing unit 330 .

[0118] The data receiving unit 450 receives the image data Data from the controller 140 , converts the image data Data into predetermined-bit digital data for each color (eg, RGB or RGBW) displayed by a plurality of sub-pixels SP included in the pixel array, and outputs the bit digital data.

[0119] The shift register 410 may include a plurality of shift registers to drive a plurality of data lines DL.

[0120] The plurality of shift registers may be configured to sequentially transfer a horizontal synchronization signal Hsync transmitted from the controller 140 in response to a horizontal clock signal HCLK.

[0121] The shift register unit 410 controls the driving time of the plurality of data lines DL using the horizontal synchronization signal Hsync and the horizontal clock signal HCLK. In other words, the horizontal synchronization signal Hsync and the horizontal clock signal HCLK are received from the controller 140, and all data corresponding to one gate line GL selecting the horizontal synchronization signal HSync as a start signal are synchronized with the horizontal clock signal HCLK, and are sequentially sampled and stored in the latch unit 420.

[0122] The latch unit 420 may include a first latch unit including a plurality of first latches and a second latch unit including a plurality of second latches.

[0123] The plurality of first latches may receive and store image data of the sub-pixels SP to be provided to the gate lines GL driven by the gate driving unit 130 among the plurality of gate lines GL.

[0124] The plurality of second latches receive and store data stored in corresponding first latches among the plurality of first latches according to the next horizontal synchronization signal Hsync received from the controller 140 .

[0125] The digital-to-analog conversion unit 430 may include a plurality of digital-to-analog converters (DACs) that convert data stored in corresponding second latches among the plurality of second latches into analog data voltages.

[0126] The digital-to-analog conversion unit 430 may receive a gamma reference voltage GRV from the outside, and may convert the digital data stored in the second latch into an analog data voltage based on the received gamma reference voltage.

[0127] The output buffer unit 440 may include a plurality of output buffers that may amplify driving forces of data voltages output from corresponding digital-to-analog converters among the plurality of digital-to-analog converters DAC and supply the amplified data voltages to corresponding data lines DL.

[0128] Each of the plurality of digital-to-analog converters DAC is electrically connected to one of the plurality of output terminals CH_OUT. The analog voltage output from the digital-to-analog converter DAC is transmitted to the output terminal CH_OUT connected to the corresponding digital-to-analog converter DAC.

[0129] Each of the plurality of data lines DL may be electrically connected to a corresponding output terminal CH_OUT.

[0130] In the data driving circuit 200 according to the embodiment of the present disclosure, k (1≦k) sensing terminals CH_IN1 to CH_INk may be provided, where k is a positive integer. The k sensing terminals CH_IN1 to CH_INk may be electrically connected to the sensing unit 330 .

[0131] The sensing unit 330 may receive an analog voltage and convert the analog voltage into a digital signal. The sensing unit 330 may include at least one analog-to-digital converter (ADC) for converting the analog voltage into a digital signal.

[0132] The data driving circuit 200 may output the converted digital signal to the controller 140 .

[0133] An analog voltage may be applied to each of the k sensing terminals CH_IN1 to CH_INk When the sensing terminal CH_IN is electrically connected to the sensing line SL, a voltage reflecting a characteristic value of the sub-pixel SP may be applied to the sensing terminal CH_IN.

[0134] Reference Figure 4 , each of the k sensing terminals CH_IN1 to CH_INk and one or more output terminals CH_OUT may constitute one input / output unit 460 together.

[0135] The first sensing terminal CH_IN1 and the four output terminals CH_OUT1, CH_OUT2, CH_OUT3 and CH_OUT4 constitute one input / output unit 460. The kth sensing terminal CH_INk constitutes one input / output unit 460 together with the four output terminals CH_OUT4k-3, CH_OUT4k-2, CH_OUT4k-1 and CH_OUT4k.

[0136] Each of the plurality of sub-pixels SP is connected to a data line DL and a sensing line SL. The data line DL and the sensing line SL connected to one sub-pixel SP are electrically connected to an output terminal CH_OUT and a sensing terminal CH_IN belonging to one input / output unit 460, respectively.

[0137] Figure 5 is a view showing a connection relationship among a sensing terminal CH_IN, an output terminal CH_OUT, a sensing line SL, and a data line DL of a display device 100 according to an embodiment of the present disclosure.

[0138] Reference Figure 5, k sensing terminals CH_IN1 to CH_INk provided on the data driving circuit 200 may be electrically connected to k sensing lines SL1 to SLk among a plurality of sensing lines SL provided on the display panel 110. The output terminal CH_OUT constituting one input / output unit 460 together with the k sensing terminals CH_IN1 to CH_INk is electrically connected to each of the data lines DL.

[0139] Reference Figure 5 The first output terminal CH_IN1 is electrically connected to the first sensing line SL1. The four output terminals CH_OUT1, CH_OUT2, CH_OUT3 and CH_OUT4 forming one input / output unit 460 together with the first output terminal CH_IN1 are electrically connected to the corresponding data lines DL1, DL2, DL3 and DL4, respectively.

[0140] The first sensing line SL1 electrically connected to the first sensing terminal CH_IN1 is electrically connected to four sub-pixels SP1 , SP2 , SP3 , and SP4 receiving a gate voltage from the same gate line GL.

[0141] The four sub-pixels SP1 , SP2 , SP3 , and SP4 receive data voltages through four data lines DL1 , DL2 , DL3 , and DL4 , respectively.

[0142] The four data lines DL1 , DL2 , DL3 and DL4 are electrically connected to four output terminals CH_OUT1 , CH_OUT2 , CH_OUT3 and CH_OUT4 , respectively, and the four output terminals CH_OUT1 , CH_OUT2 , CH_OUT3 and CH_OUT4 together with the first sensing terminal CH_IN1 constitute one input unit 460 .

[0143] The sensing unit 330 may include a plurality of sampling switches 510 , a plurality of sample and hold circuits 520 , and at least one analog-to-digital converter 530 .

[0144] The analog-to-digital converter 530 may receive analog voltages from the k sensing terminals CH_IN1 and CH_INk.

[0145] Each of the plurality of sampling and holding circuits 520 measures a voltage of one sensing terminal CH_IN among the k sensing terminals CH_IN1 to CH_INk electrically connected to the corresponding sampling and holding circuit 520. The measured voltage may be output to the analog-to-digital converter 530. In other words, the plurality of sampling and holding circuits 520 outputs the sampled analog voltage to the analog-to-digital converter 530.

[0146] One end of each of the plurality of sampling switches 510 is electrically connected to the sample and hold circuit 520 , and the other end is electrically connected to the sensing terminal CH_IN.

[0147] Reference Figure 5 , all k sensing terminals CH_IN1 to CH_INk provided in the data driving circuit 200 may be electrically connected to the sensing line SL. In this case, there is no unused sensing terminal CH_IN among the k sensing terminals CH_IN1 to CH_INk.

[0148] For example, when the data driving circuit 200 is differently designed according to the specification of the display panel 110 , all the sensing terminals CH_IN provided in the data driving circuit 200 may be used.

[0149] The specification of the display panel 110 may be, for example, information about the size of the display panel 110 , or information about which of the sensing terminals CH_IN of the data driving circuit 200 is to be connected to the sensing line SL.

[0150] The numbers of the sensing terminals CH_IN and the output terminals CH_OUT of the data driving circuit 200 required for each specification of the display panel 110 may be different.

[0151] For example, detailed specifications of the display panel 110 are as follows. The size of the display panel 110 may be size A. The display panel 110 having size A may require, for example, a data driving circuit 200 having 960 output terminals CH_OUT1 to CH_OUT960 and 240 sensing terminals CH_IN1 to CH_IN240 .

[0152] Therefore, the data driving circuit 200 should be designed to have 960 output terminals CH_OUT1 to CH_OUT960 and 240 sensing terminals CH_IN1 to CH_IN240 to drive the display panel 110 having the size A. FIG.

[0153] As another example, detailed specifications of the display panel 110 are as follows: The size of the display panel 110 may be size B. The display panel 110 having size B may require, for example, a data driving circuit 200 having 912 output terminals CH_OUT1 to CH_OUT912 and 228 sensing terminals CH_IN1 to CH_IN228 .

[0154] Therefore, the data driving circuit 200 should be designed to have 912 output terminals CH_OUT1 to CH_OUT912 and 228 sensing terminals CH_IN1 to CH_IN228 to drive the display panel 110 having the size B.

[0155] As another example, the detailed specifications of the display panel 110 are as follows. The size of the display panel 110 may be Size C. The display panel 110 having Size C may require, for example, a data driving circuit 200 having 640 output terminals CH_OUT1 to CH_OUT640 and 160 sensing terminals CH_IN1 to CH_IN160.

[0156] Therefore, the data driving circuit 200 should be designed to have 640 output terminals CH_OUT1 to CH_OUT640 and 160 sensing terminals CH_IN1 to CH_IN160 to drive the display panel 110 having Size C.

[0157] As another example, the detailed specifications of the display panel 110 are as follows. The size of the display panel 110 may be Size D. The display panel 110 having Size D may require, for example, a data driving circuit 200 having 480 output terminals CH_OUT1 to CH_OUT480 and 120 sensing terminals CH_IN1 to CH_IN120.

[0158] Therefore, the data driving circuit 200 should be designed to have 480 output terminals CH_OUT1 to CH_OUT480 and 120 sensing terminals CH_IN1 to CH_IN120 to drive the display panel 110 having Size D.

[0159] For the above reasons, the number of sensing terminals CH_IN of the data driving circuit 200 required for each specification of the display panel 110 is different, and it is difficult to use the same type of data driving circuit 200 for four different types of display panels A, B, C, and D.

[0160] Figure 6 is a view showing an example of a floating problem of the sensing terminals (CH_IN) due to the common use of the data driving circuit 200.

[0161] Refer to Figure 6 , although k sensing terminals CH_IN1 to CH_INk are provided in the data driving circuit 200, the number of sensing terminals CH_IN among the k sensing terminals CH_IN1 to CH_INk that are electrically connected to the sensing line SL may be less than k.

[0162] For example, among the k sensing terminals CH_IN1 to CH_INk provided in the data driving circuit 200, only n (1 ≤ n < k) sensing terminals CH_IN may be electrically connected to the sensing line SL, and the remaining k - n sensing terminals CH_IN among the k sensing terminals CH_IN1 to CH_INk may not be electrically connected to the sensing line SL.

[0163] Refer to Figure 6, two sensing terminals CH_IN1 and CH_INk among the k sensing terminals CH_IN1 to CH_INk may be sensing terminals CH_IN disposed in the second sensing terminal region 620 that is not connected to the sensing line SL. Among the k sensing terminals CH_IN1 to CH_INk, except for the two sensing terminals CH_IN1 and CH_Ink disposed in the second sensing terminal region 620, the remaining sensing terminals CH_IN2 to CH_INk-1 may be electrically connected to the corresponding sensing lines SL, respectively. The sensing terminals CH_IN2 to CH_INk-1 electrically connected to the sensing line SL may be disposed in the first sensing terminal region 610.

[0164] exist Figure 6 In the display device 100, two sensing terminals CH_IN1 and CH_INk disposed in the second sensing terminal region 620 are in a floating state to which a constant voltage is not applied. For example, the two sensing terminals CH_IN1 and CH_INk are not connected to the corresponding sensing lines SL because there are more sensing terminals in the data driving circuit 200 than sensing lines SL in the display panel 110 (for example, in this case, the data driving circuit 200 is sized to be larger than the display panel 110, and therefore, some extra / unused sensing terminals are not connected to any sensing line and will be in a floating state).

[0165] For example, when the data driving circuit 200 optimized for driving the display panel 110 having a size A is used for a display panel 110 having a size B (size B is smaller than size A), some sensing terminals CH_IN provided in the corresponding driving circuit 200 may be in a floating state. When the sensing terminal CH_IN is in a floating state, the electrical stability of the corresponding driving circuit 200 may be reduced. For example, when the data driving circuit 200 is sized to be larger than the display panel 110, there will be some unused sensing terminals that exist in a floating state. Since these unused sensing terminals are floating, unknown or unwanted voltages may appear on the unused sensing terminals, which may cause problems or interference with the display device (e.g., such as causing the data driving circuit 200 to enter an unstable state).

[0166] Therefore, in order to commonly use the same type of data driving circuit 200 in different types of display panels 100 having different specifications, it is desirable to apply a constant voltage to the unused sensing terminal CH_IN provided in the second sensing terminal area 620. For example, the first sensing terminal area 610 corresponds to an area where each sensing terminal is connected to a corresponding sensing line in the display panel 110, and the second sensing terminal area 620 corresponds to an area where there are additional sensing terminals that are not connected to any sensing line in the display panel 110, because the data driving circuit 200 is sized to be larger than the display panel 110, and can also be applied to other types of display panels having a size larger or smaller than the display panel 110.

[0167] Figure 7 2 is a view showing a data driving circuit 200 and a display panel 110 according to an embodiment of the present disclosure.

[0168] The display device 100 according to an embodiment of the present disclosure includes a display panel 110 and one or more data driving circuits 200 electrically connected to the display panel 110 .

[0169] Each of the one or more data driving circuits 200 may include a digital-to-analog conversion unit 430 , a sensing unit 330 , and a switching unit 710 .

[0170] The switch unit 710 may include one or more switch elements 715. Here, the switch unit 710 is a portion for controlling an electrical connection with the sensing terminal CH_IN, and may be referred to as a switch portion or a switch circuit.

[0171] One or more switch elements 715 are electrically connected to the sense terminal CH_IN via a sense terminal branch node 720 .

[0172] A plurality of sub-pixels SP and a plurality of sensing lines SL electrically connected to the plurality of sub-pixels SP are disposed on the display panel 110 .

[0173] like Figure 7 As shown, each of the plurality of sensing lines SL may be electrically connected to n (1≤n≤k) sensing terminals CH_IN among k sensing terminals CH_IN1 to CH_INk provided in each of the one or more data driving circuits 200. Each of the plurality of data lines DL corresponds to any one of the plurality of output terminals CH_OUT provided in each of the one or more data driving circuits 200, and each data line DL may be electrically connected to the output terminal CH_OUT.

[0174] Every n sensing lines SL can be electrically connected to one of one or more data driving circuits 200. When the display device 100 may include two or more data driving circuits 200, multiple sensing lines SL are divided into every n (1 ≤ n ≤ k) sensing lines SL, which are connected to the data driving circuits among two or more data driving circuits 200.

[0175] Among the k sensing terminals CH_IN1 to CH_INk provided in each of one or more data driving circuits 200, n sensing terminals CH_IN are electrically connected to corresponding sensing lines SL.

[0176] Referring to Figure 7 , in the display device 100 according to an embodiment of the present disclosure, among the k sensing terminals CH_IN1 to CH_INk, n (1 ≤ n < k) sensing terminals CH_IN may be electrically connected to corresponding sensing lines SL, and the remaining k - n sensing terminals CH_IN among the k sensing terminals CH_IN1 to CH_INk may not be electrically connected to any sensing lines SL. For example, the first sensing terminal region 610 corresponds to the region where each of the sensing terminals is connected to a corresponding sensing line in the display panel 110, while the second sensing terminal region 620 corresponds to the region where there are additional sensing terminals that are not connected to any sensing lines in the display panel 110, because the size of the data driving circuit 200 is larger than that of the display panel 110.

[0177] In addition, the n (1 ≤ n < k) sensing terminals CH_IN among the k sensing terminals CH_IN1 to CH_INk that are connected to the corresponding sensing lines SL may be positioned more inward than the remaining k - n sensing terminals CN_IN that are not connected to the sensing lines SL. In other words, the unused k - n sensing terminals CH_IN that are not connected to any sensing lines SL may be positioned more outward than the n sensing terminals CH_IN that are electrically connected to the sensing lines SL.

[0178] In other words, the second sensing terminal region 620 may be located outside the first sensing terminal region 610. In other words, when connecting the sensing lines to the sensing terminals (e.g., referring to region 610), the center of the smaller-sized display panel may be aligned with the center of the larger-sized data driving circuit 200, such that there will be additional unused sensing terminals at the outer edge of the data driving circuit 200 (e.g., referring to region 620).

[0179] The sensing terminals CH_IN located in the second sensing terminal region 620 (e.g., the unused sensing terminal region) are electrically connected to the constant voltage supply terminal CH_RTA. In addition, a constant voltage VRTA is applied to the corresponding sensing terminals CH_IN in the second sensing terminal region 620, and any unused sensing terminals can be prevented from entering a floating state.

[0180] Among one or more switching elements 715 , a switching element 715 having one end connected to a sensing terminal branch node 720 provided in the second sensing terminal region 620 may be turned on (eg, to supply a constant voltage VRTA to an unused sensing terminal located at an outer edge).

[0181] Among one or more switching elements 715, the switching element 715 having one end connected to the sensing terminal branch node 720 of the sensing terminal CH_IN set in the first sensing terminal area 610 can be turned off (for example, so as to prevent the constant voltage VRTA from being applied to the sensing terminal that is actually being used and connected to the corresponding sensing line SL in the display panel 110).

[0182] Therefore, the voltage applied to the sensing line SL may be supplied to the sensing terminal CH_IN disposed in the first sensing terminal region 610. The constant voltage VRTA may be applied to the sensing terminal CH_IN disposed in the second sensing terminal region 620. In other words, the used sensing terminals may receive a voltage from their corresponding sensing lines from the display panel, while the unused sensing terminals not connected to any sensing line in the display panel may be supplied with the constant voltage VRTA.

[0183] Reference Figure 7 , the first sensing terminal CH_IN1 and the kth sensing terminal CH_INk are not electrically connected to the corresponding sensing lines SL (for example, the outermost sensing terminals may not be used), and the remaining sensing terminals, i.e., the second sensing terminal to the k-1th sensing terminal CH_IN2 to CH_INk-1, may be electrically connected to multiple sensing lines SL, respectively.

[0184] The first sensing terminal CH_IN1 and the kth sensing terminal CH_INk are sensing terminals CH_IN located in the second sensing terminal region 620 (e.g., an unused region). The remaining sensing terminals, i.e., the second sensing terminal CH_IN2 to the k-1th sensing terminal CH_INk-1, are sensing terminals CH_IN located in the first sensing terminal region 610 (e.g., a used region).

[0185] Reference Figure 7 , the second sense terminal region 620 is located outside the first sense terminal region 610. In this way, it is easier to supply the constant voltage VRTA to the unused sense terminals because they are located towards the outer edge and are more accessible, thereby reducing wiring requirements.

[0186] One end of the switch element 715 corresponding to the first sensing terminal CH_IN1 is electrically connected to the sensing terminal branch node 720 of the first sensing terminal CH_IN1. The other end of the corresponding switch element 715 is electrically connected to the constant voltage supply terminal CH_RTA. The constant voltage VRTA is applied to the other end of the corresponding switch element 715.

[0187] The first sensing terminal CH_IN1 is not electrically connected to the sensing line SL (eg, the first sensing terminal CH_IN1 is not used). Therefore, the switching element 715 corresponding to the first sensing terminal CH_IN1 may be turned on, and the constant voltage VRTA is applied to the corresponding first sensing terminal CH_IN1 through the switching element 715 .

[0188] One end of the switch element 715 corresponding to the kth sensing terminal CH_INk is electrically connected to the sensing terminal branch node 720 of the kth sensing terminal CH_INk. The other end of the corresponding switch element 715 is electrically connected to the constant voltage supply terminal CH_RTA. The constant voltage VRTA is applied to the other end of the corresponding switch element 715.

[0189] The kth sensing terminal CH_INk is not electrically connected to the sensing line SL (the kth sensing terminal CH_INk is not used). Therefore, the switching element 715 corresponding to the kth sensing terminal CH_INk can be turned on and the constant voltage VRTA is applied to the kth sensing terminal CH_INk through the switching element 715 corresponding to the kth sensing terminal CH_INk.

[0190] The constant voltage supply terminal CH_RTA may be located at two opposite ends of the switch unit 710. One or more switch elements 715 included in the switch unit 710 may be connected in series between the constant voltage supply terminals CH_RTA at the two opposite ends. Since the constant voltage supply terminal CH_RTA and the unused sensing terminal are located at opposite outer ends, the wiring for supplying a constant voltage to the unused sensing terminal may be reduced.

[0191] In the display device 100 according to an embodiment of the present disclosure, the analog-to-digital converter 530 may sense an analog voltage applied to each of the k sensing terminals CH_IN1 to CH_INk.

[0192] The analog-to-digital converter 530 may sense a voltage applied to a sensing terminal CH_IN located in the first sensing terminal region 610. The voltage applied to the corresponding sensing terminal CH_IN in the first sensing terminal region 610 may be a voltage reflecting a characteristic value of the sub-pixel SP. The voltage level of the voltage reflecting the characteristic value of the sub-pixel SP may vary according to a sensing timing.

[0193] However, the analog-to-digital converter 530 may also sense voltages applied to the sensing terminals CH_IN located in the second sensing terminal region 620. The voltages applied to the corresponding sensing terminals CH_IN in the second sensing terminal region 620 may all have the same voltage level as the constant voltage VRTA supplied from the constant voltage supply terminal CH_RTA.

[0194] The voltage input from the sensing terminal CH_IN located in the second sensing terminal region 620 may be a voltage whose voltage level does not vary according to a sensing period (eg, a constant stable voltage level of a predetermined value).

[0195] The display device 100 according to an embodiment of the present disclosure can compensate the characteristic value of the analog-to-digital converter 530 using the characteristic of applying a predetermined voltage level of the constant voltage VRTA to the sensing terminal CH_IN disposed in the second sensing terminal area 620. A detailed description of the characteristic value compensation process of the analog-to-digital converter 530 is described below.

[0196] In short, according to Figure 7 The display device 100 of the embodiment of the present disclosure can provide a display device 100 in which a constant voltage VRTA is applied to a sensing terminal CH_IN that is not electrically connected to a corresponding sensing line SL from a display panel. Therefore, the data driving circuit 200 can be generally used for display panels 110 having various specifications. In other words, one type of data driving circuit 200 can be applied to different types of display panels 110 (for example, display panels of different sizes or areas).

[0197] The size of the first sensing terminal region 610 and the size of the second sensing terminal region 620 of the data driving circuit 200 may vary according to the specifications of the display panel 110 driven by the data driving circuit 200 .

[0198] Specifically, the size of the first sensing terminal region 610 and the size of the second sensing terminal region 620 may vary according to how many sensing terminals CH_IN among the k sensing terminals CH_IN1 to CH_INk included in the data driving circuit 200 are to be electrically connected to the sensing line SL.

[0199] Figure 8 FIG. 1 is a diagram showing a circuit having one or more switching elements 715 according to an embodiment of the present disclosure. Figure 7 FIG. 2 is a diagram of a data driving circuit 200 .

[0200] according to Figure 8 The data driving circuit 200 of the embodiment of the present disclosure includes k sensing terminals CH_IN1 to CH_INk, a constant voltage supply terminal CH_RTA, and a plurality of switching elements 715 .

[0201] exist Figure 8 In the embodiment, a plurality of switching elements 715 may be connected in series with each other.

[0202] exist Figure 8 In the present disclosure, the plurality of switch elements 715 may include switch elements 715a belonging to a first group (eg, a left group or an outer group) and switch elements 715b belonging to a second group (eg, a right group or an inner group).

[0203] The switching element 715 a belonging to the first group is defined as a switching element whose on / off is determined according to whether a specific sensing channel CH_IN among the plurality of switching elements 715 is electrically connected to the sensing line SL.

[0204] Reference Figure 8 , if the first sensing terminal CH_IN1 or the k-th sensing terminal CH_INk is electrically connected to the corresponding sensing line SL, the leftmost switching element 715a1 and the rightmost switching element 715a1 are each turned on, otherwise, if the first sensing terminal CH_IN1 and the k-th sensing terminal CH_Ink are not connected to the corresponding sensing line, the switching element 715a1 is turned off. Therefore, since the leftmost switching element 715a1 and the rightmost switching element 715a1 are switching elements whose on / off states are determined according to whether the first sensing terminal CH_IN1 or the k-th sensing terminal CH_INk is electrically connected to the sensing line SL, they are the switching elements 715a belonging to the first group.

[0205] Reference Figure 8 , if the second sensing terminal CH_IN2 or the k-1th sensing terminal CH_INk-1 is electrically connected to the sensing line SL, the second leftmost switching element 715a2 and the second rightmost switching element 715a2 are each turned on, otherwise, if these sensing terminals are not connected to the corresponding sensing line SL, the switching element 715a2 is turned off. Therefore, since the second leftmost switching element 715a2 and the second rightmost switching element 715a2 are switching elements whose on / off states are determined according to whether the second sensing terminal CH_IN2 or the k-1th sensing terminal CH_INk-1 is electrically connected to the sensing line SL, they are the switching elements 715a belonging to the first group.

[0206] The switching element 715 b belonging to the second group is defined as a switching element whose on / off state is determined only according to the state of the switching element 715 a belonging to the first group.

[0207] The switch elements 715b belonging to the second group may be the innermost two switch elements 715b of the plurality of switch elements 715 connected in series. The switch elements 715b belonging to the second group may be the remaining two switch elements 715b of the plurality of switch elements 715 connected in series except the switch element 715a belonging to the first group.

[0208] Reference Figure 8 According to the present disclosure, the plurality of switching elements 715 may be divided by the same number with respect to a middle line of the data driving circuit 200 and located in the left area and the right area.

[0209] When a plurality of switching elements 715 are connected in series, the switching elements 715 b belonging to the second group include the innermost switching elements 715 b among the switching elements 715 disposed in the left region of the data driving circuit 200. When a plurality of switching elements 715 are connected in series, the switching elements 715 b belonging to the second group include the innermost switching elements 715 b among the switching elements 715 disposed in the right region of the data driving circuit 200.

[0210] In short, according to Figure 8 The plurality of switching elements 715 of the embodiment of the present disclosure may include m (m≧1) switching elements 715 belonging to the first group and two switching elements belonging to the second group, where m is a positive integer and an even number.

[0211] The constant voltage supply terminal CH_RTA supplies the constant voltage VRTA to the constant voltage supply line 730 .

[0212] The m switching elements 715a belonging to the first group may be the switching elements 715 corresponding to any one of the k sensing terminals CH_IN1 to CH_INk. Each of the one or more switching elements 715a belonging to the first group is electrically connected to a sensing terminal branch node 720 of the sensing terminal CH_IN corresponding to the corresponding switching element 715a.

[0213] One or more switching elements 715 a belonging to the first group may be turned on or off according to whether a sensing terminal CH_IN corresponding to the corresponding switching element 715 a is electrically connected to a sensing line SL from the display panel.

[0214] The constant voltage VRTA or the voltage of the sensing line SL may be applied to the sensing terminal CH_IN provided corresponding to the m switching elements 715 a belonging to the first group.

[0215] Reference Figure 8 , six switching elements 715 can be connected in series.

[0216] Among the six switch elements 715 connected in series, the remaining four switch elements 715a except the innermost two switch elements 715b are set to correspond to the first sensing terminal CH_IN1, the second sensing terminal CH_IN2, the k-1th sensing terminal CH_INk-1 and the kth sensing terminal CH_INk. In this case, m=4 (for example, the two outermost switch elements on the left and the two outermost switch elements on the right).

[0217] Two switching elements 715 b belonging to the second group (eg, an innermost pair of switches) may be electrically connected to each other through a switching element connection line 820 .

[0218] Each of the two switching elements 715b belonging to the second group is electrically connected to any one switching element 715a2 of the one or more switching elements 715a belonging to the first group. The other ends of the two switching elements 715b belonging to the second group are electrically connected to each other through a switching element connection line 820.

[0219] Only when one or more switching elements 715a belonging to the first group are all turned on, two switching elements 715b belonging to the second group may be turned on, for example, because they are configured in series.

[0220] If the one or more switching elements 715 b belonging to the second group are turned on, the constant voltage VRTA is applied to all of the one or more switching elements 715 a belonging to the first group and the one or more switching elements 715 b belonging to the second group.

[0221] Therefore, a voltage drop at the sensing terminal branch node 720 may be minimized (eg, because the constant voltage VRTA may be supplied to the opposite end of the constant voltage supply line 730 ).

[0222] Reference Figure 8 , the sensing terminal branch node 720 may not exist in some of the k sensing terminals CH_IN1 to CH_INk. The sensing terminal CH_IN lacking the sensing terminal branch node 720 is not connected to any of the one or more switching elements 715. Regardless of the specifications of the display panel 110, such a sensing terminal CH_IN may be a sensing terminal CH_IN that is always electrically connected to the sensing line SL (for example, the sensing terminal CH_IN located toward the center of the data driving circuit 200, which is almost always connected to the corresponding sensing line SL from the display panel, even when the data driving circuit 200 is applied to a small display).

[0223] Reference Figure 8Depending on the specifications of the display panel 110 (for example, depending on whether the display panel has a large area or a small area), the first sensing terminal CH_IN1, the second sensing terminal CH_IN2, the k-1th sensing terminal CH_INk-1 and the kth sensing terminal CH_INk may or may not be connected to the sensing line SL.

[0224] On the contrary, regardless of the specifications of the display panel 110 , the third to k-2 th sensing terminals CH_IN3 to CH_INk-2 may be sensing terminals CH_IN connected to the sensing line SL.

[0225] Among the k sensing terminals CH_IN1 to CH_INk, the third sensing terminal CH_IN3 to the k-2 th sensing terminal CH_INk-2 are electrically connected to the sensing line SL. In other words, n=k-4 sensing terminals CH_IN are electrically connected to the sensing line SL.

[0226] Furthermore, m, n, and k are positive integers and satisfy the formula k=m+n.

[0227] If the number of sensing lines SL connected to the data driving circuit 200 including the k sensing terminals CH_IN1 to CH_INk and the m switching elements 715 a increases, n increases.

[0228] In short, the formula k≤mn is satisfied.

[0229] The k sensing terminals CH_IN1 to CH_INk include m sensing terminals CH_IN corresponding to which the switch elements 715 are provided. The k sensing terminals CH_IN1 to CH_INk include n sensing terminals CH_IN electrically connected to the sensing line SL.

[0230] The m sensing terminals CH_IN may consist of only different sensing terminals CH_IN, and the n sensing terminals CH_IN may consist of only different sensing terminals CH_IN. Alternatively, the m sensing terminals CH_IN and the n sensing terminals CH_IN may repeatedly include any one sensing terminal CH_IN.

[0231] Each of the k sensing terminals CH_IN1 to CH_INk may be any one of the m sensing terminals CH_IN or any one of the n sensing terminals CH_IN.

[0232] Due to the above reasons, the display device 100 according to the embodiment of the present disclosure can satisfy the equation k≤m+n. Therefore, the configuration of the data driving circuit 200 can be simplified.

[0233] Fig. 9 It shows that Figure 7FIG. 1 is a diagram showing the operation of one or more switching elements 715 when all sensing terminals CH_IN1 to CH_INk of the data driving circuit 200 in the display device 100 are electrically connected to the sensing line SL. For example, in this case, the data driving circuit 200 is sized to be equally matched with the size of the display panel, so all the switching elements 715 are maintained in a disconnected position or in an off state.

[0234] according to Fig. 9 The display device 100 according to the embodiment of the present disclosure may include a display panel 110 having a size A and one or more data driving circuits 200 .

[0235] The pad portion 900 may be located in the non-display area NA of the display panel 110. A plurality of connection pads 910 respectively connected to the plurality of sensing lines SL may be located in the pad portion 900.

[0236] Each of the plurality of connection pads 910 is electrically connected to a corresponding sensing line SL of the plurality of sensing lines SL.

[0237] Each of the plurality of connection pads 910 is electrically connected to any one of the k sensing terminals CH_IN1 to CH_INk of the data driving circuit 200. For example, when the data driving circuit 200 is located on a circuit film, the plurality of connection pads 910 may be electrically connected to the sensing terminals CH_IN to CH_INk through lines on the circuit film.

[0238] Reference Fig. 9 , when the data driving circuit 200 is connected to the display panel 110 having a size A, all k sensing terminals CH_IN1 to CH_INk may be respectively connected to the sensing lines SL. In this case, all k sensing terminals CH_IN1 to CH_INk are located in the first sensing terminal region 610 .

[0239] If all k sensing terminals CH_IN to CH_INk provided in each of one or more data driving circuits 200 are electrically connected to the sensing line SL, the data driving circuit 200 does not have a second sensing terminal area 620 but has only a first sensing terminal area 610 (for example, in this case, none of the sensing terminals is unused because the display panel is large enough to match the size of the data driving circuit).

[0240] One or more switching elements 715a belonging to the first group may all be turned off, and the k sensing terminals CH_IN1 to CH_INk are electrically connected to corresponding sensing lines SL, respectively, and the constant voltage VRTA supplied by the constant voltage supply terminal CH_RTA is not applied to any of the k sensing terminals CH_IN1 to CH_INk.

[0241] One or more switching elements 715b belonging to the second group are turned off because this is not a case where all of the one or more switching elements 715a belonging to the first group are turned on.

[0242] Therefore, the data driving circuit 200 provided with k sensing terminals CH_IN1 to CH_INk can be used for the display device 100 including the display panel 110 having the size A.

[0243] Fig.10 is a view showing Figure 7 the operation of one or more switching elements 715 in the case where some of the sensing terminals CH_IN of the data driving circuit 200 in the display device 100 are not electrically connected to any corresponding sensing lines SL.

[0244] Referring to Fig.10 , the display panel 110 having the size B can be connected to one or more data driving circuits 200.

[0245] For each of the one or more data driving circuits 200, the first sensing terminal CH_IN1 and the k-th sensing terminal CH_INk among the k sensing terminals CH_IN1 to CH_INk are not electrically connected to the sensing lines SL, and the second sensing terminal CH_IN2 to the (k - 1)-th sensing terminal CH_INk - 1 can be electrically connected to the sensing lines SL (for example, in this case, the outermost sensing terminals are not used and are connected to the constant voltage supply terminal CH_RTA and supplied with the compensated sensing voltage Vsen_RTA).

[0246] If among the k sensing terminals CH_IN1 to CH_INk provided in each of the one or more data driving circuits 200, n (1 ≤ n < k) sensing terminals CH_IN are only electrically connected to the plurality of sensing lines SL, both the first sensing terminal region 610 and the second sensing terminal region 620 can exist in each of the one or more data driving circuits 200.

[0247] The second sensing terminal region 620 can be located outside the first sensing terminal region 610.

[0248] Referring to Fig.10 , among the one or more switching elements 715a belonging to the first group, the switching elements 715a1 corresponding to the first sensing terminal CH_IN1 and the k-th sensing terminal CH_INk are turned on. The first sensing terminal CH_IN1 and the k-th sensing terminal CH_INk are electrically connected to the constant voltage supply terminal CH_RTA.

[0249] Among the one or more switching elements 715a belonging to the first group, the switching elements 715a2 corresponding to the second sensing terminal CH_IN2 and the k-1th sensing terminal CH_INk-1 are turned off. The second sensing terminal CH_IN2 and the k-1th sensing terminal CH_INk-1 are electrically connected to the corresponding sensing line SL.

[0250] One or more switching elements 715b belonging to the second group are turned off because this is not the case in which one or more switching elements 715a belonging to the first group are all turned on.

[0251] Therefore, the data driving circuit 200 in which the k sensing terminals CH_IN1 to CH_INk are provided may be used for the display device 100 including the display panel 110 having the size B.

[0252] Reference Fig.10 , the sensing unit 330 may sense each of the k sensing terminals CH_IN1 to CH_INk (eg, even outer sensing terminals not used by the display panel may still be sensed by the sensing unit 330 ).

[0253] The sensing unit 330 senses the sensing terminal CH_IN provided in the first sensing terminal region 610 and receives a voltage Vsen_SP reflecting a characteristic value of the sub-pixel SP.

[0254] The sensing unit 330 senses the sensing terminal CH_IN disposed in the second sensing terminal region 620 and receives an analog voltage.

[0255] In this case, the voltage sensed by the sensing terminal CH_IN located in the second sensing terminal region 620 is a voltage that does not reflect the change in the characteristic value of the sub-pixel SP and exhibits little deviation according to the sensing period. Therefore, such a voltage can be used to compensate for the deviation of the characteristic value of the analog-to-digital converter 530. For example, since the outer sensing terminals are not used (e.g., not connected to any sensing line from the display panel) when a small display panel is applied, these outer sensing terminals can be reused and used to help compensate for problems in the data driving circuit 200.

[0256] A voltage inputted by the analog-to-digital converter through sensing of the sensing terminal CH_IN located in the second sensing terminal region 620 may be referred to as an ADC compensation sensing voltage Vsen_RTA.

[0257] Reference Fig.10 , the sensing unit 330 may sense the first sensing terminal CH_IN1 to receive the first ADC compensation sensing voltage Vsen_RTA1. The sensing unit 330 may sense the kth sensing terminal CH_INk to receive the second ADC compensation sensing voltage Vsen_RTA2.

[0258] Reference Fig.10 , the sensing unit 330 senses each of the second to k-1th sensing terminals CH_IN2 to CH_INk-1 and receives a voltage Vsen_SP reflecting a characteristic value of the sub-pixel SP.

[0259] Fig.11 It is shown in Figure 7 FIG. 1 is a diagram illustrating an operation of one or more switching elements 715 in another case where some sensing terminals CH_IN of the data driving circuit 200 are not electrically connected to any sensing line SL in the display device 100 .

[0260] according to Fig.11 The display device 100 according to an embodiment of the present disclosure may include one or more data driving circuits 200 and a display panel 110 having a C size.

[0261] For each of one or more data driving circuits 200, the first sensing terminal CH_IN1, the second sensing terminal CH_IN2, the k-1th sensing terminal CH_INk-1 and the kth sensing terminal CH_INk among the k sensing terminals CH_IN1 to CH_INk are not electrically connected to the sensing line SL, and the third sensing terminal CH_IN3 to the k-2th sensing terminal CH_INk-2 can be electrically connected to the sensing line SL.

[0262] Reference Fig.11 , one or more switching elements 715a belonging to the first group are all turned on. One or more switching elements 715b belonging to the second group are turned on, because this is the case where one or more switching elements 715a belonging to the first group are all turned on.

[0263] The first sensing terminal CH_IN1 , the second sensing terminal CH_IN2 , the k-1th sensing terminal CH_INk-1, and the kth sensing terminal CH_INk are electrically connected to the constant voltage supply terminal CH_RTA.

[0264] Therefore, the data driving circuit 200 in which the k sensing terminals CH_IN1 to CH_INk are provided may be used for the display device 100 including the display panel 110 having the C size.

[0265] The analog-to-digital converter 530 senses the sensing terminal CH_IN provided in the first sensing terminal region 610 and receives a voltage Vsen_SP reflecting a characteristic value of the sub-pixel SP.

[0266] The analog-to-digital converter 530 senses the sensing terminal CH_IN disposed in the second sensing terminal region 620 and receives the ADC compensation sensing voltage Vsen_RTA via the closed switching element 715 .

[0267] Reference Fig.11 , the sensing unit 330 senses the first sensing terminal CH_IN1 and receives the first ADC compensation sensing voltage Vsen_RTA1. The sensing unit 330 senses the second sensing terminal CH_IN2 and receives the second ADC compensation sensing voltage Vsen_RTA2. The sensing unit 330 senses the k-1th sensing terminal CH_INk-1 and receives the third ADC compensation sensing voltage Vsen_RTA3. The sensing unit 330 senses the k-th sensing terminal CH_INk and receives the fourth ADC compensation sensing voltage Vsen_RTA4.

[0268] Reference Fig.11 , the sensing unit 330 senses each of the third to k-2 th sensing terminals CH_IN3 to CH_INk-2, and receives a voltage Vsen_SP reflecting a characteristic value of the sub-pixel SP.

[0269] Fig.12 It is shown in Figure 7 FIG. 1 is a diagram illustrating operations of various circuit elements disposed in the first sensing terminal region 610 and the second sensing terminal region 620 in the display device 100 and voltages applied to specific nodes.

[0270] Reference Fig.12 , region A corresponds to the second sensing terminal region 620 because the sensing terminal CH_IN is not electrically connected to the sensing line SL. Region B corresponds to the first sensing terminal region 610 because the sensing terminal CH_IN is electrically connected to the sensing line SL.

[0271] The sensing terminal CH_IN of region A is not electrically connected to the sensing line SL. The output terminal CH_OUT of region A is not electrically connected to the data line DL. When the input / output unit 460 has the above connection relationship with the sensing line SL and the data line DL, the corresponding input / output unit 460 can be defined as a "first input / output unit".

[0272] The sensing terminal CH_IN of the region B is electrically connected to the sensing line SL. The output terminal CH_OUT of the region B is electrically connected to the data line DL. When the input / output unit 460 has the above connection relationship with the sensing line SL and the data line DL, the corresponding input / output unit 460 can be defined as a "second input / output unit".

[0273] The switch element 715 provided corresponding to the sensing terminal CH_IN of the region A is in an on state. The sensing terminal CH_IN of the region A is electrically connected to the constant voltage supply terminal CH_RTA.

[0274] The sample and hold circuit 520 in region A may sample the voltage of the sensing terminal branch node 720 electrically connected to the corresponding sample and hold circuit 520. The voltage of the corresponding node may be the ADC compensation sensing voltage Vsen_RTA.

[0275] Since the output terminal CH_OUT of the region A is not electrically connected to the data line DL, the digital-to-analog converter DAC connected to the corresponding data line DL does not output a voltage.

[0276] The output terminal CH_OUT of the region A is not electrically connected to the data line DL. If the digital-to-analog converter DAC does not output a voltage, a constant voltage may not be applied to the output terminal CH_OUT of the region A. The corresponding output terminal CH_OUT may be in a floating state.

[0277] The switch element 715 provided corresponding to the sensing terminal CH_IN of the region B is in an off state. The sensing terminal CH_IN of the region B is electrically connected to the sensing line SL.

[0278] The sample and hold circuit 520 in region B may sample the voltage of the sensing terminal branch node 720 electrically connected to the corresponding sample and hold circuit 520. The voltage of the corresponding node may be a voltage Vsen_SP reflecting a characteristic value of the sub-pixel SP.

[0279] The output terminal CH_OUT of the region B is electrically connected to the data line DL. The plurality of digital-to-analog converters DAC output analog data voltages to the corresponding data lines DL.

[0280] The output terminal CH_OUT of the region B is electrically connected to the data line DL. The output terminal CH_OUT of the region B may receive a constant voltage from the digital-to-analog converter DAC.

[0281] Fig.13 1 is a view showing a first sensing terminal region 610 , a second sensing terminal region 620 , and a dummy region 1310 in a display device 100 according to an embodiment of the present disclosure.

[0282] The display device 100 according to an embodiment of the present disclosure may further include a dummy region 1310 in the data driving circuit 200 .

[0283] The dummy node 1315 may be located in the dummy region 1310. The dummy node 1315 may be located between the constant voltage supply terminal CH_RTA and the switching element 715.

[0284] according to Fig.13 The display device 100 according to the embodiment of the present disclosure may include a switching element 715 a 1 corresponding to the first sensing terminal CH_IN1 .

[0285] Reference Fig.13 , the outermost switching element 715 a 1 among the one or more switching elements 715 is disposed corresponding to the outermost sensing terminal CH_IN1 among the k sensing terminals CH_IN1 to CH_INk.

[0286] One end of the switch element 715 a 1 provided corresponding to the first sensing terminal CH_IN1 may be electrically connected to the sensing terminal branch node 720 of the first sensing terminal CH_IN1 and the other end thereof may be electrically connected to the constant voltage supply terminal CH_RTA.

[0287] The dummy node 1315 may be located between a switching element 715 a 1 disposed corresponding to the first sensing terminal CH_IN1 and the constant voltage supply terminal CH_RTA.

[0288] Similarly, the dummy node 1315 may also be located between the switch element 715 disposed corresponding to the kth sensing terminal CH_INk and the constant voltage supply terminal CH_RTA.

[0289] Regardless of whether the above-mentioned one or more switching elements 715 are operated, the constant voltage VRTA is applied to the dummy node 1315 from the constant voltage supply terminal CH_RTA.

[0290] according to Fig.13 The display device 100 according to the embodiment of the present disclosure may further include a dummy node sampling and holding circuit 520 a and a dummy node sampling switch 510 a .

[0291] The dummy node sampling and holding circuit 520a may sample the voltage of the dummy node 1315. The dummy node sampling and holding circuit 520a may output an ADC compensation sensing voltage Vsen_RTA to the analog-to-digital converter 530.

[0292] The pseudo node sampling switch 510a includes one end electrically connected to the pseudo node sampling and holding circuit 520a and the other end electrically connected to the pseudo node 1315. Fig.13 The display device 100 of an embodiment of the present disclosure further includes a dummy region 1310 and a dummy node 1315, so that the ADC compensation sensing voltage Vsen_RTA can be input to the analog-to-digital converter 530 even when all k sensing terminals CH_IN1 to CH_INk provided in the data driving circuit 200 are electrically connected to the sensing line SL.

[0293] Fig.14is a view showing a display device 100 according to an embodiment of the present disclosure.

[0294] Reference Fig.14 , a display device 100 according to an embodiment of the present disclosure includes a display panel 110 and one or more data driving circuits 200 electrically connected to the display panel 110 .

[0295] In this case, k sensing terminals CH_IN1 to CH_INk and a plurality of output terminals CH_OUT are provided in each of the one or more data driving circuits 200 .

[0296] The data driving circuit 200 includes a constant voltage supply terminal CH_RTA. The constant voltage supply terminal CH_RTA supplies a constant voltage VRTA to the constant voltage supply line 730.

[0297] Each of the one or more data driving circuits 200 may include a latch unit 420 , a digital-to-analog conversion unit 430 , a sensing unit 330 , and a switching unit 710 .

[0298] The sensing unit 330 may include a plurality of sampling switches 510 , a plurality of sample and hold circuits 520 , and at least one analog-to-digital converter 530 .

[0299] The switch unit 710 may include one or more switch elements 715 .

[0300] One end of each of the one or more switch elements 715 is electrically connected to the sensing terminal CH_IN via the sensing terminal branch node 720 . The other end of each of the one or more switch elements 715 is electrically connected to the constant voltage supply terminal CH_RTA via the constant voltage source branch node 1410 .

[0301] The constant voltage source branch node 1410 is a node that electrically connects the switching element 715 and the constant voltage supply line 730 .

[0302] Reference Fig.14 In the present disclosure, each of the one or more switching elements 715 may be provided corresponding to a sensing terminal CH_IN. Each of the one or more switching elements 715a may be turned on or off depending on whether the sensing terminal CH_IN corresponding to the corresponding switching element 715 is electrically connected to the sensing line SL.

[0303] Reference Fig.14 According to the present disclosure, when the switch unit 710 includes a plurality of switch elements 715 , the plurality of switch elements 715 are not connected in series with each other.

[0304] according to Fig.14The on / off state of each of the multiple switching elements 715 of the embodiments of the present disclosure is determined according to whether any one of the m sensing terminals CH_IN is electrically connected to the sensing line SL.

[0305] For example, in Fig.14 the present disclosure, the first sensing terminal CH_IN1 is not electrically connected to the sensing line SL. The switching element 715 at the sensing terminal branch node 720 having one end electrically connected to the first sensing terminal CH_IN1 is turned on.

[0306] If the switching element 715 is turned on (e.g., placed in the closed position), the sensing terminal CH_IN corresponding to the corresponding switching element 715 is electrically connected to the constant voltage supply terminal CH_RTA. The constant voltage VRTA is applied to the corresponding sensing terminal CH_IN. Accordingly, the constant voltage VRTA is applied to the corresponding first sensing terminal CH_IN1.

[0307] For example, in Fig.14 the present disclosure, the second sensing terminal CH_IN2 is electrically connected to the sensing line SL. The switching element 715 at the sensing terminal branch node 720 having one end electrically connected to the second sensing terminal CH_IN2 is turned off (e.g., placed in the open position).

[0308] If the switching element 715 is turned off, the sensing terminal CH_IN corresponding to the corresponding switching element 715 is electrically insulated from the constant voltage supply terminal CH_RTA. The corresponding sensing terminal CH_IN may be electrically connected to the sensing line SL from the display panel, and the voltage of the sensing line SL may be applied to the corresponding sensing terminal CH_IN. The voltage applied to the sensing line SL may be a voltage reflecting the characteristic value of the sub-pixel SP.

[0309] Referring to Fig.14 , among the k sensing terminals CH_IN1 to CH_INk provided in each data driving circuit 200, n (1≤n<k) sensing terminals CH_IN may be electrically connected to the sensing line SL, and the remaining k - n sensing terminals CH_IN may not be electrically connected to any sensing line SL.

[0310] The first sensing terminal region 610 is a region where the sensing terminals CH_IN among the k sensing terminals CH_IN1 to CH_INk that are electrically connected to the sensing line SL are located.

[0311] The second sensing terminal region 620 is a region where the k - n sensing terminals CH_IN among the k sensing terminals CH_IN1 to CH_INk that are not electrically connected to the sensing line SL are located.

[0312] The second sensing terminal region 620 may be positioned further outside than the first sensing terminal region 610. Alternatively, the first sensing terminal region 610 may be positioned outside the second sensing terminal region 620, or the first sensing terminal region 610 and the second sensing terminal region 620 may be positioned alternately.

[0313] Among the one or more switch elements 715, the switch element 715 corresponding to the sensing terminal CH_IN located in the first sensing terminal region 610 may be in an off state. Among the one or more switch elements 715, the switch element 715 corresponding to the sensing terminal CH_IN located in the second sensing terminal region 620 may be in an on state.

[0314] The sampling and holding circuit 520 electrically connected to the sensing terminal CH_IN located in the first sensing terminal region 610 may sample a voltage reflecting a characteristic value of the sub-pixel SP. The corresponding sampling and holding circuit 520 may output the sampled voltage to the analog-to-digital converter 530.

[0315] The sampling and holding circuit 520 electrically connected to the sensing terminal CH_IN located in the second sensing terminal area 620 can sample the voltage of the sensing terminal CH_IN to which the constant voltage VRTA is applied. The corresponding sampling and holding circuit 520 can output the sampled voltage to the analog-to-digital converter 530. The constant voltage VRTA can be a voltage supplied from the constant voltage supply terminal CH_RTA.

[0316] according to Fig.14 The display device 100 according to the embodiment of the present disclosure may apply a constant voltage VRTA to the sensing terminal CH_IN which is not electrically connected to any sensing line SL from the display panel.

[0317] according to Fig.14 The display device 100 according to the embodiment of the present disclosure may include one or more switching elements 715 , thereby providing a data driving circuit 200 that can be generally applied to display panels 110 of different specifications or even to display panels of different sizes.

[0318] Fig.15 It is shown Fig.14 FIG. 2 is a diagram of a data driving circuit 200 in the disclosure of FIG.

[0319] Reference Fig.15 , the constant voltage supply terminal CH_RTA provided in the data driving circuit 200 supplies the constant voltage VRTA to the constant voltage supply line 730 .

[0320] Each of the one or more switching elements 715 may be provided corresponding to one sensing terminal CH_IN. If the sensing terminal CH_IN corresponding to the corresponding switching element 715 is electrically connected to one of the sensing lines SL, each of the one or more switching elements 715 is turned off, and if the sensing terminal CH_IN corresponding to the corresponding switching element 715 is not electrically connected to any sensing line SL, each of the one or more switching elements 715 is turned on.

[0321] The switch element 715 c is located between the first sensing terminal CH_IN1 and the constant voltage supply terminal CH_RTA. The corresponding switch element 715 c may be the outermost switch element 715 c among the plurality of switch elements 715 .

[0322] If the first sensing terminal CH_IN1 is not electrically connected to any sensing line SL, the outermost switching element 715c is turned on (e.g., closed), and the constant voltage VRTA is supplied to the first sensing terminal CH_IN1. If the first sensing terminal CH_IN1 is electrically connected to one of the sensing lines SL, the outermost switching element 715c is turned off (e.g., disconnected).

[0323] Therefore, the on / off state of the outermost switching element 715c is determined according to whether the first sensing terminal CH_IN1 is electrically connected to the sensing line SL. In other words, the outermost switching element 715c corresponds to the switching element 715c belonging to the first group.

[0324] Reference Fig.15 , the on / off of the internal switch element 715d is determined according to whether the second sensing terminal CH_IN2 and the third sensing terminal CH_IN3 are each electrically connected to the sensing line SL. In other words, the switch element 715d located inside corresponds to the switch element 715d belonging to the first group.

[0325] Fig.15 One or more switching elements 715c and 715d disclosed in may be the switching element 715 belonging to the above-mentioned first group.

[0326] One end of each of the one or more switch elements 715 is electrically connected to the sensing terminal CH_IN via the sensing terminal branch node 720 . The other end of each of the one or more switch elements 715 is electrically connected to the constant voltage supply terminal CH_RTA via the constant voltage source branch node 1410 .

[0327] Reference Fig.15, the first sensing terminal CH_IN1 and the kth sensing terminal CH_INk may be located in the second sensing terminal region 620 . Among the k sensing terminals CH_IN1 to CH_INk, the remaining sensing terminals CH_IN except the first sensing terminal CH_IN1 and the kth sensing terminal CH_INk may be located in the first sensing terminal region 610 .

[0328] The switch element 715 c having one end connected to the first sensing terminal CH_IN1 is turned on. A constant voltage VRTA is applied to the first sensing terminal CH_IN1 located in the second sensing terminal region 620 .

[0329] The switch elements 715d each having one end connected to the second sensing terminal CH_IN2 and the third sensing terminal CH_IN3 are turned off. The second sensing terminal CH_IN2 and the third sensing terminal CH_IN3 located in the first sensing terminal region 610 are electrically connected to the sensing line SL, respectively.

[0330] The sensing unit 330 may sense the first sensing terminal CH_IN1 to receive the first ADC compensation sensing voltage Vsen_RTA1. The sensing unit 330 may sense the kth sensing terminal CH_INk to receive the second ADC compensation sensing voltage Vsen_RTA2.

[0331] The sensing unit 330 may sense each of the second to k-1th sensing terminals CH_IN2 to CH_INk-1 and receive a voltage Vsen_SP reflecting a characteristic value of the sub-pixel SP.

[0332] Therefore, according to Fig.15 The data driving circuit 200 according to the embodiment of the disclosure may be commonly used in display panels 110 having various specifications and different sizes.

[0333] Fig.16 It is shown Fig.14 1 and 2. FIG. 1 is a diagram of operations of circuit elements disposed in a first sensing terminal region 610 and a second sensing terminal region 620 and voltages at specific nodes in the disclosure of FIG.

[0334] Reference Fig.14 and Fig.16 , region C corresponds to the second sensing terminal region 620 , and region D corresponds to the first sensing terminal region 610 .

[0335] In region C, the sensing terminal CH_IN is not electrically connected to the sensing line SL, and the output terminal CH_OUT is not electrically connected to the data line DL. The switch element 715 corresponding to the corresponding sensing terminal CH_IN may be in an on state. The sampling and holding circuit 520 of region C may sample the voltage of the sensing terminal branch node 720, and the voltage of the corresponding sensing terminal branch node 720 may be the ADC compensation sensing voltage Vsen_RTA.

[0336] For region D, the sensing terminal CH_IN is electrically connected to the sensing line SL, and the output terminal CH_OUT is electrically connected to the data line DL. The switch element 715 corresponding to the corresponding sensing terminal CH_IN may be in an off state. The sampling and holding circuit 520 of region D may sample the voltage of the sensing terminal branch node 720, and the voltage of the corresponding sensing terminal branch node may be a voltage Vsen_SP reflecting the characteristic value of the sub-pixel SP.

[0337] Fig.17 2 is a view showing common usage of the data driving circuit 200 according to an embodiment of the present disclosure.

[0338] Reference Fig.17 , a constant voltage supply terminal CH_RTA is provided in each of the one or more data driving circuits 200. The constant voltage supply terminals CH_RTA may be electrically connected to each other through a constant voltage supply line 730. The constant voltage supply terminal CH_RTA supplies a constant voltage VRTA to the constant voltage supply line 730.

[0339] When the dummy region 1310 exists in the data driving circuit 200, the dummy node 1315 is located in the dummy region 1310. One or more dummy nodes 1315 may exist in the dummy region 1310. The sensing unit 330 may further include a dummy node sampling switch 510a and a dummy node sampling and holding circuit 520a for sampling a voltage of the dummy node 1315.

[0340] Each of the one or more dummy nodes 1315 is located on the constant voltage supply line 730. Each of the one or more dummy nodes 1315 may be located between the constant voltage supply terminal CH_RTA and a constant voltage source branch node 1410 electrically connected to the outermost switching element 715.

[0341] Therefore, regardless of the specifications of the display panel 110 , the constant voltage VRTA is applied to the dummy node 1315 .

[0342] The sensing unit 330 may sense a voltage of a dummy node 1315 located in the dummy region 1310. The voltage of the dummy node 1315 sensed by the sensing unit 330 may be an ADC compensation sensing voltage Vsen_RTA.

[0343] The sensing unit 330 may sense the voltage of the sensing terminal CH_IN. The sensing unit 330 may sense the sensing terminal CH_IN electrically connected to the sensing line SL to receive the voltage Vsen_SP reflecting the characteristic value of the sub-pixel SP. The sensing unit 330 may sense the sensing terminal CH_IN not electrically connected to the sensing line SL to receive the ADC compensation sensing voltage Vsen_RTA.

[0344] according to Fig.17 The display device 100 of an embodiment of the disclosed contents may include: a display panel 110; a data driving circuit 200, which supplies a data voltage to the display panel 110; a memory 1710, which stores panel information (also called "specification information") about the display panel 110; and a controller 140, which controls the operation of the data driving circuit 200 based on the value stored in the memory 1710.

[0345] The data driving circuit 200 may include k sensing terminals CH_IN1 to CH_INk and a constant voltage supply terminal CH_RTA.

[0346] Reference Fig.17 , the data driving circuit 200 may include a plurality of switching elements 715. The plurality of switching elements 715 are electrically connected to the sensing terminals CH_IN located in the regions X, X', Y, Y', Z, and Z', respectively.

[0347] The memory 1710 stores a value corresponding to panel information about the display panel 110 included in the display device 100 .

[0348] The memory 1710 may be implemented as a storage medium separate from the controller 140. Alternatively, the memory 1710 may be integrated with the controller 140, and the memory 1710 may be implemented as a register in the controller 140.

[0349] The controller 140 outputs a switching control signal SWCS based on the value stored in the memory 1710 , and controls one or more switching elements 715 included in the data driving circuit 200 through the switching control signal SWCS.

[0350] Reference Fig.17 , if the size of the display panel 110 included in the display device 100 is size A, a value of 00 may be stored in the memory 1710 .

[0351] When the size of the display panel 110 is the size A, the controller 140 controls one or more switching elements 715 located in the regions X, X′, Y, Y′, Z, and Z′ to be turned off.

[0352] When the size of the display panel 110 included in the display device 100 is the size B, a value of 01 may be stored in the memory 1710 .

[0353] When the size of the display panel 110 is size B, the controller 140 controls one or more switching elements 715 located in regions X and X' to be turned on. The controller 140 controls one or more switching elements 715 located in regions Y, Y', Z, and Z' to be turned off.

[0354] When the size of the display panel 110 included in the display device 100 is the size C, a value of 10 may be stored in the memory 1710 .

[0355] When the size of the display panel 110 is size C, the controller 140 controls one or more switching elements 715 located in regions X, X', Y, and Y' to be turned on. The controller 140 controls one or more switching elements 715 located in regions Z and Z' to be turned off.

[0356] When the size of the display panel 110 included in the display device 100 is the size D, a value of 11 may be stored in the memory 1710 .

[0357] When the size of the display panel 110 is size D, the controller 140 controls one or more switch elements 715 located in regions X, X', Y, Y', Z, and Z' to be turned on. For example, depending on the size of the display panel (e.g., size A, B, C, or D), the controller may be pre-programmed with different settings of the data driving circuit.

[0358] There may be a non-switching area SW_Free in the data driving circuit 200. The switching element 715 for switching the connection between the sensing terminal CH_IN and the constant voltage supply terminal CH_RTA may not be provided in the non-switching area SW_Free. The sensing terminal CH_IN located in the non-switching area SW_Free may be electrically connected to the sensing line SL. A voltage reflecting a change in the characteristic value of the sub-pixel SP may be applied to the sensing terminal CH_IN of the non-switching area SW_Free.

[0359] The non-switch area SW_Free does not overlap with the area X, the area X', the area Y, the area Y', the area Z, and the area Z'.

[0360] Therefore, one data driving circuit 200 can be commonly used for display panels 110 having various specifications and different sizes.

[0361] If the display panel 110 has only four specifications, the sensing terminal CH_IN located in the non-switch area SW_Free among the k sensing terminals CH_IN1 to CH_INk is connected to the corresponding sensing line SL regardless of the specification of the display panel 110. Regardless of the specification of the display panel 110, the switch element 715 may not be connected to the sensing terminal CH_IN connected to the sensing line SL.

[0362] Fig.18 is a view schematically showing an input / output correspondence relationship of the analog-to-digital converter 530 according to an embodiment of the present disclosure.

[0363] Reference Fig.18 , the sensing voltage Vsen transmitted from the display device 100 according to the embodiment of the present disclosure to the analog-to-digital converter 530 included in the data driving unit 120 may range from 0V to 3V, and the digital sensing data DSEN output from the analog-to-digital converter 530 may range from 0 to 1023, corresponding to 10 bits. In other words, in the analog-to-digital converter 530, when the sensing voltage Vsen has a range from 0V to 3V, the range of the digital sensing data DSEN that can be represented by 10 bits may correspond to 0 to 1023.

[0364] Fig.19 1 is a diagram showing an example of an initial input / output function of the analog-to-digital converter 530 and an input / output function of the analog-to-digital converter 530 in which an input / output deviation occurs according to an embodiment of the present disclosure.

[0365] Reference Fig.19 Ideally, the input / output relationship of the analog-to-digital converter 530 can be defined according to a straight line 1900 connecting the point (0, 0) where the sensing voltage Vsen is 0V and the digital sensing data DSEN is 0 and the point (3, 1023) where the sensing voltage Vsen is 3V and the digital sensing data DSEN is 1023.

[0366] An ideal analog-to-digital converter 530 may have a linear slope in which the gain corresponding to the slope is g (=1023 / 3) and the offset corresponding to the x-intercept is 0.

[0367] However, even when the analog-to-digital converter 530 has a linear characteristic, in practice, it may have a characteristic represented by a straight line 1910 having a gain greater than g corresponding to a slope or a linear characteristic represented by a straight line having a gain less than g corresponding to a slope.

[0368] Additionally, the analog-to-digital converter 530 may also have a linear characteristic represented by a straight line 1920 having an offset greater than zero corresponding to the x-intercept.

[0369] Therefore, according to the relationship between the sensing voltage Vsen and the digital sensing data DSEN, the analog-to-digital converter 530 may have a nonlinear characteristic 1930 instead of a linear characteristic.

[0370] The phenomenon that the gain of the ADC 530 is different from the ideal gain (gain=g) or the offset is different from the ideal offset (offset=0) may be caused by internal factors or external factors such as temperature changes.

[0371] For example, the characteristic value of the analog-to-digital converter 530 may vary due to long-term operation of the analog-to-digital converter 530 or the data driving circuit 200 or the display device 100 including the same, or external factors such as temperature increase or application of high voltage.

[0372] To minimize the deviation of the characteristic value (gain or offset) of the analog-to-digital converter 530 , the analog-to-digital converter 530 may receive the ADC compensation sensing voltage Vsen_RTA through the sensing terminal CH_IN or the dummy node 1315 located in the second sensing terminal region 620 .

[0373] The ADC compensation sensing voltage Vsen_RTA is not affected by the variation of the characteristic value of the sub-pixel SP. Therefore, the fluctuation of the voltage level applied to compensate the input / output characteristic value of the analog-to-digital converter 530 due to external factors can be minimized.

[0374] Fig. 20 is a view showing an example of performing ADC input / output compensation by averaging two or more ADC compensation sensing voltages Vsen_RTA.

[0375] Reference Fig. 20 , the analog-to-digital converter 530 may sense the dummy node 1315 or the sensing terminal CH_IN located in the second sensing terminal region 620 and receive two or more ADC compensation sensing voltages Vsen_RTA.

[0376] For example, the first ADC compensation sensing voltage Vsen_RTA1 and the fourth ADC compensation sensing voltage Vsen_RTA4 may be the sensing voltage of the dummy node 1315 . The second ADC compensation sensing voltage Vsen_RTA2 and the third ADC compensation sensing voltage Vsen_RTA3 may be the sensing voltage of the sensing terminal CH_IN located in the second sensing terminal region 620 .

[0377] Reference Fig. 20 Due to external factors when the sampling switch 510 connected to the pseudo node 1315 or the sensing terminal CH_IN located in the second sensing terminal area 620 is turned on or internal factors in the display device 100, two or more sensed ADC compensation sensing voltages Vsen_RTA may have different values ​​according to the detection time.

[0378] Although two or more sensed ADC compensated sensing voltages Vsen_RTA have different values, since the voltages are all detected from the same constant voltage VRTA, errors caused by sensing position and sensing time can be reduced by summing and averaging all two or more sensed ADC compensated sensing voltages Vsen_RTA.

[0379] Therefore, compared to using only any one value of the first to fourth ADC compensation sensing voltages Vsen_RTA1, Vsen_RTA2, Vsen_RTA3 and Vsen_RTA4 to compensate the characteristic value of the analog-to-digital converter 530, the error can be reduced by compensating the characteristic value of the analog-to-digital converter 530 using the value Vsen_RTA_Avg obtained by receiving, summing and averaging two or more ADC compensation sensing voltages Vsen_RTA.

[0380] Fig.21 is a view schematically illustrating a compensation process of the display device 100 according to an embodiment of the present disclosure.

[0381] Reference Fig.21 , the display device 100 according to an embodiment of the present disclosure may include one or more data driving circuits 200 a , 200 b , and 200 c .

[0382] The data driving circuits 200 a , 200 b , and 200 c may include at least one analog-to-digital converter 530 a , 530 b , and 530 c , respectively.

[0383] When the characteristic values ​​of the analog-to-digital converters 530a, 530b and 530c change, in order to compensate for at least one of the characteristic value deviations between the sensing terminals CH_IN connected to the analog-to-digital converters 530a, 530b and 530c and the characteristic value deviations between the analog-to-digital converters 530a, 530b and 530c, the compensation circuit 320 of the controller 140 in the display device 100 according to an embodiment of the present disclosure compensates for the characteristic values ​​of the analog-to-digital converters 530a, 530b and 530c by updating the lookup table LUT stored in the storage unit 310.

[0384] In other words, when it is determined that the characteristic values ​​of the analog-to-digital converters 530a, 530b and 530c are changed by the ADC compensation sensing voltage Vsen_RTA, the compensation circuit 320 can perform an "analog-to-digital converter characteristic value compensation process" - updating the characteristic values ​​(for example, offset or gain) of the analog-to-digital converters 530a, 530b and 530c of each sensing terminal CH_IN included in the lookup table in the storage unit 310 to compensate for the changes in the characteristic values ​​of the analog-to-digital converters 530a, 530b and 530c.

[0385] As described above, the compensation circuit 320 may also perform a “sub-pixel characteristic value compensation process”.

[0386] Fig. 22 is a view showing a driving timing of a display device according to an embodiment of the present disclosure.

[0387] Reference Fig. 22 When a power-on signal is generated, the display device 100 of the present disclosure may perform any of the above-mentioned compensation processes. Such a sensing process is referred to as a "power-on sensing process".

[0388] Reference Fig. 22 When a power-off signal is generated, the display device 100 of the present disclosure may perform any of the above-mentioned compensation processes before a shutdown sequence such as power-off is performed. Such a sensing process is referred to as a "power-off sensing process".

[0389] Reference Fig. 22 The display device 100 according to the embodiment of the present disclosure may perform any of the above compensation processes during the display driving period from after the power-on signal is generated until the power-off signal is generated. Such a sensing process is referred to as a "real-time sensing process".

[0390] Such a real-time sensing process may be performed at each blank period BLANK between the activation time ACT with respect to the vertical synchronization signal Vsync or at blank periods spaced apart at predetermined intervals (eg, updated after every 10 frames or 100 frames, etc.).

[0391] After the “ADC characteristic value compensation process” is performed during the display driving period after the power-on signal is generated until the power-off signal is generated, the “ADC characteristic value compensation process” may be performed during a blank period BLANK different from the “sub-pixel characteristic value compensation process”.

[0392] The controller 140 may perform the “sub-pixel characteristic value compensation process” in some blank periods BLANK among the several blank periods BLANK, and perform the “analog-to-digital converter characteristic value compensation process” in the other blank periods BLANK.

[0393] Specifically, the controller 140 may perform the “ADC characteristic value compensation process” by driving only some of the plurality of sampling switches 510 during at least one blank period among a plurality of blank periods on the vertical synchronization signal Vsync.

[0394] Here, “some sampling switches 510 ” may refer to sampling switches 510 that are not connected to the sensing line SL and dummy node sampling switches 510 a among the plurality of sampling switches.

[0395] Therefore, the data driving circuit 200 can be generally applied to display panels 110 having various specifications and different sizes.

[0396] Therefore, it is possible to compensate in real time for the variation of the characteristic value of the analog-to-digital converter 530. The above process of compensating in real time for the variation of the characteristic value of the analog-to-digital converter 530 is also referred to as a "real-time ADC offset compensation (RTAOC) process".

[0397] Therefore, it is possible to more accurately compensate for the variation in the characteristic value of the sub-pixel SP and improve the display quality of the display device 100 .

[0398] The foregoing embodiments of the present disclosure are briefly described below.

[0399] According to an embodiment of the present disclosure, a display device 100 may be provided, the display device 100 including: a data driving circuit 200 including k (k≥2) sensing terminals CH_IN1 to CH_INk and a switching unit 710 including a switching element 715 between an outermost sensing terminal CH_IN among the k sensing terminals CH_IN1 to CH_Ink and a constant voltage supply terminal CH_RTA; and a display panel 110 having a plurality of sub-pixels SP and a plurality of sensing lines SL electrically connected to the plurality of sub-pixels SP, wherein the plurality of sensing lines SL are electrically connected to n (1≤n≤k) sensing terminals CH_IN among the k sensing terminals CH_IN1 to CH_INk arranged in the data driving circuit 200.

[0400] According to an embodiment of the present disclosure, a display device 100 may be provided, wherein the switch unit 710 includes m (m≥1) switch elements arranged corresponding to m sensing terminals among k sensing terminals, and wherein k is m+n or less.

[0401] According to an embodiment of the present disclosure, a display device 100 may be provided, wherein k sensing terminals CH_IN1 to CH_INk are located in a first sensing terminal area 610 or a second sensing terminal area 620, wherein the first sensing terminal area 610 is an area in which a plurality of sensing terminals CH_IN electrically connected to a plurality of sensing lines SL among the k sensing terminals CH_IN1 to CH_INk are located in a data driving circuit 200, and wherein the second sensing terminal area 620 is an area in which the remaining sensing terminals of the k sensing terminals CH_IN1 to CH_INk except for a plurality of sensing terminals connected to the plurality of sensing lines SL are located in the data driving circuit 200.

[0402] According to an embodiment of the present disclosure, a display device 100 may be provided, wherein a data driving circuit 200 includes a sensing unit 330, wherein the sensing unit 330 includes: at least one analog-to-digital converter 530; a plurality of sampling and holding circuits 520, wherein the plurality of sampling and holding circuits 520 output analog voltages to the analog-to-digital converter 530; and a plurality of sampling switches 510, wherein each sampling switch 510 includes a first end electrically connected to each of the plurality of sampling and holding circuits 520 and a second end electrically connected to each of k sensing terminals.

[0403] According to an embodiment of the present disclosure, a display device 100 may be provided, wherein the data driving circuit 200 further includes a constant voltage supply line 730, through which a constant voltage is supplied from a constant voltage supply terminal CH_RTA, wherein a pseudo node 1315 is present on the constant voltage supply line 730, and wherein the sensing unit 330 further includes: a pseudo node sampling and holding circuit 520a, which samples the voltage of the pseudo node 1315; and a pseudo node sampling switch 510a, which has a first end electrically connected to the pseudo node sampling and holding circuit 520a and a second end electrically connected to the pseudo node.

[0404] According to an embodiment of the present disclosure, a display device 100 may be provided in which the outermost switching element 715 among the m switching elements 715 has a first end electrically connected to the outermost sensing terminal CH_IN among the k sensing terminals CH_IN1 to CH_INk and a second end electrically connected to the constant voltage supply terminal CH_RTA.

[0405] According to an embodiment of the present disclosure, a display device 100 may be provided, wherein m switching elements 715 are one or more switching elements 715 belonging to a first group, and wherein, if a sensing terminal CH_RTA corresponding to the corresponding switching element 715 is electrically connected to a sensing line SL, the one or more switching elements 715 belonging to the first group are turned off, and if a sensing terminal CH_IN corresponding to the corresponding switching element 715 is not connected to the sensing line SL, the one or more switching elements 715 belonging to the first group are turned on.

[0406] According to an embodiment of the present disclosure, a display device 100 may be provided, wherein the switching unit 710 further includes one or more switching elements 715b belonging to the second group, and wherein, if all of the one or more switching elements 715 belonging to the first group are turned on, the one or more switching elements 715b belonging to the second group are turned on.

[0407] According to an embodiment of the present disclosure, a display device 100 may be provided, wherein each of the m switching elements 715 has a first end electrically connected to each of the m sensing terminals 715 via a sensing terminal branch node 720 and a second end electrically connected to a constant voltage supply line 730 via a constant voltage source branch node 1410 .

[0408] According to an embodiment of the present disclosure, a display device 100 may be provided, the display device 100 further comprising a controller 140, the controller 140 driving a data driving circuit 200, and wherein, if all of the m sensing terminals CH_IN are connected to a plurality of sensing lines SL, the controller 140 controls all of the m switching elements 715 to be turned off; and if at least one of the m sensing terminals CH_IN is not connected to the sensing line, the controller 140 controls the following switching element 715 to be turned on: one end of the switching element 715 is connected to a sensing terminal branch node 720 of a sensing terminal CH_IN among the m sensing terminals that is not connected to the sensing line.

[0409] According to an embodiment of the present disclosure, a display device 100 may be provided, the display device 100 further comprising a memory 1710 storing panel information about a display panel, wherein a controller 140 controls two or more switching elements 715 based on a value stored in the memory 1710, and wherein the panel information about the display panel 110 is information about which sensing terminal CH_IN among k sensing terminals CH_IN1 to CH_INk provided in each of one or more data driving circuits 200 is connected to a sensing line SL.

[0410] According to an embodiment of the present disclosure, a display device 100 may be provided, wherein a controller 140 performs an analog-to-digital converter characteristic value compensation process by driving only some of a plurality of sampling switches 510 during at least one blank period BLANK among a plurality of blank periods BLANK on a vertical synchronization signal Vsync, and wherein some of the sampling switches 510 are sampling switches 510 among the plurality of sampling switches 510 that are not electrically connected to a sensing line SL.

[0411] According to an embodiment of the present disclosure, a data driving circuit 200 may be provided, the data driving circuit 200 including: k (k≥2) sensing terminals CH_IN1 to CH_INK; a constant voltage supply terminal CH_RTA, the constant voltage supply terminal CH_RTA supplies a constant voltage VRTA to a constant voltage supply line 730; a sensing unit 330, the sensing unit 330 receives an analog voltage from each of the k sensing terminals CH_IN1 to CH_INk; and a switching unit 710, the switching unit 710 including a switching element 715 located between the outermost sensing terminal CH_IN among the k sensing terminals CH_IN1 to CH_INk and the constant voltage supply line 730.

[0412] According to an embodiment of the present disclosure, a data driving circuit 200 may be provided, wherein the sensing unit 330 further includes: at least one analog-to-digital converter 530; a plurality of sampling and holding circuits 520, the plurality of sampling and holding circuits 520 outputting analog voltages to the analog-to-digital converter 530; and a plurality of sampling switches 510, each sampling switch 510 including a first end electrically connected to each of the plurality of sampling and holding circuits 520 and a second end electrically connected to each of k sensing terminals CH_IN1 to CH_INk.

[0413] According to an embodiment of the present disclosure, a data driving circuit 200 may be provided, wherein the switching unit 710 includes two or more switching elements 715 , and wherein the two or more switching elements 715 are connected to each other in series.

[0414] According to an embodiment of the present disclosure, a data driving circuit 200 may be provided in which a switching element 715 has a first end electrically connected to a sensing terminal branch node 720 of an outermost sensing terminal CH_IN and a second end electrically connected to a constant voltage source branch node 1410 of a constant voltage supply line 730 .

[0415] According to an embodiment of the present disclosure, a data driving circuit 200 may be provided, wherein if k sensing terminals CH_IN1 to CH_INk among k sensing terminals CH_IN1 to CH_INk are electrically connected to the sensing lines SL of the display panel 110, all of one or more switching elements 715 are turned off, and wherein if n (1 ≤ n < k) sensing terminals CH_IN among k sensing terminals CH_IN1 to CH_INk are electrically connected to the sensing lines SL of the display panel 110, the switching elements 715 corresponding to the n sensing terminals CH_IN are turned off, and the switching elements 715 corresponding to the remaining k - n sensing terminals CH_IN are turned on.

[0416] The foregoing description has been presented to enable any person skilled in the art to make and use the inventive concept of the present invention, and the foregoing description has been provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. The foregoing description and drawings have provided examples of the inventive concept of the present invention for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the inventive concept of the present invention. Therefore, the scope of the present invention is not limited to the illustrated embodiments, but is consistent with the broadest scope consistent with the claims. The scope of protection of the present invention should be understood based on the appended claims, and all inventive concepts within the scope of their equivalents should be understood to be included within the scope of the present invention.

Claims

1. A display device, comprising: a data driving circuit comprising k sensing terminals and a switch portion, wherein the switch portion comprises a switch element located between an outermost sensing terminal of the k sensing terminals and a constant voltage supply terminal, wherein k is a positive integer greater than or equal to 2; as well as A display panel, the display panel comprising a plurality of sub-pixels and a plurality of sensing lines electrically connected to the plurality of sub-pixels, wherein the plurality of sensing lines are electrically connected to n sensing terminals among the k sensing terminals provided in the data driving circuit, wherein n is a positive integer less than or equal to k, and n is greater than or equal to 1, The data driving circuit further comprises a constant voltage supply line, wherein the constant voltage supply line is configured to supply a constant voltage from the constant voltage supply terminal. wherein a pseudo node exists on the constant voltage supply line, Wherein, the data driving circuit includes a sensing part, and Wherein, the sensing part comprises: a dummy node sampling and holding circuit configured to sample a voltage of the dummy node; and A pseudo-node sampling switch has a first end electrically connected to the pseudo-node sample and hold circuit and a second end electrically connected to the pseudo-node.

2. The display device according to claim 1, wherein: The switch part includes m switch elements arranged corresponding to m sensing terminals among the k sensing terminals, wherein m is a positive integer greater than or equal to 1, and Wherein, k is less than or equal to m+n.

3. The display device according to claim 1, wherein: A first group of sensing terminals among the k sensing terminals is located in a first sensing terminal region, and a second group of sensing terminals among the k sensing terminals is located in a second sensing terminal region, The first sensing terminal region is a region where a plurality of sensing terminals electrically connected to the plurality of sensing lines among the k sensing terminals are located in the data driving circuit, and The second sensing terminal area is an area where the remaining sensing terminals are located in the data driving circuit, the remaining sensing terminals are different from the plurality of sensing terminals connected to the plurality of sensing lines among the k sensing terminals, and the remaining sensing terminals are not connected to any sensing line among the plurality of sensing lines in the display panel.

4. The display device according to claim 2, wherein: The sensing part also includes: at least one analog-to-digital converter; a plurality of sample and hold circuits configured to output analog voltages to the at least one analog-to-digital converter; and A plurality of sampling switches, each sampling switch including a first end electrically connected to one of the plurality of sample and hold circuits and a second end electrically connected to one of the k sensing terminals.

5. The display device according to claim 1, wherein: When the outermost sensing terminal is not electrically connected to any sensing line of the plurality of sensing lines, the constant voltage supply terminal is electrically connected to the outermost sensing terminal.

6. The display device according to claim 2, wherein: An outermost switching element among the m switching elements has a first end electrically connected to the outermost sensing terminal among the k sensing terminals and a second end electrically connected to the constant voltage supply terminal.

7. The display device according to claim 6, wherein: The m switching elements are one or more switching elements belonging to a first switching group, and Among them, the one or more switching elements belonging to the first switch group are configured to be turned off when the sensing terminal corresponding to the corresponding switching element is electrically connected to one of the multiple sensing lines, and to be turned on when the sensing terminal corresponding to the corresponding switching element is not connected to any sensing line among the multiple sensing lines.

8. The display device according to claim 7, wherein: The switch section further includes one or more switch elements belonging to a second switch group, and The one or more switching elements belonging to the second switch group are configured to be turned on when all of the one or more switching elements belonging to the first switch group are turned on.

9. The display device according to claim 7, wherein: Each of the m switch elements has a first end electrically connected to one of the m sense terminals via a sense terminal branch node and a second end electrically connected to the constant voltage supply line via a constant voltage source branch node.

10. The display device according to claim 7, further comprising a controller configured to drive the data driving circuit. in, The controller is also configured to: when all of the m sensing terminals are connected to one of the multiple sensing lines, control all of the m switching elements to be turned off; and when at least one of the m sensing terminals is not connected to any sensing line among the multiple sensing lines, control the following switching element to be turned on: one end of the switching element is connected to a sensing terminal branch node of a sensing terminal among the m sensing terminals that is not connected to any sensing line.

11. The display device according to claim 10, further comprising a memory storing panel information about the display panel, in, The controller is further configured to control two or more of the m switching elements based on the values ​​stored in the memory, and The panel information includes information on which sensing terminal among the k sensing terminals provided in each data driving circuit is connected to a sensing line among the plurality of sensing lines.

12. The display device according to claim 4, further comprising a controller configured to drive the data driving circuit. in, The controller is further configured to perform an analog-to-digital converter characteristic value compensation process by driving only some of the plurality of sampling switches during at least one blank period among a plurality of blank periods based on a vertical synchronization signal, and The some sampling switches are sampling switches that are not electrically connected to any sensing line among the plurality of sensing lines.

13. The display device according to claim 1, wherein: The constant voltage supply line is further configured to supply the constant voltage to at least some of the k sensing terminals via the switch portion, and The data driving circuit is configured to supply the constant voltage to opposite ends of the constant voltage supply line.

14. The display device according to claim 1, wherein: The switch section includes an even number of switch elements, and The first half of the even-numbered switching elements are arranged to correspond to a first outer side of the data driving circuit, and the second half of the even-numbered switching elements are arranged to correspond to a second outer side of the data driving circuit.

15. The display device according to claim 1, wherein: The constant voltage supply line is further configured to supply the constant voltage to at least some of the k sensing terminals via the switch portion, wherein the outermost sensing terminals among the k sensing terminals are connected to the constant voltage supply line, and each of the outermost sensing terminals is not connected to any sensing line among the plurality of sensing lines, and A group of innermost sensing terminals among the k sensing terminals is electrically isolated from the constant voltage supply line, and each sensing terminal in the group of innermost sensing terminals is connected to a corresponding sensing line among the plurality of sensing lines.

16. A data driving circuit, comprising: k sensing terminals, wherein k is a positive integer greater than or equal to 2; a constant voltage supply terminal configured to supply a constant voltage to the constant voltage supply line; a sensing portion configured to receive an analog voltage from each of the k sensing terminals; as well as a switching part including a switching element located between an outermost sensing terminal among the k sensing terminals and the constant voltage supply line, wherein a pseudo node exists on the constant voltage supply line, and Wherein, the sensing part comprises: a dummy node sampling and holding circuit configured to sample a voltage of the dummy node; and A pseudo-node sampling switch has a first end electrically connected to the pseudo-node sample and hold circuit and a second end electrically connected to the pseudo-node.

17. The data driving circuit according to claim 16, wherein: The sensing part also includes: at least one analog-to-digital converter; a plurality of sample and hold circuits configured to output analog voltages to the at least one analog-to-digital converter; and A plurality of sampling switches, each sampling switch having a first end electrically connected to one of the plurality of sample and hold circuits and a second end electrically connected to one of the k sensing terminals.

18. The data driving circuit according to claim 17, wherein: The switch section includes two or more switch elements, and The two or more switching elements are connected in series with each other.

19. The data driving circuit according to claim 17, wherein: The switch element has a first end electrically connected to a sense terminal branch node of the outermost sense terminal and a second end electrically connected to a constant voltage source branch node of the constant voltage supply line.

20. The data driving circuit according to claim 16, wherein: When k sensing terminals among the k sensing terminals are electrically connected to one sensing line of a plurality of sensing lines of the display panel, all of the switch elements are configured to be turned off, and When n sensing terminals among the k sensing terminals are electrically connected to the multiple sensing lines of the display panel, the switching elements corresponding to the n sensing terminals are turned off, and the switching elements corresponding to the remaining kn sensing terminals are turned on, where n is a positive integer less than or equal to k, and n is greater than or equal to 1.

21. The data driving circuit according to claim 16, wherein: When the outermost sensing terminal is not electrically connected to any sensing line of a plurality of sensing lines of the display panel, the constant voltage supply terminal is electrically connected to the outermost sensing terminal.

22. The data driving circuit according to claim 17, in, performing an analog-to-digital converter characteristic value compensation process by driving only some of the plurality of sampling switches during at least one blank period among a plurality of blank periods based on a vertical synchronization signal, and The sampling switches are sampling switches that are not electrically connected to any sensing line of the plurality of sensing lines of the display panel.

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