Pixel Circuit, Driving Method Thereof, Display Substrate, and Display Device

Abstract

A pixel circuit, a driving method thereof, a display substrate, and a display device. The pixel circuit includes a driving sub-circuit, a data writing sub-circuit, a first light-emitting control sub-circuit, a first reset sub-circuit, and a bias sub-circuit. The first reset sub-circuit is connected to the first node and configured to write a first reset voltage to the second node in response to a first reset control signal; the bias sub-circuit is connected to the second node and configured to write a reference voltage to the second node in response to a bias control signal, thereby turning on the driving sub-circuit. The pixel circuit can effectively improve the display quality.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a pixel circuit, a driving method thereof, a display substrate, and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) displays have many advantages such as active light emission, high contrast ratio, fast response speed, thin and light, etc., and have become one of the main new generation displays. With the popularization of OLED displays in the high-end market, the demand for screen quality is getting higher and higher, which puts forward more refined requirements for the design. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a pixel circuit, including a driving sub-circuit, a data writing sub-circuit, a first light emission control sub-circuit, a first reset sub-circuit, and a bias sub-circuit. The driving sub-circuit includes a control end connected to a first node, a first end connected to a second node, and a second end connected to a third node, and the driving sub-circuit is configured to control a driving current for driving a light-emitting element from the second node to the third node according to the voltage of the control end; the data writing sub-circuit is connected to the second node and is configured to write a data signal into the second node in response to a first scan signal; the first light emission control sub-circuit is connected to the second node and a first power supply voltage terminal, and is configured to write a first power supply voltage from the first power supply voltage terminal into the second node in response to a first light emission control signal; the first reset sub-circuit is connected to the first node and is configured to write a first reset voltage into the first node in response to a first reset control signal; the bias sub-circuit is connected to the second node and is configured to write a reference voltage into the second node in response to a bias control signal, thereby turning on the driving sub-circuit.

[0004] In some examples, the absolute value of the voltage difference between the reference voltage and the first reset voltage is a preset value; the preset value is set such that when the light-emitting element is driven to emit light with the highest gray-scale brightness, the absolute value of the voltage difference between the control end and the first end of the driving sub-circuit is less than the preset value.

[0005] In some examples, the pixel circuit further includes a second reset sub-circuit, the second reset sub-circuit is connected to a fourth node, and is configured to be connected to a first electrode of the light-emitting element through the fourth node, and is configured to write a second reset voltage into the fourth node in response to a second reset control signal.

[0006] In some examples, the bias control signal and the second reset control signal are the same signal.

[0007] In some examples, the pixel circuit further includes a second light-emitting control sub-circuit, which is connected to the third node and the fourth node, and is configured to be connected to the first electrode of the light-emitting element through the fourth node; the second light-emitting control sub-circuit is configured to turn on the third node and the fourth node in response to a second light-emitting control signal.

[0008] In some examples, the pixel circuit further includes a compensation sub-circuit, which is connected to the first node and the third node, and is configured to turn on the first node and the third node in response to a second scan signal, so as to control the driving sub-circuit to write a compensation voltage to the first node based on the data signal written to the second node.

[0009] In some examples, the pixel circuit further includes a storage sub-circuit, wherein the storage sub-circuit includes a first end and a second end, and the first end and the second end of the storage sub-circuit are respectively connected to the first power supply voltage terminal and the first node.

[0010] In some examples, the bias sub-circuit includes a bias transistor, and the first reset sub-circuit includes a reset transistor; the bias transistor is a P-type transistor, and the reset transistor is an N-type transistor.

[0011] At least one embodiment of the present disclosure further provides a display substrate, including a substrate and a plurality of sub-pixels, and the plurality of sub-pixels are arranged in an array along a first direction and a second direction on the substrate. At least one of the plurality of sub-pixels includes the pixel circuit provided in any of the above embodiments.

[0012] In some examples, the display substrate further includes a bias control line extending along the first direction, and the bias sub-circuit includes a bias transistor; the bias control line is electrically connected to the gate of the bias transistor to provide the bias control signal.

[0013] In some examples, the display substrate further includes a reference voltage line, and the reference voltage line is electrically connected to the first pole of the bias transistor to provide the reference voltage; the reference voltage line is located on a side of the bias control line away from the substrate.

[0014] In some examples, the display substrate further includes a connection electrode, and the second pole of the bias transistor is electrically connected to the first end of the driving sub-circuit through the connection electrode; the connection electrode is located on a side of the bias control line away from the substrate.

[0015] In some examples, when the pixel circuit includes a second reset sub-circuit, in the second direction, the bias sub-circuit and the second reset sub-circuit are located on the same side of the driving sub-circuit.

[0016] In some examples, the second reset sub - circuit includes a reset transistor, and the bias control line is also electrically connected to the gate of the reset transistor to provide the second reset control signal.

[0017] In some examples, in the second direction, the first reset sub - circuit and the bias sub - circuit are located on opposite sides of the driving sub - circuit.

[0018] In some examples, the display substrate further includes a first reset control line extending along the first direction. The first reset sub - circuit includes a reset transistor, and the first reset control line is electrically connected to the gate of the reset transistor to provide the first reset control signal.

[0019] In some examples, the display substrate further includes a first reset voltage line extending along the first direction. The first reset voltage line is electrically connected to the first pole of the reset transistor to provide the first reset voltage.

[0020] In some examples, in the direction perpendicular to the substrate, the first reset voltage line is located on the side of the active layer of the reset transistor close to the substrate, and the first reset control line is located on the side of the active layer of the reset transistor far from the substrate.

[0021] At least one embodiment of the present disclosure further provides a display device, including the display substrate provided in any of the above embodiments.

[0022] At least one embodiment of the present disclosure further provides a driving method for a pixel circuit, for driving the pixel circuit provided in any of the above embodiments. The driving method includes: in the initialization stage, turning on the first reset sub - circuit to write the first reset signal into the first node, and turning on the bias sub - circuit to write the reference voltage into the second node, so as to turn on the driving sub - circuit; in the data writing stage, turning on the data writing sub - circuit to write the data signal into the second node, where the initialization stage is before the data writing stage. Description of the Drawings

[0023] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0024] Figure 1 It is a schematic diagram of the characteristic curve of a transistor;

[0025] Figure 2A It is a schematic diagram of the pixel circuit provided by at least one embodiment of the present disclosure;

[0026] Figure 2B is Figure 2A a circuit diagram of a specific implementation example of the pixel circuit shown;

[0027] Figure 2C is a timing signal diagram of the pixel circuit provided by at least one embodiment of the present disclosure;

[0028] Figures 2D - 2G is a schematic diagram of the pixel circuit provided by some other embodiments of the present disclosure;

[0029] Figure 3 is one of the schematic diagrams of the display substrate provided by at least one embodiment of the present disclosure;

[0030] Figure 4A is another schematic diagram of the display substrate provided by at least one embodiment of the present disclosure;

[0031] Figure 4B is Figure 4A a cross-sectional view along the section line I-I';

[0032] Figure 5 is the third schematic diagram of the display substrate provided by at least one embodiment of the present disclosure;

[0033] Figure 6 is the fourth schematic diagram of the display substrate provided by at least one embodiment of the present disclosure;

[0034] Figure 7 is the fifth schematic diagram of the display substrate provided by at least one embodiment of the present disclosure;

[0035] Figure 8A is the sixth schematic diagram of the display substrate provided by at least one embodiment of the present disclosure;

[0036] Figure 8B is the seventh schematic diagram of the display substrate provided by at least one embodiment of the present disclosure;

[0037] Figure 9 is a schematic diagram of the display panel provided by at least one embodiment of the present disclosure; and

[0038] Figure 10 is a schematic diagram of the display device provided by at least one embodiment of the present disclosure. Detailed implementation manners

[0039] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0040] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the ordinary meanings understood by those of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. Similarly, the terms such as "a", "an", or "the" do not denote a quantity limitation, but mean that there is at least one. The terms such as "comprising" or "including" mean that the elements or items appearing before the term cover the elements or items listed after the term and their equivalents, without excluding other elements or items. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left", and "right" are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0041] The inventors found that the characteristics of the driving transistor (DTFT) in the pixel circuit in the current cycle (such as the magnitude of the threshold voltage) are related to the light-emitting conditions in the previous cycle (such as the written grayscale data signal) or the grayscale of the display screen. The characteristics of the driving transistor fluctuate due to the light-emitting conditions in the previous cycle, resulting in the driving signal of the current frame being related not only to the grayscale data signal of the current frame but also to the grayscale data signal of the previous frame, thereby causing a hysteresis phenomenon. This hysteresis phenomenon can cause adverse phenomena such as short-term afterimages, slow response times, and flicker during the display process of the display device.

[0042] At least one embodiment of the present disclosure provides a pixel circuit, including a driving sub-circuit, a data writing sub-circuit, a first light-emitting control sub-circuit, a first reset sub-circuit, and a bias sub-circuit. The driving sub-circuit includes a control end connected to a first node, a first end connected to a second node, and a second end connected to a third node, and the driving sub-circuit is configured to control, according to the voltage of the control end, a driving current for driving a light-emitting element from the second node to the third node; the data writing sub-circuit is connected to the second node and is configured to write a data signal into the second node in response to a first scan signal; the first light-emitting control sub-circuit is connected to the second node and a first power supply voltage terminal, and is configured to write a first power supply voltage from the first power supply voltage terminal into the first node in response to a first light-emitting control signal; the first reset sub-circuit is connected to the first node and is configured to write a first reset voltage into the second node in response to a first reset control signal; the bias sub-circuit is connected to the second node and is configured to write a reference voltage into the second node in response to a bias control signal, so as to turn on the driving sub-circuit.

[0043] The pixel driving circuit provided by at least one embodiment of the present disclosure can, by providing the first reset sub-circuit and the bias sub-circuit, reset, before the data writing stage of the current cycle (for example, in the initialization stage), the first node connected to the control end of the driving sub-circuit and the second node connected to the first end of the driving sub-circuit respectively, so as to turn on the driving sub-circuit and bias the driving sub-circuit, so that the driving sub-circuit has a unified initial state, and alleviate the poor display caused by the above-mentioned hysteresis phenomenon.

[0044] Figure 1 A characteristic curve diagram of a driving transistor of a pixel circuit is shown. The three characteristic curves are respectively the characteristic curves of the driving transistor after the pixel circuit displays a 255 gray-scale picture (corresponding to the C1 curve), a 48 gray-scale picture (corresponding to the C2 curve), and a 0 gray-scale picture (corresponding to the C3 curve) in the previous cycle. The abscissa of the characteristic curve represents the gate-source voltage difference (Vgs) of the driving transistor, and the ordinate represents the driving current (Ids) generated by the driving transistor. For example, as Figure 1 shown, the driving transistor is a P-type transistor, and the threshold voltage is less than 0; as the gray-scale data of the previous cycle increases, the threshold voltage of the driving transistor drifts to the left.

[0045] Figure 1The intersections of the three dashed lines with the three characteristic curves respectively show the characteristics of the transistor when the gray-scale values of the current frame data are 255 (L255), 48 (L48), and 0 (L0) in the cases where the previous frame was written with 255 gray scale, 48 gray scale, and 0 gray scale respectively. As can be seen from the figure, when the gray-scale values of the data written in the previous frame or the displayed image are different, and the same data is written in the current frame, different driving currents will be generated in the driving transistor; for example, as Figure 1 shown, when the gray-scale value of the displayed image in the previous frame is 255 and the data of 48 gray scale is written in the current frame, the driving transistor will follow the characteristic curve S1 and reach point B1 along the Figure 1 downward arrow in to obtain a relatively small driving current; when the data of 0 gray scale value was written in the previous frame and the data of 48 gray scale is written in the current frame, the driving transistor will follow the characteristic curve S3 and reach point B2 along the Figure 1 upward arrow in to obtain a relatively large driving current.

[0046] For example, the inventors also found that the characteristics of the driving transistor are also related to the scanning direction of the gate voltage; when the scanning direction of the gate voltage of the driving transistor is different, the characteristics of the driving transistor are also different.

[0047] For example, when the driving transistor is a low-temperature polysilicon thin-film transistor (LTPS-TFT), the hysteresis phenomenon is mainly caused by defects between the polysilicon and the gate insulating layer and defects in the gate insulating layer. When a voltage is received at the gate of the driving transistor, the defects in the gate insulating layer will capture carriers, resulting in different characteristic curves for the driving transistor during forward and reverse scans, thus causing the hysteresis phenomenon and resulting in adverse phenomena such as slow response time in the first frame and short-term afterimages.

[0048] For example, in the pixel circuit provided in at least one embodiment of the present disclosure, the absolute value of the voltage difference between the reference voltage and the first reset voltage is a preset value; the preset value is set such that when the driving sub-circuit drives the light-emitting element to emit light with the highest gray scale (i.e., 255 gray scale) brightness, the absolute value of the voltage difference Vgs between the control end and the first end of the driving sub-circuit is less than the preset value.

[0049] For example, when the driving sub-circuit drives the light-emitting element to emit light with the highest gray scale brightness, that is, when the written data signal causes the pixel circuit to display an image with the highest gray scale value, the voltage difference Vgs between the control end and the first end of the driving sub-circuit is Vd_L255 + Vth - VDD, where Vd_L255 is the data signal written to the pixel circuit when the light-emitting element emits light with the highest gray scale brightness, Vth is the current threshold voltage of the driving sub-circuit, and VDD is the first power supply voltage.

[0050] With this setting, the driving sub-circuit is in a large positive bias or negative bias state, so that regardless of the grayscale value data written in the current frame, a unified scanning direction can be obtained, further improving the above-mentioned hysteresis phenomenon.

[0051] For example, when the threshold voltage of the driving sub-circuit is less than 0, through the above setting, the driving sub-circuit is in a large negative bias state. For example, the driving sub-circuit is in the state of point A as shown in Figure 1 so that regardless of whether the previous frame is a black screen, a white screen or other screens, a single forward scan can be achieved simultaneously, thereby improving the current difference caused by the hysteresis phenomenon.

[0052] Figure 2A Schematic diagram of a pixel circuit provided by at least one embodiment of the present disclosure. As Figure 2A shown, the pixel circuit includes a driving sub-circuit 122, a data writing sub-circuit 121, a first light-emitting control sub-circuit 123, a first reset sub-circuit 125, and a bias sub-circuit 121.

[0053] The driving sub-circuit 122 includes a control terminal 122a connected to the first node N1, a first terminal 122b connected to the second node N2, and a second terminal 122c connected to the third node N3. The driving sub-circuit 122 is configured to control, according to the voltage of the first node N1, the driving current from the first node N1 to the third node N3 and for driving the light-emitting element 120.

[0054] The data writing sub-circuit 121 is connected to the second node N2 and is configured to write the data signal Vd to the second node N2 in response to the first scan signal Ga1. For example, the data writing sub-circuit 121 includes a control terminal 121a, a first terminal 121b, and a second terminal 121c. The control terminal 121a is configured to receive the first scan signal Ga1, the first terminal 121b is configured to receive the data signal Vd, and the second terminal 121c is connected to the second node N2. For example, in the data writing stage, the data writing sub-circuit 121 can be turned on in response to the first scan signal Ga1, so that the data signal can be written to the first terminal 122b (second node N2) of the driving sub-circuit 122 and stored, so as to generate a driving signal for driving the light-emitting element 120 to emit light according to the data signal during, for example, the light-emitting stage.

[0055] The first light-emitting control sub-circuit 123 is connected to the first power supply voltage terminal VDD and the second node N2, and is configured to write the first power supply voltage VDD from the first power supply voltage terminal VDD to the second node N2 in response to the first light-emitting control signal EM1.

[0056] The first reset sub-circuit 125 is connected to the first node N1 and is configured to write a first reset voltage Init1 to the first node N1 in response to a first reset control signal Rst1.

[0057] The bias sub-circuit 126 is connected to the second node N2 and is configured to write a reference voltage to the second node N2 in response to a bias control signal SCN, thereby turning on the driving sub-circuit.

[0058] For example, in the initialization stage, the first reset sub-circuit 125 and the bias sub-circuit 126 are respectively turned on in response to the first reset control signal Rst1 and the bias control signal SCN to apply the first reset voltage Init1 to the first node N1 and the reference voltage Vref to the second node N2, so that the driving sub-circuit 122 is turned on and biased, thereby enabling adjustment of the initial state of the driving sub-circuit and alleviating display defects caused by the hysteresis phenomenon in the previous frame's light-emitting stage.

[0059] For example, in some exemplary embodiments, the absolute value of the first reset voltage Init1 is greater than 1.5 times the threshold voltage of the driving sub-circuit to ensure that the biasing effect can be quickly achieved within a short time. For example, the absolute value of the first reset voltage Init1 can be greater than 2 times, 2.5 times, or 3 times the absolute value of the threshold voltage, but not limited thereto.

[0060] For example, the amplitude of the first reset voltage Init1 is greater than 0.

[0061] For example, the first reset voltage Init1 is 4V - 10V, and the threshold voltage of the driving sub-circuit is generally -5V to -2V. Optionally, the threshold voltage of the driving sub-circuit can be -3V.

[0062] For example, as Figure 2A shown, the pixel circuit may further include a compensation sub-circuit 128. The compensation sub-circuit 128 is connected to the first node N1 and the third node N3 and is configured to turn on the first node N1 and the third node N3 in response to a second scan signal Ga2, thereby controlling the driving sub-circuit 122 to write a compensation voltage to the first node N1 based on a data signal Vd written to the second node N2. For example, the compensation sub-circuit 128 includes a control terminal 128a, a first terminal 128b, and a second terminal 128c. The control terminal 128a is configured to receive the second scan signal Ga2, the first terminal 128b is connected to the third node N3, and the second terminal 128c is connected to the first node N1.

[0063] For example, the first scan signal Ga1 can be the same as or different from the second scan signal Ga2. For example, the first scan signal Ga1 and the second scan signal Ga2 are complementary signals.

[0064] For example, the pixel circuit may further include a storage sub-circuit 127, which includes a first terminal 127a and a second terminal 127b. The first terminal 127a and the second terminal 127b are respectively connected to the first power supply voltage terminal VDD and the first node N1. For example, during the data writing and compensation phases, the compensation sub-circuit 128 may be turned on in response to the second scan signal Ga2, so that the data signal written by the data writing sub-circuit 121 can be stored in the storage sub-circuit 127. At the same time, the compensation sub-circuit 128 may conduct the first node N1 and the third node N3, that is, electrically connect the control terminal 122a and the second terminal 122c of the driving sub-circuit 122, so that the relevant information of the threshold voltage of the driving sub-circuit 122 can also be stored in the storage sub-circuit accordingly. Thus, for example, during the light-emitting phase, the driving sub-circuit 122 can be controlled by using the stored data signal and the threshold voltage, so that the driving sub-circuit 122 is compensated.

[0065] For example, the pixel circuit may further include a second light-emitting control sub-circuit 129, which is connected to the fourth node N4 and configured to be connected to the first electrode 134 of the light-emitting element 120 through the fourth node N4. The second light-emitting control sub-circuit 129 is configured to control the conduction of the driving current between the third node N3 and the fourth node N4 in response to the second light-emitting control signal EM2, so that the driving signal can be applied to the light-emitting element 120. For example, the first light-emitting control sub-circuit 129 includes a control terminal 129a, a first terminal 129b, and a second terminal 129c. The control terminal 129a is configured to receive the second light-emitting control signal EM2, and the first terminal 129b and the second terminal 129c are respectively connected to the third node N3 and the fourth node N4.

[0066] For example, the second light-emitting control signal EM2 and the first light-emitting control signal EM1 may be the same signal or different signals.

[0067] For example, during the light-emitting phase, the second light-emitting control sub-circuit 129 is turned on in response to the second light-emitting control signal EM2 provided by the second light-emitting control terminal EM2, so that the driving sub-circuit 122 can be electrically connected to the light-emitting element 120 through the second light-emitting control sub-circuit 129, thereby driving the light-emitting element 120 to emit light under the control of the driving current. During the non-light-emitting phase, the second light-emitting control sub-circuit 129 is turned off in response to the second light-emitting control signal EM2, so as to avoid current flowing through the light-emitting element 120 and causing it to emit light, which can improve the contrast of the corresponding display device.

[0068] For example, the pixel circuit may further include a second reset sub - circuit 123, which is connected to the fourth node N4 and configured to be connected to the first electrode 134 of the light - emitting element 120 through the fourth node N4. The second reset sub - circuit 123 is configured to write a second reset voltage Init2 to the fourth node N4 in response to a second reset control signal Rst2.

[0069] For example, the second reset voltage is from - 2V to - 6V.

[0070] For example, the second reset control signal Rst2 and the bias control signal SCN may be the same or different.

[0071] For example, the second reset control signal Rst2 and the bias control signal SCN are connected to the same signal output terminal. For example, the second reset control signal Rst2 and the bias control signal SCN are transmitted through the same scan line.

[0072] In other examples, the second reset control signal Rst2 and the bias control signal SCN may also be different. For example, the second reset control signal Rst2 and the bias control signal SCN are connected to different signal output terminals. For example, the second reset control signal Rst2 and the bias control signal SCN are respectively transmitted through different scan lines.

[0073] For example, the second reset sub - circuit 129 may be turned on in response to the second reset control signal Rst2, so that the second reset voltage Init2 can be applied to the first electrode 134 of the light - emitting element 120, thereby performing a reset operation on the first electrode 134 of the light - emitting element 120 to eliminate the influence of the previous light - emitting stage.

[0074] For example, the light - emitting element 120 includes a first electrode 134 and a second electrode 135. The first electrode 134 of the light - emitting element 120 is configured to be connected to the second end 122c of the driving sub - circuit 122, and the second electrode 135 of the light - emitting element 120 is configured to be connected to the second power - supply voltage terminal VSS.

[0075] It should be noted that in the description of the embodiments of the present disclosure, the first node N1, the second node N2, the third node N3, and the fourth node N4 do not necessarily represent actually existing components, but represent the convergence points of relevant circuit connections in the circuit diagram.

[0076] It should be noted that in the description of the embodiments of the present disclosure, the symbol Vd can represent both the data signal terminal and the level of the data signal. Similarly, the symbols Ga1 and Ga2 can represent both the first scan signal and the second scan signal, and also the first scan signal terminal and the second scan signal terminal. EM1 and EM2 can represent both the first light emission control signal and the second light emission control signal, and also the first light emission control terminal and the second light emission control terminal. Rst1 and Rst2 can represent both the first reset control signal and the second reset control signal, and also the first reset control terminal and the second reset control terminal. The symbols Init1 and Init2 can represent both the first reset voltage terminal and the second reset voltage terminal and the levels of the first reset voltage and the second reset voltage. SCN can represent both the bias control terminal and the bias control signal. Vref can represent both the reference voltage terminal and the level of the reference voltage. The symbol VDD can represent both the first power supply voltage terminal and the first power supply voltage. The symbol VSS can represent both the second power supply voltage terminal and the second power supply voltage. The same applies to the following embodiments and will not be repeated.

[0077] Figure 2B shows Figure 2A a circuit diagram of a specific implementation example of the circuit shown. As Figure 2B shown, the pixel circuit includes first to eighth transistors T1, T2, T3, T4, T5, T6, T7, T8 and a storage capacitor Cst.

[0078] For example, as Figure 2B shown, the driving sub - circuit 122 can be implemented as the first transistor T1 (i.e., the driving transistor). The gate of the first transistor T1 serves as the control terminal 122a of the driving sub - circuit 122 and is connected to the first node N1; the first pole of the first transistor T1 serves as the first end 122b of the driving sub - circuit 122 and is connected to the second node N2; the second pole of the first transistor T1 serves as the second end 122c of the driving sub - circuit 122 and is connected to the third node N3.

[0079] For example, as Figure 2B shown, the data writing sub - circuit 121 can be implemented as the second transistor T2. The gate of the second transistor T2 is connected to the first scan line (the first scan signal terminal Ga1) to receive the first scan signal, the first pole of the second transistor T2 is connected to the data line (the data signal terminal Vd) to receive the data signal, and the second pole of the second transistor T2 is connected to the first end 122b (the second node N2) of the driving sub - circuit 122.

[0080] For example, as Figure 2BAs shown, the compensation sub-circuit 128 can be implemented as a third transistor T3 (i.e., the compensation transistor). The gate, the first pole, and the second pole of the third transistor T3 serve as the control terminal 128a, the first terminal 128b, and the second terminal 128c of the compensation sub-circuit, respectively. The gate of the third transistor T3 is configured to be connected to the second scan line (the second scan signal terminal Ga2) to receive the second scan signal. The first pole of the third transistor T3 is connected to the second terminal 122c (the third node N3) of the driving sub-circuit 122, and the second pole of the third transistor T3 is connected to the control terminal 122a (the first node N1) of the driving sub-circuit 122.

[0081] For example, as Figure 2B shown, the first light-emitting control sub-circuit 123 can be implemented as a fourth transistor T4. The gate of the fourth transistor T4 is electrically connected to the first light-emitting control line to receive the first light-emitting control signal. The first pole and the second pole of the fourth transistor T3 are electrically connected to the first power supply voltage terminal VDD and the first terminal 122b (the second node N2) of the driving sub-circuit 122, respectively.

[0082] For example, as Figure 2B shown, the first reset sub-circuit 125 can be implemented as a sixth transistor T6 (i.e., the reset transistor). The gate of the sixth transistor T6 is configured to be connected to the first reset control line (the first reset control terminal) to receive the first reset control signal Rst1. The first pole of the sixth transistor T6 is connected to the first reset voltage line to receive the first reset voltage Init1. The second pole of the sixth transistor T6 is configured to be connected to the first node N1.

[0083] For example, as Figure 2B shown, the bias sub-circuit 126 can be implemented as an eighth transistor T8 (i.e., the bias transistor). The gate of the eighth transistor T8 is configured to be electrically connected to the bias control line (the bias control terminal) to receive the bias control signal SCN. The first pole of the eighth transistor T8 is electrically connected to the reference voltage line (the reference terminal) to receive the reference voltage Vref. The second pole of the eighth transistor T8 is electrically connected to the first terminal 122b (the second node N2) of the driving sub-circuit 122.

[0084] For example, as Figure 2B shown, the second reset sub-circuit 129 can be implemented as a seventh transistor T7. The gate of the seventh transistor T7 is configured to be connected to the second reset control line to receive the second reset control signal Rst2. The first pole of the seventh transistor T7 is connected to the second reset voltage line to receive the second reset voltage Init2. The second pole of the seventh transistor T7 is configured to be connected to the fourth node N4.

[0085] For example, as Figure 2BAs shown, the second light emission control sub-circuit 124 can be implemented as a fifth transistor T5. The gate of the fifth transistor T5 is connected to the second light emission control line (second light emission control terminal EM2) to receive the second light emission control signal EM2, and the first and second poles of the fifth transistor T5 are respectively connected to the third node N3 and the fourth node N4.

[0086] For example, as Figure 2B shown, the storage sub-circuit 127 can be implemented as a storage capacitor Cst. The storage capacitor Cst includes a first capacitor electrode Ca and a second capacitor electrode Cb. The first capacitor electrode Ca is connected to the first power supply voltage terminal VDD, and the second capacitor electrode Cb is connected to the control terminal 122a of the drive sub-circuit 122.

[0087] For example, the light-emitting element 120 is specifically implemented as a light-emitting diode (LED), such as an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or an inorganic light-emitting diode, such as a micro light-emitting diode (Micro LED) or a micro OLED. For example, the light-emitting element 120 can be a top-emission structure, a bottom-emission structure, or a double-sided emission junction. The light-emitting element 120 can emit red light, green light, blue light, white light, etc. The embodiments of the present disclosure do not limit the specific structure of the light-emitting element. For example, the light-emitting element 120 includes a first electrode 134, a second electrode 135, and a light-emitting layer sandwiched between the first electrode 134 and the second electrode 135.

[0088] For example, the first electrode 134 (also referred to as a pixel electrode, such as an anode) of the light-emitting element 120 is connected to the fourth node N4, and the second electrode 135 (such as a cathode) of the light-emitting element 120 is configured to be connected to the second power supply voltage terminal VSS to receive the second power supply voltage VSS. The current flowing into the light-emitting element 120 from the second terminal 122c of the drive sub-circuit 122 determines the brightness of the light-emitting element. For example, the second power supply voltage terminal can be grounded, that is, VSS can be 0V. For example, the second power supply voltage VSS can also be a negative voltage.

[0089] For example, the pixel circuit needs to turn on the driving transistor T1 during the threshold compensation phase. Therefore, the voltage difference Init1 - VDD between the first reset voltage Init1 and the first power supply voltage VDD needs to be less than the threshold voltage Vth of the driving transistor T1. For example, the range of the first reset voltage Init1 can be from -2V to -6V, such as -2V, -3V, -4V, -5V, -6V, etc. For example, Init1 - VDD can be less than a * Vth, where the value range of a can be from 2 to 7, such as a can be 2, 4, 6, 7; Vth can be from -2V to -5V, such as -2V, -3V, -5V, etc. VDD can be greater than 1.5 times of Vth. For example, VDD can be 1.6 times, 1.8 times, 2 times of Vth, etc.

[0090] For example, the aspect ratio W / L of the eighth transistor T8 can be approximately equal to the aspect ratio W / L of the seventh transistor T7; alternatively, the aspect ratio W / L of the eighth transistor T8 can be greater than the aspect ratio W / L of the seventh transistor T7, that is, the aspect ratio W / L of T8 can be slightly larger, so that the N2 node can be quickly reset.

[0091] For example, the channel width W of the eighth transistor T8 is 1.5 - 3.5, such as it can be 1.6, 1.8, 1.9, 2.0, 2.2, 2.5, 3.0, etc.; the channel length L is 2.0 - 4.5; such as it can be 2.5, 2.7, 3.0, 3.2, 3.5, 4.0, etc.; the channel width W of the seventh transistor T7 is 1.5 - 3.5, such as it can be 1.6, 1.8, 1.9, 2.0, 2.2, 2.5, 3.0, etc.; the channel length L is 2.0 - 4.5; such as it can be 2.5, 2.7, 3.0, 3.2, 3.5, 4.0, etc.

[0092] For example, the aspect ratio W / L of the eighth transistor T8 can be approximately equal to the aspect ratio W / L of the sixth transistor T6; alternatively, the aspect ratio W / L of the eighth transistor T8 can be less than the aspect ratio W / L of the sixth transistor T6, so as to balance the reset capabilities of the N1 node and the N2 node.

[0093] For example, the aspect ratio W / L of the eighth transistor T8 can be greater than the aspect ratio W / L of the sixth transistor T6, so as to improve the reset capability of the N2 node.

[0094] For example, the channel width W of the eighth transistor T8 is 1.5 - 3.5, which can be, for example, 1.6, 1.8, 1.9, 2.0, 2.2, 2.5, 3.0, etc.; the channel length L is 2.0 - 4.5; which can be, for example, 2.5, 2.7, 3.0, 3.2, 3.5, 4.0, etc.; the channel width W of the sixth transistor T6 is 1.5 - 3.5, which can be, for example, 1.6, 1.8, 1.9, 2.0, 2.2, 2.5, 3.0, etc.; the channel length L is 2.0 - 4.5; which can be, for example, 2.5, 2.7, 3.0, 3.2, 3.5, 4.0, etc.

[0095] It should be noted that the transistors used in the embodiments of the present disclosure can all be thin - film transistors or field - effect transistors or other switching devices with the same characteristics. In the embodiments of the present disclosure, thin - film transistors are taken as examples for illustration. The source and drain of the transistors used here can be symmetric in structure, so there is no difference in structure between the source and drain. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one of the poles is directly described as the first pole and the other as the second pole.

[0096] In addition, transistors can be classified into N - type and P - type transistors according to their characteristics. When the transistor is a P - type transistor, the turn - on voltage is a low - level voltage (for example, 0V, - 5V, - 10V or other suitable voltages), and the turn - off voltage is a high - level voltage (for example, 5V, 10V or other suitable voltages); when the transistor is an N - type transistor, the turn - on voltage is a high - level voltage (for example, 5V, 10V or other suitable voltages), and the turn - off voltage is a low - level voltage (for example, 0V, - 5V, - 10V or other suitable voltages).

[0097] For example, the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are P - type transistors, for example, low - temperature polycrystalline silicon thin - film transistors (LTPS - TFTs); the third transistor T3 and the sixth transistor T6 are N - type transistors, for example, metal - oxide thin - film transistors.

[0098] Low - temperature polycrystalline silicon thin - film transistors have a high carrier mobility, and the required manufacturing temperature is low, which is compatible with glass substrates. Therefore, they are widely used in OLED display substrates. Display devices using low - temperature polycrystalline silicon thin - film transistors have advantages such as high resolution, fast response speed, high brightness, and high aperture ratio.

[0099] The stability of the gate voltage of the driving transistor (i.e., the first transistor T1) has an important impact on the display uniformity of the display substrate. For example, if the gate leakage of the driving transistor is serious, it will cause insufficient compensation of the gate voltage of the driving transistor during the threshold compensation stage, that is, the threshold voltage of the driving transistor cannot be fully compensated. As a result, the driving current during the light-emitting stage is still related to the threshold voltage Vth of the driving transistor, resulting in a decrease in the brightness uniformity of the display device.

[0100] Metal oxide thin film transistors have the advantage of low leakage current. Since the third transistor T3 and the sixth transistor T6 are both transistors directly connected to the gate of the first transistor T1 (i.e., the driving transistor), the stability of the third transistor T3 and the sixth transistor T6 directly affects the stability of the gate (N1 node) voltage of the first transistor T1. Using N-type metal oxide thin film transistors for the third transistor T3 and the sixth transistor helps to reduce the leakage current of the transistors, thereby helping to maintain the voltage of the N1 node. Thus, during the compensation stage, the threshold voltage of the first transistor T1 is conducive to being fully compensated, and further improving the display uniformity of the display substrate during the light-emitting stage.

[0101] The following combines Figure 2C the signal timing diagram shown, to Figure 2B illustrate the working principle of the pixel circuit shown. As Figure 2C shown, the display process of each frame of image includes an initialization stage t1, a data writing and compensation stage t2, and a light-emitting stage t3.

[0102] As Figure 2C shown, in this embodiment, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 use the same signal, and the second reset control signal Rst2 and the bias control signal SCN use the same signal; the second scan signal Ga2 of the sub-pixels in this row has the same waveform as the first reset control signal Rst1 of the sub-pixels in the previous row, that is, the same signal is used. However, this is not a limitation to the present disclosure.

[0103] During the initialization stage 1, the first reset control signal Rst1 is input to turn on the sixth transistor T6, and the first reset voltage Init1 is applied to the gate (first node N1) of the first transistor T1, thereby resetting the first node N1; the second reset control signal Rst2 is input to turn on the eighth transistor T8 and the seventh transistor T7, so that the reference voltage Vref is applied to the first pole (second node N2) of the first transistor T1, and the second reset voltage Init2 is applied to the first electrode 134 (fourth node N4) of the light-emitting element 120 to respectively reset the second node N2 and the fourth node N4.

[0104] The first reset voltage Init1 and the reference voltage Vref turn on the first transistor T1. When the first transistor T1 is a P-type transistor, Init1 - Vref is less than 0 and the absolute value is greater than the absolute value of the threshold voltage Vth of the first transistor T1.

[0105] By biasing the first transistor T1 during the initialization phase, the first transistor T1 has a unified initial state, thereby alleviating the hysteresis phenomenon caused by the previous light-emitting phase.

[0106] In the data writing and compensation stage 2, the first scan signal Ga1, the second scan signal Ga2, and the data signal Vd are input. The second transistor T2 and the third transistor T3 are turned on. The data signal Vd is written into the second node N2 by the second transistor T2, and the first node N1 is charged through the first transistor T1 and the third transistor T3 until the potential of the first node N1 changes to Vd + Vth and the first transistor T1 is turned off, where Vth is the threshold voltage of the first transistor T1. The potential of the first node N1 is stored and held in the storage capacitor Cst, that is, the voltage information with the data signal and the threshold voltage Vth is stored in the storage capacitor Cst, so as to provide grayscale display data and compensate the threshold voltage of the first transistor T1 itself during the subsequent light-emitting stage.

[0107] Since the first transistor T1 has been pre-biased during the initialization phase, it has a specific unified characteristic curve and is not affected by the previous frame's light-emitting phase.

[0108] For example, the absolute value of the voltage difference between the reference voltage and the first reset voltage is a preset value; the preset value is set such that when the light-emitting element is driven to emit light with the highest gray scale (i.e., 255 gray scales) brightness, the absolute value of the voltage difference (i.e., Vd_L255 + Vth - VDD) between the gate and the first pole of the first transistor T1 is less than the preset value; where Vd_L255 is the data signal written into the pixel circuit when the light-emitting element emits light with the highest gray scale brightness.

[0109] With this setting, the first transistor T1 is in a large positive bias or negative bias state, so that regardless of what gray scale value data is written in the current frame, a unified scanning direction can be obtained, further improving the above-mentioned hysteresis phenomenon.

[0110] For example, when the first transistor T1 is a P-type transistor, the threshold voltage Vth of the first transistor T1 is less than 0. Through the above setting, the first transistor T1 is in a large negative bias state. For example, the driving sub-circuit is in a state such as Figure 1The state of point A shown, so that regardless of whether the previous frame is a black screen, a white screen or other screens, a single forward scan can be achieved simultaneously, thereby improving the current difference caused by the hysteresis phenomenon.

[0111] In the light-emitting stage 4, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are input to turn on the fourth transistor T4 and the fifth transistor T5 respectively, and the fifth transistor T5 applies a driving current to the OLED to make it emit light. The value of the driving current Ids flowing through the OLED can be obtained according to the following formula:

[0112] Ids = K(VGS - Vth) 2 = K[(Vd + Vth - VDD) - Vth] 2 = K(Vd - VDD) 2 , where

[0113] K is the conductivity coefficient of the first transistor.

[0114] In the above formula, Vth represents the threshold voltage of the first transistor T1, VGS represents the voltage between the gate and the source (here the first pole) of the first transistor T1, and K is a constant value related to the first transistor T1 itself. It can be seen from the above calculation formula of Ids that the driving current Ids flowing through the OLED is no longer related to the threshold voltage Vth of the first transistor T1. Thus, compensation for the pixel circuit can be achieved, solving the problem of threshold voltage drift of the driving transistor (the first transistor T1 in the embodiments of the present disclosure) due to the manufacturing process and long-term operation, eliminating its influence on the driving current Ids, and thereby improving the display effect of the display device using it.

[0115] At least one embodiment of the present disclosure further provides a driving method for a pixel circuit, which is used to drive the pixel circuit provided in any of the above embodiments. The driving method at least includes: in the initialization stage, turning on the first reset sub-circuit to write the first reset signal to the first node, and turning on the bias sub-circuit to write the reference voltage to the second node, thereby turning on the driving sub-circuit; in the data writing stage, turning on the data writing sub-circuit to write the data signal to the second node, where the initialization stage is before the data writing stage. For specific descriptions, reference can be made to the above text and will not be elaborated here.

[0116] Figures 2D - 2G The schematic diagram of a pixel circuit provided in some other embodiments of the present disclosure is shown. The main difference between the pixel circuit provided in this embodiment and Figures 2A - 2B the pixel circuit provided in the embodiment shown is that this pixel circuit further includes a first capacitor C1 and a second capacitor C2.

[0117] The inventors found that in some cases of the layout of the pixel circuit, the fourth node N4 is prone to coupling with the fifth node N5 connected to the control terminal of the second light-emitting control sub-circuit 124 to form a coupling capacitor, that is, the first capacitor C1. The generation of this coupling capacitor may be due to the relatively close arrangement of the fifth transistor T5 (second light-emitting control sub-circuit) connected to the fourth node N4 and the first electrode 134 of the light-emitting element 120. For example, as follows Figure 4B As shown, in the direction perpendicular to the substrate, the first electrode 134 of the light-emitting element 120 overlaps with the gate of the fifth transistor T5 to form the first capacitor C1.

[0118] This first capacitor C1 makes the signal on the fourth node N4 vulnerable to the jump of the second light-emitting control signal EM2, thereby affecting the voltage on the first electrode 134 of the light-emitting element 120. This can easily cause unstable light-emitting brightness during the light-emitting stage and change the voltage on the first electrode 134 during the non-light-emitting stage, thereby causing a voltage difference between the first electrodes 134 of the light-emitting elements of adjacent sub-pixels, resulting in lateral leakage and color bleeding between adjacent sub-pixels.

[0119] To alleviate the above problems, a second capacitor can be provided between the fourth node N4 and the sixth node N6, thereby reducing the influence of the first capacitor C1 on the signal on the fourth node N4. The sixth node N6 can be other circuit nodes in the pixel circuit except the fifth node N5.

[0120] For example, the signal loaded on the sixth node N6 and the signal loaded on the fifth node N5 are in antiphase signals, thereby balancing the influence of the first capacitor C1 on the signal on the fourth node N4.

[0121] For example, a fixed voltage signal can be loaded on the sixth node N6, thereby stabilizing the signal on the fourth node N4. For example, the sixth node N6 is connected to a voltage line (such as a power supply voltage line, a reset voltage line, etc.).

[0122] For example, in combination with reference Figure 2F and the following Figure 4B As shown, in the direction perpendicular to the substrate, the first electrode 134 of the light-emitting element 120 overlaps with the second reset voltage line 407 in the direction perpendicular to the substrate to form the second capacitor C2.

[0123] In some other examples, for example, in combination with reference Figure 2G and the following Figure 4B , in the direction perpendicular to the substrate, the first electrode 134 of the light-emitting element 120 overlaps with the first capacitor electrode Ca in the direction perpendicular to the substrate to form the second capacitor C2, that is, the sixth node N6 is connected to the first power supply voltage terminal VDD.

[0124] For example, the capacitance value of the first capacitor C1 is less than that of the second capacitor C2; for example, the capacitance value of the first capacitor C1 can be 0.5-0.9 times that of the second capacitor C2, such as 0.6, 0.7, or 0.8 times.

[0125] For example, the capacitance value of the second capacitor C2 can be in the range of 3 fF - 7 fF, such as 3.5 fF, 4 fF, 4.5 fF, 5 fF, 6 fF, etc. In this way, the lateral leakage of the display substrate can be effectively reduced, thereby alleviating the color bleeding problem.

[0126] At least one embodiment of the present disclosure further provides a display substrate, including the pixel circuit provided in any of the above embodiments.

[0127] Figure 3 A plan view of the display substrate provided by at least one embodiment of the present disclosure is shown. As Figure 3 shown, the display substrate 20 includes a display area 110 and a non-display area 103 outside the display area 110. For example, the non-display area 103 is located in the peripheral area of the display area 110. The display substrate 20 includes a plurality of sub-pixels 100 located in the display area 110. For example, the plurality of sub-pixels are arranged in an array, such as arranging a plurality of pixel rows and a plurality of pixel columns along a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 are different, for example, they are orthogonal. For example, the pixel rows and pixel columns do not necessarily extend strictly along a straight line, and can also extend along a curve (such as a broken line), and the curve generally extends along the first direction D1 or the second direction D2 respectively.

[0128] Each sub-pixel includes a pixel circuit for driving a light-emitting element to emit light, and a plurality of pixel circuits are arranged in an array along the first direction D1 and the second direction D2. For example, the sub-pixels form pixel units in the traditional RGB manner to achieve full-color display, and the present disclosure does not limit the arrangement manner of the sub-pixels and the manner of achieving full-color display.

[0129] For example, as Figure 3 shown, the display substrate 20 further includes a wire (such as a gate line 11) extending along the first direction D1 and a plurality of wires (such as data lines 12) extending along the second direction D2 in the display area 110. The plurality of horizontal wires and the plurality of vertical wires cross each other, defining a plurality of pixel areas in the display area 110, and one sub-pixel 100 is correspondingly arranged in each pixel area. Figure 3 Only the approximate positional relationship of the gate line 11, the data line 12, and the sub-pixel 100 in the display substrate is schematically shown in, and can be specifically designed according to actual needs.

[0130] Each sub-pixel 100 includes a pixel circuit and a light-emitting element, and the pixel circuit is configured to drive the light-emitting element to emit light. The pixel circuit of at least one sub-pixel 100 adopts the pixel circuit provided in any of the above embodiments.

[0131] For example, the display substrate may further include a gate driving circuit 13 and a data driving circuit 14 located in the non-display area. The gate driving circuit 13 is connected to the pixel circuit through a gate line 11 to provide various scanning signals, and the data driving circuit 14 is connected to the pixel circuit through a data line 12 to provide data signals. Figure 3 For the gate driving sub-circuit 13 and the data driving sub-circuit 14 shown, the positional relationship between the gate line 11 and the data line 12 in the display substrate is only an example, and the actual arrangement position can be designed according to needs.

[0132] For example, the display substrate 20 may further include a control circuit (not shown). For example, the control circuit is configured to control the data driving circuit 14 to apply the data signal, and control the gate driving sub-circuit to apply the scanning signal. An example of the control circuit is a timing control circuit (T-con). The control circuit can be in various forms, for example, including a processor and a memory, the memory includes executable code, and the processor runs the executable code to execute the above detection method.

[0133] For example, the processor may be a central processing unit (CPU) or other forms of processing devices having data processing capabilities and / or instruction execution capabilities, such as a microprocessor, a programmable logic controller (PLC), etc.

[0134] For example, the storage device may include one or more computer program products, and the computer program products may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory, etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor may run the program instructions to perform the desired functions. Various application programs and various data may also be stored in the computer-readable storage medium.

[0135] The following will take the sub-pixel adopting Figure 2B the pixel circuit shown as an example and combine it with Figures 4A - 4B , Figure 5 , Figure 6 , Figure 7 , Figures 8A - 8B to exemplarily illustrate the structure of the display substrate provided by at least one embodiment of the present disclosure, however, this does not limit the present disclosure.

[0136] Figure 4A Schematic diagram of a sub-pixel in a display substrate 20 provided by at least one embodiment of the present disclosure Figure 4B is Figure 4A An example of a cross-sectional view along the section line I-I'. It should be noted that, for clarity, Figure 4A the structure of the light-emitting element is omitted, and only the substrate structure below the light-emitting element is shown; Figure 4B Structures that do not have a direct electrical connection relationship at the section line are omitted.

[0137] As Figures 4A - 4B shown, a first semiconductor layer 102, a first insulating layer 301, a first conductive layer 201, a second insulating layer 302, a second conductive layer 202, a third insulating layer 303, a second semiconductor layer 107, a fourth insulating layer 304, a third conductive layer 203, a fifth insulating layer 305, a fourth conductive layer 204, a sixth insulating layer 306, a fifth conductive layer 205, a seventh insulating layer 307, and a sixth conductive layer 206 are sequentially disposed on a substrate 101, thereby forming a structure of a display substrate as Figure 4A shown.

[0138] Figure 5 Corresponding to Figure 4A shows the patterns of the first semiconductor layer 102 and the first conductive layer 201 of the sub-pixel, Figure 6 On the basis of Figure 5 shows the second conductive layer 202; Figure 7 On the basis of Figure 6 shows the second semiconductor layer 107 and the third conductive layer 203; Figure 8A shows the fourth conductive layer 204, Figure 8B On the basis of Figure 7 shows the fourth conductive layer 204.

[0139] For ease of explanation, in the following description, Tng, Tns, Tnd, and Tna are used to represent the gate, the first pole, the second pole, and the channel region of the nth transistor Tn, respectively, where n is 1-8.

[0140] It should be noted that the so-called "same-layer setting" in the present disclosure refers to a structure formed by two (or more) structures through the same deposition process and patterned through the same lithography process, and they do not necessarily lie in the same horizontal plane, and their materials can be the same or different. The "integral structure" in the present disclosure refers to a structure in which two (or more) structures are formed through the same deposition process and patterned through the same lithography process to form a connected structure, and their materials can be the same or different.

[0141] For example, as Figure 5As shown, the first semiconductor layer 102 includes channel regions (T1a, T2a, T4a, T5a, T7a, T8a) of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8, as well as a first pole (T1s, T2s, T4s, T5s, T7s, T8s) and a second pole (T1d, T2d, T4d, T5d, T7d, T8d).

[0142] For example, the display substrate 20 adopts a self-alignment process, and uses the first conductive layer 201 as a mask to conductivize (e.g., dope) the first semiconductor layer 102, so that the portion of the first semiconductor layer 102 not covered by the first conductive layer 201 is conductivized. Thus, the portions of the first semiconductor layer on both sides of the channel regions of the respective transistors are conductivized to form the first pole and the second pole of the respective transistors. For example, the material of the first semiconductor layer 102 is a low-temperature polysilicon material.

[0143] For example, as Figure 5 shown, the first conductive layer 201 further includes a first scan line 210 extending along the first direction D1, a reset control line (second reset control line) 220, a light emission control line 230, and a first reset voltage line 240. For example, as Figure 5 shown, each row of sub-pixels corresponds to one reset control line 220, one first scan line 210, one light emission control line 230, and one first reset voltage line 240.

[0144] It should be noted that in the present disclosure, a signal line extending in a certain direction means that the extending direction of the main body portion of the signal line is the certain direction, and it does not necessarily mean that the signal line is a straight structure. For example, the signal line may include a bent structure or a protruding portion or a branched portion extending from the main body portion. The same applies to the following embodiments and will not be elaborated further.

[0145] The first scan line 210 is electrically connected (or is an integral structure) to the gate of the second transistor T2 in a corresponding row of sub-pixels to provide a first scan signal Ga1, and the reset control line 220 is electrically connected (or is an integral structure) to the gate of the seventh transistor T7 in a corresponding row of sub-pixels to provide a second reset control signal Rst2; the reset control line 220 is also electrically connected (or is an integral structure) to the gate of the eighth transistor T8 in a corresponding row of sub-pixels to provide a bias control signal SCN. Therefore, the reset control line 250 also serves as a reset control line; the light emission control line 230 is electrically connected (or is an integral structure) to the gates of the fourth transistor T4 and the fifth transistor T5 in a corresponding row of sub-pixels to provide a first light emission signal EM1 and a second light emission control signal EM2.

[0146] For example, as Figure 6As shown, the second conductive layer 202 includes a first capacitive electrode Ca. The first capacitive electrode Ca overlaps with the gate T1g of the first transistor T1 in a direction perpendicular to the substrate 101 to form a storage capacitor Cst, that is, the gate T1g of the first transistor T1 serves as the second capacitive electrode Cb of the storage capacitor Cst. For example, the first capacitive electrode Ca includes an opening 222 that exposes at least a portion of the gate T1g of the first transistor T1 to facilitate electrical connection of the gate T1g to other structures.

[0147] For example, the second conductive layer 202 may further include a first auxiliary control line 310 and a second auxiliary control line 320 extending in the first direction D1, which will be described in detail later in conjunction with Figure 7 this.

[0148] For example, as Figure 7 shown, the second semiconductor layer 170 includes channel regions (T3a, T6a) of the third transistor T3 and the sixth transistor T6, first poles (T3s, T6s) of the third transistor T3 and the sixth transistor T6, and second poles (T3d, T6d) of the third transistor T3 and the sixth transistor T6.

[0149] For example, as Figure 7 shown, the third conductive layer 203 includes a second scan line 350, a first reset control line 340, and a reference voltage line 330 extending in the first direction D1.

[0150] For example, the display substrate 20 adopts a self-alignment process, using the third conductive layer 203 as a mask to conductivize (e.g., dope) the second semiconductor layer 107, so that the portion of the second semiconductor layer 107 not covered by the third conductive layer 203 is conductivized, and thus the portions of the second semiconductor layer on both sides of the channel regions of the third transistor T3 and the sixth transistor T6 are conductivized to form the first poles and the second poles of the third transistor T3 and the sixth transistor T6, respectively.

[0151] For example, the material of the second semiconductor layer 107 is metal oxide semiconductor, such as IGZO, ZnO, AZO, IZTO, etc.

[0152] For example, in combination with reference to Figures 4A - 4B and Figure 7 , in a direction perpendicular to the substrate, the second scan line 350 and the second auxiliary control line 320 at least partially overlap; for example, the channel region T3a of the third transistor T3 located below the second scan line 350 is within the orthographic projection of the second auxiliary control line 320 on the substrate.

[0153] Thus, the second auxiliary control line 320 can serve as a light-shielding layer to prevent light from entering the channel region of the third transistor T3 from the back surface of the channel region, thereby having an adverse effect on the characteristics of the third transistor T3. For example, metal oxide semiconductor materials are sensitive to light. When the third transistor T3 uses the metal oxide semiconductor material as the channel region, light incident on the channel region easily causes a threshold drift of the third transistor T3. By setting the second auxiliary control line 320, the stability of the third transistor T3 can be improved, and further the gate voltage of the first transistor T1 can be stabilized.

[0154] For example, the second scan line 350 and the second auxiliary control line 320 are configured to receive the same scan signal, so that the third transistor T3 forms a double-sided gate structure, thereby improving the gate control ability of the third transistor T3 and further stabilizing the gate voltage of the first transistor T1.

[0155] For example, with reference to Figures 4A - 4B and Figure 7 , in the direction perpendicular to the substrate, the first reset control line 340 and the first auxiliary control line 310 at least partially overlap; for example, the channel region T6a of the sixth transistor T6 located below the first reset control line 340 is within the orthographic projection of the first auxiliary control line 310 on the substrate.

[0156] Thus, the first auxiliary control line 310 can serve as a light-shielding layer to prevent light from entering the channel region of the sixth transistor T6 from the back surface of the channel region, thereby having an adverse effect on the characteristics of the sixth transistor T6. For example, metal oxide semiconductor materials are sensitive to light. When the sixth transistor T6 uses the metal oxide semiconductor material as the channel region, light incident on the channel region easily causes a threshold drift of the sixth transistor T6. By setting the first auxiliary control line 310, the stability of the sixth transistor T6 can be improved, and further the gate voltage of the first transistor T1 can be stabilized.

[0157] For example, the first reset control line 340 and the first auxiliary control line 310 are configured to receive the same scan signal, so that the sixth transistor T6 forms a double-sided gate structure, thereby improving the gate control ability of the sixth transistor T6 and further stabilizing the gate voltage of the first transistor T1.

[0158] For example, with reference to Figures 4A - 4B and Figures 8A - 8B, the fourth conductive layer 204 includes a connection electrode 401. One end of the connection electrode 401 is electrically connected to the gate T1g of the first transistor T1, i.e., the second capacitor electrode Cb, through an opening 222 in the first capacitor electrode Ca and a via 501 in the insulating layer, and the other end is electrically connected to the second pole T3d of the third transistor T3 through a via 502, thereby electrically connecting the second capacitor electrode Cb to the second pole T3d of the third transistor T3. For example, the via 501 penetrates the second insulating layer 302, the third insulating layer 303, the fourth insulating layer 304, and the fifth insulating layer 305. For example, the via 502 penetrates the fourth insulating layer 304 and the fifth insulating layer 305.

[0159] For example, as Figures 8A - 8B shown, the fourth conductive layer 204 further includes a connection electrode 402. The connection electrode 402 is electrically connected to the first pole T6s of the sixth transistor T6 and the first reset voltage line 240 through a via 503 and a via 513 respectively, thereby electrically connecting the first pole T6s of the sixth transistor T6 to the first reset voltage line 240, such that the first pole T6s of the sixth transistor T6 can receive a first reset voltage Init1 from the first reset voltage line 240.

[0160] For example, with reference to Figures 4A - 4B and Figures 8A - 8B , the fourth conductive layer 204 further includes a connection electrode 403. The connection electrode 403 is electrically connected to the first pole T3s of the third transistor T3 and the first pole T5s of the fifth transistor T5 through a via 504 and a via 514 respectively, thereby electrically connecting the first pole T3s of the third transistor T3 to the first pole T5s of the fifth transistor T5.

[0161] For example, with reference to Figures 4A - 4B and Figures 8A - 8B , the fourth conductive layer 204 further includes a connection electrode 404. The connection electrode 404 is electrically connected to the second pole T5d of the fifth transistor T5 and the second pole T7d of the seventh transistor T7 through a via 505, so as to electrically connect the second pole T5d of the fifth transistor T5 and the second pole T7d of the seventh transistor T7 to the first electrode 134 of the light-emitting element 120.

[0162] For example, with reference to Figures 4A - 4B and Figures 8A - 8B , the fourth conductive layer 204 further includes a connection electrode 405. The connection electrode 405 is electrically connected to the first pole T8s of the eighth transistor T8 and the reference voltage line 330 through a via 507 and a via 508 respectively, thereby electrically connecting the first pole T8s of the eighth transistor T8 to the reference voltage line 330.

[0163] For example, with reference to Figures 4A - 4B andFigures 8A - 8B The fourth conductive layer 204 further includes a connection electrode 406, and the connection electrode 406 is electrically connected to the second pole T8d of the eighth transistor T8 and the first pole T1s of the first transistor T1 through vias 511 and 512 respectively, so as to electrically connect the second pole T8d of the eighth transistor T8 and the first pole T1s of the first transistor T1.

[0164] For example, with reference to Figure 4A and Figure 7 , in the second direction D2, the eighth transistor T8 (i.e., the bias sub-circuit) and the seventh transistor T7 (i.e., the second reset sub-circuit) are located on the same side (the first side) of the first transistor T1 (i.e., the driving sub-circuit), the sixth transistor T6 (i.e., the first reset sub-circuit) and the third transistor T3 (i.e., the compensation sub-circuit) are located on the same side (the second side) of the first transistor T1, and the first side and the second side are opposite sides of the first transistor T1 in the second direction D2.

[0165] This design facilitates the bias sub-circuit and the second reset sub-circuit to share the scan line (i.e., the second reset control line 220). And when the second pole T8d of the eighth transistor T8 is electrically connected to the first pole T1s of the first transistor T1 (i.e., the second pole T4d of the fourth transistor T4) through the connection electrode 406, the connection electrode 406 does not overlap with the first reset control line 340 and the second scan line 350 in the direction perpendicular to the substrate, thereby avoiding the interference of the signal on the connection electrode 406 with the signals on the first reset control line 340 and the second scan line 350. In this way, the reset of the gate T1g (i.e., the N1 node) of the first transistor T1 can be more stable.

[0166] For example, with reference to Figures 4A - 4B and Figures 8A - 8B , the fourth conductive layer 204 further includes a second reset voltage line 407, and the second reset voltage line 407 is electrically connected to the first pole T7s of the seventh transistor T7 through a via 506, so that the first pole T7s of the seventh transistor T7 can receive the second reset voltage Init2 from the second reset voltage line 407.

[0167] For example, the second reset voltage line 407 extends substantially along the first direction D1, and the second reset voltage line 407 includes a portion parallel to the first direction D1.

[0168] For example, with reference to Figures 4A - 4B and Figure 8B , in the direction perpendicular to the substrate, the second reset control line 220, the reference voltage line 330, and the second reset voltage line 407 at least partially overlap, so as to minimize the shielding area of the signal lines and effectively improve the aperture ratio of the display substrate.

[0169] For example, as shown in Figure 5 and Figures 8A - 8B , the fourth conductive layer 204 further includes a connection electrode 408 configured to load a first power supply voltage VDD. The connection electrode 408 is electrically connected to the first pole T4s of the fourth transistor T4 and the first capacitor electrode Ca through vias 509 and 510, respectively.

[0170] For example, as shown in Figures 8A - 8B , the fourth conductive layer 204 further includes a connection electrode 409 that is electrically connected to the first pole T2s of the second transistor T2 through a via 508.

[0171] With reference to Figure 4A , the fifth conductive layer 205 includes a data line 610 extending along the second direction D2. The data line 610 is electrically connected to the connection electrode 409 through a via 601, thereby connecting to the first pole T2s of the second transistor T2.

[0172] For example, the fifth conductive layer 205 includes a plurality of data lines 610 extending along the second direction D2. For example, the plurality of data lines 610 are electrically connected to a plurality of columns of sub-pixels one-to-one to provide a data signal Vd, and each data line 610 is electrically connected to the first pole T2s of the second transistor T2 in the corresponding column of sub-pixels to provide the data signal Vd.

[0173] For example, with reference to Figures 4A - 4B and Figures 8A - 8B , the fifth conductive layer 205 further includes a connection electrode 620 that is electrically connected to the connection electrode 404 through a via 602 to electrically connect the connection electrode 404 to the first electrode 134 of the light-emitting element 120.

[0174] The above connection electrodes 620 and 404 serve as transfer electrodes to lead out the first pole of the transistor located below and electrically connect it to the light-emitting element above. This setting can avoid, in the direction perpendicular to the substrate, the problem that the via directly penetrates through, resulting in too deep filling depth of the conductive material, leading to poor connection, disconnection, or unevenness. By setting the transfer electrodes, the depth of the via is reduced, and the contact yield is improved.

[0175] With reference to Figure 4B , the sixth conductive layer 206 includes the first electrode 134 of the light-emitting element 120.

[0176] For example, with reference to Figure 4B, the display substrate 20 may further include a pixel defining layer 308 located on the first electrode of the light-emitting element. An opening is formed in the pixel defining layer 308 to expose at least a part of the pixel electrode 134, thereby defining an opening region (i.e., an effective light-emitting region) 600 of each sub-pixel of the display substrate. The light-emitting layer 136 of the light-emitting element 120 is at least formed in the opening (the light-emitting layer 136 may also cover the surface of a part of the pixel defining layer on the side away from the first electrode of the light-emitting element), and the second electrode 135 is formed on the light-emitting layer 136 to form the light-emitting element 120. For example, the second electrode 135 is a common electrode and is arranged over the entire surface of the display substrate 20. For example, the pixel electrode 134 is the anode of the light-emitting element, and the second electrode 135 is the cathode of the light-emitting element.

[0177] For example, the substrate 101 may be a rigid substrate, such as a glass substrate, a silicon substrate, etc., or may be formed of a flexible material having excellent heat resistance and durability, such as polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene, polypropylene, polyacrylate, polyaryl compound, polyetherimide, polyethersulfone, polyethylene glycol terephthalate (PET), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), triacetyl cellulose (TAC), cycloolefin polymer (COP), and cycloolefin copolymer (COC), etc.

[0178] For example, the materials of the first semiconductor layer 102 and the second semiconductor layer 107 include but are not limited to silicon-based materials (amorphous silicon a-Si, polycrystalline silicon p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.), and organic material (hexathiophene, polythiophene, etc.).

[0179] For example, the materials of the first to fifth conductive layers may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), and alloy materials composed of the above metals; or conductive metal oxide materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), aluminum zinc oxide (AZO), etc.

[0180] For example, the light-emitting element 120 has a top-emission structure, the first electrode 134 is reflective, and the second electrode 135 is transmissive or semi-transmissive. For example, the first electrode 134 is an anode and the second electrode 135 is a cathode. For example, the first electrode 134 has a stacked structure of ITO / Ag / ITO. The transparent conductive material ITO is a material with a high work function, and direct contact with the light-emitting material can improve the hole injection rate; the metal material Ag helps to improve the reflectivity of the first electrode. For example, the second electrode 135 is a material with a low work function to act as a cathode, such as a semi-transmissive metal or metal alloy material, such as an Ag / Mg alloy material.

[0181] For example, the first insulating layer 301, the second insulating layer 302, the third insulating layer 303, the fourth insulating layer 304, the fifth insulating layer 305, and the sixth insulating layer 306 are, for example, inorganic insulating layers, such as oxides of silicon such as silicon oxide, silicon nitride, silicon oxynitride, nitrides of silicon, or oxynitrides of silicon, or insulating materials including metal nitrides such as aluminum oxide and titanium nitride. For example, the seventh insulating layer 307 and the pixel defining layer 308 are respectively organic insulating materials, such as organic insulating materials such as polyimide (PI), acrylate, epoxy resin, and polymethyl methacrylate (PMMA). For example, the seventh insulating layer 307 is a planarization layer; for example, the material of the seventh insulating layer 307 is a photoresist material.

[0182] At least one embodiment of the present disclosure further provides a display panel, including any one of the above display substrates 20. For example, the display panel is an OLED display panel, and correspondingly, the display substrate 20 included therein is an OLED display substrate. The display substrate 20 may include light-emitting elements or may not include light-emitting elements, that is, the light-emitting elements may be formed in a panel factory after the display substrate 20 is completed. In the case where the display substrate 20 itself does not include light-emitting elements, the display panel provided by the embodiment of the present disclosure further includes light-emitting elements in addition to the display substrate 20.

[0183] As Figure 9 shown, for example, the display panel 30 further includes a packaging layer 801 and a cover plate 802 disposed on the display substrate 20. The packaging layer 801 is configured to seal the light-emitting elements on the display substrate 20 to prevent the penetration of external moisture and oxygen into the light-emitting elements and the driving sub-circuits, thereby causing damage to the device. For example, the packaging layer 801 includes an organic thin film or a structure in which an inorganic thin film, an organic thin film, and an inorganic thin film are alternately stacked. For example, a water absorption layer (not shown) may be further disposed between the packaging layer 801 and the display substrate 20, configured to absorb residual water vapor or sol in the light-emitting elements during the previous manufacturing process. The cover plate 802 is, for example, a glass cover plate or a flexible cover plate. For example, the cover plate 802 and the packaging layer 801 may be an integral structure.

[0184] At least one embodiment of the present disclosure further provides a display device 40, such as Figure 10 shown. The display device 40 includes any one of the above-mentioned display substrates 20 or display panels 30. The display device in this embodiment may be: a monitor, an OLED panel, an OLED TV, an electronic paper, a mobile phone, a tablet computer, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function.

[0185] The above are only exemplary embodiments of the present invention and are not intended to limit the protection scope of the present invention. The protection scope of the present invention is determined by the appended claims.

Claims

1. A pixel circuit, comprising: A driving sub - circuit, including a control end connected to a first node, a first end connected to a second node, and a second end connected to a third node, and the driving sub - circuit is configured to control a driving current for driving a light - emitting element from the second node to the third node according to a voltage of the control end; A data - writing sub - circuit, connected to the second node, and configured to write a data signal into the second node in response to a first scan signal; A first light - emitting control sub - circuit, connected to the second node and a first power - voltage terminal, configured to write a first power voltage from the first power - voltage terminal into the second node in response to a first light - emitting control signal; A first reset sub - circuit, connected to the first node, and configured to write a first reset voltage into the first node in response to a first reset control signal; A biasing sub - circuit, connected to the second node, and configured to write a reference voltage into the second node in response to a biasing control signal, thereby turning on the driving sub - circuit; A second light - emitting control sub - circuit, connected to the third node, a fourth node, and a fifth node, and configured to be connected to a first electrode of the light - emitting element through the fourth node; The second light - emitting control sub - circuit includes a control electrode, the control electrode is connected to the fifth node and configured to receive a second light - emitting control signal, and the second light - emitting control sub - circuit is configured to conduct the third node and the fourth node in response to the second light - emitting control signal; A first capacitor, a first end of the first capacitor is connected to the fourth node, and a second end of the first capacitor is connected to the fifth node; And A second capacitor, a first end of the second capacitor is connected to the fourth node, and a second end of the second capacitor is connected to a sixth node; Wherein, a capacitance value of the first capacitor is less than a capacitance value of the second capacitor; A signal loaded on the sixth node and a signal loaded on the fifth node are anti - phase signals; or, the second end of the second capacitor is configured to receive a fixed voltage.

2. The pixel circuit according to claim 1, wherein, An absolute value of a voltage difference between the reference voltage and the first reset voltage is a preset value; The preset value is set such that when the light - emitting element is driven to emit light with the highest gray - scale brightness, an absolute value of a voltage difference between the control end and the first end of the driving sub - circuit is less than the preset value.

3. The pixel circuit according to claim 1, further comprising a second reset sub - circuit, Among them, The second reset sub - circuit is connected to the fourth node, and is configured to be connected to a first electrode of the light - emitting element through the fourth node, The second reset sub - circuit includes a first electrode for receiving a second reset voltage, and the second reset sub - circuit is configured to write the second reset voltage into the fourth node in response to a second reset control signal.

4. The pixel circuit according to claim 3, wherein The second end of the second capacitor is connected to the first electrode of the second reset sub - circuit.

5. The pixel circuit according to claim 1, further comprising a compensation sub - circuit, Among them, The compensation sub - circuit is connected to the first node and the third node, and is configured to turn on the first node and the third node in response to a second scan signal, thereby controlling the driving sub - circuit to write a compensation voltage to the first node based on a data signal written to the second node.

6. The pixel circuit according to claim 1, further comprising a storage sub - circuit. Among them, The storage sub - circuit includes a first end and a second end, and the first end and the second end of the storage sub - circuit are respectively connected to the first power - voltage terminal and the first node.

7. The pixel circuit according to any one of claims 1-6, wherein, The bias sub - circuit includes a bias transistor, and the first reset sub - circuit includes a reset transistor. The bias transistor is a P - type transistor, and the reset transistor is an N - type transistor.

8. A display substrate, comprising: A substrate; A plurality of sub - pixels, which are arranged in an array along a first direction and a second direction on the substrate. Wherein, at least one of the plurality of sub - pixels includes the pixel circuit according to any one of claims 1 - 7.

9. The display substrate according to claim 8, further comprising a bias control line extending along the first direction. Among them, The bias sub - circuit includes a bias transistor. The bias control line is electrically connected to the gate of the bias transistor to provide the bias control signal.

10. The display substrate according to claim 9, further comprising a reference voltage line. Among them, The reference voltage line is electrically connected to the first pole of the bias transistor to provide the reference voltage. The reference voltage line is located on a side of the bias control line away from the substrate.

11. The display substrate according to claim 9, further comprising a connection electrode. Among them, The second pole of the bias transistor is electrically connected to the first end of the driving sub - circuit through the connection electrode. The connection electrode is located on a side of the bias control line away from the substrate.

12. The display substrate according to claim 9, wherein, When the pixel circuit includes a second reset sub - circuit, in the second direction, the bias sub - circuit and the second reset sub - circuit are located on the same side of the driving sub - circuit.

13. The display substrate according to claim 12, wherein, The second reset sub - circuit includes a reset transistor. The bias control line is also electrically connected to the gate of the reset transistor to provide the second reset control signal.

14. The display substrate according to claim 8, wherein In the second direction, the first reset sub - circuit and the bias sub - circuit are located on opposite sides of the driving sub - circuit.

15. The display substrate according to claim 8, further comprising a first reset control line extending along the first direction. Among them, The first reset sub - circuit includes a reset transistor, and the first reset control line is electrically connected to the gate of the reset transistor to provide the first reset control signal.

16. The display substrate according to claim 15, further comprising a first reset voltage line extending along the first direction. Among them, The first reset voltage line is electrically connected to the first pole of the reset transistor to provide the first reset voltage.

17. The display substrate according to claim 16, wherein, In a direction perpendicular to the substrate, the first reset voltage line is located on a side of the active layer of the reset transistor close to the substrate, and the first reset control line is located on a side of the active layer of the reset transistor away from the substrate.

18. A display device, comprising a display substrate according to any one of claims 8-17.

19. A driving method for a pixel circuit according to any one of claims 1-7, comprising: In an initialization stage, turning on the first reset sub-circuit to write the first reset voltage to the first node, and turning on the bias sub-circuit to write the reference voltage to the second node, thereby turning on the driving sub-circuit; In a data writing stage, turning on the data writing sub-circuit to write the data signal to the second node, wherein the initialization stage is before the data writing stage.

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