A display panel and a driving method thereof

Abstract

The present invention provides a display panel and a driving method thereof. A bias transistor in a pixel circuit of the display panel biases the second end of a driving transistor to solve the problem of threshold drift of the driving transistor. A first reset transistor resets the gate of the driving transistor. The bias transistor in the pixel circuit only needs to receive a signal for biasing the second end of the driving transistor. Obviously, the biasing signal can be a fixed signal, so there is no need to set up an independent shift register circuit to control the signal. Moreover, since the data writing transistor and the first reset transistor are of the same transistor type, it is obviously possible to simultaneously control the data writing transistor and the first reset transistor through a group of shift register circuits, further reducing the number of shift register circuits, thereby realizing a narrow frame design of the display panel, and ensuring the performance of the driving transistor, thereby ensuring the display effect of the display panel.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and more particularly to a display panel and a driving method thereof. Background Art

[0002] Organic light-emitting display devices have the advantages of self-luminescence, low driving voltage, high luminous efficiency, fast response speed, light weight, and high contrast, and are considered to be the next generation of display devices with the most development potential.

[0003] A pixel in an organic light emitting display device includes a pixel circuit and a light emitting element. A driving transistor in the pixel circuit can generate a driving current, and the light emitting element emits light in response to the driving current.

[0004] However, the circuit structure of the current pixel circuit requires multiple groups of shift register circuits to control it, which makes the display panel not conducive to narrow frame design. Summary of the invention

[0005] In view of this, in order to solve the above problems, the present invention provides a display panel and a driving method thereof, and the technical solution is as follows:

[0006] A display panel comprises: a pixel circuit and a light emitting element;

[0007] The pixel circuit includes a driving transistor, a data writing transistor, a threshold compensation transistor, a first reset transistor, a bias transistor and a light emitting control module;

[0008] The data writing transistor is electrically connected to the first end of the driving transistor;

[0009] The threshold compensation transistor is connected in series between the gate of the driving transistor and the second end of the driving transistor, and is used to detect and self-compensate for the deviation of the threshold voltage of the driving transistor;

[0010] The first reset transistor is electrically connected to the second end of the driving transistor;

[0011] The bias transistor is electrically connected to the second end of the driving transistor;

[0012] The light emitting control module is connected in series with the driving transistor and the light emitting element respectively, and is used to control whether the driving current flows through the light emitting element;

[0013] The transistor type of the data write transistor is the same as the transistor type of the first reset transistor.

[0014] A display panel comprises: a pixel circuit and a light emitting element;

[0015] The pixel circuit includes a driving transistor, a data writing transistor, a threshold compensation transistor, a first reset transistor, a bias transistor and a light emitting control module;

[0016] The data writing transistor is electrically connected to the first end of the driving transistor;

[0017] The threshold compensation transistor is connected in series between the gate of the driving transistor and the second end of the driving transistor, and is used to detect and self-compensate for the deviation of the threshold voltage of the driving transistor;

[0018] The first reset transistor is electrically connected to the gate of the driving transistor;

[0019] The bias transistor is electrically connected to the second end of the driving transistor;

[0020] The light emitting control module is connected in series with the driving transistor and the light emitting element respectively, and is used to control whether the driving current flows through the light emitting element;

[0021] The transistor type of the first reset transistor is the same as the transistor type of the bias transistor.

[0022] A display panel driving method, applicable to the display panel described above;

[0023] The working process of the pixel circuit includes a first biasing stage, a resetting stage, a data writing stage and a light emitting stage;

[0024] In the first biasing stage, the biasing transistor is turned on to provide a bias voltage to the second end of the driving transistor;

[0025] In the reset phase, the first reset transistor and the threshold compensation transistor are turned on to provide a first reference voltage to the gate of the driving transistor;

[0026] In the data writing phase, the data writing transistor and the threshold compensation transistor are turned on to provide a data signal to the gate of the driving transistor;

[0027] In the light emitting stage, the light emitting control module is turned on to control the driving current to flow through the light emitting element.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] The bias transistor in the pixel circuit of the display panel provided by the present invention is used to bias the second end of the driving transistor to solve the problem of threshold drift of the driving transistor. The gate of the driving transistor is reset by the first reset transistor. That is to say, at this time, the bias transistor in the pixel circuit only needs to receive a signal that can bias the second end of the driving transistor. Obviously, the received signal for biasing the second end of the driving transistor can be a fixed signal, so there is no need to set up an independent shift register circuit to control the signal. Furthermore, since the transistor type of the data writing transistor in the pixel circuit is the same as the transistor type of the first reset transistor, it is obvious that the control of the data writing transistor and the first reset transistor can be simultaneously achieved through a group of shift register circuits, thereby reducing the number of shift register circuits, thereby realizing a narrow frame design of the display panel, and can ensure the performance of the driving transistor, thereby ensuring the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0031] Figure 1 It is a structural schematic diagram of a pixel circuit in the prior art;

[0032] Figure 2 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0033] Figure 3 A schematic diagram of the structure of a pixel provided by an embodiment of the present invention;

[0034] Figure 4 A schematic diagram of the structure of another pixel provided by an embodiment of the present invention;

[0035] Figure 5 A schematic diagram of the structure of another pixel provided by an embodiment of the present invention;

[0036] Figure 6 A schematic diagram of the structure of another pixel provided by an embodiment of the present invention;

[0037] Figure 7 A schematic diagram of a display panel provided by an embodiment of the present invention;

[0038] Figure 8 A timing diagram provided for an embodiment of the present invention;

[0039] Fig. 9 Another timing diagram provided for an embodiment of the present invention;

[0040] Fig.10 A schematic diagram of the structure of another pixel provided by an embodiment of the present invention;

[0041] Fig.11 A schematic flow chart of a method for driving a display panel provided by an embodiment of the present invention;

[0042] Fig.12 A schematic flow chart of another method for driving a display panel provided by an embodiment of the present invention;

[0043] Fig.13 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] Based on the content of the background technology, refer to Figure 1 , Figure 1 FIG. 1 is a schematic diagram of a pixel circuit structure in the prior art. If the driving transistor T3 is in the same bias state for a long time, it is easy to have a threshold drift, which affects the generated driving current and further affects the luminous effect of the display panel. In order to solve this technical problem, in the prior art, a control Figure 1 The middle transistor T5 receives different signals in different working stages of the pixel circuit to control the driving transistor T3, thereby reducing the threshold drift problem of the driving transistor T3, thereby improving the display effect of the display panel.

[0046] In order to enable the transistor T5 to receive different signals in different working stages of the pixel circuit, it is necessary to add a set of independent shift register circuits to provide the input signal DVINI for the transistor T5. This also leads to a large number of shift register circuits located in the border area of ​​the display panel, which is not conducive to the narrow border design of the display panel.

[0047] Based on this, an embodiment of the present invention provides a display panel, which can reduce the number of shift register circuits in the border area of ​​the display panel by improving the pixel circuit while solving the threshold drift problem of the driving transistor, thereby realizing a narrow border design of the display panel.

[0048] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0049] refer to Figure 2 , Figure 2 A structural schematic diagram of a display panel provided in an embodiment of the present invention, the display panel includes a plurality of pixels 11. In order to achieve full-color display of the display panel, the plurality of pixels 11 may optionally include pixels for emitting green light, pixels for emitting blue light, and pixels for emitting red light.

[0050] refer to Figure 3 , Figure 3 A structural schematic diagram of a pixel provided in an embodiment of the present invention, the pixel includes: a light-emitting element Q, and a pixel circuit 12 electrically connected to the light-emitting element Q, the pixel circuit 12 includes a driving transistor T3, a data writing transistor T2, a threshold compensation transistor T4, a first reset transistor T8, a bias transistor T5 and a light-emitting control module 13.

[0051] like Figure 3 As shown, the data writing transistor T2 is electrically connected to the first end of the driving transistor T3.

[0052] The threshold compensation transistor T4 is connected in series between the gate of the driving transistor T3 and the second end of the driving transistor T3, and is used for detecting and self-compensating for the deviation of the threshold voltage of the driving transistor T3.

[0053] The first reset transistor T8 is electrically connected to the second end of the driving transistor T3.

[0054] The bias transistor T5 is electrically connected to the second end of the driving transistor T3.

[0055] The light emitting control module 13 is connected in series with the driving transistor T3 and the light emitting element Q respectively, and is used to control whether the driving current flows through the light emitting element Q.

[0056] The transistor type of the data writing transistor T2 is the same as the transistor type of the first reset transistor T8 .

[0057] Specifically, in the embodiment of the present invention, the data writing transistor T2 writes the data signal V data to the driving transistor T3, and the driving transistor T3 is connected to the driving transistor T3 according to the data signal V data A driving current is generated, and the light control module 13 controls whether the driving current flows through the light emitting element Q, thereby controlling the display state of the light emitting element Q.

[0058] like Figure 3 As shown, the bias transistor T5 in the pixel circuit 12 is used to bias the second end of the driving transistor T3 to solve the problem of threshold drift of the driving transistor T3, and the gate of the driving transistor T3 is reset by the first reset transistor T8. That is to say, at this time, the bias transistor T5 in the pixel circuit 12 only needs to receive a signal that can bias the second end of the driving transistor T3. The received signal for biasing the second end of the driving transistor T3 can be a fixed signal, so there is no need to set up an independent shift register circuit to provide the bias signal to the bias transistor T5. It should be noted that in the embodiment of the present invention, the fixed signal is taken as an example of a high-level signal DVH already in the display panel, and the high-level signal is a signal with a constant voltage.

[0059] Further, the transistor type of the data writing transistor T2 in the pixel circuit 12 is the same as the transistor type of the first reset transistor T8. For example, the data writing transistor T2 and the first reset transistor T8 are both P-type transistors, then the enable level for controlling the data writing transistor T2 to be turned on and the enable level for controlling the first reset transistor T8 to be turned on are both low levels, or, the data writing transistor T2 and the first reset transistor T8 are both N-type transistors, then the enable level for controlling the data writing transistor T2 to be turned on and the enable level for controlling the first reset transistor T8 to be turned on are both high levels. The first reset transistor T8 and the data writing transistor T2 of the pixel circuit 12 are turned on in time-sharing mode, and the signals provided by the adjacent two-stage shift registers in the same group of shift register circuits can be used to control the first reset transistor T8 and the data writing transistor T2 respectively. Obviously, the control of the data writing transistor T2 and the first reset transistor T8 can be realized simultaneously through a group of shift register circuits, thereby reducing the number of shift register circuits, thereby realizing the narrow frame design of the display panel, and ensuring the performance of the driving transistor T3, thereby ensuring the display effect of the display panel.

[0060] Figure 4 A schematic diagram of another pixel structure provided by an embodiment of the present invention is shown in FIG. Figure 4 As shown,

[0061] The gate of the data writing transistor T2 is electrically connected to the first scanning signal terminal SC_P(n); the gate of the first reset transistor T8 is electrically connected to the second scanning signal terminal SC_P(n-1).

[0062] For the pixel circuits 12 located in adjacent rows, the signal of the second scanning signal terminal SC_P(n-1) electrically connected to the gate of the first reset transistor T8 of the pixel circuit 12 located in the current row (for example, the nth row) is the same as the signal of the first scanning signal terminal SC_P(n-1) electrically connected to the gate of the data writing transistor T2 of the pixel circuit 12 located in the previous row (for example, the n-1th row).

[0063] Specifically, in the embodiment of the present invention, the gate of the data writing transistor T2 is electrically connected to the first scanning signal terminal SC_P(n), and the first scanning signal terminal SC_P(n) is used to output a first control signal for controlling the data writing transistor T2. The first control signal is a pulse signal. The effective pulse of the first control signal controls the data writing transistor T2 to be in a conducting state, so as to write the data signal V data The invalid pulse of the first control signal controls the data writing transistor T2 to be in the off state, that is, under the control of the first control signal, the data writing transistor T2 writes the data signal V data Provided to the first terminal of the driving transistor T3.

[0064] It should be noted that the data writing transistor T2 cooperates with the threshold compensation transistor T4 to write the data signal V data To the gate of the driving transistor T3, at this time, the data writing transistor T2 and the threshold compensation transistor T4 are both in the on state.

[0065] The gate of the first reset transistor T8 is electrically connected to the second scan signal terminal SC_P(n-1), and the second scan signal terminal SC_P(n-1) is used to output a second control signal for controlling the first reset transistor T8. The second control signal is a pulse signal. The effective pulse of the second control signal controls the first reset transistor T8 to be in the on state and provides the reference voltage to the second end of the driving transistor T3; the invalid pulse of the second control signal controls the first reset transistor T8 to be in the off state.

[0066] It should be noted that the first reset transistor T8 cooperates with the threshold compensation transistor T4 to reset the gate of the driving transistor T3. At this time, both the first reset transistor T8 and the threshold compensation transistor T4 are in the on state.

[0067] The display panel includes a shift register circuit, and a shift register circuit includes a plurality of shift registers arranged in cascade connection. Each shift register is arranged corresponding to a row of pixel circuits, for example, the nth-stage shift register provides a control signal for the nth-row pixel circuit. The signal provided by the second scanning signal terminal SC_P(n-1) to which the gate of the first reset transistor T8 in the pixel circuit 12 is electrically connected can be provided by the n-1th-stage shift register in the cascaded shift register, that is, the control signal provided by the shift register corresponding to the n-1th-row pixel circuit is borrowed, and the signal provided by the first scanning signal terminal SC_P(n) to which the gate of the data write transistor T2 is electrically connected can be provided by the nth-stage shift register in the cascaded shift register, and the transistor type of the data write transistor T2 in the pixel circuit 12 is the same as the transistor type of the first reset transistor T8, and the first reset transistor T8 in the nth-row pixel circuit is provided by the nth-1th-stage shift register. The signal provided by the second scanning signal terminal SC_P(n-1) electrically connected to the gate of the transistor T8 and the signal provided by the first scanning signal terminal SC_P(n-1) electrically connected to the gate of the data writing transistor T2 in the pixel circuit of the n-1th row can be provided by the same level of shift register (for example, the n-1th level), that is, the data writing transistor T2 and the first reset transistor T8 in the pixel circuit can be provided with control signals by the same shift register electrical device, that is to say, the display panel provided in the embodiment of the present invention can reduce the number of shift register circuits in the border area of ​​the display panel by improving the pixel circuit 12, thereby realizing a narrow border design of the display panel.

[0068] Continue to refer Figure 3 , the gate of the bias transistor T5 is electrically connected to the third scan signal terminal SC_P1; the pixel circuit 12 also includes a second reset transistor T7, a first end of the second reset transistor T7 is electrically connected to the second reference voltage terminal Vref2, a second end of the second reset transistor T7 is electrically connected to the light emitting element Q, and both are electrically connected to a fourth node N4, a gate of the second reset transistor T7 is electrically connected to the fourth scan signal terminal SC_P2, and the signal provided by the third scan signal terminal SC_P1 connected to the same pixel circuit 12 is the same as the signal provided by the fourth scan signal terminal SC_P2, for example, the same scan signal line can be used to provide signals to the third scan signal terminal SC_P1 and the fourth scan signal terminal SC_P2 respectively.

[0069] Specifically, in the embodiment of the present invention, the gate of the bias transistor T5 is electrically connected to the third scan signal terminal SC_P1, and the gate of the second reset transistor T7 is electrically connected to the fourth scan signal terminal SC_P2. The third scan signal terminal SC_P1 is used to output a signal for controlling the bias transistor T5, and the fourth scan signal terminal SC_P2 is used to output a signal for controlling the second reset transistor T7, both of which are third control signals. The third control signal is a pulse signal. The effective pulse of the third control signal controls the bias transistor T5 to be in a conducting state to bias the second end of the driving transistor T3, and controls the second reset transistor T7 to be in a conducting state to reset the anode of the light-emitting element Q; the invalid pulse of the third control signal controls the bias transistor T5 and the second reset transistor T7 to be in a turned-off state.

[0070] In the embodiment of the present invention, the bias transistor T5 and the second reset transistor T7 use the same signal to control whether they are in the on state or the off state. The same level shift register of the same shift register circuit can be used to provide control signals for the bias transistor T5 and the second reset transistor T7, thereby reducing the number of shift register circuits configured for each transistor.

[0071] Figure 5 A schematic diagram of the structure of another pixel provided by an embodiment of the present invention is shown in FIG. Figure 5 As shown, the gate of the bias transistor T5 is electrically connected to the third scan signal terminal SC_P1, and the pixel circuit 12 also includes a second reset transistor T7, a first end of the second reset transistor T7 is electrically connected to the second reference voltage terminal Vref2, a second end of the second reset transistor T7 is electrically connected to the light emitting element Q, and a gate of the second reset transistor T7 is electrically connected to the fourth scan signal terminal SC_P2.

[0072] For pixel circuits in two adjacent groups, the signal of the third scanning signal terminal SC_P1 to which the gate of the bias transistor T5 of the pixel circuit 12 in the current group is electrically connected is the same as the signal of the fourth scanning signal terminal SC_P2 to which the gate of the second reset transistor T7 of the pixel circuit 12 in the previous group is electrically connected. One group includes two adjacent rows of pixel circuits 12.

[0073] Specifically, in the embodiment of the present invention, since the display panel is provided with array-arranged pixels 11, each pixel 11 includes a light-emitting element Q and a pixel circuit 12 electrically connected to the light-emitting element Q. In each driving cycle, the pixel circuits 12 of each row can be driven by a row-by-row scanning method; Figure 5In order to reduce the number of signal lines in the display panel, the third scanning signal terminal SC_P1 in the pixel circuit 12 of the n-1 pixel row can be set to be electrically connected with the fourth scanning signal terminal SC_P2 of the pixel circuit 12 of the n-1 pixel row; when the pixel circuit 12 of the n-1 pixel row resets the anode of the light-emitting element Q, the pixel circuit 12 of the n-1 pixel row simultaneously implements bias processing on the second end of the driving transistor T3 to improve the bias effect on the driving transistor T3, solve the threshold drift problem of the driving transistor T3 to the greatest extent, improve the stability of the driving current generated by the driving transistor T3, and thus improve the display effect of the display panel.

[0074] The shift register circuit of the display panel can be set as a first-level shift register corresponding to two rows of pixel circuits, for example, the first-level shift register provides signals for the third scanning signal terminal SC_P1 of the bias transistor in two adjacent rows of pixel circuits respectively. The two rows of pixel circuits corresponding to the same level of shift register constitute a group, and for the pixel circuits located in two adjacent groups, the signal of the third scanning signal terminal electrically connected to the gate of the bias transistor T5 of the pixel circuit located in the current group (for example, the nth row and the n+1th row) is the same as the signal of the fourth scanning signal terminal SC_P2 electrically connected to the gate of the second reset transistor T7 of the pixel circuit located in the previous group (for example, the n-2th row and the n-1th row), and is provided by the same level of shift register.

[0075] The active layer of the threshold compensation transistor T4 may include metal oxide.

[0076] Specifically, in the embodiment of the present invention, the threshold compensation transistor T4 can adopt a metal oxide transistor with a low leakage level, that is, the active layer of the threshold compensation transistor T4 adopts metal oxide, which can firstly keep the gate of the driving transistor T3 at a stable potential during the light-emitting stage, thereby avoiding the problem of brightness reduction during the light-emitting stage caused by the leakage of the threshold compensation transistor T4.

[0077] Optionally, the active layer of the threshold compensation transistor T4 may be made of indium gallium zinc oxide (IGZO for short).

[0078] IGZO is composed of In2O3, Ga2O3 and ZnO, has a bandgap of about 3.5 eV, and is an N-type semiconductor material; that is, in the embodiment of the present invention, the threshold compensation transistor T4 is an N-type transistor for example.

[0079] Based on the low leakage current characteristic of the threshold compensation transistor T4, the data writing transistor T2 and the first reset transistor T8 can be LTPS (Low Temperature Poly Silicon) transistors, which will not affect the data writing transistor T2 writing the data signal Vdata The stability of the gate of the driving transistor T3 will not be affected, nor will the resetting effect of the first reset transistor T8 on the gate of the driving transistor T3 be affected, and the leakage current problem of the first reset transistor T8 will not affect the gate potential of the driving transistor T3.

[0080] In the embodiment of the present invention, the driving transistor T3, the data writing transistor T2, the bias transistor T5, the first reset transistor T8, the second reset transistor T7 and the active layers of the transistors in the light emitting control module 13 may include polysilicon materials.

[0081] like Figure 3-Figure 5 As shown, the pixel circuit further includes a second reset transistor T7.

[0082] The gate of the driving transistor T3 is electrically connected to the first node N1, the first end of the driving transistor T3 is electrically connected to the second node N2, and the second end of the driving transistor T3 is electrically connected to the third node N3;

[0083] The gate of the data writing transistor T2 is electrically connected to the first scan signal terminal SC_P(n), the first terminal of the data writing transistor T2 is electrically connected to the data signal terminal Vdata, and the second terminal of the data writing transistor T2 is electrically connected to the second node N2.

[0084] A gate of the first reset transistor T8 is electrically connected to the second scan signal terminal SC_P(n-1), a first terminal of the first reset transistor T8 is electrically connected to the first reference voltage terminal Vref1, and a second terminal of the first reset transistor T8 is electrically connected to the third node N3.

[0085] A gate of the bias transistor T5 is electrically connected to the third scan signal terminal SC_P1 , a first terminal of the bias transistor T5 is electrically connected to the bias voltage terminal DVH, and a second terminal of the bias transistor T5 is electrically connected to the third node N3 .

[0086] A gate of the threshold compensation transistor T4 is electrically connected to the fifth scan signal terminal SC_N(n), a first terminal of the threshold compensation transistor T4 is electrically connected to the third node N3, and a second terminal of the threshold compensation transistor T4 is electrically connected to the first node N1.

[0087] A gate of the second reset transistor T7 is electrically connected to the fourth scan signal terminal SC_P2, a first terminal of the second reset transistor T7 is electrically connected to the second reference voltage terminal Vref2, and a second terminal of the second reset transistor T7 is electrically connected to the fourth node N4.

[0088] The light emitting control module 13 includes a first light emitting control transistor T1 and a second light emitting control transistor T6, the first light emitting control transistor T1 is electrically connected to the second node N2, the first end of the second light emitting control transistor T6 is electrically connected to the third node N3, the second end of the second light emitting control transistor T6 is electrically connected to the fourth node N4, and the gate of the first light emitting control transistor T1 and the gate of the second light emitting control transistor T6 are both electrically connected to the light emitting control signal terminal EM.

[0089] The light emitting element Q is electrically connected to the fourth node N4.

[0090] Specifically, in the embodiment of the present invention, the gate of the data writing transistor T2 is electrically connected to the first scanning signal terminal SC_P(n), the first terminal of the data writing transistor T2 is electrically connected to the data signal terminal Vdata, the second terminal of the data writing transistor T2 is electrically connected to the second node N2, and the data signal terminal Vdata is used to output the data signal V data The first scanning signal terminal SC_P(n) is used to output a first control signal for controlling the data writing transistor T2. The first control signal is a pulse signal. The effective pulse of the first control signal controls the data writing transistor T2 to be in a conducting state so as to write the data signal V data The data signal V is written to the gate of the driving transistor T3; the invalid pulse of the first control signal controls the data writing transistor T2 to be in the off state; therefore, under the control of the first control signal, the data writing transistor T2 selectively writes the data signal V required by the pixel. data .

[0091] The gate of the first reset transistor T8 is electrically connected to the second scan signal terminal SC_P(n-1), the first end of the first reset transistor T8 is electrically connected to the first reference voltage terminal Vref1, the second end of the first reset transistor is electrically connected to the third node N3, the first reference voltage terminal Vref1 is used to output a first reset signal for resetting the gate of the driving transistor T3, the second scan signal terminal SC_P(n-1) is used to output a second control signal for controlling the first reset transistor T8, the second control signal is a pulse signal, the effective pulse of the second control signal controls the first reset transistor T8 to be in the on state to reset the gate of the driving transistor T3; the invalid pulse of the second control signal controls the first reset transistor T8 to be in the off state.

[0092] The gate of the bias transistor T5 is electrically connected to the third scan signal terminal SC_P1, the first end of the bias transistor T5 is electrically connected to the bias voltage terminal DVH, the second end of the bias transistor T5 is electrically connected to the third node N3, the bias voltage terminal DVH is used to output a bias signal for biasing the second end of the driving transistor T3, the third scan signal terminal SC_P1 is used to output a third control signal for controlling the bias transistor T5, the third control signal is a pulse signal, the effective pulse of the third control signal controls the bias transistor T5 to be in the on state to bias the second end of the driving transistor T3; the invalid pulse of the third control signal controls the bias transistor T5 to be in the off state.

[0093] The gate of the second reset transistor T7 is electrically connected to the fourth scan signal terminal SC_P2, the first terminal of the second reset transistor T7 is electrically connected to the second reference voltage terminal Vref2, the second terminal of the second reset transistor T7 is electrically connected to the fourth node N4, the second reference voltage terminal Vref2 is used to output a second reset signal for resetting the anode of the light-emitting element Q, and the fourth scan signal terminal SC_P2 is used to output a fourth control signal for controlling the second reset transistor T7, the fourth control signal is a pulse signal, and the effective pulse of the fourth control signal controls the second reset transistor T7 to be in the on state to reset the anode of the light-emitting element Q; the invalid pulse of the fourth control signal controls the second reset transistor T7 to be in the off state.

[0094] The gate of the threshold compensation transistor T4 is electrically connected to the fifth scanning signal terminal SC_N(n), the first end of the threshold compensation transistor T4 is electrically connected to the third node N3, and the second end of the threshold compensation transistor T4 is electrically connected to the first node N1. The fifth scanning signal terminal SC_N(n) is used to output a fifth control signal for controlling the threshold compensation transistor T4. The fifth control signal is a pulse signal. The effective pulse of the fifth control signal controls the threshold compensation transistor T4 to be in the on state to detect and self-compensate for the deviation of the threshold voltage of the driving transistor T3; the invalid pulse of the fifth control signal controls the threshold compensation transistor T4 to be in the off state.

[0095] The first light emitting control transistor T1 is electrically connected to the second node N2, the first end of the second light emitting control transistor T6 is electrically connected to the third node N3, the second end of the second light emitting control transistor T6 is electrically connected to the fourth node N4, the gate of the first light emitting control transistor T1 and the gate of the second light emitting control transistor T2 are both electrically connected to the light emitting control signal terminal EM, and the light emitting control signal terminal EM is used to output a light emitting control signal for controlling the first light emitting control transistor T1 and the second light emitting control transistor T6. The light emitting control signal is a pulse signal. The effective pulse of the light emitting control signal controls the first light emitting control transistor T1 and the second light emitting control transistor T6 to be in the on state. At this time, the driving current flows through the light emitting element Q, and the light emitting element Q emits light in response to the driving current; the invalid pulse of the light emitting control signal controls the first light emitting control transistor T1 and the second light emitting control transistor T6 to be in the off state.

[0096] It should be noted that the first end of the first light-emitting control transistor T1 is electrically connected to the first power supply voltage terminal PVDD, the second end of the first light-emitting control transistor T1 is electrically connected to the second node N2, the anode of the light-emitting element Q is electrically connected to the fourth node N4, and the cathode of the light-emitting element Q is electrically connected to the second power supply voltage terminal PVEE.

[0097] It should be noted that the data writing transistor T2 writes the data signal V data To the gate of the driving transistor T3, at this time, the data writing transistor T2 and the threshold compensation transistor T4 are both in the on state; when the first reset transistor T8 resets the gate of the driving transistor T3, the first reset transistor T8 and the threshold compensation transistor T4 are both in the on state.

[0098] It should be noted that the pixel circuit 12 further includes a capacitor C1 , a first plate of the capacitor C1 is electrically connected to the first power supply voltage terminal PVDD, and a second plate of the capacitor C1 is electrically connected to the first node N1 .

[0099] Figure 6 A schematic diagram of the structure of another pixel provided by an embodiment of the present invention is shown in FIG. Figure 6 As shown, the control signal SC_P(n-1) of the first reset transistor T8 is the same as the control signal SC_P(n-1) of the second reset transistor T7.

[0100] Specifically, in the embodiment of the present invention, the first reset transistor T8 is used to reset the gate of the driving transistor T3, and the second reset transistor T7 is used to reset the anode of the light-emitting element Q. In the embodiment of the present invention, the control signal of the first reset transistor T8 and the control signal of the second reset transistor T7 are made the same, so the same group of shift register circuits can be used to control the two, and the number of wirings of the display panel can also be simplified.

[0101] In other words, the gate of the first reset transistor T8 and the gate of the second reset transistor T7 are connected to the same scan signal terminal. In the embodiment of the present invention, the gate of the first reset transistor T8 and the gate of the second reset transistor T7 are connected to the second scan signal terminal SC_P(n-1) as an example.

[0102] Figure 7 A schematic diagram of a display panel provided by an embodiment of the present invention. Figure 7 As shown, the display panel includes N rows of pixel circuits, as shown by the first row of pixel circuits P1 to the Nth row of pixel circuits PN in the figure, the display panel also includes a first scanning circuit SC C, a second scanning circuit SCN C, a third scanning circuit SCP C and a light emitting control circuit Emit C, and the first scanning circuit SC C, the second scanning circuit SCN C, the third scanning circuit SCP C and the light emitting control circuit Emit C all include multi-stage cascaded shift registers.

[0103] The first scanning circuit SC C includes N+1 stages of shift registers, namely SC 0-SC N, and each stage of the shift register is arranged corresponding to a row of pixel circuits.

[0104] The second scanning circuit SCN C includes M stages of shift registers, namely SCN 1-SCN M, and each stage of shift register is arranged corresponding to two rows of pixel circuits.

[0105] The third scanning circuit SCP C includes M stages of shift registers, namely SCP 1-SCP M, and each stage of shift register is arranged corresponding to two rows of pixel circuits.

[0106] The light emitting control circuit Emit C includes M-level shift registers, namely Emit 1-Emit M, and each level of shift register is set corresponding to two rows of pixel circuits.

[0107] Here, M can be 1 / 2 of N.

[0108] Each shift register is set corresponding to a row of pixel circuits, which means that each shift register only provides signals to transistors with the same function in one row, but does not provide signals to transistors with the same function in other rows. Each shift register is set corresponding to two rows of pixel circuits, which means that each shift register provides the same signal to transistors with the same function in two rows, but does not provide signals to transistors with the same function in other rows.

[0109] Figure 7It is shown in the figure that the first scanning circuit SC C and the second scanning circuit SCN C are bilaterally driven, that is, two groups of circuits are set at the opposite ends of the pixel circuit row, and the third scanning circuit SCP C and the light emitting control circuit Emit C are unilaterally driven, that is, they are set at one end of the pixel circuit row.

[0110] The control signal of the data writing transistor T2 and the control signal of the first reset transistor T8 are provided by the first scanning circuit SCC.

[0111] The control signal of the threshold compensation transistor T4 is provided by the second scanning circuit SCN C.

[0112] The control signal of the bias transistor T5 is provided by the third scanning circuit SCP C.

[0113] The light emitting control module 13 includes a first light emitting control transistor T1 and a second light emitting control transistor T6 , and control signals of the first light emitting control transistor T1 and the second light emitting control transistor T6 are provided by Emit C of the light emitting control circuit.

[0114] Specifically, in the embodiment of the present invention, the first control signal for controlling the data writing transistor T2 and the second control signal for controlling the first reset transistor T8 are both provided by the first scanning circuit SC C; the third control signal for controlling the bias transistor T5 is provided by the second scanning circuit SCN C; the fifth control signal for controlling the threshold compensation transistor T4 is provided by the third scanning circuit SCPC; and the light emitting control signal for controlling the first light emitting control transistor T1 and the second light emitting control transistor T6 is provided by the light emitting control circuit Emit C.

[0115] Optionally, the shift register included in the first scanning circuit is a first shift register, and the first shift register provides a control signal for the data writing transistor T2 of the pixel circuit 12 located in the current row and provides a control signal for the first reset transistor T8 of the pixel circuit 12 located in the next row, that is, when the data signal V is written into the pixel circuit 12 in the current row, data At the same time, the gate of the driving transistor T3 in the next row of pixel circuits 12 is reset to fully reset the gate of the driving transistor T3 in the next row of pixel circuits 12, thereby improving the resetting effect of the gate of the driving transistor T3 in the next row of pixel circuits 12, thereby ensuring that the next row of pixel circuits 12 will receive the data signal V data Stability of the signal written to the gate of the driving transistor T3.

[0116] The shift register included in the second scanning circuit is a second shift register, and the second shift register provides a control signal for the threshold compensation transistor T4 of the pixel circuit located in the current two rows.

[0117] The shift register included in the third scanning circuit is a third shift register, and the third shift register provides a control signal for the bias transistor T5 of the pixel circuits of the current two rows.

[0118] The shift register included in the light emitting control circuit is a fourth shift register, and the fourth shift register provides control signals for the first light emitting control transistor T1 and the second light emitting control transistor T6 of the pixel circuits of the current two rows.

[0119] Optionally, in another embodiment of the present invention, refer to Figure 8 , Figure 8 A timing diagram provided for an embodiment of the present invention.

[0120] The enabling duration of the control signal provided by the first shift register is 1H.

[0121] The enabling duration of the control signal provided by the second shift register is greater than or equal to 6H.

[0122] Wherein, H represents the unit clock duration.

[0123] Specifically, in the embodiment of the present invention, the enabling duration of the control signal provided by the first shift register is 1H, that is, the effective duration of the data writing transistor T2 of the pixel circuit 12 in the current row and the first reset transistor T8 of the pixel circuit 12 in the next row being in the on state is 1H; the enabling duration of the control signal provided by the second shift register is greater than or equal to 6H, that is, the effective duration of the threshold compensation transistor T4 being in the on state is greater than or equal to 6H, while ensuring that the gate of the driving transistor T3 is reset and the data signal V is written data In this case, the deviation of the threshold voltage of the driving transistor T3 can be fully detected and self-compensated. In addition, a second shift register of one level can be set to correspond to two rows of pixel circuits.

[0124] Optionally, in another embodiment of the present invention, refer to Fig. 9 , Fig. 9 Another timing diagram provided for an embodiment of the present invention.

[0125] The enabling duration of the control signal provided by the first shift register is 1H.

[0126] The enabling duration of the control signal provided by the third shift register is greater than or equal to 6H.

[0127] Wherein, H represents the unit clock duration.

[0128] Specifically, in the embodiment of the present invention, the enabling duration of the control signal provided by the first shift register is 1H, that is, the effective duration of the data writing transistor T2 of the pixel circuit 12 in the current row and the first reset transistor T8 of the pixel circuit 12 in the next row being in the on state is 1H; the enabling duration of the control signal provided by the third shift register is greater than or equal to 6H, that is, the effective duration of the bias transistor T5 being in the on state is greater than or equal to 6H, so as to fully bias the second end of the driving transistor T5, so as to improve the bias effect of the driving transistor T5, solve the threshold drift problem of the driving transistor T5 to the greatest extent, improve the stability of the driving current generated by the driving transistor T5, and thereby improve the display effect of the display panel.

[0129] Optionally, in another embodiment of the present invention, refer to Fig.10 , Fig.10 A schematic diagram of the structure of another pixel provided by an embodiment of the present invention.

[0130] The pixel 11 in the display panel includes a pixel circuit 12 and a light-emitting element Q.

[0131] The pixel circuit 12 includes a driving transistor T3 , a data writing transistor T2 , a threshold compensation transistor T4 , a first reset transistor T8 , a bias transistor T5 and a light emitting control module 13 .

[0132] The data writing transistor T2 is electrically connected to a first end of the driving transistor T3 .

[0133] The threshold compensation transistor T4 is connected in series between the gate of the driving transistor T3 and the second end of the driving transistor T3, and is used for detecting and self-compensating for the deviation of the threshold voltage of the driving transistor T3.

[0134] The first reset transistor T8 is electrically connected to the gate of the driving transistor T3.

[0135] The bias transistor T5 is electrically connected to the second end of the driving transistor T3.

[0136] The light emitting control module 13 is connected in series with the driving transistor T3 and the light emitting element Q respectively, and is used to control whether the driving current flows through the light emitting element Q.

[0137] The transistor type of the first reset transistor T8 is the same as the transistor type of the bias transistor T5 .

[0138] Specifically, in the embodiment of the present invention, the first reset transistor T8 is electrically connected to the gate of the driving transistor T3, and the transistor type of the first reset transistor T8 is the same as the transistor type of the bias transistor T5. Then, the first reset transistor T8 and the bias transistor T5 can be controlled simultaneously by the same control signal, that is, the control signal of the first reset transistor T8 is the same as the control signal of the bias transistor T5. Then, while the gate of the driving transistor T3 is reset, the second end of the driving transistor T3 is also biased.

[0139] That is to say, in the embodiment of the present invention, the bias transistor T5 and the first reset transistor T8 are controlled by the same signal line to be in an on state or an off state, thereby reducing the number of signal lines in the display panel.

[0140] like Fig.10 As shown, the control signal of the second reset transistor T7 may be the same as the control signal of the bias transistor T5 and the first reset transistor T8.

[0141] Optionally, based on the above embodiments of the present invention, a method for driving a display panel is further provided in another embodiment of the present invention, which is applicable to the display panel provided in any of the above embodiments of the present invention, referring to Fig.11 , Fig.11 A schematic flow chart of a method for driving a display panel provided by an embodiment of the present invention.

[0142] S101: The working process of the pixel circuit 12 includes a first biasing stage, a reset stage, a data writing stage and a light emitting stage; in the first biasing stage, the biasing transistor T5 is turned on to provide a bias voltage to the second end of the driving transistor T3.

[0143] S102: In the reset phase, the first reset transistor T8 and the threshold compensation transistor T4 are turned on to provide a first reference voltage to the gate of the driving transistor T3.

[0144] S103: In the data writing phase, the data writing transistor T2 and the threshold compensation transistor T4 are turned on to provide a data signal to the gate of the driving transistor T3.

[0145] S104: In the light emitting stage, the light emitting control module 13 is turned on to control the driving current to flow through the light emitting element Q.

[0146] Specifically, in the first bias stage, the bias transistor is turned on to provide a bias voltage to the second end of the driving transistor T3 to solve the threshold drift problem of the driving transistor T3 and improve the data signal V dataThe stability of the gate of the driving transistor T3 is based on the stable data signal V data The driving transistor T3 after the bias processing can obtain the required driving current, that is, the accuracy of the driving current generated by the driving transistor T3 is improved.

[0147] In the data writing phase, the data signal V is written into the data writing transistor T2. data Write to the gate of the driving transistor T3, the driving transistor T3 is based on the data signal V data A corresponding driving current is generated, and at the same time, the threshold compensation transistor T4 is also in an on state, which is used to detect and self-compensate for the deviation of the threshold voltage of the driving transistor T3, and also to improve the performance of the driving transistor T3, and ultimately improve the accuracy of the driving current generated by the driving transistor T3, so as to improve the display effect of the display panel.

[0148] In the light-emitting stage, the light-emitting control module 13 is turned on, and the driving current generated by the driving transistor T3 flows through the light-emitting element Q. The light-emitting element Q emits light in response to the driving current. Then, the required brightness can be achieved based on the driving current with higher precision, thereby improving the display effect of the display panel.

[0149] Optionally, in another embodiment of the present invention, refer to Fig.12 , Fig.12 A schematic flow chart of another method for driving a display panel provided by an embodiment of the present invention.

[0150] The driving method further comprises:

[0151] S105: The operation process of the pixel circuit 12 also includes a second biasing stage located after the data writing stage and before the light emitting stage; in the second biasing stage, the biasing transistor T5 is turned on to provide a bias voltage to the second end of the driving transistor T3.

[0152] Specifically, in the embodiment of the present invention, the data signal V data After writing is completed and before the light-emitting stage, the second end of the driving transistor T3 is biased again to improve the performance of the pixel circuit so that the light-emitting element Q can reach the target brightness in the light-emitting stage to comprehensively improve the display effect of the display panel.

[0153] Optionally, in another embodiment of the present invention, Figure 8 As shown, the enabling time length of the threshold compensation transistor T4 receiving the control signal is greater than or equal to 6H.

[0154] Wherein, H represents the unit clock duration.

[0155] Specifically, in the embodiment of the present invention, the threshold compensation transistor T4 receives the control signal enabling time greater than or equal to 6H, that is, the threshold compensation transistor T4 is in the effective on-state for a time greater than or equal to 6H, while ensuring that the gate of the driving transistor T3 is reset and the data signal V is written. data In this case, the threshold voltage deviation of the driving transistor can be fully detected and self-compensated.

[0156] Optionally, in another embodiment of the present invention, Fig. 9 As shown, the enabling time length of the bias transistor T5 receiving the control signal is greater than or equal to 6H.

[0157] Wherein, H represents the unit clock duration.

[0158] Specifically, in the embodiment of the present invention, the enabling time length of the bias transistor T5 receiving the control signal is greater than or equal to 6H, that is, the effective time length of the bias transistor T5 in the on state is greater than or equal to 6H, so as to fully bias the second end of the driving transistor T3 in both the first bias stage and the second bias stage, so as to improve the bias effect of the driving transistor T3, solve the threshold drift problem of the driving transistor T3 to the greatest extent, improve the stability of the driving current generated by the driving transistor T3, and thus improve the display effect of the display panel.

[0159] Optionally, based on all the above embodiments of the present invention, another embodiment of the present invention further provides a display device, referring to Fig.13 , Fig.13 A schematic structural diagram of a display device provided by an embodiment of the present invention.

[0160] The display device 100 includes any one of the display panels provided in the above embodiments.

[0161] Since the display device 100 provided in the embodiment of the present invention includes any one of the display panels provided in the above embodiments, the display device 100 has the same or corresponding technical effects as the display panels provided in the above embodiments.

[0162] The display device 100 may specifically be a mobile phone, a computer, or other electronic devices.

[0163] The display panel and the driving method thereof provided by the present invention are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

[0164] It should be noted that each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0165] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device that includes a series of elements is inherent to the elements, or also includes elements inherent to these processes, methods, articles or devices. In the absence of further restrictions, the elements defined by the sentence "including a..." do not exclude the presence of other identical elements in the process, method, article or device that includes the elements.

[0166] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: include: Pixel circuit and light emitting element; The pixel circuit includes a driving transistor, a data writing transistor, a threshold compensation transistor, a first reset transistor, a bias transistor and a light emitting control module; The data writing transistor is electrically connected to the first end of the driving transistor; The threshold compensation transistor is connected in series between the gate of the driving transistor and the second end of the driving transistor, and is used to detect and self-compensate for the deviation of the threshold voltage of the driving transistor; The first reset transistor is electrically connected to the second end of the driving transistor; The bias transistor is electrically connected to the second end of the driving transistor; The light emitting control module is connected in series with the driving transistor and the light emitting element respectively, and is used to control whether the driving current flows through the light emitting element; The transistor type of the data write transistor is the same as the transistor type of the first reset transistor.

2. The display panel according to claim 1, characterized in that: The data writing transistor and the first reset transistor are both P-type transistors.

3. The display panel according to claim 1, characterized in that: The gate of the data writing transistor is electrically connected to the first scanning signal terminal; The gate of the first reset transistor is electrically connected to the second scan signal terminal; For pixel circuits located in adjacent rows, the signal at the second scanning signal terminal electrically connected to the gate of the first reset transistor of the pixel circuit located in the current row is the same as the signal at the first scanning signal terminal electrically connected to the gate of the data writing transistor of the pixel circuit located in the previous row.

4. The display panel according to claim 1, characterized in that: The gate of the bias transistor is electrically connected to the third scan signal terminal; The pixel circuit further includes a second reset transistor, a first terminal of the second reset transistor is electrically connected to the second reference voltage terminal, a second terminal of the second reset transistor is electrically connected to the light emitting element, and a gate of the second reset transistor is electrically connected to a fourth scan signal terminal; The signal provided by the third scanning signal terminal connected to the same pixel circuit is the same as the signal provided by the fourth scanning signal terminal.

5. The display panel according to claim 1, characterized in that: The gate of the bias transistor is electrically connected to the third scan signal terminal; The pixel circuit further includes a second reset transistor, a first terminal of the second reset transistor is electrically connected to the second reference voltage terminal, a second terminal of the second reset transistor is electrically connected to the light emitting element, and a gate of the second reset transistor is electrically connected to a fourth scan signal terminal; For pixel circuits located in two adjacent groups, the signal of the third scanning signal terminal to which the gate of the bias transistor of the pixel circuit located in the current group is electrically connected is the same as the signal of the fourth scanning signal terminal to which the gate of the second reset transistor of the pixel circuit located in the previous group is electrically connected; One group includes two adjacent rows of pixel circuits.

6. The display panel according to claim 1, characterized in that: The active layer of the threshold compensation transistor includes a metal oxide.

7. The display panel according to claim 1, characterized in that: The pixel circuit further includes a second reset transistor; The gate of the driving transistor is electrically connected to the first node, the first terminal of the driving transistor is electrically connected to the second node, and the second terminal of the driving transistor is electrically connected to the third node; The gate of the data writing transistor is electrically connected to the first scanning signal terminal, the first terminal of the data writing transistor is electrically connected to the data signal terminal, and the second terminal of the data writing transistor is electrically connected to the second node; The gate of the first reset transistor is electrically connected to the second scan signal terminal, the first terminal of the first reset transistor is electrically connected to the first reference voltage terminal, and the second terminal of the first reset transistor is electrically connected to the third node; The gate of the bias transistor is electrically connected to the third scan signal terminal, the first terminal of the bias transistor is electrically connected to the bias voltage terminal, and the second terminal of the bias transistor is electrically connected to the third node; The gate of the threshold compensation transistor is electrically connected to the fifth scan signal terminal, the first terminal of the threshold compensation transistor is electrically connected to the third node, and the second terminal of the threshold compensation transistor is electrically connected to the first node; The gate of the second reset transistor is electrically connected to the fourth scan signal terminal, the first terminal of the second reset transistor is electrically connected to the second reference voltage terminal, and the second terminal of the second reset transistor is electrically connected to the fourth node; The light emitting control module comprises a first light emitting control transistor and a second light emitting control transistor, wherein the first light emitting control transistor is electrically connected to the second node, a first end of the second light emitting control transistor is electrically connected to the third node, a second end of the second light emitting control transistor is electrically connected to the fourth node, and a gate of the first light emitting control transistor and a gate of the second light emitting control transistor are both electrically connected to a light emitting control signal terminal; The light emitting element is electrically connected to the fourth node.

8. The display panel according to claim 1, characterized in that: It also includes a first scanning circuit, a second scanning circuit, a third scanning circuit and a light emitting control circuit, wherein the first scanning circuit, the second scanning circuit, the third scanning circuit and the light emitting control circuit all include a multi-stage cascaded shift register; The control signal of the data writing transistor and the control signal of the first reset transistor are provided by the first scanning circuit; The control signal of the threshold compensation transistor is provided by the second scanning circuit; The control signal of the bias transistor is provided by the third scanning circuit; The light emitting control module includes a first light emitting control transistor and a second light emitting control transistor, and control signals of the first light emitting control transistor and the second light emitting control transistor are provided by the light emitting control circuit.

9. The display panel according to claim 8, characterized in that: The shift register included in the first scanning circuit is a first shift register, and the first shift register provides a control signal for a data writing transistor of a pixel circuit located in a current row and provides a control signal for a first reset transistor of a pixel circuit located in a next row; The shift register included in the second scanning circuit is a second shift register, and the second shift register provides a control signal for the threshold compensation transistors of the pixel circuits located in the current two rows; The shift register included in the third scanning circuit is a third shift register, and the third shift register provides control signals for the bias transistors of the pixel circuits of the current two rows; The shift register included in the light emitting control circuit is a fourth shift register, and the fourth shift register provides control signals for the first light emitting control transistor and the second light emitting control transistor of the pixel circuits of the current two rows.

10. The display panel according to claim 9, characterized in that: The enabling duration of the control signal provided by the first shift register is 1H; The enabling duration of the control signal provided by the second shift register is greater than or equal to 6H; Wherein, H represents the unit clock duration.

11. The display panel according to claim 9, characterized in that: The enabling duration of the control signal provided by the first shift register is 1H; The enabling duration of the control signal provided by the third shift register is greater than or equal to 6H; Wherein, H represents the unit clock duration.

12. A display panel, characterized in that: including a pixel circuit and a light emitting element; The pixel circuit includes a driving transistor, a data writing transistor, a threshold compensation transistor, a first reset transistor, a bias transistor and a light emitting control module; The data writing transistor is electrically connected to the first end of the driving transistor; The threshold compensation transistor is connected in series between the gate of the driving transistor and the second end of the driving transistor, and is used to detect and self-compensate for the deviation of the threshold voltage of the driving transistor; The first reset transistor is electrically connected to the gate of the driving transistor; The bias transistor is electrically connected to the second end of the driving transistor; The light emitting control module is connected in series with the driving transistor and the light emitting element respectively, and is used to control whether the driving current flows through the light emitting element; The transistor type of the first reset transistor is the same as the transistor type of the bias transistor.

13. The display panel according to claim 12, characterized in that: The control signal of the first reset transistor is the same as the control signal of the bias transistor.

14. A method for driving a display panel, characterized in that: Applicable to the display panel according to any one of claims 1 to 12; The working process of the pixel circuit includes a first biasing stage, a resetting stage, a data writing stage and a light emitting stage; In the first biasing stage, the biasing transistor is turned on to provide a bias voltage to the second end of the driving transistor; In the reset phase, the first reset transistor and the threshold compensation transistor are turned on to provide a first reference voltage to the gate of the driving transistor; In the data writing phase, the data writing transistor and the threshold compensation transistor are turned on to provide a data signal to the gate of the driving transistor; In the light emitting stage, the light emitting control module is turned on to control the driving current to flow through the light emitting element.

15. The driving method according to claim 14, characterized in that: The operation process of the pixel circuit further includes a second biasing phase located after the data writing phase and before the light emitting phase; In the second bias stage, the bias transistor is turned on to provide a bias voltage to the second end of the driving transistor.

16. The driving method according to claim 14, characterized in that: The enabling time length of the bias transistor receiving the control signal is greater than or equal to 6H; Wherein, H represents the unit clock duration.

17. The driving method according to claim 14, characterized in that: The threshold compensation transistor receives the control signal enabling time greater than or equal to 6H; Wherein, H represents the unit clock duration.

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