Methods for improving timing in memory devices and related devices and systems

Abstract

Methods for improving timing in a memory device and related devices and systems are disclosed. One method can include sampling a command signal according to a clock signal to obtain a standard-timed command. The method can also include sampling the command signal according to an adjusted clock signal to obtain a time-adjusted command. The method can also include comparing the standard-timed command to the time-adjusted command. The method can also include determining an improved timing of the clock signal based on the comparison of the standard-timed command to the time-adjusted command. The method can also include adjusting the clock signal based on the improved timing. Related systems and methods are also disclosed.

Description

[0001] Priority Claim

[0002] This application claims the benefit of U.S. Patent Application Serial No. 17 / 385,412, filed July 26, 2021, entitled “METHODS FOR IMPROVING TIMING IN MEMORY DEVICES, AND RELATEDDEVICES AND SYSTEMS,” the entire disclosure of which is hereby incorporated herein by reference. Technical Field

[0003] Embodiments of this disclosure relate to timing in memory devices. More specifically, various embodiments relate to methods, apparatus, and systems for improving timing of signal sampling. Background Technology

[0004] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic systems. Many different types of memory exist, including, for example, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), resistive random access memory (RRAM), double data rate memory (DDR), low-power double data rate memory (LPDDR), phase-change memory (PCM), and flash memory.

[0005] Furthermore, the memory device can be configured to sample data signals (including, for example, command signals) according to a clock signal. Timing alignment between the clock signal and the data signal can be important for accurate sampling (and / or delivery) of the data signal. Summary of the Invention

[0006] Various embodiments may include a method. The method may include sampling a command signal based on a clock signal to obtain a standard timing command. The method may also include sampling the command signal based on an adjusted clock signal to obtain a time-adjusted command. The method may further include comparing the standard timing command with the time-adjusted command. The method may further include determining an improved timing of the clock signal based on the comparison between the standard timing command and the time-adjusted command.

[0007] Various embodiments may include a method for reducing timing errors in a memory device. The method may include obtaining a clock signal and obtaining a command signal. The method may also include performing an operation at the memory device based on the command signal. The method may further include adjusting the clock signal to align it with the command signal while the operation is in progress, without interrupting the operation.

[0008] Various embodiments may include a memory device. The memory device may include a first sampler configured to sample a command signal based on a clock signal to generate a standard timing command. The memory device may also include an adjustment element configured to advance or delay the clock signal to generate an adjusted clock signal. The memory device may further include a second sampler configured to sample the command signal based on the adjusted clock signal to generate a time-adjusted command. The memory device may also include a timing analysis module communicatively coupled to the first sampler, the adjustment element, and the second sampler. The timing analysis module may be configured to compare the standard timing command with the time-adjusted command. The timing analysis module may also be configured to determine an improved timing of the clock signal based on the comparison between the standard timing command and the time-adjusted command.

[0009] Various embodiments may include a system. The system may include at least one input device, at least one output device, at least one processor device operatively coupled to the input device and the output device, and at least one memory device operatively coupled to the at least one processor device. The at least one memory device may include a first sampler configured to sample a command signal according to a clock signal to generate a standard timing command. The at least one memory device may also include an adjustment element configured to advance or delay the clock signal to generate an adjusted clock signal. The at least one memory device may also include a second sampler configured to sample the command signal according to the adjusted clock signal to generate a time-adjusted command. The at least one memory device may also include a timing analysis module communicatively coupled to the first sampler, the adjustment element, and the second sampler. The timing analysis module may be configured to compare the standard timing command with the time-adjusted command. The timing analysis module may also be configured to determine an improved timing of the clock signal based on the comparison between the standard timing command and the time-adjusted command. Attached Figure Description

[0010] Although this disclosure concludes with claims that specifically point out and expressly assert particular embodiments, the various features and advantages of embodiments within the scope of this disclosure will become more apparent from the following description, which is read in conjunction with the accompanying drawings, in which:

[0011] Figure 1 This is a block diagram illustrating an example memory device according to at least one embodiment of the present disclosure.

[0012] Figure 2 This is a timing diagram illustrating the relationship between instance sampling time and instance command signal according to at least one embodiment of the present disclosure.

[0013] Figure 3 This is a timing diagram illustrating the relationship between instance sampling time and instance command signal according to at least one embodiment of the present disclosure.

[0014] Figure 4 This is a functional block diagram illustrating an example timing circuit according to at least one embodiment of the present disclosure.

[0015] Figure 5 This invention describes a method for reducing timing errors in a memory device according to at least one embodiment of the present disclosure.

[0016] Figure 6 A method according to at least one embodiment of the present disclosure is described.

[0017] Figure 7 A method according to at least one embodiment of the present disclosure is described.

[0018] Figure 8 This is a simplified block diagram illustrating an example memory system according to at least one embodiment of the present disclosure.

[0019] Figure 9 This is a simplified block diagram illustrating an example electronic system according to at least one embodiment of the present disclosure. Detailed Implementation

[0020] Data signals (such as command signals) may include transition times for the data signal as it changes between values ​​(such as logic high and logic low). These transition times may occur periodically. Data signals may be sampled according to a clock signal. Specifically, at sampling times indicated by the clock signal, the data signal may be sampled (i.e., data samples may be obtained from the data signal).

[0021] Aligning the clock signal with the data signal to prevent the sampling time from overlapping with the transition time can be important. Acquiring data samples during the transition time can result in indeterminate or incorrect data samples (i.e., data samples that do not match the value of the data signal expected to be read at a given time). Therefore, aligning the timing of the clock signal with the data signal (e.g., aligning the clock signal with the clock edges between the transition times of the data signal) provides accurate sampling of the data signal.

[0022] The timing of the data signal and / or clock signal may drift over time (e.g., the data signal and / or clock signal may advance or delay over time). This drift may be a result of temperature changes, voltage changes, and / or noise. Drift of the data signal and / or clock signal can cause misalignment between the data signal and the clock signal, which can lead to incorrect data sampling.

[0023] Various embodiments can improve the accuracy of data sampling by, for example, determining an improved timing of the clock signal. Furthermore, some embodiments can adjust the clock signal based on the improved timing.

[0024] For example, in some embodiments, during one or more sampling periods, a command signal may be sampled based on a clock signal to obtain a standard timing command. An adjusted clock signal may be generated by advancing and / or delaying the clock signal by a time offset according to a search algorithm. During one or more sampling periods, a command signal may be sampled based on the adjusted clock signal to obtain a time-adjusted command. The standard timing command and the time-adjusted command may be compared to determine a pass range, such as determining which time offsets match the standard timing command and the time-adjusted command. The boundaries of the pass range may be determined (e.g., time offsets exceeding the pass range at or within a time increment). Improved timing may be determined based on the pass range; for example, the center of the pass range may be determined as the improved timing. The clock signal may be adjusted to align with the improved timing.

[0025] Although various embodiments are described herein with reference to memory devices, this disclosure is not limited thereto, and the embodiments are generally applicable to microelectronic systems and / or semiconductor devices that may or may not include memory devices. Furthermore, although various embodiments are described herein with reference to command signals, this disclosure is not limited thereto, and the embodiments are applicable to other timing-dependent signals, such as address signals, input signals, and / or output signals. Embodiments of this disclosure will now be explained with reference to the accompanying drawings.

[0026] Figure 1 This is a functional block diagram illustrating an example memory device 100 according to at least one embodiment of the present disclosure. The memory device 100 may include, for example, DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), SDRAM (Synchronous Dynamic Random Access Memory), DDR SDRAM (Dual Data Rate SDRAM, such as DDR4 SDRAM and the like), SGRAM (Synchronous Graphics Random Access Memory), or three-dimensional (3D) DRAM. The memory device 100, which can be integrated onto a semiconductor chip, may include a memory array 102.

[0027] exist Figure 1In this embodiment, memory array 102 is shown to include eight memory banks BANK0 to 7. More or fewer memory banks may be included in memory array 102 in other embodiments. Each memory bank includes several access lines (word lines WL), several data lines (bit lines BL and / BL), and several memory cells MC arranged at the intersections of the several word lines WL and the several bit lines BL and / BL. The selection of word lines WL may be performed by row decoder 104, and the selection of bit lines BL and / BL may be performed by column decoder 106. Figure 1 In one embodiment, row decoder 104 may include a corresponding row decoder for each memory bank BANK0 to 7, and column decoder 106 may include a corresponding column decoder for each memory bank BANK0 to 7.

[0028] Bit lines BL and / BL are coupled to the corresponding sense amplifiers SAMP. Read data from bit lines BL or / BL can be amplified by the sense amplifiers SAMP and transferred to the read / write amplifier 160 via the complementary local data line (LIOT / B), the transfer gate (TG), and the complementary main data line (MIOT / B). Conversely, write data output from the read / write amplifier 160 can be transferred to the sense amplifier SAMP via the complementary main data line MIOT / B, the transfer gate TG, and the complementary local data line LIOT / B, and written to the memory cell MC coupled to bit line BL or / BL.

[0029] The memory device 100 is typically configured to receive various inputs (e.g., from an external controller or host) via various terminals such as address terminal 110, command terminal 112, clock terminal 114, data terminal 116, and data mask terminal 118. The memory device 100 may include additional terminals such as power supply terminals 120 and 122.

[0030] During expected operation, one or more command signals COM received via command terminal 112 can be transmitted to command decoder 150 via command input circuitry 152. Command decoder 150 may include circuitry configured to generate various internal commands by decoding one or more command signals COM. Examples of internal commands include the valid command ACT and the read / write signal R / W.

[0031] Furthermore, one or more address signals ADD received via address terminal 110 can be transmitted to address decoder 130 via address input circuit 132. Address decoder 130 can be configured to supply row address XADD to row decoder 104 and column address YADD to column decoder 106. Although command input circuit 152 and address input circuit 132 are described as separate circuits, in some embodiments, address signals and command signals can be received via a common circuit.

[0032] The valid command ACT may include a pulse signal activated in response to a command signal COM (e.g., a valid command) indicating row access. In response to the valid signal ACT, the row decoder 104 at the specified memory address can be activated. Therefore, the word line WL specified by the row address XADD can be selected and activated.

[0033] The read / write signal R / W may include a pulse signal activated in response to a command signal COM (e.g., a read command or a write command) indicating column access. In response to the read / write signal R / W, the column decoder 106 may be activated and the bit line BL specified by the column address YADD may be selected.

[0034] In response to a valid command ACT, a read signal, row address XADD, and column address YADD, data can be read from the memory cell MC specified by row address XADD and column address YADD. The read data can be output via a sense amplifier SAMP, a transfer gate TG, a read / write amplifier 160, an input / output circuit 162, and a data terminal 116. Furthermore, in response to a valid command ACT, a write signal, row address XADD, and column address YADD, write data can be supplied to the memory array 102 via data terminal 116, input / output circuit 162, read / write amplifier 160, transfer gate TG, and sense amplifier SAMP. The write data can be written to the memory cell MC specified by row address XADD and column address YADD.

[0035] Clock signals CK and / or CK can be received via clock terminal 114. CLK input circuit 170 can generate an internal clock signal ICLK based on clock signals CK and / or CK. The internal clock signal ICLK can be transmitted to various components of memory device 100, such as command decoder 150 and internal clock generator 172. Internal clock generator 172 can generate an internal clock signal LCLK, which can be transmitted to input / output circuit 162 (e.g., for controlling the operating timing of input / output circuit 162). Furthermore, data mask terminal 118 can receive one or more data mask signals DM. When a data mask signal DM is activated, overwriting the corresponding data can be disabled.

[0036] The memory device 100 may further include command timing circuitry 176. Command timing circuitry 176 may be configured to improve the timing of ICLK (at least internally) to improve the sampling of one or more command signals COM. For example, command decoder 150 may be configured to sample one or more command signals COM according to ICLK to identify commands (e.g., ACT and / or R / W). Command timing circuitry 176 may be configured to adjust ICLK (at least internally) so that the identified commands are correct.

[0037] Figure 2 This is a timing diagram 200 illustrating the relationship between instance sampling time and instance command signal 202 according to at least one embodiment of the present disclosure. Specifically, Figure 2 Explain the relationship between command signal 202 and sampling time 214, sampling time 216, sampling time 218, sampling time 220, sampling time 222, sampling time 224 and sampling time 226 (which may be collectively referred to as sampling time and / or individually referred to as sampling time).

[0038] The sampling time can be, for example, the duration of input charge transfer from the command line to the command decoder, such as setup and hold time. The sampling time can occur in response to a clock signal. Specifically, the sampling time can occur in response to the clock edge of the clock signal. Alternatively or concurrently, one or more of the sampling times can be time-shifted before or after the clock edge of the clock signal, for example, as... Figure 2 As explained in the text.

[0039] exist Figure 2 The following example illustrates the concept of seven sampling times. Any number of sampling times can be used during sampling period 212. The relative duration and time increment of sampling period 212 control the number of sampling times per sampling period and are selectable based on the design. Figure 2 The sampling times described herein, in order from earliest to latest, are: sampling time 214 (which is X+1 time increments earlier than sampling time 220, where X is an integer greater than 1), sampling time 216 (which is X time increments earlier than sampling time 220), sampling time 218 (which is 1 time increment earlier than sampling time 220), sampling time 220, sampling time 222 (which is 1 time increment later than sampling time 220), sampling time 224 (which is X time increment later than sampling time 220), and sampling time 226 (which is X+1 time increment later than sampling time 220).

[0040] The sampling period 212 may be the duration of transmitting (by means included in the command signal 202) and / or receiving (by means sampling) a single command. The time increment may be a duration shorter than the sampling period 212; for example, the sampling period 212 may be divided into multiple time increments. As an example, the time increment may be represented by the duration described between sampling time 220 and sampling time 222.

[0041] Figure 2The description shows a command signal 202 that exhibits, for example, the shape of a data eye 204. The data eye 204 includes a transition time 206, a settling time 208, and a transition time 210. Transition times 206 and 210 are the times during which the command signal 202 can transition between values ​​(e.g., logic high and logic low). Settling time 208 is the time during which the command signal 202 settles, for example, between transition times.

[0042] The settling time 208 is an ideal time to sample the command signal 202. For example, sampling the command signal 202 at sampling time 216 results in sample 230, sampling it at sampling time 218 results in sample 232, sampling it at sampling time 220 results in sample 234, sampling it at sampling time 222 results in sample 236, and sampling it at sampling time 224 results in sample 238. Samples 230, 232, 234, 236, and 238 are all matchable, meaning they can have the same logic value.

[0043] Sampling the command signal 202 during transition time 206 and / or transition time 210 can result in indeterminate or incorrect sampled values. For example, sampling the command signal 202 at sampling time 214 can result in sample 228 and sampling the command signal 202 at sampling time 226 can result in sample 240. Samples 228 and / or sample 240 can be indeterminate. Alternatively, samples 228 and / or sample 240 can not match samples 234, 232, 236, 230, and 238. In other words, samples 228 and 240 can be indeterminate and / or have logic values ​​different from any of samples 234, 232, 236, 230, and 238.

[0044] In some cases, the timing of the clock signal and / or data signal may drift, for example due to temperature changes, voltage changes, and / or noise. This drift can cause misalignment between the clock signal and the command signal, which can lead to incorrect sampling of the command signal.

[0045] For example, command decoder (e.g.) Figure 1 The command decoder 150 can be configured to respond to a clock signal (e.g., Figure 1 The clock edge of ICLK is used to control the command signal (e.g., ...). Figure 1The command decoder samples the command signal (COM) at the time corresponding to sampling time 220, based on the clock edge of the clock signal. Either the command signal or the clock signal can drift relative to the other. For example, if the clock signal is advanced (or the command signal is delayed), then the clock edge of the clock signal causing sampling time 220 can be advanced, i.e., shifted to... Figure 2 The left side. If this drift continues, then a clock edge can occur during transition time 206, which can lead to incorrect sampling of the command signal.

[0046] Various embodiments can be configured to improve the sampling of command signals by determining improved timing and / or adjusting the clock signal according to improved timing. Adjusting the clock signal according to improved timing can cause sampling to occur during the settling time and / or prevent sampling during the transition time, which can improve the accuracy of sampling the command signal.

[0047] For example, various embodiments can be configured to sample the data signal during each of one or more sampling periods (e.g., at sampling time 220) based on the clock edge of the clock signal, resulting in a standard timing command (e.g., sample 234) for each sampling period. Additionally, various embodiments can be configured to sample the data signal during each of one or more sampling periods at a time offset from the clock edge of the clock signal (e.g., at one of sampling times 214, 216, 218, 222, 224, or 226), resulting in a time-adjusted command for each sampling period (e.g., sample 228, sample 230, sample 232, sample 236, sample 238, or sample 240). The time offset may differ at each of the one or more sampling periods. During or after each of the one or more sampling periods, the standard timing command in the standard timing command can be compared with the corresponding time-adjusted command in the time-adjusted command. Improved timing can be determined by comparing standard timing commands with time-adjusted commands. In some embodiments, a clock signal can be adjusted according to the improved timing such that data samples based on the adjusted clock signal are subsequently aligned with the data signal. Figure 3 An example is provided of sampling the command signal 302 based on the clock signal and the adjusted clock signal in three consecutive sampling periods.

[0048] Figure 3This is a timing diagram 300 illustrating the relationship between instance sampling time and instance command signal 302 according to at least one embodiment of the present disclosure. Specifically, during sampling period 304, command signal 302 may be sampled at sampling time 310 to generate sample 312 and at sampling time 314 to generate sample 316. During sampling period 306, command signal 302 may be sampled at sampling time 318 to generate sample 320 and at sampling time 322 to generate sample 324. During sampling period 308, command signal 302 may be sampled at sampling time 326 to generate sample 328 and at sampling time 330 to generate sample 332.

[0049] Each of sampling time 310, sampling time 318, and sampling time 326 can be adjusted without change based on the clock signal. For example, each of sampling time 310, sampling time 318, and sampling time 326 can... Figure 2 Sampling time 220 and Figure 2 The sampling period 212 is associated with sampling periods 304, 306, and 308 in the same manner. Alternatively, each of sampling times 310, 318, and 326 can be adjusted according to the clock edge without any advance or delay. Thus, each of samples 312, 320, and 328 can be an example of a standard timing command.

[0050] Each of sampling time 314, sampling time 322, and sampling time 330 can be adjusted relative to a clock signal. For example, sampling time 314 can be delayed relative to a clock signal by, for example, X time increments. Therefore, sampling time 314 can... Figure 2 Sampling time 224 and Figure 2 The sampling period 212 is related to the sampling period 304 in the same way. The sampling time 322 can be advanced relative to the clock signal, for example, by one time increment. Therefore, the sampling time 322 can... Figure 2 Sampling time 218 and Figure 2 The sampling period 212 is related to the sampling period 306 in the same way. The sampling time 330 can be delayed relative to the clock signal by, for example, X+1 time increments. Therefore, the sampling time 330 can... Figure 2 Sampling time 226 and Figure 2 The same method is associated with sampling period 212 and sampling period 308. Therefore, each of samples 316, 324, and 332 can be an example of a time-adjusted command.

[0051] During or after sampling period 304, samples 316 and 312 can be compared; during or after sampling period 306, samples 324 and 320 can be compared; and during or after sampling period 308, samples 332 and 328 can be compared.

[0052] Because sample 316 matches sample 312, it can be determined that sampling time 314 is within the passing range. Furthermore, because sample 324 matches sample 320, it can be determined that sampling time 322 is within the passing range. Because sample 332 does not match sample 328, it can be determined that sampling time 330 is outside the passing range. The passing range can be determined through additional sampling during additional sampling periods (not specified), and alternatively, the boundaries of the passing range can be determined.

[0053] For example, return to Figure 2 Based on the instance sampling time and samples, the pass range can be determined to include X time increments preceding sampling time 220 and X time increments following sampling time 220 (in other words, the pass range can be determined to be -X to X). Alternatively, the boundaries of the pass range can be determined, for example, based on a mismatch between corresponding examples of samples 228 and / or 240 and 234 (and based on a match between corresponding examples of samples 230 and 238 and 234), the pass range can be determined to be -X to X and / or -(X+1) and (X+1) beyond the pass range. Alternatively, the center of the pass range can be determined. Furthermore, in some embodiments, the center of the pass range can be determined to be an improved timing. In some embodiments, the clock signal can be adjusted to align with the improved timing.

[0054] For example, if the clock signal has drifted relative to the data clock signal such that the data is sampled at sampling time 218 according to the drifted clock signal (so that sample 232 is a standard timing command), then sampling at sampling time 214, sampling time 216, sampling time 224 and sampling time 226 can reveal that sampling time 220 is an improved timing and the clock signal can be adjusted so that the clock edge is aligned with sampling time 220.

[0055] In some embodiments, the selection of a time offset for each sampling period may be based on the results of one or more previous comparisons. For example, if sample 228 (sampled with a time offset of X+1 increments in advance) does not match sample 234, then a time offset of X+2 increments in advance may or may not be selected as the time offset. As another example, based on the match between sample 230 (sampled with a time offset of X increments in advance) and sample 234, a time offset of less than X increments in advance (e.g., sampling time 218) may or may not be selected as the time offset.

[0056] The sampling order and / or content of each of sampling times 214, 216, 218, 222, 224, and 226 may be based on a search algorithm, such as a linear search algorithm, a binary search algorithm, or a random search algorithm. For example, according to a linear search algorithm, in each subsequent sampling period, the time offset may be increased or decreased by one time increment until the boundary of the range is determined. As another example, according to a random search algorithm, in each subsequent sampling period, a random time offset may be selected until the range is identified.

[0057] Command signal 202 may be continuous; for example, command signal 202 may include data eye 204, which periodically (e.g., each clock cycle of the circuit) contains new data. Some embodiments may be configured to sample the command signal at each sampling period (e.g., according to the periodicity of command signal 202) based on each of a clock signal and an adjusted clock signal to obtain a standard timing command and a time-adjusted command. At each sampling period, the standard timing command and the time-adjusted command may be compared. Furthermore, in some embodiments, the improved timing may be analyzed periodically (e.g., each sampling period, every other sampling period, or every two sampling periods). For example, at each sampling period, it may be determined whether a previously performed comparison provides sufficient information to determine the improved timing. For example, it may be determined whether a previously performed comparison provides sufficient information to determine the range or the center of the range.

[0058] In some embodiments, determining the improved timing may include determining that the timing that causes the standard timing command will be closer to the center sample of the settling time 208 than the timing that causes the standard timing command. Alternatively or additionally, determining the improved timing may include determining that the timing that causes the standard timing command is within the settling time 208 and / or requires no adjustment.

[0059] Figure 4 This is a functional block diagram illustrating an example timing circuit 400 according to at least one embodiment of the present disclosure. The timing circuit 400 can be configured to obtain standard timing commands and determine improved timing. The timing circuit 400 may include a clk input 402, an adjustment module 406 (including adjustment elements 408 and 410), a sampler 416, a sampler 418, a command (CMD) input 420, a timing analysis module 428, and a CMD input 436.

[0060] An incoming clock signal (e.g., incoming clock signal 404) can be received via clk input 402. For example, Figure 1 ICLK or LCLK can be received at clk input 402.

[0061] The incoming clock signal 404 may be delayed and / or advanced at the adjustment module 406 to generate clock signal 412 and adjusted clock signal 414. Specifically, the incoming clock signal 404 may be delayed (or advanced) at the adjustment element 408 to generate clock signal 412, and the incoming clock signal 404 may be delayed (or advanced) at the adjustment element 410 to generate adjusted clock signal 414.

[0062] Each of adjustment element 408 and adjustment element 410 can be any suitable delay element, such as one or more inverter buffers and / or RC delay components. Alternatively, one or more of adjustment element 408 and adjustment element 410 can be configured to advance the clock signal.

[0063] Command signal 422 can be received at CMD input 420. For example, command signal 422 can be a command signal (e.g. Figure 1 (COM).

[0064] Sampler 416 can be configured to sample command signal 422 according to clock signal 412 to generate a standard timing command 424. Sampler 418 can be configured to sample command signal 422 according to an adjusted clock signal 414 to generate a time-adjusted command 426. Each of sampler 416 and sampler 418 may include latching circuitry and / or a decoder, for example... Figure 1 The command decoder 150. The timing circuit 400 can be configured to output standard timing command 424 as output command 434.

[0065] The timing analysis module 428 can be configured to receive a standard timing command 424 from sampler 416 and a time-adjusted command 426 from sampler 418. The timing analysis module 428 can be configured to compare the standard timing command 424 with the time-adjusted command 426. Based on comparisons between multiple examples of the standard timing command 424 and multiple examples of the time-adjusted command 426, the timing analysis module 428 can be configured to determine improved timing.

[0066] For example, timing analysis module 428 can be configured to receive a standard timing command 424 and a time-adjusted command 426 in each of a plurality of sampling periods. In each of the plurality of sampling periods, timing analysis module 428 can compare the received standard timing command 424 with the received time-adjusted command 426. Based on one or more of the comparisons in the plurality of sampling periods, timing analysis module 428 can be configured to determine improved timing. For example, based on one or more comparisons, the pass range and / or the center of the pass range can be determined.

[0067] Timing analysis module 428 can be configured to determine a time offset 432 for generating time-adjusted command 426. For example, timing analysis module 428 can be configured to determine time offset 432 and provide it to adjustment module 406. Adjustment module 406 can be configured to delay (or advance) the incoming clock signal 404 based on time offset 432 to generate adjusted clock signal 414. For example, adjustment element 410 may include multiple delay paths or tap points that can be selected based on time offset 432 to generate adjusted clock signal 414. Sampler 418 can be configured to sample command signal 422 based on adjusted clock signal 414 to generate time-adjusted command 426. Therefore, feedback from timing analysis module 428 can control the sampling of command signal 422 to obtain time-adjusted command 426.

[0068] The timing analysis module 428 can be configured to determine the time offset 432 per sampling period. For example, the timing analysis module 428 can determine different time offsets per sampling period. Furthermore, the timing analysis module 428 can be configured to store information about which time offsets have been used and / or comparison results between standard timing commands and time-adjusted commands used for the time offsets.

[0069] The timing analysis module 428 can be configured to determine the time offset 432 according to a search algorithm, such as a linear search algorithm, a binary search algorithm, and a random search algorithm. In some embodiments, the time offset 432 can be determined based on previous comparisons.

[0070] Timing analysis module 428 can be configured to determine an improved timing 430, which may be or may include a time offset for a standard timing command 424 (which may be output as output command 434). For example, timing analysis module 428 can be configured to determine the improved timing 430 and provide the improved timing 430 to adjustment module 406. Adjustment module 406 can be configured to delay (or advance) the incoming clock signal 404 according to the improved timing 430 to generate clock signal 412. For example, adjustment element 408 may include multiple delay paths or tap points, which can be selected based on the improved timing 430 to generate clock signal 412 according to the improved timing 430. Sampler 416 can be configured to sample command signal 422 according to clock signal 412 to generate a standard timing command 424 that can be output as output command 434. Therefore, timing analysis module 428 can control and / or adjust the sampling timing of command signal 422 to obtain output command 434.

[0071] Additionally, in some embodiments, the timing analysis module 428 may be configured to receive, for example, an alternative command signal 438 from a CMD input 436. The alternative command signal 438 may be a signal selected to verify a standard timing command 424 and / or a time-adjusted command 426. For example, in some cases, a comparison between the standard timing command 424 and the time-adjusted command 426 may result in a mismatch. For example, the standard timing command 424 may indicate a write command and the time-adjusted command 426 may indicate a read command. In some cases, when the standard timing command 424 and the time-adjusted command 426 do not match, it may be unclear which of the two commands is correct. The alternative command signal 438 may be provided to the timing analysis module 428 so that the timing analysis module 428 can determine which of the two commands is correct. As an example, a write data strobe signal, a read data strobe signal, a parity signal, and / or a data mask signal may be selected as the alternative command signal 438.

[0072] Additionally, in some embodiments, the timing analysis module 428 may be configured to perform pattern analysis and / or learning based on patterns. For example, the timing analysis module 428 may be configured to identify improved timing associated with command patterns. For example, the timing analysis module 428 may be configured to identify command patterns (e.g., three or more read commands in a row, a write command following a read command, a read command following a write command, and a valid command following either a read command or a valid command following a write command) and identify improved timing associated with the command patterns. For example, the timing analysis module 428 may identify a delay improvement of one time increment for subsequent sampling after three or more read commands in a row, for example, by shifting the timing of a standard timing command one time increment backward.

[0073] Figure 5 This is a flowchart illustrating an example method 500 according to at least one embodiment of the present disclosure. Method 500 may be arranged according to at least one embodiment described in this disclosure. In some embodiments, method 500 may be performed by an apparatus or system, such as... Figure 1 Memory device 100 Figure 8 Memory system 800, Figure 9 The electronic system 900 or another device or system. Some steps of method 500 may be performed by... Figure 4 The timing circuit 400 is executed. Although described as discrete blocks, the various blocks can be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation.

[0074] The clock signal can be obtained in box 502. Figure 1 The clock signal ICLK and / or the clock signal LCLK and Figure 4 The incoming clock signal 404 is an example of the clock signal of block 502.

[0075] Command signals can be obtained in box 504. Figure 1 Command signals COM and Figure 4 Command signal 422 is an example of a command signal received in box 504.

[0076] In box 506, an operation can be performed at the memory device based on a command signal. For example, the command signal may indicate a read or write command, and the operation may involve reading or writing data. The reading or writing of data may occur at the memory device, for example... Figure 1 The memory device 100.

[0077] In box 508, while an operation is in progress and without interruption, the clock signal can be adjusted to align the clock signal with the command signal. About Figure 4 400 timing circuit, about Figure 2 Timing diagram 200 illustrates an example of adjusting the clock signal to align the clock signal with the command signal.

[0078] Modifications, additions, or omissions may be made to method 500 without departing from the scope of this disclosure. For example, the operations of method 500 may be performed in different orders. Furthermore, the operations and actions outlined are for illustrative purposes only, and some operations and actions may be optional, combined into fewer operations and actions, or extended into additional operations and actions without prejudice to the essence of the disclosed embodiments.

[0079] Figure 6 This is a flowchart illustrating an example method 600 according to at least one embodiment of the present disclosure. Method 600 may be arranged according to at least one embodiment described in this disclosure. In some embodiments, method 600 may be performed by an apparatus or system, such as... Figure 1 Memory device 100 Figure 4 400 timing circuit Figure 8 Memory system 800, Figure 9 The electronic system 900 or another device or system. Although described as discrete blocks, the various blocks may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation.

[0080] In box 602, the command signal can be sampled according to the clock signal to obtain a standard timing command. Figure 1 Command signals COM and Figure 4 Command signal 422 is an instance of a command signal sampled in block 602. Figure 1 The clock signal ICLK and / or the clock signal LCLK and Figure 4Clock signal 412 is an example of the clock signal of block 602. Figure 2 Sample 234 can be an instance of one of the standard timing commands in box 602.

[0081] In box 604, the command signal can be sampled based on the adjusted clock signal to obtain a time-adjusted command. Figure 4 The adjusted clock signal 414 is an example of the adjusted clock signal of block 604. Any of sample 228, sample 230, sample 232, sample 236, sample 238 or sample 240 may be an example of one of the time-adjusted commands of block 604.

[0082] In box 606, standard timing commands and time-adjusted commands can be compared. Specifically, each of a plurality of standard timing commands can be compared with the corresponding time-adjusted command of a plurality of time-adjusted commands.

[0083] In box 608, the improved timing of the clock signal can be determined based on a comparison between the standard timing command and the time-adjusted command. The improved timing may be, or may include, causing subsequent standard timing commands to be closer to the settling time (e.g., ...). Figure 2 The timing of the center sample (208) is the settling time. The improved timing can be or may include several increments applied to the time delay of the clock signal.

[0084] In optional box 610, the clock signal can be adjusted based on the improved timing.

[0085] Modifications, additions, or omissions may be made to method 600 without departing from the scope of this disclosure. For example, the operations of method 600 may be performed in different orders. Furthermore, the operations and actions outlined are for illustrative purposes only, and some operations and actions may be optional, combined into fewer operations and actions, or extended into additional operations and actions without prejudice to the essence of the disclosed embodiments.

[0086] Figure 7 This is a flowchart illustrating an example method 700 according to at least one embodiment of the present disclosure. Method 700 may be arranged according to at least one embodiment described in this disclosure. In some embodiments, method 700 may be performed by an apparatus or system, such as... Figure 1 Memory device 100 Figure 4 400 timing circuit Figure 8 Memory system 800, Figure 9 The electronic system 900 or another device or system. Although described as discrete blocks, the various blocks may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation.

[0087] In block 702, the command signal can be sampled at the first clock edge of the clock signal to obtain a first standard timing command. Figure 1 Command signals COM and Figure 4 Command signal 422 is an example of a command signal sampled in block 702. Figure 1 The clock signal ICLK and / or the clock signal LCLK and Figure 4 Clock signal 412 is an example of the clock signal of block 702. Figure 2 Sample 234 can be an instance of the first standard timing command of box 702.

[0088] In block 704, the command signal can be sampled at the first clock edge plus or minus the first time offset to obtain the first time-adjusted command. Figure 4 The adjusted clock signal 414 is an example of the adjusted clock signal of block 704. Any of sample 228, sample 230, sample 232, sample 236, sample 238 or sample 240 may be an example of the first time-adjusted command of block 704.

[0089] In box 706, a first standard timing command can be compared with a first time-adjusted command. For example, a first standard timing command can be compared with a first time-adjusted command.

[0090] In block 708, the command signal can be sampled at the second clock edge of the clock signal to obtain a second standard timing command. Figure 2 Sample 234 can be an instance of the second standard timing command of box 708.

[0091] In block 710, the command signal can be sampled at the second clock edge plus or minus the second time offset to obtain the second time-adjusted command. Different of samples 228, 230, 232, 236, 238, or 240 may be instances of the second time-adjusted command of block 708. In some embodiments, the second time offset may be selected based on one or both of a first time offset or a comparison in block 706.

[0092] In box 712, a second standard timing command can be compared with a second time-adjusted command. For example, a second standard timing command can be compared with a second time-adjusted command.

[0093] In block 714, the improved timing of the clock signal can be determined based on a comparison of the standard timing command and the time-adjusted command (i.e., based on the comparison of blocks 706 and 712).

[0094] In optional box 716, the clock signal can be adjusted based on the improved timing.

[0095] Modifications, additions, or omissions may be made to method 700 without departing from the scope of this disclosure. For example, the operations of method 700 may be performed in different orders. For example, depending on a first time offset, block 704 may precede or follow block 702. Similarly, depending on a second time offset, block 710 may precede or follow block 708. Furthermore, the operations and actions outlined are for illustrative purposes only, and some operations and actions may be optional, combined into fewer operations and actions, or extended into additional operations and actions without prejudice to the nature of the disclosed embodiments.

[0096] Figure 8 This is a simplified block diagram illustrating an example memory system 800 implemented according to at least one embodiment of the present disclosure. The memory system 800, which may include, for example, semiconductor devices, includes a plurality of memory devices 802 and a controller 804. The controller 804 may be operatively coupled to the memory devices 802 to transfer command / address signals (e.g., from...) Figure 1 The command / address signals received by the command terminal 112 and / or address terminal 110 are transmitted to the memory device 802.

[0097] According to one or more embodiments disclosed herein, at least one of the memory devices 802 of the memory system 800 (e.g.) Figure 1 The memory device 100 and / or controller 804 may include Figure 4 One or more timing circuits 400. Alternatively, the memory system 800 may be configured to implement... Figure 5 Method 500 Figure 6 Method 600 or Figure 7 One or more of the 700 methods.

[0098] An electronic system is also disclosed. According to various embodiments, the electronic system may include a memory device comprising a plurality of memory dies, each memory die having an array of memory cells. Each memory cell may include an access transistor and a memory element operatively coupled to the access transistor.

[0099] Figure 9 This is a simplified block diagram illustrating an electronic system 900 implemented according to at least one embodiment of the present disclosure. The electronic system 900 includes at least one input device 902, which may include, for example, a keyboard, mouse, or touchscreen. The electronic system 900 further includes at least one output device 904, such as a monitor, touchscreen, or speaker. The input device 902 and the output device 904 are not necessarily separate from each other. The electronic system 900 further includes a storage device 906. The input device 902, output device 904, and storage device 906 may be coupled to a processor 908. The electronic system 900 further includes a storage device 910 coupled to the processor 908. The storage device 910 may include... Figure 8The electronic system 900 may include at least a portion of the memory system 800. The electronic system 900 may include, for example, computing, processing, industrial, or consumer products. For example, but not limited to, the electronic system 900 may include a personal computer or computer hardware component, a server or other networking hardware component, a database engine, an intrusion prevention system, a handheld device, a tablet computer, an electronic notebook, a camera, a telephone, a music player, a wireless device, a display, a chipset, a game, a vehicle, or other known systems.

[0100] Various embodiments may include a method. The method may include sampling a command signal based on a clock signal to obtain a standard timing command. The method may also include sampling the command signal based on an adjusted clock signal to obtain a time-adjusted command. The method may further include comparing the standard timing command with the time-adjusted command. The method may further include determining an improved timing of the clock signal based on the comparison between the standard timing command and the time-adjusted command.

[0101] Various embodiments may include a method for reducing timing errors in a memory device. The method may include obtaining a clock signal and obtaining a command signal. The method may also include performing an operation at the memory device based on the command signal. The method may further include adjusting the clock signal to align it with the command signal while the operation is in progress, without interrupting the operation.

[0102] Various embodiments may include a memory device. The memory device may include a first sampler configured to sample a command signal based on a clock signal to generate a standard timing command. The memory device may also include an adjustment element configured to advance or delay the clock signal to generate an adjusted clock signal. The memory device may further include a second sampler configured to sample the command signal based on the adjusted clock signal to generate a time-adjusted command. The memory device may also include a timing analysis module communicatively coupled to the first sampler, the adjustment element, and the second sampler. The timing analysis module may be configured to compare the standard timing command with the time-adjusted command. The timing analysis module may also be configured to determine an improved timing of the clock signal based on the comparison between the standard timing command and the time-adjusted command.

[0103] Various embodiments may include a system. The system may include at least one input device, at least one output device, at least one processor device operatively coupled to the input device and the output device, and at least one memory device operatively coupled to the at least one processor device. The at least one memory device may include a first sampler configured to sample a command signal according to a clock signal to generate a standard timing command. The at least one memory device may also include an adjustment element configured to advance or delay the clock signal to generate an adjusted clock signal. The at least one memory device may also include a second sampler configured to sample the command signal according to the adjusted clock signal to generate a time-adjusted command. The at least one memory device may also include a timing analysis module communicatively coupled to the first sampler, the adjustment element, and the second sampler. The timing analysis module may be configured to compare the standard timing command with the time-adjusted command. The timing analysis module may also be configured to determine an improved timing of the clock signal based on the comparison between the standard timing command and the time-adjusted command.

[0104] As is customary, the various features illustrated in the drawings may not be drawn to scale. The descriptions presented in this disclosure are not intended to be actual drawings of any particular device (e.g., apparatus, system, etc.) or method, but are merely idealized representations for describing various embodiments of this disclosure. Therefore, the dimensions of various features may be arbitrarily enlarged or reduced for clarity. Additionally, some drawings may be simplified for clarity. Thus, the drawings may not depict all components of a given device (e.g., apparatus) or all operations of a particular method.

[0105] As used herein, the terms "apparatus" or "memory device" may include, but are not limited to, devices having only memory. For example, an apparatus or memory device may include memory, a processor, and / or other components or functions. For example, an apparatus or memory device may include a system-on-a-chip (SoC).

[0106] As used herein, unless otherwise specified, the term “semiconductor” should be interpreted broadly to include microelectronic and MEMS devices (e.g., magnetic memories, optical devices, etc.) that may or may not operate using semiconductor functions.

[0107] The terms used herein and especially in the appended claims (e.g., the body of the appended claims) are generally intended to be “open-ended” terms (e.g., the term “including” should be interpreted as “including (but not limited to)”, the term “having” should be interpreted as “having at least”, the term “includes” should be interpreted as “including (but not limited to)”, etc.).

[0108] Furthermore, if a specific number of claims is intended to be introduced, this intention will be explicitly stated in the claims, and if such a statement is absent, then this intention does not exist. For example, to aid understanding, the appended claims may contain the introductory phrases “at least one” and “one or more” to introduce the claims. However, the use of such phrases should not be construed as implying that introducing a claim with the indefinite article “a” limits any particular claim containing such an introductory claim to an embodiment containing only one such claim, even if the same claim contains the introductory phrases “one or more” or “at least one” and an indefinite article such as “a” (e.g., “a” should be interpreted as meaning “at least one” or “one or more”); the same applies to the use of definite articles used to introduce the claims. As used herein, “and / or” includes any and all combinations of one or more of the associated items.

[0109] Furthermore, even if a specific number of claims is explicitly stated, it should be understood that this statement should be interpreted as meaning at least a certain number of claims (e.g., the bare statement "two claims" without other modifiers means at least two claims or two or more claims). Moreover, in instances where conventions such as "at least one of A, B, and C" or "one or more of A, B, and C" are used, this construction is generally intended to include only A, only B, only C, both A and B, both A and C, both B and C, or both A, B, and C, etc. For example, the use of the term "and / or" is intended to be interpreted in this manner.

[0110] Furthermore, any transition words or phrases presenting two or more alternatives, whether in the detailed description, claims, or drawings, should be understood to imply the possibility of including one, any one, or both of them. For example, the phrase "A or B" should be understood to imply the possibility of including "A" or "B" or "A and B".

[0111] Furthermore, the use of terms such as "first," "second," and "third" in this document does not necessarily indicate a specific order or number of elements. Generally, the terms "first," "second," and "third" serve as general identifiers to distinguish different elements. Unless otherwise stated, these terms should not be interpreted as indicating a specific order. Similarly, unless otherwise stated, these terms should not be interpreted as indicating a specific number of elements.

[0112] Additional non-limiting embodiments of this disclosure include:

[0113] Example 1: A method comprising: sampling the command signal according to a clock signal to obtain a standard timing command; sampling the command signal according to an adjusted clock signal to obtain a time-adjusted command; comparing the standard timing command with the time-adjusted command; and determining an improved timing of the clock signal based on the comparison between the standard timing command and the time-adjusted command.

[0114] Example 2: According to the method described in Example 1, the method further includes advancing or delaying the clock signal by a time offset to obtain the adjusted clock signal.

[0115] Example 3: The method according to any one of Examples 1 and 2 further includes selecting the time offset according to a search algorithm.

[0116] Example 4: The method according to any one of Examples 1 to 3, wherein sampling the command signal according to the adjusted clock signal includes: sampling the command signal at a first time to obtain a first time-adjusted command, the first time being at a first clock edge of the clock signal plus or minus a first time offset; and sampling the command signal at a second time, the second time being at a second clock edge of the clock signal plus or minus a second time offset.

[0117] Example 5: The method according to any one of Examples 1 to 4 further includes selecting the second time offset based on a search algorithm and a comparison between the first standard timing command and the first time-adjusted command in the standard timing command.

[0118] Example 6: The method according to any one of Examples 1 to 5, wherein selecting the second time offset based on the search algorithm includes selecting the second time offset based on one of the following: a linear search algorithm, a binary search algorithm, and a random search algorithm.

[0119] Example 7: The method according to any one of Examples 1 to 6, wherein sampling the command signal according to the clock signal includes: sampling the command signal at a first clock edge of the clock signal to obtain a first standard timing command; and sampling the command signal at a second clock edge of the clock signal to obtain a second standard timing command; wherein sampling the command signal according to the adjusted clock signal includes: sampling the command signal at the first clock edge plus or minus a first time offset to obtain a first time-adjusted command; and sampling the command signal at the second clock edge plus or minus a second time offset to obtain a second time-adjusted command; and wherein comparing the standard timing command and the time-adjusted command includes: comparing the first standard timing command with the first time-adjusted command; and comparing the second standard timing command with the second time-adjusted command.

[0120] Example 8: The method according to any one of Examples 1 to 7 further includes determining, based on the comparison between the standard timing command and the time-adjusted command, the passing range of the time offset to which the time-adjusted command and the standard timing command are matched.

[0121] Example 9: The method according to any one of Examples 1 to 8 further includes: storing a first time offset of the adjusted clock signal for which the time adjustment command matches the standard timing command; and storing a second time offset of the adjusted clock signal for which the time adjustment command does not match the standard timing command, wherein determining the pass range is further based on the first time offset and the second time offset.

[0122] Example 10: The method according to any one of Examples 1 to 9, wherein the improved timing is based on the pass range.

[0123] Example 11: The method according to any one of Examples 1 to 10, wherein the improved timing is at the center of the passing range.

[0124] Example 12: The method according to any one of Examples 1 to 11 further includes adjusting the clock signal based on the improved timing.

[0125] Example 13: The method according to any one of Examples 1 to 12 further includes: in response to a mismatch between the standard timing command in the standard timing command and the corresponding time-adjusted command in the time-adjusted command, comparing one or more of the standard timing command and the corresponding time-adjusted command with another command signal to determine which of the standard timing command and the time-adjusted command corresponds to the other command signal.

[0126] Example 14: A method for reducing timing errors in a memory device, the method comprising: obtaining a clock signal; obtaining a command signal; performing an operation at the memory device based on the command signal; and, while the operation is in progress, adjusting the clock signal to align the clock signal with the command signal without interrupting the operation.

[0127] Example 15: The method according to Example 14 further includes: sampling the command signal according to the clock signal to obtain a standard timing command; sampling the command signal according to the adjusted clock signal to obtain a time-adjusted command; comparing the standard timing command with the time-adjusted command; and determining an improved timing of the clock signal based on the comparison of the standard timing command and the time-adjusted command, wherein adjusting the clock signal includes adjusting the clock signal according to the improved timing.

[0128] Example 16: The method according to any of Examples 14 and 15, wherein adjusting the clock signal further includes repeatedly adjusting the clock signal.

[0129] Example 17: A memory device comprising: a first sampler configured to sample the command signal according to the clock signal to generate a standard timing command; an adjustment element configured to advance or delay the clock signal to generate an adjusted clock signal; a second sampler configured to sample the command signal according to the adjusted clock signal to generate a time-adjusted command; and a timing analysis module communicatively coupled to the first sampler, the adjustment element, and the second sampler, the timing analysis module being configured to: compare the standard timing command with the time-adjusted command; and determine an improved timing of the clock signal based on the comparison between the standard timing command and the time-adjusted command.

[0130] Example 18: The memory device according to Example 17, wherein the timing analysis module is further configured to determine the time offset of the adjusted clock signal based on a search algorithm and the comparison between the standard timing command and the time-adjusted command, and wherein the adjustment element is configured to generate the adjusted clock signal based on the time offset.

[0131] Example 19: A memory device according to any of Examples 17 and 18, further comprising an improved adjustment element configured to advance or delay the clock signal based on the improved timing.

[0132] Example 20: A memory device according to any of Examples 17 to 19, wherein the timing analysis module is further configured to compare one or more of the standard timing command and the corresponding time-adjusted command with another command signal in response to a mismatch between the standard timing command in the standard timing command and the corresponding time-adjusted command in the time-adjusted command to determine which of the standard timing command and the time-adjusted command is correct.

[0133] Example 21: A system comprising: at least one input device; at least one output device; at least one processor device operatively coupled to the input device and the output device; and at least one memory device operatively coupled to the at least one processor device, the at least one memory device comprising: a first sampler configured to sample the command signal according to a clock signal to generate a standard timing command; an adjustment element configured to advance or delay the clock signal to generate an adjusted clock signal; a second sampler configured to sample the command signal according to the adjusted clock signal to generate a time-adjusted command; and a timing analysis module communicatively coupled to the first sampler, the adjustment element, and the second sampler, the timing analysis module being configured to: compare the standard timing command with the time-adjusted command; and determine an improved timing of the clock signal based on the comparison of the standard timing command and the time-adjusted command.

[0134] The embodiments of this disclosure described above and illustrated in the accompanying drawings do not limit the scope of this disclosure, which is covered by the appended claims and their legal equivalents. Any equivalent embodiments are within the scope of this disclosure. In fact, in addition to what is shown and described herein, various modifications to this disclosure, such as alternative useful combinations of the described elements, will become apparent to those skilled in the art from the specific embodiments. Such modifications and embodiments also fall within the scope of the appended claims and their equivalents.

Claims

1. A method comprising: The command signal is sampled at the first clock edge of the clock signal to obtain the first standard timing command; The command signal is sampled at the second clock edge of the clock signal to obtain a second standard timing command; The command signal is sampled at the first time offset plus or minus the first clock edge to obtain a first time-adjusted command; The command signal is sampled at the edge of the second clock by adding or subtracting the second time offset to obtain the second time-adjusted command; Compare the first standard timing command with the first time-adjusted command; Compare the second standard timing command with the second time-adjusted command; and The improved timing of the clock signal is determined by comparing the first standard timing command with the first time-adjusted command and by comparing the second standard timing command with the second time-adjusted command.

2. The method of claim 1, further comprising selecting the second time offset according to a search algorithm.

3. The method of claim 1, further comprising selecting the second time offset based on a search algorithm and the comparison between the first standard timing command and the first time-adjusted command.

4. The method of claim 3, wherein selecting the second time offset based on the search algorithm includes selecting the second time offset based on one of the following: a linear search algorithm, a binary search algorithm, and a random search algorithm.

5. The method of claim 1, further comprising: The command signal is sampled according to the clock signal to obtain additional standard timing commands; The command signal is sampled according to the adjusted clock signal to obtain an additional time-adjusted command; Compare the additional standard timing command with the additional time-adjusted command; as well as The passage range for the time offset targeted by the comparison between the additional standard timing command and the additional time-adjusted command is determined based on the comparison.

6. The method of claim 5, further comprising: Store the first time offset of the adjusted clock signal to which the additional time-adjusted command is matched with the additional standard timing command; and Store the second time offset of the adjusted clock signal for which the additional time-adjusted command does not match the additional standard timing command; The range is further determined based on the first time offset and the second time offset.

7. The method of claim 5, wherein the improved timing is determined based on the range.

8. The method of claim 5, wherein the improved timing is determined at the center of the range.

9. The method of claim 1, further comprising adjusting the clock signal based on the improved timing.

10. The method of claim 1, further comprising, in response to a mismatch between a standard timing command in the standard timing command and a corresponding time adjustment command in the time adjustment command, comparing one or more of the standard timing command and the corresponding time adjustment command with another command signal to determine which of the standard timing command and the time adjustment command corresponds to the other command signal.

11. A method for reducing timing errors in a memory device, the method comprising: Obtain the clock signal; Receive command signal; The command signal is sampled at the first clock edge of the clock signal to obtain a first standard timing command; The command signal is sampled at the second clock edge of the clock signal to obtain a second standard timing command; The command signal is sampled at the first time offset plus or minus the first clock edge to obtain a first time-adjusted command; The command signal is sampled at the edge of the second clock by adding or subtracting the second time offset to obtain the second time-adjusted command; Compare the first standard timing command with the first time-adjusted command; Compare the second standard timing command with the second time-adjusted command; The improved timing of the clock signal is determined by comparing the first standard timing command with the first time-adjusted command and by comparing the second standard timing command with the second time-adjusted command. An operation is performed at the memory device based on the command signal; and While the operation is in progress, without interrupting the operation, the clock signal is adjusted based on the improved timing to align the clock signal with the command signal.

12. The method of claim 11, wherein adjusting the clock signal further comprises repeatedly adjusting the clock signal.

13. A memory device comprising: A first sampler is configured to sample a command signal according to a clock signal to generate a standard timing command, the standard timing command including a first standard timing command corresponding to a first clock edge of the clock signal and a second standard timing command corresponding to a second clock edge of the clock signal; An adjustment element, configured to advance or delay the clock signal to generate an adjusted clock signal; A second sampler is configured to sample the command signal according to the adjusted clock signal to generate a time-adjusted command, the time-adjusted command including a first time-adjusted command corresponding to adding or subtracting a first time offset at the first clock edge and a second time-adjusted command corresponding to adding or subtracting a second time offset at the second clock edge. A timing analysis module, communicatively coupled to the first sampler, the adjustment element, and the second sampler, is configured to: The standard timing command, which includes the first standard timing command and the second standard timing command, is compared with the time-adjusted command, which includes the first time-adjusted command and the second time-adjusted command. and The improved timing of the clock signal is determined based on the comparison between the standard timing command, which includes the first standard timing command and the second standard timing command, and the time-adjusted command, which includes the first time-adjusted command and the second time-adjusted command.

14. The memory device of claim 13, wherein the timing analysis module is further configured to determine a time offset of the adjusted clock signal, including the second time offset, based on a search algorithm and the comparison between the standard timing command and the time-adjusted command, and wherein the adjustment element is configured to generate the adjusted clock signal based on the time offset.

15. The memory device of claim 13, further comprising an improved adjustment element configured to advance or delay the clock signal based on the improved timing.

16. The memory device of claim 13, wherein the timing analysis module is further configured to compare one or more of the standard timing command and the corresponding time adjustment command with another command signal in response to a mismatch between the standard timing command in the standard timing command and the corresponding time adjustment command in the time adjustment command to determine which of the standard timing command and the time adjustment command is correct.

17. A system comprising: At least one input device; At least one output device; At least one processor device operatively coupled to the input device and the output device; and At least one memory device operatively coupled to the at least one processor device, the at least one memory device comprising: A first sampler is configured to sample a command signal according to a clock signal to generate a standard timing command, the standard timing command including a first standard timing command corresponding to a first time and a second standard timing command corresponding to a second time. An adjustment element, configured to advance or delay the clock signal to generate an adjusted clock signal; A second sampler is configured to sample the command signal according to the adjusted clock signal to generate a time-adjusted command, the time-adjusted command including a first time-adjusted command corresponding to the first time plus or minus a first time offset and a second time-adjusted command corresponding to the second time plus or minus a second time offset. A timing analysis module, communicatively coupled to the first sampler, the adjustment element, and the second sampler, is configured to: Compare the standard timing command, which includes the first standard timing command and the second standard timing command, with the time-adjusted command, which includes the first time-adjusted command and the second time-adjusted command; and The improved timing of the clock signal is determined based on the comparison between the standard timing command, which includes the first standard timing command and the second standard timing command, and the time-adjusted command, which includes the first time-adjusted command and the second time-adjusted command.

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