Composite layer circuit element and method for manufacturing the same

Abstract

Embodiments of the present disclosure provide a composite layer circuit element and a manufacturing method thereof. The manufacturing method of the composite layer circuit element includes the following steps. A carrier plate is provided. A first dielectric layer is formed on the carrier plate, and the first dielectric layer is patterned. The carrier plate with the first dielectric layer is disposed on a first curved mold, and the first dielectric layer is solidified. A second dielectric layer is formed on the first dielectric layer. The second dielectric layer is patterned. The carrier plate with the first dielectric layer and the second dielectric layer is disposed on a second curved mold, and the second dielectric layer is solidified. The thickness of the protruding part of the first curved mold is less than the thickness of the protruding part of the second curved mold.

Description

[0001] This disclosure is a divisional application of the invention patent application filed on July 23, 2021, with application number 202110835017.9 and invention title "Composite Layer Circuit Element and Manufacturing Method Thereof". Technical Field

[0002] The embodiments disclosed herein relate to a circuit element, and more particularly to a composite layer circuit element and a method for fabricating the same. Background Technology

[0003] With the increasing application of electronic devices, the manufacturing yield of electronic devices has become a concern. Existing methods for manufacturing composite layer circuit components are prone to warping during the process due to the difference in thermal expansion coefficients between the substrate and the individual layers within the composite layer circuit component. This warping can negatively impact the structure and quality of electronic devices. Therefore, a manufacturing process for electronic devices that can mitigate these problems is needed. Summary of the Invention

[0004] According to embodiments disclosed herein, a method for fabricating a composite layer circuit element includes the following steps: Providing a carrier board. Forming a first dielectric layer on the carrier board. Patterning the first dielectric layer. Placing the carrier board with the first dielectric layer formed on a first curved mold and curing the first dielectric layer. Forming a second dielectric layer on the first dielectric layer. Patterning the second dielectric layer. Placing the carrier board with both the first and second dielectric layers formed on a second curved mold and curing the second dielectric layer. The thickness of the protrusions in the first curved mold is less than the thickness of the protrusions in the second curved mold.

[0005] According to embodiments disclosed herein, a composite layer circuit element includes a first dielectric layer, a first circuit layer disposed on the first dielectric layer, and a second dielectric layer disposed on the first circuit layer. The thickness of the first dielectric layer is greater than the thickness of the second dielectric layer. Attached Figure Description

[0006] Figure 1 This is a flowchart illustrating a method for fabricating a composite layer circuit element according to an embodiment of the present disclosure;

[0007] Figures 2A to 2G This is a cross-sectional schematic diagram of the fabrication process of a composite layer circuit element according to an embodiment of the present disclosure;

[0008] Figure 2H This is a schematic cross-sectional view of an electronic device including composite layer circuit elements according to an embodiment of this disclosure. Detailed Implementation

[0009] This disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that, for ease of understanding and for the sake of brevity, many of the drawings in this disclosure depict only a portion of the electronic device, and certain components in the drawings are not drawn to scale. Furthermore, the number and dimensions of the components in the drawings are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0010] Throughout this specification and the appended claims, certain terms are used to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same components. This document is not intended to distinguish between components that function identically but have different names. In the following specification and claims, words such as “comprising,” “containing,” and “having” are open-ended terms and should therefore be interpreted as “containing but not limited to…”. Thus, when the terms “comprising,” “containing,” and / or “having” are used in the description of this disclosure, they specify the presence of the corresponding feature, area, step, operation, and / or component, but do not exclude the presence of one or more of the corresponding feature, area, step, operation, and / or component.

[0011] The directional terms used herein, such as "up," "down," "front," "back," "left," and "right," are for reference only when referring to the accompanying drawings. Therefore, the directional terms used are illustrative and not intended to limit this disclosure. In the accompanying drawings, each figure illustrates general features of the methods, structures, and / or materials used in specific embodiments. However, these figures should not be construed as defining or limiting the scope or nature covered by these embodiments. For example, for clarity, the relative dimensions, thicknesses, and locations of various films, regions, and / or structures may be reduced or enlarged.

[0012] It should be understood that when an element or membrane is referred to as being "connected to" another element or membrane, it can be directly connected to this other element or membrane, or there can be an interposed element or membrane between them. When an element is referred to as being "directly connected to" another element or membrane, there is no interposed element or membrane between them. Furthermore, when a component is referred to as being "coupled to another component (or a variant thereof)," it can be directly or electrically connected to this other component, or indirectly or electrically connected to this other component through one or more components.

[0013] In this disclosure, length and width can be measured using an optical microscope, and thickness can be measured from cross-sectional images using an electron microscope, but these methods are not limited to these. Furthermore, any two values ​​or directions used for comparison may contain a certain degree of error.

[0014] The terms “approximately,” “equal to,” “same,” “substantially,” or “roughly” are generally interpreted as being within 20% of a given value or range, or as being within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range.

[0015] The term "between value A and value B" is interpreted as including value A and value B, or at least one of value A and value B, as well as other values ​​between value A and value B.

[0016] In this disclosure, a structure (or layer, component, substrate) located on top of another structure (or layer, element, substrate) can refer to the two structures being adjacent and directly connected, or to the two structures being adjacent but not directly connected. A non-direct connection means that there is at least one intermediary structure (or intermediary layer, intermediary component, intermediary substrate, intermediary spacer) between the two structures. The lower surface of one structure is adjacent to or directly connected to the upper surface of the intermediary structure, and the upper surface of the other structure is adjacent to or directly connected to the lower surface of the intermediary structure. The intermediary structure can be composed of a single-layer or multi-layer solid structure or a non-solid structure, without limitation. In this disclosure, when a structure is disposed "on" other structures, it may mean that the structure is "directly" on other structures, or that the structure is "indirectly" on other structures, meaning that at least one structure is sandwiched between the structure and other structures.

[0017] The terms "first," "second," etc., used in this disclosure may be used to describe various elements, components, regions, layers, and / or parts, but these elements, components, regions, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, the terms "first element," "component," "region," "layer," or "part" discussed below are used to distinguish them from "second element," "component," "region," "layer," or "part," and are not used to define a sequence or specific element, component, region, layer, and / or part.

[0018] The electronic device, through the composite layer electronic components of the embodiments disclosed herein, can achieve good electronic effects. The electronic device may include, but is not limited to, a display device, a packaging device, a backlight device, an antenna device, a sensing device, or a splicing device. The electronic device may be bendable or flexible. The display device may be a non-self-emissive display device or a self-emissive display device. The antenna device may be a liquid crystal type antenna device or a non-liquid crystal type antenna device. The sensing device may be a sensing device that senses capacitance, light, heat, or ultrasound, but is not limited to these. The electronic components may include passive and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. The diode may include a light-emitting diode or a photodiode. Light-emitting diodes may include, for example, organic light-emitting diodes (OLEDs), mini LEDs, micro LEDs, or quantum dot LEDs, but are not limited to these. The splicing device may be, for example, a display splicing device or an antenna splicing device, but is not limited to these. It should be noted that the electronic device can be any combination of the foregoing, but is not limited to these. The following will use composite layer electronic components as electronic devices or splicing devices to illustrate the contents of this disclosure, but this disclosure is not limited thereto.

[0019] In this disclosure, the various embodiments described below can be used in combination without departing from the spirit and scope of this disclosure. For example, some features of one embodiment can be combined with some features of another embodiment to form another embodiment.

[0020] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0021] Figure 1 This is a flowchart illustrating a method for fabricating a composite layer circuit element according to an embodiment of the present disclosure. Figures 2A to 2G This is a cross-sectional schematic diagram illustrating the fabrication process of a composite layer circuit element according to an embodiment of this disclosure. The drawings are for clarity and ease of explanation. Figures 2A to 2G Several components are omitted from the diagram. Please refer to the documentation first. Figure 1In one embodiment of this disclosure, the fabrication method S10 of the composite layer circuit element 100 includes the following steps: First, in step S110, a carrier board 300 is provided. Next, in step S120, a first dielectric layer 110 is formed on the carrier board 300. In step S130, the first dielectric layer 110 is patterned. In step S140, the carrier board on which the first dielectric layer 110 is formed is placed on a first curved mold 200 and the first dielectric layer 110 is cured, wherein the first curved mold 200 has a protrusion 210 with a thickness H1. In step S150, a second dielectric layer 120 is formed on the first dielectric layer 110. In step S160, the second dielectric layer 120 is patterned. In step S170, a carrier plate 300 having a first dielectric layer 110 and a second dielectric layer 120 formed thereon is placed on a second curved mold 200A, and the second dielectric layer 120 is cured. The second curved mold 200A has a protrusion 210A with a thickness H2. In the step of curing the first dielectric layer 110 or the second dielectric layer 120, for example, a heating process is used to cure the first dielectric layer 110 or the second dielectric layer 120 to make its shape more rigid; details will be explained later. Since the coefficient of thermal expansion of the carrier plate 300 is different from that of the dielectric layer, in the step of curing the first dielectric layer 110 or the second dielectric layer 120, the carrier plate 300 may experience a warping force, causing the carrier plate 300 to warp towards the first dielectric layer 110 or the second dielectric layer 120. For example, the carrier plate may have an inner surface S1 and an outer surface S2, with the inner surface S1 being closer to the first dielectric layer 110 or the second dielectric layer 120 than the outer surface S2. The statement that "the carrier plate 300 may warp towards the first dielectric layer 110 or the second dielectric layer 120" means that the inner surface S1 is compressed due to warping, causing the inner surface S1 to project onto the plane formed by the X-axis and Y-axis (e.g., ...). Figure 2A The area of ​​the outer surface S2 projected onto the plane formed by the X and Y axes (e.g.) will be smaller than that of the outer surface S2 projected onto the plane formed by the X and Y axes (e.g.) Figure 2A The area of ​​) in the top-down direction (e.g. Figure 2A The Z-axis is perpendicular to the X-axis and Y-axis, respectively.

[0022] In one embodiment of this disclosure, by providing a first curved mold 200 or a second curved mold 200A during the step of curing the first dielectric layer 110 and / or the second dielectric layer 120, the protrusion 210 of the first curved mold 200 or the protrusion 210A of the second curved mold 200A can form a bending force on the carrier plate 300. This bending force can, for example, cause the carrier plate 300 to bend along the shape of the first curved mold 200 or the second curved mold 200A (details of forming the bending force will be explained later), and this bending force is, for example, generally opposite to the direction of the warping force of the carrier plate 300, thereby reducing the warping problem.

[0023] The following will be based on Figures 2A to 2G The manufacturing process shown is used to briefly illustrate the method for manufacturing the composite layer circuit element 100. The method disclosed herein for manufacturing the composite layer circuit element 100 enables the composite layer circuit element 100 to have good structural strength or quality.

[0024] Please refer to Figure 2A First, in step S110, a carrier plate 300 is provided. In some embodiments, the material of the carrier plate 300 may include organic or inorganic materials, such as glass, quartz, sapphire, ceramic, stainless steel, silicon wafer, molding compound (e.g., resin, epoxy resin, silicone compound), other suitable substrate materials, or combinations thereof, but is not limited thereto. In some embodiments, the thickness T of the carrier plate 300 may be between 0.5 mm and 1.5 mm (0.5 mm ≤ thickness T ≤ 1.5 mm) or between 0.7 mm and 1.3 mm (0.7 mm ≤ thickness T ≤ 1.3 mm), but is not limited thereto. Thickness T may be defined as the average thickness of any three regions of the carrier plate 300 measured in the normal direction of the carrier plate 300. In some embodiments, when the carrier plate 300 is generally rectangular, the length L of the side of the carrier plate 300 may be between 600 mm and 800 mm (600 mm ≤ length L ≤ 800 mm) or between 650 mm and 750 mm (650 mm ≤ length L ≤ 750 mm), but is not limited thereto. For example, when the carrier plate 300 is generally square, the length L may be defined as the length of the side of the carrier plate 300, while when the carrier plate 300 is of other shapes, a minimum rectangle may be defined to frame the carrier plate 300, and the length L may be, for example, the length of the longer side of the minimum rectangle. In some embodiments, the coefficient of thermal expansion (CTE) of the carrier plate 300 is between 2 ppm / ℃ and 10 ppm / ℃ (2 ppm / ℃ ≦ coefficient of thermal expansion ≦ 10 ppm / ℃) or between 4 ppm / ℃ and 8 ppm / ℃ (4 ppm / ℃ ≦ coefficient of thermal expansion ≦ 8 ppm / ℃), but is not limited thereto.

[0025] In some embodiments, a release layer 310 may be selectively provided on the carrier plate 300.

[0026] Next, a first seed layer 330 may be sequentially formed on the release layer 310. The release layer 310 may be removed in a subsequent step. In some embodiments, the release layer 310 may be an epoxy resin-based heat-releasing material that loses its adhesive properties when heated, such as a light-to-heat-conversion (LTHC) release coating, but is not limited thereto. In other embodiments, the release layer 310 may include an ultraviolet (UV) adhesive, and the release layer 310 may be a UV adhesive that loses its adhesive properties when exposed to ultraviolet (UV) light, but is not limited thereto.

[0027] In some embodiments, the first seed layer 330 is formed by physical vapor deposition, chemical vapor deposition, or electroplating. The material of the first seed layer 330 includes titanium, copper, or other suitable materials, but is not limited thereto. In some embodiments, the first seed layer 330 comprises a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the first seed layer 330 may include a titanium layer and a copper layer situated on the titanium layer, but is not limited thereto.

[0028] Then, a conductive material layer (not shown) is formed on the first seed layer 330. This conductive material layer can be formed, for example, by electroplating or other suitable methods. Next, the conductive material layer is patterned. Specifically, a patterned photoresist is formed on the conductive material layer to form a mask. Then, the conductive material exposed by the mask is etched to form a plurality of conductive structures 111 on the first seed layer 330. It should be noted here that... Figure 2A Two conductive structures 111 are shown only schematically; however, the embodiments disclosed herein do not limit the number and / or shape of the conductive structures 111. Depending on design requirements, the number of conductive structures 111 may be less than or more than two.

[0029] In some embodiments, the material of the conductive material layer (or conductive structure 111) includes, for example, a metal or a metal alloy. For instance, the material of the conductive material layer (or conductive structure 111) may include copper, titanium, tungsten, aluminum, other suitable materials, or combinations thereof, but is not limited thereto. In some embodiments, the conductive structure 111 may be formed by stacking a single layer of conductive material or multiple layers of conductive material. In some embodiments, the thickness of the conductive structure 111 is approximately between 3 micrometers and 20 micrometers (3 μm ≤ thickness ≤ 20 μm) or between 4 micrometers and 18 micrometers (4 μm ≤ thickness ≤ 18 μm), but is not limited thereto.

[0030] Please refer to Figure 1 and Figure 2BIn step S120, a first dielectric layer 110 is formed on the carrier plate 300, and in step S130, the first dielectric layer 110 is patterned. The cross-sectional structure after step S130 is as follows: Figure 2B As shown. Specifically, the first dielectric layer 110 can be disposed on the first seed layer 330 and cover the conductive structure 111, and the first dielectric layer 110 is subsequently patterned. The step of patterning the first dielectric layer 110 includes "removing a portion of the first dielectric layer 110 corresponding to the conductive structure 111 to expose the surface of the conductive structure 111", such as Figure 2B As shown. In detail, the method of patterning the first dielectric layer 110 may include forming a patterned mask on the first dielectric layer 110 and then etching the first dielectric layer 110 (e.g., wet etching or dry etching). The patterned first dielectric layer 110 may have a plurality of first openings O1, which may, for example, expose conductive structures 111. In other words, in the normal direction of the substrate 300, the first openings O1 may overlap with the conductive structures 111.

[0031] In some embodiments, the first dielectric layer 110 may have a thickness T1, which may be defined as the maximum thickness of the first dielectric layer 110 in a cross-section along the normal direction of the carrier plate 300. In some embodiments, the thickness T1 of the first dielectric layer 110 is, for example, between 5 micrometers and 25 micrometers (5 μm ≤ thickness T1 ≤ 25 μm) or between 10 micrometers and 20 micrometers (10 μm ≤ thickness T1 ≤ 20 μm), but is not limited thereto.

[0032] In some embodiments, the material of the first dielectric layer 110 may include an organic insulating layer or an inorganic insulating layer, and its material may include photosensitive polyimide materials, organic polymer materials, photoresist materials, or other suitable materials. In some embodiments, the first dielectric layer 110 may include polyimide (PI), polyamide, polybenzoxazole (PBO), acrylic, siloxane, ajinomoto build-up layer (ABF), cyclo olefin polymer, other suitable materials, or combinations of the above materials, but is not limited thereto.

[0033] In some embodiments, the coefficient of thermal expansion of the first dielectric layer 110 is between 3 ppm / ℃ and 80 ppm / ℃ (3 ppm / ℃ ≤ coefficient of thermal expansion ≤ 80 ppm / ℃), between 10 ppm / ℃ and 70 ppm / ℃ (10 ppm / ℃ ≤ coefficient of thermal expansion ≤ 70 ppm / ℃), or between 15 ppm / ℃ and 65 ppm / ℃ (15 ppm / ℃ ≤ coefficient of thermal expansion ≤ 65 ppm / ℃), but is not limited thereto.

[0034] Please refer to Figure 1 and Figure 2C Next, in step S140, a carrier plate 300 with the first dielectric layer 110 formed thereon is placed on the first curved mold 200, and the first dielectric layer 110 is cured. The first curved mold 200 has a protrusion 210 with a thickness H1. In some embodiments, the coefficient of thermal expansion of the first curved mold 200 may be similar to, for example, that of the carrier plate 300, but is not limited thereto. In some embodiments, the coefficient of thermal expansion of the first curved mold 200 may be less than or equal to 10 ppm / ℃ or less than or equal to 8 ppm / ℃, but is not limited thereto. In some embodiments, the hardness of the first curved mold 200 may be, for example, less than the hardness of the carrier plate 300 to reduce the risk of the carrier plate 300 being scratched, but is not limited thereto.

[0035] In some embodiments, the first curved surface mold 200 may have a base plate 211 and a protrusion 210, the protrusion 210 being connected to the base plate 211. In some embodiments, the material of the base plate 211 and the material of the protrusion 210 may be the same or different. In some embodiments, the base plate 211 and the protrusion 210 may be integrally formed, for example.

[0036] In some embodiments, the surface 201 of the base plate 211 may, for example, be connected to the curved surface 205 of the protrusion 210.

[0037] The curved surface 205 can contact the carrier plate 300. In some embodiments, the curved surface 205 has a vertex 203 located at the highest point of the curved surface 205. In some embodiments, the protrusion 210 of the first curved surface mold 200 has a thickness H1, which can be defined as the distance between the vertex 203 and the upper surface 201 in the normal direction of the base plate 211 (the direction of the Z-axis in the figure). The thickness H1 of the protrusion 210 of the first curved surface mold 200 ranges from 0.1 mm to 0.4 mm (0.1 mm ≤ thickness H1 ≤ 0.4 mm) or from 0.15 mm to 0.35 mm (0.15 mm ≤ thickness H1 ≤ 0.35 mm), but is not limited thereto.

[0038] In some embodiments, a carrier plate 300 having a first dielectric layer 110 formed thereon may be disposed on a first curved mold 200, and the carrier plate 300 may be adjacent to or in contact with a protrusion 210 of the first curved mold 200. In some embodiments, the protrusion 210 of the first curved mold 200 may have, for example, a plurality of holes (not shown). In some embodiments, during the step of curing the first dielectric layer 110, a vacuum fixture (not shown) may, for example, vacuum-adsorb the carrier plate 300 through these holes, so that the carrier plate 300 is adsorbed onto the curved surface 205 of the protrusion 210, thereby forming a bending force on the carrier plate 300. As described above, the first curved mold 200 may, for example, generate a bending force on the carrier plate 300 opposite to the warping direction, so that the carrier plate 300 may be bent substantially along the protrusion 120 of the first curved mold 200, thereby reducing the warping problem of the composite layer circuit element 100. The method for fabricating the composite layer circuit element 100 disclosed herein can enable the composite layer circuit element 100 to have good structural strength or quality.

[0039] In some embodiments, during the step of curing the first dielectric layer 110, a portion of the carrier plate 300 may contact the first curved mold 200 (e.g., the protrusion 210), while another portion of the carrier plate 300 may not contact the first curved mold 200, thus creating a gap SP between the carrier plate 300 and the portion of the protrusion 210 of the first curved mold 200. In some embodiments, a plurality of holes (not shown) may be distributed, for example, only in the portion of the protrusion 210, and the holes may be distributed, for example, only in the central portion of the portion of the protrusion 210, so that the other portion of the carrier plate 300 cannot be adsorbed onto the protrusion 210. Therefore, a gap SP may be created between the carrier plate 300 and the portion of the protrusion 210 of the first curved mold 200, but this is not a limitation. Through the above design, in the step of curing the first dielectric layer 110, the risk of excessive bending force caused by the first curved mold 200 being completely adsorbed onto the protrusion 210 of the first curved mold 200, which may lead to the cracking of the carrier plate 300, can be reduced, but it is not limited to this.

[0040] In some embodiments, the step of curing the first dielectric layer 110 includes a baking process for the first dielectric layer 110. The baking process includes heating the first dielectric layer 110 in an environment with an oxygen concentration of less than 100 ppm for approximately 3 hours or more, at a temperature, for example, between 180°C and 350°C (180°C ≤ temperature ≤ 350°C), but not limited thereto. In some embodiments, the first dielectric layer 110 may be baked, for example, in a vacuum oven. In other embodiments, the first dielectric layer 110 may be baked in a nitrogen (N2) oven, but this is not a limitation.

[0041] Please refer to Figure 1 and Figure 2DSimilarly, a second seed layer 113 is then formed on the upper surface 110T of the first dielectric layer 110. The second seed layer 113 may, for example, partially fill the opening O1 of the first dielectric layer 110. The material or formation method of the second seed layer 113 may be similar to that of the first seed layer 330. Next, a conductive material layer is disposed on the second seed layer 113, and then a patterned photoresist is formed on the conductive material layer to form a mask. The conductive material and the second seed layer 113 exposed by the mask are etched to pattern the conductive material layer and the second seed layer 113, and the patterned conductive material layer forms a plurality of conductive structures 116.

[0042] Please refer to Figure 1 and Figure 2E Next, in step S150, a second dielectric layer 120 is formed on the first dielectric layer 110. Specifically, a first circuit layer (including the aforementioned conductive structure 116) is disposed on the first dielectric layer 110, and the second dielectric layer 120 is disposed on the first circuit layer (including the aforementioned conductive structure 116). In other words, the second dielectric layer 120 may, for example, be disposed on the upper surface 110T of the first dielectric layer 110 and on the conductive structure 116. In some embodiments, the second dielectric layer 120 has a thickness T2. Thickness T2 can be defined as the maximum thickness of the second dielectric layer 120 in a cross-section along the normal direction of the carrier plate 300. In some embodiments, the thickness T2 of the second dielectric layer 120 is, for example, between 5 micrometers and 25 micrometers (5 μm ≤ thickness T2 ≤ 25 μm) or between 8 micrometers and 20 micrometers (8 μm ≤ thickness T2 ≤ 20 μm), but is not limited thereto.

[0043] In some embodiments, the thickness T1 of the first dielectric layer 110 may be greater than the thickness T2 of the second dielectric layer 120. In some embodiments, the thickness ratio of the first dielectric layer 110 thickness T1 to the second dielectric layer 120 thickness T2 may be between 1.5 and 10 (1.5 ≤ T1 / T2 ≤ 10) or between 2 and 5 (2 ≤ T1 / T2 ≤ 5), but is not limited thereto. Since the more dielectric layers stacked in the composite layer circuit element 100, the greater the degree of warpage may be, the severity of warpage can be reduced by designing the thickness of the Nth dielectric layer to be thinner than the thickness of the Mth dielectric layer, where M is less than N. For example, by making the thickness T2 of the second dielectric layer 120 disposed on the first dielectric layer 110 less than the thickness T1 of the first dielectric layer 110, the degree of warpage of the composite layer circuit element 100 stack can be reduced.

[0044] In some embodiments, the material of the second dielectric layer 120 may be the same as or different from the material of the first dielectric layer 110. The material of the second dielectric layer 120 may refer to the material of the first dielectric layer 110 described above, and will not be repeated here. In some embodiments, the coefficient of thermal expansion of the second dielectric layer 120 is between 3ppm / ℃ and 80ppm / ℃ (3ppm / ℃ ≤ coefficient of thermal expansion ≤ 80ppm / ℃), between 10ppm and 70ppm (10ppm / ℃ ≤ coefficient of thermal expansion ≤ 70ppm / ℃), or between 15ppm and 65ppm (15ppm / ℃ ≤ coefficient of thermal expansion ≤ 65ppm / ℃), but is not limited thereto.

[0045] Next, please refer to Figure 1 and Figure 2E In step S160, the second dielectric layer 120 is patterned. The method for patterning the second dielectric layer 120 is similar to the method for patterning the first dielectric layer 100, and therefore will not be described in detail here. The patterned second dielectric layer 120 may have a plurality of second openings O2, which may, for example, expose portions of the conductive structure 116.

[0046] Please refer to Figure 1 and Figure 2F Next, in step S170, a carrier plate 300 with a first dielectric layer 110 and a second dielectric layer 120 is placed on a second curved mold 200A, and the second dielectric layer 120 is cured. The second curved mold 200A has a protrusion 210A with a thickness H2. In some embodiments, the material of the second curved mold 200A is similar to that of the first curved mold 200, and its coefficient of thermal expansion or hardness characteristics can be referenced to those of the first curved mold 200.

[0047] It should be noted that the difference between the second curved surface mold 200A and the first curved surface mold 200 is that the thickness H1 of the protrusion of the first curved surface mold 200 may be, for example, smaller than the thickness H2 of the protrusion of the second curved surface mold 200A. Specifically, the second curved surface mold 200A has a base plate 211A and a protrusion 210A, with the protrusion 210A connected to the base plate 211A. In some embodiments, the materials of the base plate 211A and the protrusion 210A may be the same or different. In some embodiments, the base plate 211A and the protrusion 210A may be integrally formed, for example. In some embodiments, the surface 201A of the base plate 211A may, for example, be connected to the curved surface 205A of the protrusion 210A, and the curved surface 205A may contact the carrier plate 300. In some embodiments, the curved surface 205A has a vertex 203A located at the highest point of the curved surface 205A. The protrusion 210A of the second curved surface mold 200A has a thickness H2, which can be defined as the distance between the vertex 203A and the upper surface 201A in the normal direction of the base plate 211A (the Z-axis direction in the figure). The thickness H2 of the protrusion 210A of the second curved surface mold 200A is between 0.3 mm and 0.8 mm (0.3 mm ≤ thickness H2 ≤ 0.8 mm), but is not limited to this.

[0048] In some embodiments, the ratio of the thickness H1 of the protrusion 210 of the first curved mold 200 to the thickness H2 of the protrusion 210A of the second curved mold 200A may be between 1 and 5 (1 < thickness H1 / thickness H2 ≦ 5) or between 1 and 3 (1 < thickness H1 / thickness H2 ≦ 3) or between 1 and 2 (1 < thickness H1 / thickness H2 ≦ 2), but is not limited thereto.

[0049] In some embodiments, the coefficient of thermal expansion of the second curved surface mold 200A may be less than or equal to 10 ppm / ℃ or less than or equal to 8 ppm / ℃, but is not limited thereto. In some embodiments, the hardness of the second curved surface mold 200A may be, for example, less than the hardness of the carrier plate 300 to reduce the risk of the carrier plate 300 being scratched, but is not limited thereto.

[0050] In some embodiments, a carrier plate 300 having a first dielectric layer 110 and a second dielectric layer 120 formed thereon may be disposed, for example, on a second curved mold 200A, and the carrier plate 300 may be adjacent to or in contact with a protrusion 210A of the second curved mold 200A. In some embodiments, the protrusion 210A of the second curved mold 200A may have, for example, a plurality of holes (not shown). In some embodiments, during the step of curing the second dielectric layer 120, a vacuum fixture (not shown) may, for example, vacuum-adsorb the carrier plate 300 through these holes, so that the carrier plate 300 is adsorbed onto the curved surface 205A of the protrusion 210A, thereby forming the bending force as described above. As described above, the second curved mold 200A may, for example, generate a bending force on the carrier plate 300 opposite to the warping direction, so that the carrier plate 300 may be bent substantially along the protrusion 120A of the second curved mold 200A, thereby reducing the warping problem of the composite layer circuit element 100. The method for fabricating the composite layer circuit element 100 disclosed herein can enable the composite layer circuit element 100 to have good structural strength or quality.

[0051] In some embodiments, during the step of curing the second dielectric layer 120, a portion of the carrier plate 300 may contact the second curved mold 200A (e.g., protrusion 210A), while another portion of the carrier plate 300 may not contact the second curved mold 200A, thus creating a gap SP between the carrier plate 300 and the portion of the protrusion 210A of the second curved mold 200A. In some embodiments, a plurality of holes (not shown) may be distributed only in the portion of the protrusion 210A, for example, and the holes (not shown) may be distributed only in the central portion of the portion of the protrusion 210A, preventing the portion of the carrier plate 300 from being adsorbed onto the protrusion 210A. Therefore, a gap SP may exist between the carrier plate 300 and the portion of the protrusion 210A of the second curved mold 200, but this is not a limitation. Through the above design, in the step of curing the second dielectric layer 120, the risk of excessive bending force caused by the second curved mold 200A being completely adsorbed onto the protrusion 210A of the second curved mold 200A, which may lead to the cracking of the carrier plate 300, can be reduced, but it is not limited to this.

[0052] In some embodiments, the step of curing the second dielectric layer 120 includes a baking process on the second dielectric layer 120, the conditions of which may be similar to the conditions of the baking process for curing the first dielectric layer 110.

[0053] Please refer to Figure 2GNext, a third seed layer 123 is formed on the upper surface 120T of the second dielectric layer 120. The third seed layer 123 can, for example, fill the opening O2 of the second dielectric layer 120. Next, a conductive material layer is disposed on the third seed layer 123, and then the conductive material layer and the third seed layer 123 are patterned to form a plurality of conductive structures 126. The method of patterning the conductive material layer to form the conductive structures 126 can be referenced to the method of forming the plurality of conductive structures 111 described above. At this point, the fabrication of the composite layer circuit element 100 is substantially completed. It should be noted that the composite layer circuit element 100 disclosed herein is illustrated, for example, as shown in the diagram. Figure 2G The stacked state of the composite layer circuit element 100 is as follows, but not limited to this. In other embodiments, the number or connection method of the stacked layers of the composite layer circuit element 100, such as seed layers, conductive structures and / or dielectric layers, can be varied as needed. It should be noted that the method for fabricating the composite layer circuit element 100 disclosed herein is illustrated, for example, only using a first curved surface mold 200 and a second curved surface mold 200A, but is not limited to this. In other embodiments, the number of curved surface molds used in the method for fabricating the composite layer circuit element 100 can be varied, for example, according to the number of dielectric layers to be cured.

[0054] Figure 2H This is a schematic cross-sectional view of an electronic device including composite layer circuit elements according to an embodiment of this disclosure. The drawings are for clarity and ease of explanation. Figure 2H Several components are omitted from the diagram. Please refer to [link / reference]. Figure 2H The carrier 300, release layer 310, and first seed layer 330 are removed. For example, the carrier 300, release layer 310, and / or first seed layer 330 can be removed by laser or other suitable methods, but are not limited thereto. Furthermore, by designing the thickness T1 of the first dielectric layer 110 to be greater than the thickness T2 of the second dielectric layer 120, the impact on the composite layer circuit elements during the removal of the carrier 300, release layer 310, and / or first seed layer 330 can be reduced. Specifically, during the removal of the carrier 300, release layer 310, and / or first seed layer 330, a portion of the first dielectric layer 110 may be slightly removed or damaged. By designing a thicker thickness T1 for the first dielectric layer 110, the thinning of the first dielectric layer 110 can be reduced, thus minimizing the impact on the yield of the composite layer circuit elements.

[0055] Next, external electronic components may be selectively bonded to the composite layer circuit element 100 to form the electronic device 10. For example, the external electronic components may include a first electronic component 400 or a second electronic component 400A. The first electronic component 400 and the second electronic component 400A may include, for example, an integrated circuit chip (IC chip), a light-emitting diode (LED), or other suitable electronic or circuit elements, but are not limited thereto. In some embodiments, the step of setting the external electronic components may be performed before the step of removing the carrier board 300; the embodiments disclosed herein are not limiting.

[0056] In some embodiments, the first electronic component 400 may be, for example, a light-emitting diode (LED), but is not limited thereto. The first electronic component 400 may be electrically connected to the composite layer circuit element 100 via conductive bumps 420. The second electronic component 400A may be, for example, an integrated circuit chip, but is not limited thereto. In some embodiments, the second electronic component 400A may be electrically connected to the composite layer circuit element 100 via conductive bumps 420A. Thus, the composite layer circuit element 100 can be applied to a light-emitting display device or other suitable electronic device. The electronic device 10 including the composite layer circuit element 100 may have good structural strength or quality.

[0057] In some embodiments, the fabrication method of the composite layer circuit element disclosed herein can be applied to the fabrication of semiconductor packaged electronic devices, such as system-on-chip (SoC), system-in-package (SiP), or other suitable electronic devices. Specifically, the fabrication method of the composite layer circuit element disclosed herein can be applied to redistribution layer first (RDL first) fabrication methods, chip first / face up fabrication methods, or chip first / face down fabrication methods. In one embodiment of the composite layer circuit element disclosed herein, in the redistribution layer first fabrication method, the carrier 300 may include glass, quartz, sapphire, ceramic, stainless steel, silicon wafer, encapsulating colloid (e.g., resin, epoxy resin, silicone compound), other suitable substrate materials, or combinations thereof, but is not limited thereto. In die-first / face-up fabrication methods and die-first / face-down fabrication methods, the carrier 300 may include an integrated circuit chip encapsulated with an encapsulating colloid (e.g., epoxy resin, silicone compound), a silicon wafer, other suitable substrate materials, or combinations thereof, but is not limited thereto. In some embodiments, in the redistribution layer-first fabrication method, the carrier 300 may be removed after the redistribution layer is fabricated, so that the redistribution layer can be bonded to components such as integrated circuit chips and / or printed circuit boards in subsequent processes, but is not limited thereto. In some embodiments, in the die-first / face-up fabrication method and die-first / face-down fabrication method, a release layer may be selectively provided on the carrier 300 or not, so that it can be bonded to components such as printed circuit boards in subsequent processes, but is not limited thereto.

[0058] In summary, in the composite layer circuit element of this embodiment, by providing a curved mold during the dielectric layer curing step, the carrier board can be bent toward the curved mold during dielectric layer curing to counteract the warping force during curing. This reduces the warping of the cured dielectric layer and carrier board, thereby providing the composite layer circuit unit with good structural strength or quality. Furthermore, the overall warping of the composite layer circuit unit can be reduced by adjusting the thickness of the dielectric layer.

[0059] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for fabricating a composite layer circuit element, characterized in that, include: Provide carrier board; A first dielectric layer is formed on the carrier plate; Pattern the first dielectric layer; The carrier plate on which the first dielectric layer is formed is placed on the first curved mold and the first dielectric layer is cured. A second dielectric layer is formed on the first dielectric layer; Pattern the second dielectric layer; as well as The carrier plate on which the first dielectric layer and the second dielectric layer are formed is placed on the second curved surface mold and the second dielectric layer is cured. The thickness of the protrusion of the first curved mold is less than the thickness of the protrusion of the second curved mold.

2. The method according to claim 1, characterized in that, In the step of curing the first dielectric layer, there is a gap between the carrier plate and part of the protrusion of the first curved mold.

3. The method according to claim 1, characterized in that, In the step of curing the second dielectric layer, there is a gap between the carrier plate and part of the protrusion of the second curved mold.

4. The method according to claim 1, characterized in that, The thickness of the first dielectric layer is greater than the thickness of the second dielectric layer.

5. The method according to claim 1, characterized in that, The coefficient of thermal expansion of the first curved surface mold or the second curved surface mold is less than or equal to 10 ppm / ℃.

6. The method according to claim 1, characterized in that, The carrier plate is made of materials including glass, quartz, sapphire, or ceramic.

7. The method according to claim 1, characterized in that, The thickness of the protrusion of the first curved mold is between 0.1 mm and 0.4 mm, and the thickness of the protrusion of the second curved mold is between 0.3 mm and 0.8 mm.

8. A composite layer circuit element, characterized in that, include: First dielectric layer; The first circuit layer is disposed on the first dielectric layer; and The second dielectric layer is disposed on the first circuit layer. The thickness of the first dielectric layer is greater than the thickness of the second dielectric layer. The thickness of the first dielectric layer is between 5 micrometers and 25 micrometers, the thickness of the second dielectric layer is between 5 micrometers and 25 micrometers, and the ratio of the thickness of the first dielectric layer to the thickness of the second dielectric layer is between 1.5 and 5. The coefficient of thermal expansion of the first dielectric layer is between 15 ppm / ℃ and 65 ppm / ℃, and the coefficient of thermal expansion of the second dielectric layer is between 15 ppm / ℃ and 65 ppm / ℃.

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