A layout structure and method for using single and double row PAD and ESD together

Abstract

The present invention provides a layout structure and method for using a single-row and double-row PAD and ESD in combination. The layout structure includes a circuit layout, a PAD, and an ESD protection device. The area of ​​a single PAD is a first preset value, and the number of PADs is a second preset value. A first area formed by arranging the PADs in a single row along the periphery of the circuit layout is larger than a second area of ​​the circuit layout; a third area formed by arranging the PADs in double rows or multiple rows along the periphery of the circuit layout is smaller than the second area of ​​the circuit layout; the PAD includes a first PAD and a second PAD, and the ESD protection device includes a single-row ESD protection device and a double-row ESD protection device; the PADs are arranged in single and double rows along the periphery of the circuit layout, wherein the first PAD is arranged in a single row along the periphery of the analog circuit layout to form a single-row PAD, and the single-row PAD is connected to the single-row ESD protection device; the second PAD is arranged in double rows along the periphery of the digital circuit layout to form a double-row PAD, and the double-row PAD is connected to the double-row ESD protection device. The present invention helps to improve the utilization rate of the chip area from within the chip.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit layout design, and in particular to a layout structure and method for using single and double row PADs and ESDs in combination. Background Art

[0002] In integrated circuit layout design, many power pads (pads) and signal pads need to be brought out. However, chips with relatively small internal analog and digital circuit layouts often face PAD limits, where the chip area is limited by the number of pads. Existing PAD designs often incorporate electrostatic discharge (ESD) protection devices to prevent ESD shocks. Given the limitations of peripheral packaging, wire bonding materials, and wire diameter selection, as well as the inability to significantly reduce power and signal pads, addressing the PAD limit becomes a significant factor limiting chip area. Summary of the Invention

[0003] The first object of the present invention is to provide a layout structure for using single and double row PADs and ESDs in combination, which reduces the redundant area of ​​a chip and improves chip area utilization.

[0004] The second object of the present invention is to provide a method for realizing the layout structure of the above-mentioned single and double rows and ESD.

[0005] In order to achieve the above-mentioned first purpose, the present invention provides a layout structure for using a single or double row PAD and ESD in combination, including a circuit layout, a PAD, and an ESD protection device. The circuit layout includes an analog circuit layout and a digital circuit layout, the analog circuit layout is connected to the digital circuit layout, the PAD is connected to the ESD protection device, the PAD and the ESD protection device are arranged along the four sides of the circuit layout, a single PAD is connected to a single ESD protection device, and the shape of the circuit layout is a rectangle or a square, wherein: the area of ​​a single PAD is a first preset value, and the number of PADs is a second preset value; the PADs are arranged in a single row along the four sides of the circuit layout to form a The first area is larger than the second area of ​​the circuit layout; the third area formed by the PAD being arranged in double rows or multiple rows along the four sides of the circuit layout is smaller than the second area of ​​the circuit layout; the PAD includes a first PAD and a second PAD, and the ESD protection device includes a single-row ESD protection device and a double-row ESD protection device; the PAD is arranged in single and double rows along the four sides of the circuit layout, wherein the first PAD is arranged in a single row along the four sides of the analog circuit layout to form a single-row PAD, and the single-row PAD is connected to the single-row ESD protection device; the second PAD is arranged in double rows along the four sides of the digital circuit layout to form a double-row PAD, and the double-row PAD is connected to the double-row ESD protection device.

[0006] It can be seen from the above scheme that the present invention solves the problem of a significant increase in chip area under the PAD limit when the circuit layout of the chip is the second area by using a single-row PAD and a single-row ESD protection device in combination in the analog circuit layout, and a double-row PAD arrangement and a double-row ESD protection device in combination in the digital circuit layout. At the same time, the use of a single-row PAD and a single-row ESD in the analog circuit layout is beneficial to the adjustment of the shape of analog modules with larger areas, which helps to improve the area utilization from the inside of the chip.

[0007] A further solution is that the ESD protection device is arranged below the PAD.

[0008] It can be seen that the above solution can reduce the chip area.

[0009] A further solution is that the analog circuit layout includes a first analog circuit module and a second analog circuit module, the first analog circuit module and the second analog circuit module are spliced ​​together, and the first PAD is arranged in a single row along the continuous adjacent edge of the common edge formed by the splicing of the first analog circuit module and the second analog circuit module.

[0010] A further solution is that the digital circuit layout is arranged in a central area of ​​the circuit layout.

[0011] In order to achieve the above-mentioned second purpose, the present invention provides a method for realizing the layout structure of the above-mentioned single and double-row PADs and ESDs, which includes the following steps: determining the area of ​​a single PAD, the number of PADs, and the circuit layout; judging whether the first area formed by the PADs arranged in a single row along the four sides of the circuit layout is larger than the second area of ​​the circuit layout, and judging whether the third area formed by the PADs arranged in double rows or multiple rows along the four sides of the circuit layout is smaller than the second area of ​​the circuit layout; arranging the first PAD in a single row along the four sides of the analog circuit layout to form a single-row PAD, and the single-row PAD is connected to a single-row ESD protection device; arranging the second PAD in double rows along the four sides of the digital circuit layout to form a double-row PAD, and the double-row PAD is connected to a double-row ESD protection device.

[0012] It can be seen from this that the present invention first determines the area of ​​the PAD to be used, the number of PADs, and the circuit layout, and decides whether to adopt a single or double row PAD arrangement method based on the area of ​​the PAD, the number of PADs, and the area of ​​the circuit layout. If a single or double row arrangement method is adopted, the analog circuit layout adopts a single row of PADs connected to a single row of ESD protection devices, which is beneficial to the splicing of the analog circuit layout. The digital circuit layout adopts a double row of PADs connected to a double row of ESD protection devices, which adapts to the characteristics that the digital circuit layout requires more input and output pins than the analog layout. By designing the layout layout structure of the present invention, the utilization rate of the internal area of ​​the chip can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 In the embodiment of the layout structure of the present invention, the PAD is used along the circuit board in combination with the single and double row PAD and ESD. Figure 4 Schematic diagram of the structure arranged in a single row in the circumferential direction.

[0014] Figure 2 In the embodiment of the layout structure of the present invention, the PAD is used along the circuit board in combination with the single and double row PAD and ESD. Figure 4 Schematic diagram of the structure with double rows arranged in the circumferential direction.

[0015] Figure 3 In the embodiment of the layout structure of the present invention, the PAD is used along the circuit board in combination with the single and double row PAD and ESD. Figure 4 Schematic diagram of the structure with single and double rows arranged in the circumferential direction.

[0016] Figure 4 This is a schematic structural diagram of the first analog circuit module and the second analog circuit module under the single-row PAD being spliced ​​in pairs in an embodiment of the layout structure for using single and double-row PADs and ESDs in combination with each other in the present invention.

[0017] Figure 5 This is a schematic structural diagram of the pairwise splicing of first analog circuit modules and second analog circuit modules in a double-row PAD arrangement in an embodiment of a layout structure for use with single and double-row PADs and ESDs of the present invention.

[0018] Figure 6 This is a schematic structural diagram of a double-row PAD and a double-row ESD protection device in an embodiment of a layout structure for use with a single-row and double-row PAD and ESD according to the present invention.

[0019] Figure 7 This is a schematic structural diagram of a double-row PAD and a single-row ESD protection device in an embodiment of a layout structure for using a single-row and double-row PAD and ESD in combination according to the present invention.

[0020] Figure 8 It is a flow chart of an embodiment of a layout method for using single and double row PADs and ESDs in combination with each other according to the present invention.

[0021] The present invention will be further described below with reference to the accompanying drawings and embodiments. DETAILED DESCRIPTION

[0022] In the present invention, when the second area of ​​the circuit layout is between the first area and the second area, the PAD is arranged in single or double rows along the four sides of the circuit layout. The analog circuit layout uses a single row of PAD and a single row of ESD, and the digital circuit layout uses a double row of PAD and a double row of ESD, thereby reducing the chip area.

[0023] In the present invention, “first” and “second” are used to distinguish things of the same kind and do not have the meaning of order.

[0024] Example of layout structure for using single and double row PAD and ESD together:

[0025] In this embodiment, the layout structure of the single and double row PAD and ESD used in combination includes a circuit layout, a PAD, and an ESD protection device, wherein the PAD includes a first PAD and a second PAD, the circuit layout includes an analog circuit layout and a digital circuit layout, the analog circuit layout is connected to the digital circuit layout, the PAD is connected to the ESD protection device, the PAD and the ESD protection device are arranged along the four sides of the circuit layout, a single PAD is connected to a single ESD protection device, and the circuit layout is a rectangle. It should be noted that the ESD protection device in this embodiment is arranged below the PAD, that is, the DUP (Device Under Pad) structure, which is a prior art.

[0026] During the chip layout design process, it is necessary to determine the chip circuit layout and the PAD used, including determining the second area of ​​the chip circuit layout, the number of PADs, and the area of ​​a single PAD. Each PAD also needs to be connected to an ESD protection device, where the area of ​​a single PAD is a first preset value, which is determined by the design rules provided by the integrated circuit manufacturer and is generally the minimum value under the design rules. The number of PADs is a second preset value, which is determined during the chip circuit design process. The shape of the circuit layout is a rectangle or a square, and the four sides are along the four directions, that is, along the four sides of the rectangle or square. Figure 1 The first PADs 121 are arranged in a single row along the four sides of the circuit layout 11. Due to the number and area limitations of the first PADs 121, a first area S1 for accommodating the circuit layout is formed in the middle, and S2 is the second area of ​​the circuit layout 11. It can be seen that the first area S1 formed by the first PADs 121 arranged in a single row along the four sides of the circuit layout 11 is larger than the second area S2 of the circuit layout 11. There is redundant space between the first area S1 and the second area S2, resulting in a waste of chip area.

[0027] Reference Figure 2 The second PADs 122 are arranged in two rows around the circuit layout 11. The double row arrangement means arranging two rows of PADs around the circuit layout 11, thereby forming a third area S3 that can accommodate the circuit layout. S2 is the second area of ​​the circuit layout 11. It can be seen that the third area S2 formed by the second PADs 122 arranged in two rows around the circuit layout 11 is smaller than the second area S2 of the circuit layout 11 and cannot accommodate the circuit layout 11.

[0028] Reference Figure 3, PADs are arranged in single or double rows along the four sides of the circuit layout 11. The single or double row arrangement means that some PADs are arranged in single row and some PADs are arranged in double row, so that the area surrounded by the PADs can just accommodate the circuit layout 11, thereby minimizing redundant space and increasing the utilization rate of the chip area. Among them, for the analog circuit layout, the first PAD 121 is arranged in a single row along the four sides of the analog circuit layout 11 to form a single row of PADs, and a single row of ESD protection devices (not shown in the figure) is connected below the single row of PADs; for the digital circuit layout, the second PAD 122 is arranged in double rows along the four sides of the digital circuit layout to form a double row of PADs, and an ESD protection device (not shown in the figure) is connected below the double row of PADs. The digital circuit layout is set in the central area of ​​the circuit layout.

[0029] For analog circuit layout, refer to Figure 4 , including a first analog circuit module 111 and a second analog circuit module 112, the first analog circuit module 111 is connected to 6 first PADs 121 arranged in a single row through GPIO (GPIO (General-purpose input / output)) (dashed line in the figure), the second analog circuit module 112 is connected to 4 first PADs 121 arranged in a single row through GPIO (dashed line in the figure), the first analog circuit module 111 and the second analog circuit module 112 are spliced, and the first PADs 121 are arranged in a single row along the continuous adjacent edges of the common edge formed by the splicing of the first analog circuit module and the second analog circuit module, that is, along two of the four adjacent edges of the common edge in a single row, and these two adjacent edges are not parallel. Since the first PADs 121 of the first analog circuit module 111 and the second analog circuit module 112 are both arranged in a single row, the shape of the analog circuit module can be easily adjusted, making it more convenient to splice the first analog circuit module and the second analog circuit module. If the PADs of the first analog circuit module and the second analog circuit are not arranged in a single row, refer to Figure 5, the first analog circuit module 111 is connected to 6 second PADs 122 via GPIO (dashed lines in the figure), and the 6 second PADs 122 are arranged in double rows. The second analog circuit module 112 is connected to 4 second PADs 122 via GPIO (dashed lines in the figure), and the 4 second PADs 122 are arranged in double rows. It can be seen that, compared with the single-row arrangement, the splicing of the first analog circuit module 111 and the second analog circuit module 1112 is more troublesome, and there is redundant space in terms of area utilization. If the shape is adjusted by compressing the first analog circuit module 111 or the second analog circuit module 112, the space of the chip in the height direction of the module will be greatly compressed, which will bring difficulties to the chip design. In addition, if you want to use this redundant space, due to the presence of the ESD protection device (not shown in the figure) below the second PAD 122, special processing and protection are required on the layout to reduce potential risks. At the same time, the metal rings of the power line and ground line of the ESD protection device also need to be designed with special interfaces for connection.

[0030] For digital circuit layouts, since the digital input and output pins of the chip in the digital circuit layout occupy the majority, if a single-row PAD is used in combination with a single-row EDS protection device, the width and length of the chip will increase a lot, resulting in a lot of redundant space, low chip area utilization, and increased production costs. The use of a double-row PAD arrangement in combination with a double-row ESD protection device can improve the area utilization of the internal module at the module level.

[0031] In addition, refer to Figure 6 and Figure 7 , Figure 6 It is a double-row PAD arrangement with a double-row ESD protection device. Figure 7 The double-row PAD arrangement is matched with a single-row ESD protection device. The dotted lines represent GPIO. The use of double-row PAD arrangement with double-row ESD protection devices can optimize the wiring space. Because the double-row PAD arrangement with a single-row ESD protection device requires additional consideration of the connection of the metal wires of the ESD protection device, and in Figure 6 A certain amount of layout space needs to be added between the upper and lower rows of second PADs 122 to isolate the ESD protection device and other devices to avoid possible latch-up effects.

[0032] Example of layout method for using single and double row PAD and ESD together:

[0033] Reference Figure 8 The layout method for using single and double row PADs and ESDs in combination in this embodiment first performs step S31 to determine the area of ​​a single PAD, the number of PADs, and the circuit layout. Specifically, these are determined during the layout design process based on the chip's circuit schematic.

[0034] Then, step S32 is executed to determine whether the first area formed by the single row arrangement of the PAD along the four sides of the circuit layout is larger than the second area of ​​the circuit layout. If so, it means that there is redundant space between the first area and the second area, resulting in a waste of chip internal space. For details, please refer to the layout structure embodiment of the use of single and double row PADs and ESDs. Figure 1 At this time, continue to execute step S33 to perform subsequent judgment.

[0035] Then, step S33 is executed to determine whether the third area formed by the double or multiple rows of PADs arranged along the four sides of the circuit layout is smaller than the second area of ​​the circuit layout. Figure 4 The area formed by the circumferential arrangement is not enough to accommodate the circuit layout. For details, please refer to the layout structure embodiment of the single and double row PAD and ESD combination. Figure 2 At this point, continue with step S3.

[0036] Finally, step S34 is performed to arrange the first PADs in a single row along the perimeter of the analog circuit layout to form a single-row PAD, which is connected to a single-row ESD protection device. The PADs are then arranged in a double row along the perimeter of the digital circuit layout to form a double-row PAD, which is connected to a double-row ESD protection device. The specific process can be referred to in the layout structure embodiment for using single and double-row PADs with ESDs, and will not be repeated here.

[0037] To summarize, the present invention solves the problem of a substantial increase in chip area due to PAD limit when the circuit layout of the chip is the second area by using a single-row PAD and a single-row ESD protection device in combination in the analog circuit layout, and a double-row PAD arrangement and a double-row ESD protection device in combination in the digital circuit layout. At the same time, the use of a single-row PAD and a single-row ESD in the analog circuit layout is beneficial to the adjustment of the shape of analog modules with a larger area, which helps to improve the area utilization from within the chip.

Claims

1. A layout structure for use with single and double row PADs and ESDs, comprising a circuit layout, a PAD, and an ESD protection device, wherein the circuit layout comprises an analog circuit layout and a digital circuit layout, the analog circuit layout is connected to the digital circuit layout, the PAD is connected to the ESD protection device, the PAD and the ESD protection device are arranged along the four sides of the circuit layout, a single PAD is connected to a single ESD protection device, and the circuit layout is rectangular or square in shape, characterized in that: The area of ​​a single PAD is a first preset value, and the number of PADs is a second preset value; When the PADs are arranged in a single row around the four sides of the circuit layout, a first area formed in the middle is larger than a second area of ​​the circuit layout; When the PADs are arranged in two rows along the four sides of the circuit layout, a third area formed in the middle is smaller than the second area of ​​the circuit layout; The PAD includes a first PAD and a second PAD, and the ESD protection device includes a single-row ESD protection device and a double-row ESD protection device; the PADs are arranged in single and double rows along the four sides of the circuit layout, wherein the first PAD is arranged in a single row along the four sides of the analog circuit layout to form a single-row PAD, and the single-row PAD is connected to the single-row ESD protection device; the second PAD is arranged in a double row along the four sides of the digital circuit layout to form a double-row PAD, and the double-row PAD is connected to the double-row ESD protection device.

2. A layout structure for using a single or double row PAD and an ESD in combination as claimed in claim 1, characterized in that: The ESD protection device is arranged below the PAD.

3. A layout structure for using a single or double row PAD and an ESD in combination as claimed in claim 2, characterized in that: The analog circuit layout includes a first analog circuit module and a second analog circuit module, the first analog circuit module and the second analog circuit module are spliced ​​together, and the first PAD is arranged in a single row along the continuous adjacent edge of the common edge formed by the splicing of the first analog circuit module and the second analog circuit module.

4. The layout structure for using a single or double row PAD and an ESD in combination as claimed in claim 3, characterized in that: The digital circuit layout is arranged in a central area of ​​the circuit layout.

5. A method for realizing a layout structure for using a single or double row PAD and an ESD in combination as claimed in any one of claims 1 to 4, characterized in that: The following steps are involved: Determining the area of ​​a single PAD, the number of PADs, and the circuit layout; Determining whether the first area formed by the PADs arranged in a single row along the periphery of the circuit layout is larger than the second area of ​​the circuit layout, and determining whether the third area formed by the PADs arranged in a double row along the periphery of the circuit layout is smaller than the second area of ​​the circuit layout; When the first area is larger than the second area of ​​the circuit layout and the third area is smaller than the second area of ​​the circuit layout, the first PAD is arranged in a single row along the four sides of the analog circuit layout to form the single row PAD, and the single row PAD is connected to the single row ESD protection device; the second PAD is arranged in a double row along the four sides of the digital circuit layout to form the double row PAD, and the double row PAD is connected to the double row ESD protection device.

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