A bevel type wide process window power device and a manufacturing method thereof

Abstract

The present application relates to a kind of bevel type wide process window power device and its manufacturing method, comprising: first conductive type semiconductor substrate;First conductive type semiconductor epitaxial layer is located in the one side of first conductive type semiconductor substrate;The first surface of the first conductive type semiconductor epitaxial layer is the side surface of the first conductive type semiconductor epitaxial layer away from first conductive type semiconductor substrate;The first surface includes flat area and the inclined area located in the one side of flat area and is connected with flat area, at least first included angle exists between the inclined area of the first surface and the second surface of the first conductive type semiconductor epitaxial layer, the first included angle, the mixed scheme of bevel angle combination field ring and junction terminal extension is used in the present application, and device has very extensive process window, bevel angle does not consume chip area, can reduce chip size, reduce cost.

Description

Technical Field

[0001] This invention relates to the field of semiconductor power devices, and more specifically to a power device with a beveled wide process window and a method for manufacturing the same. Background Technology

[0002] Silicon carbide (SiC), a third-generation semiconductor material, has a larger bandgap and a higher critical breakdown field strength than silicon. Compared to silicon power devices of the same voltage rating, SiC has a higher doping concentration and a smaller epitaxial layer thickness, thus significantly reducing forward on-resistance and power loss. Simultaneously, SiC possesses high thermal conductivity, high-temperature resistance, and a high electron saturation velocity, making it suitable for high-current, high-power applications. This reduces the requirements for heat dissipation equipment, shrinks device size, improves reliability, and lowers costs. Therefore, SiC is considered an important development direction for next-generation high-efficiency power electronic devices, with broad application prospects in new energy vehicles, rail transportation, locomotive traction, and smart grids.

[0003] Currently, in the design and fabrication of silicon carbide power devices, to improve the device's breakdown voltage performance, a good termination structure is required, such as a field plate (FP), field limiting ring (FLR), and junction termination extension (JTE). The field limiting ring (FLR) and junction termination extension (JTE) structures are the most widely used in existing SiC power device structures.

[0004] In silicon carbide (SiC) power devices, especially under high voltage conditions, a floating field-limiting ring (FCR) termination structure is commonly used. However, the sharp corners on the outer surface of the FCR (the side furthest from the main junction) are more prone to electric field spikes. Furthermore, due to the inherent characteristics of the material, the thermal growth of thick silicon dioxide films on the SiC surface is limited. Therefore, the passivation layer on the junction termination surface of SiC power devices is typically deposited silicon dioxide, which is of relatively poor quality. Compared to the high critical breakdown electric field of SiC, the passivation layer becomes a vulnerable point for breakdown. Thus, the electric field spikes at the sharp corners can reduce the breakdown voltage and reliability of SiC power devices. Therefore, there is an urgent need for a SiC power device junction termination structure with good breakdown voltage and high reliability. Summary of the Invention

[0005] In view of this, the present invention provides a power device with a beveled wide process window and a method for manufacturing the same. The device adopts a hybrid scheme of beveled combined with field ring and junction termination extension to give it a very wide process window. The bevel does not consume chip area, which can reduce chip size and reduce cost. The beveled junction termination extension (JTE) makes the electric field distribution more uniform during breakdown and has a higher breakdown voltage.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] A power device with a sloping wide process window includes: a first conductivity type semiconductor substrate; a first conductivity type semiconductor epitaxial layer located on one side of the first conductivity type semiconductor substrate; a first surface of the first conductivity type semiconductor epitaxial layer having a second conductivity type main junction and a plurality of second conductivity type junction field rings and a plurality of second conductivity type well regions spaced apart, wherein at least a portion of the second conductivity type junction field rings and the second conductivity type well regions are alternately arranged; wherein, the first surface of the first conductivity type semiconductor epitaxial layer is the side surface of the first conductivity type semiconductor epitaxial layer away from the first conductivity type semiconductor substrate; the first surface includes a flat region and a sloping region located on one side of the flat region and connected to the flat region, and the second conductivity type main junction is located on the side of the flat region away from the sloping region.

[0008] The first electrode layer is located on the side of the first conductivity type semiconductor substrate away from the first conductivity type semiconductor epitaxial layer; the second electrode layer is located on the side of the first conductivity type semiconductor epitaxial layer away from the first conductivity type semiconductor substrate, and the projection of the second electrode layer on the first conductivity type semiconductor substrate is located within the projection of the second conductivity type main junction on the first conductivity type semiconductor substrate.

[0009] There is at least a first included angle between the inclined region of the first surface and the second surface of the first conductive type semiconductor epitaxial layer, the first included angle α < 90°, and the second surface of the first conductive type semiconductor epitaxial layer is the side surface of the first conductive type semiconductor epitaxial layer that is closer to the first conductive type semiconductor substrate.

[0010] Compared with the prior art, the beneficial effects of the present invention are:

[0011] The hybrid approach of using a beveled structure combined with a field ring and junction termination extension gives the device a very wide process window. Compared with the planar junction termination extension structure, the beveled step structure with one or more tilt angles can make the edge electric field intensity uniformly distributed on multiple three-dimensional structures, resulting in higher breakdown voltage and good forward conduction and reverse turn-off characteristics.

[0012] At the same time, the angled structure does not consume chip area, which can effectively reduce the size of the chip and reduce costs.

[0013] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures pointed out in the description, claims and drawings. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a cross-sectional schematic diagram of a power device 100 with a sloping wide process window according to the present invention;

[0016] Figure 2 This is a cross-sectional schematic diagram of a power device 200 with a sloping wide process window according to the present invention;

[0017] Figure 3 This is a cross-sectional schematic diagram of a power device 300 with a sloping wide process window according to the present invention;

[0018] Figure 4 This is a cross-sectional schematic diagram of a power device 400 with a sloping wide process window according to the present invention;

[0019] Figure 5 This is a schematic diagram of the process steps for a power device 500 with a sloping wide process window according to the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" or "several" means two or more, unless otherwise explicitly specified.

[0022] The term "and / or" in this invention is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, B existing alone, and A and B existing simultaneously. Clearly, the described embodiments are only some, not all, of the embodiments of this invention.

[0023] As one implementation method, Figure 1 This is a cross-sectional schematic diagram of a power device 100 with a beveled wide process window according to the present invention. Figure 1 As shown, the present invention provides a power device 100 with a beveled wide process window, comprising: a first conductivity type semiconductor substrate 101; a first conductivity type semiconductor epitaxial layer 102 located on one side of the first conductivity type semiconductor substrate 101; a first surface FS of the first conductivity type semiconductor epitaxial layer 102 having a second conductivity type main junction 1021 and a plurality of second conductivity type junction field rings 1022 and a plurality of second conductivity type well regions 1023 spaced apart, wherein at least a portion of the second conductivity type junction field rings 1022 and the second conductivity type well regions 1023 are alternately arranged; wherein, the first surface FS of the first conductivity type semiconductor epitaxial layer 102 is the side surface of the first conductivity type semiconductor epitaxial layer 102 away from the first conductivity type semiconductor substrate 101; the first surface FS includes a flat region PA and a sloped region NPA located on one side of the flat region PA and connected to the flat region PA, and the second conductivity type main junction 1021 is located on the side of the flat region PA away from the sloped region NPA.

[0024] The first electrode layer 103 is located on the side of the first conductivity type semiconductor substrate 101 away from the first conductivity type semiconductor epitaxial layer 102; the second electrode layer 104 is located on the side of the first conductivity type semiconductor epitaxial layer 102 away from the first conductivity type semiconductor substrate 101, and the projection of the second electrode layer 104 on the first conductivity type semiconductor substrate 101 is located within the projection of the second conductivity type main junction 1021 on the first conductivity type semiconductor substrate 101.

[0025] There is at least a first included angle between the tilted region NPA of the first surface FS and the second surface SS of the first conductive type semiconductor epitaxial layer 102, the first included angle α < 90°, and the second surface SS of the first conductive type semiconductor epitaxial layer 102 is the side surface of the first conductive type semiconductor epitaxial layer 102 that is close to the first conductive type semiconductor substrate 101.

[0026] The hybrid approach combining an angled structure with a field ring and junction termination extension provides the device with a very wide process window. Compared to planar junction termination extension structures, the angled stepped structure with one or more tilt angles allows for a uniform distribution of the edge electric field intensity across multiple three-dimensional structures, resulting in higher breakdown voltage and excellent forward conduction and reverse turn-off characteristics. Simultaneously, the angled structure does not consume chip area, effectively reducing chip size and lowering costs.

[0027] In one implementation, the second conductivity type junction field ring 1022 terminates in the flat region along a first direction. This first direction is parallel to the first conductivity type semiconductor substrate 101 and points from the flat region PA to the inclined region NPA. The second conductivity type junction field ring 1022 can effectively suppress electric field spikes in the second conductivity type main junction 1021. In an optional implementation, the number of second conductivity type junction field rings 1022 is greater than or equal to three. For ease of description in subsequent embodiments, the embodiments of this invention are all described with the number of second conductivity type junction field rings 1022 being three. It is understood that the number of second conductivity type junction field rings 1022 can be set according to the specific voltage withstand requirements of the power device and is not limited here.

[0028] In one implementation, along the first direction, the distance between the second conductivity type main junction 1021 and its adjacent second conductivity type junction field ring 1022 is d0, and the distance between two adjacent second conductivity type junction field rings 1022 gradually increases, but is not less than d0. In an optional implementation, 0.5μm≤d0≤5μm. Within the range allowed by the process, the smaller the value of d0, the higher the breakdown voltage of the device. However, if the value of d0 is too large, the second conductivity type junction field ring 1022 cannot effectively suppress the electric field spikes of the main junction, and the device will be broken down before the edge of the depletion region reaches the next second conductivity type junction field ring 1022.

[0029] As an optional implementation, along the first direction, the width of each of the second conductivity type junction rings 1022 can be the same or approximately the same to provide a more uniform peak electric field. In this invention, "approximately the same" means that, within a certain allowable process error range, there are slight differences in the width between the individual second conductivity type junction rings 1022. The specific differences depend on the precision of the mask and the degree of control over the diffusion process. As a preferred implementation, along the first direction, the width of the second conductivity type junction ring 1022 can be 3μm-6μm. It is understood that the specific width value of each second conductivity type junction ring 1022 can be set according to the specific voltage withstand requirements of the power device and is not limited here.

[0030] As an optional implementation, the doping concentration of the second conductivity type junction field ring 1022 can be the same or approximately the same to provide a more uniform peak electric field, thereby improving the breakdown voltage of the junction termination structure. In this invention, "approximately the same" means that within a certain allowable process error range, there are slight differences in the doping concentration among the individual second conductivity type junction field rings 1022. The specific differences depend on the precision of the mask and the degree of accurate control of the diffusion process. As a preferred implementation, when the number of second conductivity type junction field rings 1022 is 3, the doping concentration ratio of each second conductivity type junction field ring 1022 is 1:1:1.

[0031] As an optional implementation method, Figure 2 This is a cross-sectional schematic diagram of a power device 200 with a beveled wide process window according to the present invention. Figure 2 As shown, along a first direction, the height of two adjacent second conductivity type junction field rings 2022 gradually increases. This first direction is parallel to the first conductivity type semiconductor substrate 201 and points from the flat region PA to the inclined region NPA. The height of the second conductivity type junction field ring 2022 refers to its dimension h along the direction perpendicular to the first conductivity type semiconductor substrate 201. This incremental field ring arrangement improves the uniformity of the electric field distribution and is more conducive to increasing the voltage breakdown value. In a preferred embodiment, when the number of second conductivity type junction field rings 1022 is 3, the ratio of h1:h2:h3 is 1:2:3.

[0032] As an optional implementation, the doping concentration of the second conductivity type well region is lower than that of the second conductivity type junction field ring. The second conductivity type well region can further adjust the electric field distribution. Under the same device area, the hybrid structure of junction field ring and well region can share more voltage, and the presence of the second conductivity type well region can, to some extent, eliminate the adverse effects of implanted ion diffusion and improve the overall stability of the device. At the same time, the first JTE structure located in the flat region PA can improve the breakdown voltage of low doping, and the second JTE structure located in or mainly in the tilted region NPA can improve the breakdown voltage of high doping. The present invention uses the above two hybrid structures to have a better process window while saving device area, and at the same time improves the breakdown voltage of low and high doping concentrations.

[0033] As an optional implementation, the width of the second conductivity type well region located in the inclined region gradually decreases along the first direction, which is parallel to the first conductivity type semiconductor substrate and points from the flat region to the inclined region. By employing an angled configuration, the electric field distribution is more uniform during JTE breakdown, and the device withstands a higher electric field. During ion implantation, a variable-width JTE structure can be formed at the angle, significantly increasing the total space charge region width on the inclined surface. This reduces the surface electric field of the device, decreasing the likelihood of device breakdown occurring at the edge, thereby improving the reverse breakdown voltage.

[0034] As an optional implementation, the first included angle is 40° < α < 60°. The first included angle can be formed using an orthogonal beveling technique. Preferably, to reduce the surface roughness and chips on the SiC bevel, the first included angle α = 45°. Furthermore, to eliminate cutting damage and reduce leakage current, the bevel can be subjected to a reactive ion etching (RIE) treatment of approximately 0.3 μm. As an optional implementation, the first included angle does not need to be a fixed value. Figure 3 This is a cross-sectional schematic diagram of a power device 300 with a beveled wide process window according to the present invention. Along the first direction, the size of the first included angle gradually decreases. That is, as... Figure 3 As shown, α2 > α1. Since the electric field of a right-angled platform structure tends to concentrate at the bottom of the platform, resulting in a lower breakdown voltage, a rounded platform structure, based on the angled design, can more effectively improve the local concentration of the electric field.

[0035] As an optional implementation method, Figure 4 This is a cross-sectional schematic diagram of a power device 400 with a beveled wide process window according to the present invention. Figure 4 As shown, a first insulating layer 405 is provided on the side of the first conductive semiconductor epitaxial layer 402 away from the first conductive semiconductor substrate 401. The first insulating layer 405 at least partially covers the first surface FS. The projection of the first insulating layer 405 on the first conductive semiconductor substrate 401 overlaps with the projection of the second electrode layer 404 on the first conductive semiconductor substrate 401.

[0036] As an optional implementation, a first field plate structure 406 is provided on the side of the first insulating layer 405 away from the first conductivity type semiconductor substrate 401, and the projection of the first field plate structure 406 on the first conductivity type semiconductor epitaxial layer 402 at least partially overlaps with the flat region PA. The first field plate structure 406 can further homogenize the electric field. As a preferred implementation, the width of the first field plate structure 406 along the first direction can be selected to be 15μm-50μm.

[0037] As an optional implementation, the first conductivity type semiconductor is an N-type semiconductor, the second conductivity type semiconductor is a P-type semiconductor, the second conductivity type junction field ring is a P+ junction field ring, and the second conductivity type well region is a P-well. Alternatively, the first conductivity type semiconductor can also be a P-type semiconductor; in this case, the second conductivity type semiconductor should be an N-type semiconductor, and the corresponding device structure will be adjusted accordingly.

[0038] Figure 5 This is a schematic diagram of the process steps for a power device 500 with a beveled wide process window according to the present invention. Figure 5 As shown, the present invention also provides a method for manufacturing a power device 500 with a beveled wide process window, comprising the following steps:

[0039] like Figure 5 As shown in (a), a first conductivity type semiconductor substrate 501 is provided; a first conductivity type semiconductor epitaxial layer 502 is epitaxially formed on one side of the first conductivity type semiconductor substrate 501.

[0040] like Figure 5 As shown in (b), a bevel is formed on one side of the first surface FS of the first conductivity type semiconductor epitaxial layer 502. The first surface FS of the first conductivity type semiconductor epitaxial layer 502 is the side surface of the first conductivity type semiconductor epitaxial layer 502 away from the first conductivity type semiconductor substrate 501. The first surface FS includes a flat region PA and an inclined region NPA located on one side of the flat region PA and connected to the flat region PA. As a feasible implementation, the process for forming the bevel can be an orthogonal beveling technique or a direct etching process. Any process that can form the bevel can be used in the manufacturing method of the bevel-type wide process window power device 500 involved in this invention, and is not specifically limited here.

[0041] like Figure 5 As shown in (c), a second conductivity type main junction 5021 and a plurality of second conductivity type junction field rings 5022 are formed by high-temperature ion implantation on the side of the flat region PA away from the inclined region NPA.

[0042] like Figure 5 As shown in (d), a second conductivity type well region 5023 is formed on the first surface FS by high-temperature ion implantation, and at least a portion of the second conductivity type junction field ring 5022 and the second conductivity type well region 5023 are alternately arranged.

[0043] like Figure 5As shown in (e), a first electrode layer 503 is deposited on the surface of the first conductivity type semiconductor substrate 501 on the side away from the first conductivity type semiconductor epitaxial layer 502; and a second electrode layer 504 is deposited on the side of the first conductivity type semiconductor epitaxial layer 502 away from the first conductivity type semiconductor substrate 501.

[0044] Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A power device with a sloping wide process window, characterized in that, include: First conductivity type semiconductor substrate; A first conductivity type semiconductor epitaxial layer located on one side of the first conductivity type semiconductor substrate; The first surface of the first conductivity type semiconductor epitaxial layer is provided with a second conductivity type main junction and a plurality of second conductivity type junction field rings and a plurality of second conductivity type well regions spaced apart, wherein at least a portion of the second conductivity type junction field rings and the second conductivity type well regions are alternately arranged; wherein, the first surface of the first conductivity type semiconductor epitaxial layer is the side surface of the first conductivity type semiconductor epitaxial layer away from the first conductivity type semiconductor substrate; The first surface includes a flat region and an inclined region located on one side of the flat region and connected to the flat region, and the second conductivity type main junction is located on the side of the flat region away from the inclined region; The first electrode layer is located on the side of the first conductivity type semiconductor substrate away from the first conductivity type semiconductor epitaxial layer; The second electrode layer is located on the side of the first conductivity type semiconductor epitaxial layer away from the first conductivity type semiconductor substrate, and the projection of the second electrode layer on the first conductivity type semiconductor substrate is located within the projection of the second conductivity type main junction on the first conductivity type semiconductor substrate. There is at least a first angle between the inclined region of the first surface and the second surface of the first conductivity type semiconductor epitaxial layer, the first angle... The second surface of the first conductivity type semiconductor epitaxial layer is the side surface of the first conductivity type semiconductor epitaxial layer that is close to the first conductivity type semiconductor substrate.

2. The power device with a sloping wide process window as described in claim 1, characterized in that, Along the first direction, the width of the second conductivity type well region located in the inclined region gradually decreases. The first direction is parallel to the first conductivity type semiconductor substrate and points from the flat region to the inclined region.

3. The power device with a sloping wide process window as described in claim 1, characterized in that, The doping concentration of the well region of the second conductivity type is lower than the doping concentration of the junction field ring of the second conductivity type.

4. The power device with a sloping wide process window as described in claim 1, characterized in that, Along a first direction, the second conductivity type junction field ring terminates at the flat region, the first direction being parallel to the first conductivity type semiconductor substrate and pointing from the flat region toward the inclined region.

5. The power device with a sloping wide process window as described in claim 4, characterized in that, Along the first direction, the distance between the second conductivity type main junction and its adjacent second conductivity type junction field ring is d0, and the distance between two adjacent second conductivity type junction field rings gradually increases and is not less than d0.

6. The power device with a sloping wide process window as described in claim 1, characterized in that, The first included angle .

7. The power device with a beveled wide process window as described in claim 1, characterized in that, A first insulating layer is provided on the side of the first conductivity type semiconductor epitaxial layer away from the first conductivity type semiconductor substrate. The first insulating layer at least partially covers the first surface. The projection of the first insulating layer on the first conductivity type semiconductor substrate overlaps with the projection of the second electrode layer on the first conductivity type semiconductor substrate.

8. The power device with a beveled wide process window as described in claim 7, characterized in that, The first insulating layer has a first field plate structure on the side away from the first conductivity type semiconductor substrate, and the projection of the first field plate structure on the first conductivity type semiconductor epitaxial layer at least partially overlaps with the flat region.

9. A power device with a sloping wide process window as described in claim 1, characterized in that, The first type of semiconductor is an N-type semiconductor, the second type of semiconductor is a P-type semiconductor, the second type of junction field ring is a P+ junction field ring, and the second type of well region is a P-well.

10. A method for manufacturing a power device with a sloping wide process window, characterized in that, Includes the following steps: Provide a semiconductor substrate of the first conductivity type; A first conductivity type semiconductor epitaxial layer is formed on one side of the first conductivity type semiconductor substrate; An inclined surface is formed on one side of the first surface of the first conductive type semiconductor epitaxial layer. The first surface of the first conductive type semiconductor epitaxial layer is the side surface of the first conductive type semiconductor epitaxial layer away from the first conductive type semiconductor substrate. The first surface includes a flat region and an inclined region located on one side of the flat region and connected to the flat region. On the side of the flat region away from the inclined region, a second conductivity type main junction and multiple spaced second conductivity type junction field rings are formed by high-temperature ion implantation. A second conductivity type well region is formed on the first surface by high-temperature ion implantation, and at least a portion of the second conductivity type junction field ring is alternately arranged with the second conductivity type well region; A first electrode layer is deposited on the surface of the first conductivity type semiconductor substrate on the side away from the first conductivity type semiconductor epitaxial layer; A second electrode layer is deposited on the side of the first conductivity type semiconductor epitaxial layer away from the first conductivity type semiconductor substrate.

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