A SLVS-EC serial decoding method based on FPGA

Abstract

The present invention discloses a FPGA-based SLVS-EC serial decoding method. The method receives N-channel SLVS-EC high-speed serial data through the FPGA's hard-core GT to obtain N-channel parallel data. The method then converts the data bit width to half, while still outputting N-channel parallel data. The method detects control codes in the data and identifies valid data. The method also removes pad codes from the data and simultaneously performs channel alignment. The method also removes ECC error correction codes from the data. The method converts bytes into pixels, reducing the data bit width. The method parses the packet header to obtain packet header information. Timing parameters are obtained based on the packet header information. Based on the timing parameters, a timing generator generates an XSVI timing sequence. The method then caches the data, matches the data with the XSVI timing sequence, and converts the data into N / 2-channel parallel data. The method solves the problem that existing decoding methods cannot complete SLVS-EC encoding and decoding.

Description

Technical Field

[0001] The present invention belongs to the technical field of decoding methods, and in particular relates to a SLVS-EC serial decoding method based on FPGA. Background Art

[0002] SLVS-EC coding is Sony's next-generation high-speed interface for CMOS image sensors. It features high bandwidth, low power consumption, and strong noise and interference immunity, making it suitable for high-speed and long-distance transmission.

[0003] With the increasing adoption of high-frame-rate, high-resolution CMOS image sensors, SLVS-EC has replaced Sub-LVDS and SLVS as the interface of choice for high-speed designs. Companies like FRAMOS and CIS currently offer mature SLVS-EC RX IP, but these are available for purchase. Some industry peers are also developing SLVS-EC serial decoding, but none have yet provided practical design solutions. Therefore, there is an urgent need for an interface that can receive SLVS-EC high-speed serial data from Sony CMOS image sensors, decode the data, and convert it into parallel data output. However, existing basic decoding methods are unable to effectively decode SLVS-EC encoding. Summary of the Invention

[0004] To address the above issues, the present invention proposes an FPGA-based SLVS-EC serial decoding method, which receives SLVS-EC high-speed serial data from an image sensor, decodes the data, and converts it into parallel data output, thus resolving the problem that existing decoding methods cannot complete SLVS-EC encoding and decoding.

[0005] To achieve the above object, the technical solution adopted by the present invention is: a method for implementing SLVS-EC serial decoding based on FPGA, comprising the steps of:

[0006] S10, receives the N-channel SLVS-EC high-speed serial data through the FPGA's hard core GT to obtain N-channel parallel data;

[0007] S20, convert the data bit width into half, and the output is still N-channel parallel data;

[0008] S30, detecting the control code in the data and identifying the valid data;

[0009] S40, removing the Pad code in the data and completing the channel alignment function at the same time;

[0010] S50, removing the ECC error correction code in the data;

[0011] S60, converting bytes into pixels, and reducing the data bit width;

[0012] S70, performing packet header analysis to obtain packet header information;

[0013] S80, obtaining timing parameters according to the packet header information;

[0014] S80, generating an XSVI timing using a timing generator based on the timing parameters;

[0015] S90 performs data caching, matches the data obtained in S60 with the XSVI timing, and converts it into N / 2 channel parallel data.

[0016] Furthermore, the 8-channel SLVS-EC high-speed serial data is received through the FPGA's hard-core GT to obtain 8-channel parallel data with a data bit width of 16 bits.

[0017] Furthermore, the FPGA's hard-core GT is called to complete the reception of 8-channel SLVS-EC high-speed serial data, using the 8-channel GT_CHANNEL of two adjacent BANK groups; clock correction and channel bonding are enabled.

[0018] Furthermore, the data bit width is converted from 16 bits to 8 bits, and the output is still 8-channel parallel data.

[0019] Furthermore, the control code in the detection data includes a start code, a pad code and an end code, and identifies valid data.

[0020] Furthermore, the Pad encoding in the data is removed and implemented using a row cache, while also completing the channel alignment function.

[0021] Furthermore, when removing the ECC error correction code from the data: first detect the ECC error correction code in the data, identify valid data, and finally remove the ECC error correction code through the row buffer.

[0022] Furthermore, bytes are converted into pixels, and the pixel width is dynamically configured; the output data width is fixed to 12 bits. When the pixel width is less than 12 bits, the valid data is located in the high order of the 12 bits.

[0023] Furthermore, in the output timing generator, the line period is kept consistent with the sensor output line period, and the vertical resolution is dynamically and adaptively adjusted.

[0024] The beneficial effects of adopting this technical solution are:

[0025] The present invention first receives SLVS-EC high-speed serial data through the FPGA's hard-core GT to obtain parallel data; then performs bit width conversion; detects control codes; removes pad codes from the data while simultaneously performing channel alignment; removes ECC error correction codes from the data; converts bytes into pixels; obtains timing parameters based on the obtained packet header information, and uses a timing generator based on the timing parameters to generate XSVI timing; and then matches the obtained data with the XSVI timing to complete decoding. The present invention's serial decoding method for SLVS-EC encoding can effectively complete SLVS-EC encoding decoding and obtain highly reliable decoding results. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 This is a flow chart of a method for implementing SLVS-EC serial decoding based on FPGA according to the present invention;

[0027] Figure 2 Schematic diagram of the channel bonding principle in an embodiment of the present invention;

[0028] Figure 3 This is a schematic diagram of outputting a valid data mark after detecting a control code in an embodiment of the present invention;

[0029] Figure 4 This is a schematic diagram of the output after the Pad code is removed and the channel alignment is completed in an embodiment of the present invention;

[0030] Figure 5 Schematic diagram of the principle of valid identification of data after detecting ECC error correction code in an embodiment of the present invention;

[0031] Figure 6 Schematic diagram of pixel bit width conversion to 10 bits in an embodiment of the present invention;

[0032] Figure 7 Schematic diagram of pixel bit width 12-bit conversion in an embodiment of the present invention;

[0033] Figure 8 This is a timing diagram of the timing generator output in an embodiment of the present invention. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is further described below with reference to the accompanying drawings.

[0035] In this embodiment, see Figure 1 As shown, the present invention proposes a method for implementing SLVS-EC serial decoding based on FPGA, comprising the steps of:

[0036] S10: Receive the 8-channel SLVS-EC high-speed serial data through the FPGA's hard-core GT to obtain 8-channel parallel data with a data width of 16 bits.

[0037] S20, convert the data bit width from 16 bits to 8 bits, and the output is still 8-channel parallel data;

[0038] S30, detecting the control codes in the data including the start code, pad code and end code, and identifying the valid data;

[0039] S40, removing the Pad code in the data and completing the channel alignment function at the same time;

[0040] S50, removing the ECC error correction code in the data;

[0041] S60, converting bytes into pixels, and reducing the data bit width;

[0042] S70, performing packet header analysis to obtain packet header information;

[0043] S80, obtaining timing parameters according to the packet header information;

[0044] S80, generating an XSVI timing using a timing generator based on the timing parameters;

[0045] S90 performs data caching, matches the data obtained in S60 with the XSVI timing, and converts it into N / 2 channel parallel data.

[0046] As an optimization solution for the above embodiment, the FPGA's hard core GT is used to complete the reception of 8-way SLVS-EC high-speed serial data, using 8-channel GT_CHANNEL of two adjacent BANK groups; clock correction and channel bonding are enabled. The channel bonding composition is shown as follows: Figure 2 As shown in the figure, GT0 is used as the controller and GT1 to GT7 are used as the controlled ones.

[0047] As an optimization solution of the above embodiment, the control code in the detection data includes a start code, a pad code and an end code, and identifies valid data; taking a CMOS image sensor with a line period of 1944 and a pixel width of 10 bits as an example, the valid data identification is as follows: Figure 3 shown.

[0048] Remove the Pad code in the data and use the line buffer to achieve it, while completing the channel alignment function. Reduce resource consumption. Taking the CMOS image sensor with a line period of 1944 and a pixel width of 10 bits as an example, the output is as follows Figure 4 shown.

[0049] As an optimization solution of the above embodiment, when removing the ECC error correction code in the data: first detect the ECC error correction code in the data and identify the valid data, and finally remove the ECC error correction code through the line buffer. Taking the CMOS image sensor with a line period of 1944 and a pixel width of 10 bits as an example, the data valid identification is as follows: Figure 5 shown.

[0050] As an optimization solution for the above embodiment, bytes (8 bits) are converted into pixels (8 / 10 / 12 bits), and the pixel width is dynamically configured; the output data width is fixed to 12 bits. When the pixel width is less than 12 bits, the valid data is located in the high bit of 12 bits.

[0051] Taking the CMOS image sensor line period of 1944 as an example, the pixel width is 8 bits and is directly output.

[0052] When the pixel width is 10 bits, the conversion is as follows Figure 6 shown.

[0053] When the pixel width is 12 bits, the conversion is as follows Figure 7 shown.

[0054] As an optimization solution of the above embodiment, in the output timing generator, the line period is consistent with the sensor output line period, and the vertical resolution is dynamically and adaptively adjusted. Figure 8 shown.

[0055] The basic principles, main features, and advantages of the present invention are shown and described above. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions are merely illustrative of the principles of the present invention. Various changes and modifications may be made to the present invention without departing from the spirit and scope of the present invention. Such changes and modifications are intended to fall within the scope of the present invention. The scope of protection claimed in the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for implementing SLVS-EC serial decoding based on FPGA, characterized in that: Including steps: S10, receives the N-channel SLVS-EC high-speed serial data through the FPGA's hard-core GT to obtain N-channel parallel data; S20, convert the data bit width into half, and the output is still N-channel parallel data; S30, detecting the control code in the data and identifying the valid data; S40, removing the Pad code in the data and completing the channel alignment function at the same time; S50, removing the ECC error correction code in the data; S60, converting bytes into pixels, and reducing the data bit width; S70, performing packet header analysis to obtain packet header information; S80, obtaining timing parameters according to the packet header information; S80, generating an XSVI timing using a timing generator based on the timing parameters; S90 performs data caching, matches the data obtained in S60 with the XSVI timing, and converts it into N / 2 channel parallel data.

2. The method for implementing SLVS-EC serial decoding based on FPGA according to claim 1, characterized in that: The 8-channel SLVS-EC high-speed serial data is received through the FPGA's hard-core GT to obtain 8-channel parallel data with a data width of 16 bits.

3. The method for implementing SLVS-EC serial decoding based on FPGA according to claim 2, wherein: The FPGA's hard-core GT is used to receive 8 channels of SLVS-EC high-speed serial data. The 8-channel GT_CHANNEL in two adjacent banks is used. Clock correction and channel bonding are enabled.

4. The method for implementing SLVS-EC serial decoding based on FPGA according to claim 2, wherein: Convert the data bit width from 16 bits to 8 bits, and the output is still 8-channel parallel data.

5. The method for implementing SLVS-EC serial decoding based on FPGA according to any one of claims 1 to 3, characterized in that: The control codes in the detection data include start code, pad code and end code, and identify valid data.

6. The method for implementing SLVS-EC serial decoding based on FPGA according to claim 5, characterized in that: Remove the pad encoding from the data, use the row cache to implement it, and complete the channel alignment function at the same time.

7. The method for implementing SLVS-EC serial decoding based on FPGA according to claim 6, characterized in that: When removing the ECC error correction code from the data: first detect the ECC error correction code in the data, identify the valid data, and finally remove the ECC error correction code through the row buffer.

8. The method for implementing SLVS-EC serial decoding based on FPGA according to claim 4, characterized in that: Convert bytes to pixels, and dynamically configure the pixel width. The output data width is fixed at 12 bits. When the pixel width is less than 12 bits, the valid data is located in the high order of the 12 bits.

9. The method for implementing SLVS-EC serial decoding based on FPGA according to claim 1, characterized in that: In the output timing generator, the line period is consistent with the sensor output line period, and the vertical resolution is dynamically and adaptively adjusted.

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