Display substrate and display device

Abstract

A display substrate and a display panel. The display substrate comprises: a base substrate; the base substrate comprises a display area and a peripheral area located at least on one side of the display area, the peripheral area comprises a first peripheral sub-area and a second peripheral sub-area, the display area comprises a first display sub-area corresponding to the first peripheral sub-area and a second display sub-area corresponding to the second peripheral sub-area and different from the first display sub-area, the second peripheral sub-area comprises a first gate driving circuit, the first gate driving circuit is configured to be connected to a plurality of gate scanning signal lines located in the first display sub-area through a plurality of connecting lines located in the display area, so as to respectively provide gate scanning signals to a plurality of rows of pixel units located in the first display sub-area; the first peripheral sub-area does not comprise the first gate driving circuit. The display substrate can narrow the width of the first peripheral sub-area, and reduce stress concentration when the peripheral sub-area is bent.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display substrate and a display device. Background Art

[0002] With the continuous improvement of consumers' sensory demands for display screens and the continuous advancement of manufacturing technology in the display panel industry, curved screens and curved displays have become one of the hottest technologies in the current display industry. For example, forming curved surfaces on the edges of display devices such as mobile phones and tablets can visually increase the display range of the display device, such as achieving a full-screen display effect and improving the user's sensory experience. Summary of the invention

[0003] At least one embodiment of the present disclosure provides a display substrate, comprising: a base substrate, comprising a display area and a peripheral area located on at least one side of the display area, the display area comprising a plurality of rows and columns of pixel units arranged in an array, a plurality of gate scanning signal lines respectively connected to the plurality of rows of pixel units, and a plurality of connecting wires located at different layers from the plurality of gate scanning signal lines; the peripheral area comprising a first peripheral sub-area and a second peripheral sub-area, the display area comprising a first display sub-area corresponding to the first peripheral sub-area and a second display sub-area corresponding to the second peripheral sub-area and different from the first display sub-area; the second peripheral sub-area comprises a first gate driving circuit, the first gate driving circuit being configured to be connected to the plurality of gate scanning signal lines located in the first display sub-area through the plurality of connecting wires located in the display area, so as to respectively provide gate scanning signals to the plurality of rows of pixel units located in the first display sub-area; the first peripheral sub-area does not include the first gate driving circuit.

[0004] For example, in the display substrate provided in at least one embodiment of the present disclosure, the second peripheral sub-region also includes a second gate driving circuit, and the second gate driving circuit is configured to be connected to a plurality of gate scanning signal lines located in the second display sub-region to respectively provide the gate scanning signals to a plurality of rows of pixel units located in the second display sub-region; the first peripheral sub-region does not yet include the second gate driving circuit.

[0005] For example, in the display substrate provided in at least one embodiment of the present disclosure, each of the multiple connecting lines includes a first line extending along a first direction and a second line extending along a second direction, and the first direction and the second direction intersect; the first gate drive circuit is connected to the first line through the second line, and the first line is connected to the corresponding gate scan signal line located in the first display sub-area through a via penetrating the insulating layer to provide the gate scan signal to the corresponding gate scan signal line.

[0006] For example, in the display substrate provided by at least one embodiment of the present disclosure, when the second routing overlaps with the first routing of other connecting routings, the second routing includes at least one switching electrode and multiple connecting electrodes, the connecting electrode and the first routing are located in the same layer, and the at least one switching electrode and the multiple connecting electrodes are located in different layers; the at least one switching electrode and the first routing of the other connecting routing at least partially overlap in a direction perpendicular to the base substrate; the multiple connecting electrodes are connected to the at least one switching electrode through vias penetrating the insulating layer to form the second routing.

[0007] For example, in the display substrate provided in at least one embodiment of the present disclosure, the orthographic projection of the first wiring on the base substrate is located between the orthographic projections of two adjacent columns of sub-pixels in the display area on the base substrate.

[0008] For example, in the display substrate provided in at least one embodiment of the present disclosure, the orthographic projection of the second wiring on the base substrate is located between the orthographic projections of two adjacent rows of sub-pixels in the display area on the base substrate.

[0009] For example, in the display substrate provided in at least one embodiment of the present disclosure, the display area also includes a plurality of first voltage lines, which are respectively connected to the plurality of columns of pixel units and extend along the first direction to respectively provide a first voltage to the plurality of columns of pixel units, and the orthographic projection of the first wiring line on the substrate and the orthographic projection of the corresponding first voltage line on the substrate at least partially overlap.

[0010] For example, in the display substrate provided in at least one embodiment of the present disclosure, the display area also includes a plurality of initial signal lines, which are respectively connected to the plurality of rows of pixel units and extend along the second direction to respectively provide initial voltages to the plurality of rows of pixel units, and the orthographic projection of the second line on the base substrate and the orthographic projection of the corresponding initial signal line on the base substrate at least partially overlap.

[0011] For example, in the display substrate provided in at least one embodiment of the present disclosure, each of the multiple rows and columns of pixel units includes a light-emitting element and a pixel circuit for driving the light-emitting element to emit light, and the pixel circuit includes a driving subcircuit, a data writing subcircuit, a threshold compensation subcircuit and a reset subcircuit; the driving subcircuit includes a control end, a first end and a second end, and is configured to control a driving current flowing through the light-emitting element, the data writing subcircuit is connected to the first end of the driving subcircuit, the data line and the gate scanning signal line, and is configured to write the data signal provided by the data line into the first end of the driving subcircuit in response to the gate scanning signal provided by the gate scanning signal line; the threshold compensation subcircuit is connected to the control end and the second end of the driving subcircuit, the first voltage line and the gate scanning signal line, and is configured to compensate the driving subcircuit in response to the gate scanning signal provided by the gate scanning signal line and the written data signal; the reset subcircuit is connected to the second end of the driving subcircuit, the initial signal line and the reset signal line, and is configured to apply the initial voltage provided by the initial signal line to the second end of the driving subcircuit in response to the reset signal provided by the reset signal line.

[0012] For example, the display substrate provided by at least one embodiment of the present disclosure also includes a semiconductor layer, a first conductive layer, a second conductive layer and a third conductive layer stacked in sequence in a direction perpendicular to the base substrate; the pixel circuit includes a thin film transistor and a storage capacitor; the thin film transistor includes a gate, a source, a drain and a source-drain region corresponding to the source and the drain, and the storage capacitor includes a first capacitor electrode and a second capacitor electrode opposite to the first capacitor electrode in a direction perpendicular to the board surface of the base substrate; the semiconductor layer includes the source-drain region; the first conductive layer includes the gate of the thin film transistor, the first capacitor electrode of the storage capacitor and the gate scanning signal line, the second conductive layer includes the initial signal line and the second capacitor electrode of the storage capacitor; the third conductive layer includes the first voltage line and, the source and the drain.

[0013] For example, the display substrate provided in at least one embodiment of the present disclosure further includes a fourth conductive layer, and the fourth conductive layer includes the at least one switching electrode.

[0014] For example, the display substrate provided in at least one embodiment of the present disclosure further includes a fifth conductive layer, and the fifth conductive layer includes the first wiring and the second wiring.

[0015] For example, in the display substrate provided in at least one embodiment of the present disclosure, each row of pixel units in the first display sub-area is arranged in a step-like manner in the first direction.

[0016] For example, in the display substrate provided in at least one embodiment of the present disclosure, the number of pixel units in each row in the first display sub-region is less than or equal to the number of pixel units in each row in the second display sub-region.

[0017] At least one embodiment of the present disclosure further provides a display device, comprising the display substrate as described in any of the above embodiments.

[0018] For example, in the display device provided in at least one embodiment of the present disclosure, the peripheral area of ​​the display substrate also includes a third peripheral sub-area, the first peripheral sub-area is located between the second peripheral sub-area and the third peripheral sub-area; the second peripheral sub-area has a first straight line edge portion extending along a first direction, the third peripheral sub-area has a second straight line edge portion extending along a second direction, and the first peripheral sub-area has a corner edge portion connecting the first straight line edge portion and the second straight line edge portion; the first direction and the second direction intersect.

[0019] For example, in the display device provided in at least one embodiment of the present disclosure, the display substrate has a display side and a non-display side, and the first straight line edge portion and the second straight line edge portion are configured to be bendable toward the non-display side.

[0020] For example, in the display device provided by at least one embodiment of the present disclosure, the corner edge portion includes an arc-shaped edge portion.

[0021] For example, in the display device provided in at least one embodiment of the present disclosure, the display substrate has a display side and a non-display side, and the corner edge portion is configured to be bendable toward the non-display side. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0023] Figure 1A A schematic plan view of a display substrate is shown;

[0024] Figure 1B Shows Figure 1A A schematic cross-sectional view of a display substrate along line MM;

[0025] Figure 2 A schematic plan view of a display substrate provided for some embodiments of the present disclosure;

[0026] Figure 3 A schematic diagram of a corner area of ​​a display substrate provided for some embodiments of the present disclosure;

[0027] Figure 4 A schematic cross-sectional view of a switching electrode and a connecting electrode provided in some embodiments of the present disclosure;

[0028] Figure 5 A schematic diagram of a partial layout of a display area provided for some embodiments of the present disclosure;

[0029] Figure 6 An equivalent circuit diagram of a pixel circuit in a display substrate provided in some embodiments of the present disclosure;

[0030] Fig. 7A A schematic diagram of the stacking position relationship of the semiconductor layer, the first conductive layer, the second conductive layer and the third conductive layer of the pixel circuit provided in some embodiments of the present disclosure;

[0031] Figure 7B A schematic diagram showing a semiconductor layer of a pixel circuit provided by some embodiments of the present disclosure;

[0032] Figure 7C A schematic diagram showing a first conductive layer of a pixel circuit provided in some embodiments of the present disclosure is shown;

[0033] Fig.7D A schematic diagram showing a second conductive layer of a pixel circuit provided in some embodiments of the present disclosure is shown;

[0034] Fig. 7E A schematic diagram showing a third conductive layer of a pixel circuit provided in some embodiments of the present disclosure is shown;

[0035] Figure 7F A schematic diagram showing a fourth conductive layer of a pixel circuit provided in some embodiments of the present disclosure is shown;

[0036] Figure 7G A schematic diagram showing a fifth conductive layer of a pixel circuit provided in some embodiments of the present disclosure is shown;

[0037] Figure 7H A schematic diagram showing the stacking position relationship of a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer of a pixel circuit provided by some embodiments of the present disclosure;

[0038] Figure 8 A partial cross-sectional schematic diagram showing another stacked structure of a pixel circuit provided by an embodiment of the present disclosure;

[0039] Fig. 9 A schematic diagram of a display panel provided for at least one embodiment of the present disclosure; and

[0040] Fig.10 A schematic block diagram of another display device provided for some embodiments of the present disclosure. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0042] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0043] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components.

[0044] Figure 1A A schematic plan view of a display substrate is shown, Figure 1A As shown, the display substrate has a display area 11 and a peripheral area 12 surrounding the display area 11. The display area 11 includes a plurality of sub-pixels arranged in an array for display. The peripheral area 12 has a driving circuit and other structures for driving the plurality of sub-pixels in the display area 11 for display.

[0045] For example, Figure 1B Shows Figure 1A A schematic cross-sectional view of the display substrate along line MM in FIG. Figure 1B As shown, the display substrate can be formed by placing the peripheral area 12 toward the non-display side ( Figure 1A The side of the paper facing away from the paper, Figure 1B The display area 11 is curved by bending the peripheral area 12 to realize the curved display around the display area 11. For example, when the peripheral area 12 is curved, the corner part 13 of the peripheral area 12 is prone to generate large stress, and then wrinkles and other defects are prone to occur in the corner part 13, which greatly affects the product yield.

[0046] In order to reduce the wrinkle problem of the display substrate when it is bent at the periphery, a larger corner angle can be set at the corner part 13, and the frame width of the corner part can be reduced. The large angle and the narrow frame of the corner part can reduce the stress concentration when the four sides of the display panel are bent, and improve the yield of the four-sided curved product. However, since the peripheral area usually needs to be provided with a display driving circuit, and a certain packaging area needs to be reserved in the peripheral area, it is not easy to realize the design of a narrow frame at the corner part. For example, for an OLED (Organic Light-Emitting Display) display panel, due to the limitation of the characteristics of its organic film layer such as easy water absorption, a certain area of ​​packaging needs to be guaranteed at the corner part, and the packaging area is, for example, 300 to 400 μm (micrometers), and when the frame width of the OLED display panel is 400 to 600 μm, the corner part 13 does not have enough space for placing the display driving circuit, thereby increasing the difficulty of realizing the narrow frame of the four-sided curved product, which is not conducive to the improvement of the yield of the four-sided curved product.

[0047] At least one embodiment of the present disclosure provides a display substrate and a display device, wherein the display substrate includes a base substrate, the base substrate includes a display area and a peripheral area located on at least one side of the display area, the display area includes a plurality of rows and columns of pixel units arranged in an array, a plurality of gate scanning signal lines respectively connected to the plurality of rows of pixel units, and a plurality of connecting wires located at different layers from the plurality of gate scanning signal lines; the peripheral area includes a first peripheral sub-area and a second peripheral sub-area, the display area includes a first display sub-area corresponding to the first peripheral sub-area and a second display sub-area corresponding to the second peripheral sub-area and different from the first display sub-area; the second peripheral sub-area includes a first gate driving circuit, the first gate driving circuit is configured to be connected to the plurality of gate scanning signal lines located in the first display sub-area through the plurality of connecting wires located in the display area, so as to provide gate scanning signals to the plurality of rows of pixel units located in the first display sub-area respectively; the first peripheral sub-area does not include the first gate driving circuit.

[0048] In the display substrate provided in the embodiment of the present disclosure, the first gate driving circuit that provides a gate scanning signal to the first display sub-region is arranged in the second peripheral sub-region corresponding to the second display sub-region, rather than being arranged in the first peripheral sub-region corresponding to the first display sub-region. This can avoid setting the first gate driving circuit (and its connecting lines) in the first peripheral sub-region, and the width of the first peripheral sub-region where the first gate driving circuit is arranged becomes narrower, which makes it easier to achieve a narrow frame, thereby reducing stress concentration during large-angle bending, improving defects such as wrinkles, and improving product yield.

[0049] For example, the first display sub-region and the first peripheral sub-region may both correspond to the corner portion of the display substrate, and the second display sub-region and the second peripheral sub-region may both correspond to the non-corner portion of the display substrate. In an embodiment of the present disclosure, by setting the gate drive circuit located in the peripheral sub-region corresponding to the corner portion in the peripheral sub-region corresponding to the non-corner portion, and connecting the gate drive circuit located in the non-corner portion to the pixel unit located in the display sub-region corresponding to the corner portion through the wiring located in the display region, the scanning drive of the pixel unit located in the display sub-region corresponding to the corner portion is realized. Since the gate drive circuit (and its connecting line) is not set in the peripheral sub-region corresponding to the corner portion, the width of the peripheral sub-region corresponding to the corner portion can be reduced, and a narrow frame of the corner portion can be realized, thereby reducing stress concentration during large-angle bending, improving defects such as wrinkles, and improving product yield.

[0050] Several embodiments of the present disclosure are described in detail below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.

[0051] Figure 2 Schematic diagram of a display substrate provided in some embodiments of the present disclosure. Figure 2 As shown, the display substrate 1 includes a base substrate 10, and the base substrate 10 includes a display area 100 and a peripheral area 200 located at at least one side of the display area 100. For example, the display area 100 includes a plurality of rows and columns of pixel units 130 arranged in an array, a plurality of gate scanning signal lines ( Figure 2 ) and a plurality of connection wirings ( Figure 2 The peripheral region 200 includes a first peripheral sub-region 210 and a second peripheral sub-region 220 , and the display region 100 includes a first display sub-region 110 corresponding to the first peripheral sub-region 210 and a second display sub-region 120 corresponding to the second peripheral sub-region 220 and different from the first display sub-region 110 .

[0052] For example, Figure 2 As shown, the peripheral region 200 of the display substrate further includes a third peripheral sub-region 230, and the first peripheral sub-region 210 is located between the second peripheral sub-region 220 and the third peripheral sub-region 230. The second peripheral sub-region 220 has a first straight edge portion 221 extending along the first direction Y, the third peripheral sub-region 230 has a second straight edge portion 231 extending along the second direction X, and the first peripheral sub-region 210 has a corner edge portion 211 connecting the first straight edge portion 221 and the second straight edge portion 231, and the first direction X intersects with the second direction Y. For example, the corner edge portion 211 includes an arc-shaped edge portion.

[0053] For example, the display substrate has a display side and a non-display side, and the first straight edge portion and the second straight edge portion are configured to be bendable toward the non-display side. The corner edge portion is configured to be bendable toward the non-display side.

[0054] For example, the second peripheral sub-region 220 includes a first gate driving circuit 310, and the first gate driving circuit 310 is configured to be connected to multiple gate scanning signal lines located in the first display sub-region 110 through multiple connecting lines located in the display area 100, so as to provide gate scanning signals to multiple rows of pixel units 130 located in the first display sub-region 110 respectively.

[0055] Figure 3 The corner area (eg Figure 2 The enlarged schematic diagram of the area corresponding to the circle C1 in FIG. Figure 2 and Figure 3 As shown, the first peripheral sub-region 210 may be a peripheral region at a corner, as shown in Figure 3 The first peripheral sub-region 210 may be arc-shaped. The second peripheral sub-region 220 corresponds to the peripheral region at the non-corner position, for example, a straight-edge region close to the first peripheral sub-region 210, as shown in FIG. Figure 3 The second peripheral sub-region 220 and the first peripheral sub-region 210 can be arranged along the first direction Y. For example, if the first peripheral sub-region 210 is the upper left corner region of the display substrate, the second peripheral sub-region 220 can be the left side region below the upper left corner region; if the first peripheral sub-region 210 is the lower left corner region of the display substrate, the second peripheral sub-region 220 can be the left side region above the lower left corner region. The peripheral region on the right is similar to this, and the embodiments of the present disclosure are not limited to this.

[0056] For example, the first display sub-area 110 may refer to Figure 3 The first display sub-area 110 corresponds to the first peripheral sub-area 210, for example, it is arranged along the second direction X with the first peripheral sub-area 210, that is, it is horizontally aligned with the first peripheral sub-area 210. Figure 3 In the display sub-region below the dividing line NN shown, the second display sub-region 120 corresponds to the second peripheral sub-region 220 , for example, is arranged along the second direction X with the second peripheral sub-region 220 , that is, is laterally aligned with the second peripheral sub-region 220 .

[0057] For example, the pixel units of each row of the first display sub-area 120 are arranged in a step-like manner in the first direction Y. For example, in order to adapt to the arc shape at the corner, the number of pixel units contained in each row of the first display sub-area 120 increases row by row starting from the first row. For example, m (m is an integer greater than 0) pixel units can be set in the first row, m+n (n is an integer greater than 0) pixel units can be set in the second row, m+2n pixel units can be set in the third row, m+3n pixel units can be set in the fourth row, and so on. It should be noted that as long as the number of pixel units in the next row is greater than or equal to the number of pixel units in the previous row, the specific number greater than can be determined according to the actual situation, and the embodiments of the present disclosure are not limited to this.

[0058] For example, Figure 3 The first display sub-region 120 shown in the figure only includes 4 rows of pixel units, and may also include more or fewer rows of pixel units, which is not limited in the embodiments of the present disclosure.

[0059] For example, the number of pixel units in each row of the first display sub-region is less than or equal to the number of pixel units in each row of the second display sub-region. For example, the number of pixel units in each row of the second display sub-region is equal, and the number of pixel units in each row of the first display sub-region 120 increases row by row until the number of pixel units in the last row of the first display sub-region 120 is less than or equal to the number of pixel units in each row of the second display sub-region, and the embodiments of the present disclosure are not limited to this.

[0060] For example, the first gate driving circuit 310 is located in the second peripheral sub-region 220 , and the first gate driving circuit 310 may include a plurality of cascaded shift register units, and each shift register unit may output a gate scanning signal.

[0061] For example, the first display sub-region 110 includes multiple rows and columns of pixel units 130, and the multiple pixel units 130 in each row are connected to at least one gate scan signal line Ga, and each gate scan signal line Ga can provide a gate scan signal for each pixel unit 130 in its row, for example, providing a gate scan signal for a data write transistor in the pixel unit. The display region includes multiple connecting wires L, and each connecting wire L can be connected to a shift register unit and a gate scan signal line Ga to transmit the gate scan signal output by the shift register unit to the gate scan signal line Ga. For example, in some examples, the number of connecting wires L, the number of gate scan signal lines Ga, and the number of rows of pixel units in the first display sub-region 110 can be equal, that is, the multiple connecting wires L can correspond one-to-one to the multiple gate scan signal lines Ga in the first display sub-region 110 and the multiple rows of pixel units in the first display sub-region 110.

[0062] In an embodiment of the present disclosure, a first gate drive circuit that provides a gate scanning signal for a first display sub-region is disposed in a second peripheral sub-region corresponding to a second display sub-region, rather than in a first peripheral sub-region corresponding to a first display sub-region. In this way, a gate drive circuit (and its connecting wires) may not be disposed in the first peripheral sub-region, and the width of the peripheral sub-region where the gate drive circuit is disposed is narrowed, so that a narrow frame can be easily realized, and stress concentration during large-angle bending can be reduced, defects such as wrinkles can be improved, and product yield can be improved. For example, the first display sub-region and the first peripheral sub-region may both correspond to a corner portion of a display substrate, and the second display sub-region and the second peripheral sub-region may both correspond to a non-corner portion of a display substrate. By disposing a gate drive circuit of a peripheral sub-region of a corner portion in a peripheral sub-region of a non-corner portion, and connecting a gate drive circuit of a peripheral sub-region corresponding to a non-corner portion to a pixel unit of a display sub-region corresponding to a corner portion through a wiring located in the display region, a scanning drive of a pixel unit of a display sub-region corresponding to a corner portion is realized. Since the gate drive circuit (and its connecting lines) are not set in the sub-region around the corner part, the width of the sub-region around the corner part can be reduced, and a narrow frame of the corner part can be achieved, which can reduce stress concentration during large-angle bending, improve defects such as wrinkles, and improve product yield.

[0063] For example, Figure 2 As shown, the second peripheral sub-region 220 also includes a second gate driving circuit 320, which is configured to be connected to multiple gate scanning signal lines located in the second display sub-region 120 to provide gate scanning signals to multiple rows of pixel units located in the second display sub-region 120 respectively.

[0064] For example, the second display sub-area 120 may also include multiple rows and columns of pixel units 130, and the multiple pixel units 130 in each row are connected to at least one gate scanning signal line Ga, and each gate scanning signal line Ga may provide a gate scanning signal to each pixel unit 130 in its row. The second gate driving circuit 320 and the first gate driving circuit 310 may be arranged along the first direction Y, and the second gate driving circuit 320 may be located, for example, at Figure 3The second gate driving circuit 320 includes a plurality of shift register units arranged along the first direction Y, each of which can output a gate driving signal, and each of which can be connected to a gate scanning signal line Ga in the second display sub-region 120. For example, in some examples, the input signal of the first-stage shift register unit of the second gate driving circuit 320 is the output signal of the last-stage shift register unit of the first gate driving circuit 310, so that the gate scanning signal can be output row by row from the first-stage shift register unit of the first gate driving circuit 310 to the gate scanning signal line connected thereto, thereby realizing row-by-row driving of the pixel units located in the display area.

[0065] For example, the first peripheral sub-region does not include the first gate driving circuit or the second gate driving circuit. The first peripheral sub-region may not be provided with any gate driving circuit, and the gate driving circuits are all provided in the peripheral sub-region corresponding to the straight edge of the display substrate, thereby reducing the width of the first peripheral sub-region.

[0066] For example, Figure 3 As shown, each of the plurality of connecting wires includes a first wire extending along a first direction Y and a second wire extending along a second direction X, and the first direction Y intersects with the second direction X. The first gate driving circuit 310 is connected to the first wire through the second wire, and the first wire is connected to the corresponding gate scanning signal line located in the first display sub-region 120 through a via hole penetrating the insulating layer to provide a gate scanning signal to the corresponding gate scanning signal line.

[0067] For example, each connecting line L may be in an inverted "L" shape, including a vertical first line L1 and a horizontal second line L2. One end of the horizontal second line L2 is connected to the first gate drive circuit 310, and the other end is connected to the vertical first line L1. One end of the first line L1 is connected to the second line L2, and the other end is connected to the corresponding gate scan signal line. In a direction perpendicular to the substrate, the connecting line L and the gate scan signal line Ga may be located in different layers. For example, the gate scan signal line Ga may be located in the first conductive layer (as shown below). Figure 7C As shown), the connecting trace L can be located in the fourth conductive layer (as shown below Figure 7F As shown), an insulating layer is provided between the first conductive layer and the fourth conductive layer, and a via hole may be provided on the insulating layer at a position overlapping with the gate scanning signal line Ga and the connecting wiring L, and the gate scanning signal line Ga and the connecting wiring L may be connected through the via hole.

[0068] For example, Figure 3As shown, when the second line L2 overlaps with the first line L1 of other connecting lines L, the second line L2 includes at least one switching electrode L22 and multiple connecting electrodes L21, the connecting electrode L21 and the first line L1 are located in the same layer, and the at least one switching electrode L22 and the multiple connecting electrodes L21 are located in different layers. At least one switching electrode L22 and the first line L1 of other connecting lines at least partially overlap in a direction perpendicular to the substrate, and the multiple connecting electrodes L21 are connected to at least one switching electrode L22 through vias penetrating the insulating layer to form the second line L2.

[0069] Figure 4 A schematic cross-sectional view of a switching electrode and a connecting electrode provided in some embodiments of the present disclosure (eg Figure 3 The circled area C2 in FIG. 1 is a cross section along the dividing line NN). Figure 3 and Figure 4 As shown, the second line L2 located on the dividing line NN overlaps with at least three vertical first lines L1. Since the first line L1 and the second line L2 are located in the same layer, if the first line L1 and the second line L2 cross, it will affect the transmission of the signal. In order to avoid the influence on the signal transmission, the second line L2 can be divided into multiple sections of connecting electrodes L21. The first line L1 can pass through the gap between the connecting electrodes L21, and two adjacent sections of the connecting electrodes L21 are connected through the switching electrodes L22 located on different layers. For example, the connecting electrode L21 and the first line L1 can be located in the fourth conductive layer, and the switching electrode L22 can be located in the first conductive layer and the second conductive layer (as shown below). Fig.7D as shown) or a third conductive layer (as shown below Fig. 7E As shown, an insulating layer may be provided between the fourth conductive layer and the first conductive layer, the second conductive layer and the third conductive layer, a via hole is provided on the insulating layer, and the switching electrode L22 is connected to the connecting electrode L21 through the via hole of the insulating layer.

[0070] For example, the orthographic projection of the first wiring on the substrate is located between the orthographic projections of two adjacent columns of sub-pixels in the display area on the substrate.

[0071] For example, the orthographic projection of the second wiring on the substrate is located between the orthographic projections of two adjacent rows of sub-pixels in the display area on the substrate.

[0072] For example, Figure 3As shown, the size of the pixel unit can be reduced from the original pixel unit 130' to a pixel unit 130 with a smaller occupied area. For example, the pixel unit 130' can be reduced as a whole, that is, the occupied area of ​​each transistor in the pixel unit and the spacing between the transistors can be reduced. The outline of the reduced pixel unit 130 can be reduced by 4 to 18 μm relative to the outline of the original pixel unit 130'. After the pixel unit is reduced, the gap between adjacent pixel units 130 becomes larger, so the connecting wire L can be arranged between the pixel units 130. For example, in the direction perpendicular to the substrate, the horizontal second wire can be located between two adjacent rows of pixel units, and the vertical first wire can be located between two adjacent columns of pixel units.

[0073] In another embodiment of the present disclosure, the longitudinal dimension of the pixel unit can be kept unchanged, and the lateral dimension of the pixel unit can be reduced to increase the spacing between two adjacent columns of pixel units, so that the first vertical trace can be arranged between two adjacent columns of pixel units.

[0074] In another embodiment of the present disclosure, the lateral size of the pixel unit can be kept unchanged, and the longitudinal size of the pixel unit can be reduced to increase the spacing between two adjacent rows of pixel units, so that the second lateral trace can be arranged between two adjacent rows of pixel units.

[0075] In the embodiment of the present disclosure, by arranging the first routing line and / or the second routing line between two adjacent columns and / or rows of pixel units, the layout structure of each pixel unit may not be changed, and the influence of the change of the gate scanning signal in the connecting routing line on the circuit of the pixel unit may be avoided.

[0076] Figure 5 A schematic diagram of a partial layout of a display area provided in some embodiments of the present disclosure. Figure 5 As shown, the display area also includes a plurality of first voltage lines VDD, which are respectively connected to the plurality of columns of pixel units 130 and extend along the first direction Y to respectively provide a first voltage to the plurality of columns of pixel units 130, and the orthographic projection of the first wiring on the substrate and the orthographic projection of the corresponding first voltage line VDD on the substrate at least partially overlap.

[0077] For example, each column of pixel units may be connected to at least one first voltage line VDD, and the first voltage line VDD may extend along the first direction Y and be connected to each pixel unit 130 in the corresponding column to provide a first voltage to each pixel unit 130 in the column. Each first routing line may not be arranged in the gap between the pixel units, but may overlap with a column of pixel units 130 in a direction perpendicular to the substrate, and may at least partially overlap with the first voltage line VDD connected to a column of pixel units 130. Since a DC signal is transmitted in the first voltage line VDD, making the first routing line at least partially overlap with the first voltage line VDD in a direction perpendicular to the substrate can shield the influence of the change of the gate scanning signal in the first routing line on the pixel circuit in the pixel unit.

[0078] For example, the display area also includes multiple initial signal lines Vinit, which are respectively connected to multiple rows of pixel units 130 and extend along the second direction X to provide initial voltages to the multiple rows of pixel units 130 respectively, and the orthographic projection of the second wiring on the substrate and the orthographic projection of the corresponding initial signal line on the substrate at least partially overlap.

[0079] For example, each row of pixel units 130 may be connected to at least one initial signal line Vinit, and the initial signal line Vinit may extend along the second direction X and be connected to each pixel unit 130 in the corresponding row to provide an initial voltage for each pixel unit in the row. The second line may not be arranged in the gap between the pixel units, but may overlap with a row of pixel units in a direction perpendicular to the substrate, and may at least partially overlap with the initial signal line Vinit connected to a row of pixel units. Since a DC signal is transmitted in the initial signal line Vinit, making the second line at least partially overlap with the first voltage line VDD in a direction perpendicular to the substrate can shield the influence of the change of the gate scan signal in the second line on the pixel circuit.

[0080] In the embodiments of the present disclosure, by making the first wiring at least partially overlap with the first voltage line VDD in a direction perpendicular to the substrate and / or making the second wiring at least partially overlap with the initial signal line Vinit in a direction perpendicular to the substrate, on the one hand, there is no need to reduce the occupied area of ​​the pixel unit to meet the requirements of high resolution, and on the other hand, the influence of the connecting wiring on the pixel circuit can be shielded, thereby improving the stability of the display substrate.

[0081] For example, each of the multiple rows and columns of pixel units includes a light emitting element and a pixel circuit driving the light emitting element to emit light. Figure 6 An equivalent circuit diagram of a pixel circuit in a display substrate provided in some embodiments of the present disclosure, such as Figure 6 As shown, the pixel circuit 400 includes a driving sub-circuit 410, a data writing sub-circuit 420, a threshold compensation sub-circuit 430 and a reset sub-circuit.

[0082] The driving subcircuit 410 includes a control terminal, a first terminal, and a second terminal, and is configured to control a driving current flowing through the light-emitting element. The data writing subcircuit 420 is connected to the first terminal of the driving subcircuit 410, the data line, and the gate scanning signal line Ga, and is configured to write a data signal provided by the data line Vda into the first terminal of the driving subcircuit 410 in response to a gate scanning signal provided by the gate scanning signal line Ga.

[0083] The threshold compensation subcircuit 420 is connected to the control terminal and the second terminal of the driving subcircuit 410, the first voltage line VDD and the gate scanning signal line Ga, and is configured to compensate the driving subcircuit 410 in response to the gate scanning signal provided by the gate scanning signal line Ga and the written data signal.

[0084] The reset subcircuit is connected to the second end of the driving subcircuit 410 , the initial signal line Vinit and the reset signal line Re, and is configured to apply an initial voltage provided by the initial signal line Vinit to the second end of the driving subcircuit 410 in response to a reset signal provided by the reset signal line Re.

[0085] The reset subcircuit may include a first reset subcircuit 440 and a second reset subcircuit 450. The first reset subcircuit 440 is connected to the second end of the driving subcircuit 410, the initial signal line Vinit, and the reset signal line Re, and is configured to apply an initial voltage provided by the initial signal line Vinit to the second end of the driving subcircuit 410 in response to a reset signal provided by the reset signal line Re. The second reset subcircuit 450 is connected to the initial signal line Vinit, the reset signal line Re, and the first end of the light-emitting element 500, and is configured to apply an initial voltage provided by the initial signal line Vinit to the first end of the light-emitting element 500 in response to the reset signal received by the reset signal line Re.

[0086] For example, the pixel circuit 400 further includes a first light-emitting control subcircuit 460 and a second light-emitting control subcircuit 470. The first light-emitting control subcircuit 460 is connected to the first voltage line VDD, the first end of the driving subcircuit 410, and the light-emitting control signal line EM, and is configured to apply the first voltage provided by the first voltage line VDD to the first end of the driving subcircuit 410 in response to the light-emitting control signal provided by the light-emitting control signal line EM. The second light-emitting control subcircuit 470 is connected to the second end of the driving subcircuit 410, the first end of the light-emitting element 500, and the light-emitting control signal line EM, and is configured to apply the driving current to the first end of the light-emitting element in response to the light-emitting control signal provided by the light-emitting control signal line EM.

[0087] For example, the pixel circuit 400 further includes a storage subcircuit 480 connected to the control terminal of the driving subcircuit 410 and the first voltage line VDD and configured to store the compensation signal and keep it at the control terminal of the driving subcircuit 410 .

[0088] For example, the pixel circuit includes a thin film transistor and a storage capacitor. The thin film transistor includes an active layer, a gate, a source and a drain, and the storage capacitor includes a first capacitor electrode and a second capacitor electrode opposite to the first capacitor electrode in a direction perpendicular to the board surface of the substrate. The source and the drain are located on the side of the active layer away from the substrate, and the gate scanning signal line is located on the same layer as the gate of the thin film transistor and the first capacitor electrode. The initial signal line and the second capacitor electrode are located on the same layer. The first voltage line and the source and drain are located on the same layer.

[0089] For example, Figure 6 As shown, in some examples, the driving subcircuit 410 includes a driving transistor T1, the data writing subcircuit 420 includes a data writing transistor T2, the threshold compensation subcircuit 430 includes a threshold compensation transistor T3, the first reset subcircuit 440 includes a first reset transistor T4, the second reset subcircuit 450 includes a second reset transistor T7, the first light emission control subcircuit 460 includes a first light emission control transistor T5, the second light emission control subcircuit 470 includes a second light emission control transistor T6, and the storage subcircuit 480 includes a storage capacitor Cst. For example, in this example, the pixel circuit 400 can be a 7T1C pixel driving circuit.

[0090] For example, Figure 6 As shown, the first gate of the driving transistor T1 is electrically connected to the third drain D3 of the threshold compensation transistor T3 and the fourth drain D4 of the first reset transistor T4. The first source S1 of the driving transistor T1 is electrically connected to the second drain D2 of the data writing transistor T2 and the fifth drain D5 of the first light emission control transistor T5. The first drain D1 of the driving transistor T1 is electrically connected to the third source S3 of the threshold compensation transistor T3 and the sixth source S6 of the second light emission control transistor T6.

[0091] For example, Figure 6 As shown, the second gate of the data writing transistor T2 is configured to be electrically connected to the gate scanning signal line Ga to receive the gate scanning signal, the second source S2 of the data writing transistor T2 is configured to be electrically connected to the data line Vda to receive the data signal, and the second drain D2 of the data writing sub-circuit T2 is electrically connected to the first source S1 of the driving transistor T1.

[0092] For example, Figure 6As shown, the third gate of the threshold compensation transistor T3 is configured to be electrically connected to the gate scanning signal line Ga, the third source S3 of the threshold compensation transistor T3 is electrically connected to the first drain D1 of the driving transistor T1, and the third drain D3 of the threshold compensation transistor T3 is electrically connected to the first gate G1 of the driving transistor T1.

[0093] For example, Figure 6 As shown, the fourth gate of the first reset transistor T4 is configured to be electrically connected to the reset signal line Re to receive the reset signal, the fourth source S4 of the first reset transistor T4 is configured to be electrically connected to the initialization line Vinit to receive the initialization signal, and the fourth drain D4 of the first reset transistor T4 is electrically connected to the first gate of the driving transistor T1.

[0094] For example, Figure 6 As shown, the fifth gate of the first light emitting control transistor T5 is configured to be electrically connected to the light emitting control line EM to receive the light emitting control signal, the fifth source S5 of the first light emitting control transistor T5 is configured to be electrically connected to the first power line VDD to receive the first power signal, and the fifth drain D5 of the first light emitting control transistor T5 is electrically connected to the first source S1 of the driving transistor T1.

[0095] For example, Figure 6 As shown, the sixth gate of the second light emitting control transistor T6 is configured to be electrically connected to the light emitting control line EM to receive a light emitting control signal, the sixth source S6 of the second light emitting control transistor T6 is electrically connected to the first drain D1 of the driving transistor T1, and the sixth drain D6 of the second light emitting control transistor T6 is electrically connected to the first display electrode (e.g., anode) of the light emitting element 500.

[0096] For example, Figure 6 As shown, the seventh gate of the second reset transistor T7 is configured to be electrically connected to the reset signal line Re to receive the reset signal, the seventh source S7 of the second reset transistor T7 is electrically connected to the first electrode (e.g., anode) of the light emitting element 500, and the seventh drain D7 of the second reset transistor T7 is configured to be electrically connected to the initialization line Vinit to receive the initialization signal. For example, the seventh drain D7 of the second reset transistor T7 can be electrically connected to the initialization line Vinit by being connected to the fourth source S4 of the first reset transistor T4.

[0097] For example, Figure 6 As shown, the storage capacitor Cst includes a first capacitor electrode CE1 and a second capacitor electrode CE2. The second capacitor electrode CE2 is electrically connected to the first power line VDD, and the first capacitor electrode CE1 is electrically connected to the first gate G1 of the driving transistor T1 and the third drain D3 of the threshold compensation transistor T3.

[0098] For example, Figure 6 As shown, the second electrode (eg, cathode) of the light emitting element 500 is electrically connected to the second power line VSS.

[0099] It should be noted that one of the first power line VDD and the second power line VSS is a power line providing a high voltage, and the other is a power line providing a low voltage. Figure 6 In the illustrated embodiment, the first power line VDD provides a constant first voltage (ie, the first voltage signal mentioned above), which is a positive voltage, and the second power line VSS provides a constant second voltage, which may be a negative voltage, etc. For example, in some examples, the second voltage may be a ground voltage.

[0100] It should be noted that, according to the characteristics of transistors, transistors can be divided into N-type transistors and P-type transistors. For the sake of clarity, the embodiments of the present disclosure are described by taking the transistors as P-type transistors (e.g., P-type MOS transistors) as an example. That is to say, in the description of the present disclosure, transistors T1-T7, etc. can all be P-type transistors. However, the transistors of the embodiments of the present disclosure are not limited to P-type transistors. Those skilled in the art can also use N-type transistors (e.g., N-type MOS transistors) according to actual needs to implement the functions of one or more transistors in the embodiments of the present disclosure.

[0101] It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics, and the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors or polycrystalline silicon thin film transistors, etc. The source and drain of the transistor may be symmetrical in structure, so the source and drain may be indistinguishable in physical structure, and the source and drain of all or part of the transistors in the embodiments of the present disclosure may be interchangeable as needed.

[0102] For example, Fig. 7A Schematic diagram of the stacking position relationship of the semiconductor layer, the first conductive layer, the second conductive layer and the third conductive layer of the pixel circuit 400.

[0103] Figure 7B FIG. 4 shows the semiconductor layers of the pixel circuit 400. Figure 7BAs shown, the semiconductor layer can be formed by patterning semiconductor materials. The semiconductor layer can be used to make the active layers of the above-mentioned driving transistor T1, data writing transistor T2, threshold compensation transistor T3, first reset transistor T4, first light emission control transistor T5, second light emission control transistor T6 and second reset transistor T7, and each active layer may include a source region, a drain region and a channel region between the source region and the drain region. For example, the semiconductor layer can be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the above-mentioned source region and drain region can be regions doped with n-type impurities or p-type impurities.

[0104] In the display substrate provided in some embodiments of the present disclosure, a gate insulating layer is formed on the above-mentioned semiconductor layer to protect the above-mentioned semiconductor layer.

[0105] Figure 7C 4 shows a first conductive layer of the pixel circuit 400. For example, Figure 7C As shown, the first conductive layer of the pixel circuit 400 is disposed on the gate insulating layer so as to Figure 7B The semiconductor layer shown is insulated. The first conductive layer may include a first capacitor electrode CE1 of a storage capacitor Cst, a gate scanning signal line Ga, a reset signal line Re, a light emission control signal EM, and gates of a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a first reset transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, and a second reset transistor T7. Figure 7C As shown, the gates of the data writing transistor T2, the first reset transistor T4, the first light emission control transistor T5, the second light emission control transistor T6 and the second reset transistor T7 are the portions where the gate scanning signal line Ga and the reset signal line Re overlap with the semiconductor layer, the threshold compensation transistor T3 may be a thin film transistor with a dual-gate structure, one gate of the threshold compensation transistor T3 may be the portion where the gate scanning signal line Ga overlaps with the semiconductor layer, and the other gate of the threshold compensation transistor T3 may be a protrusion protruding from the gate scanning signal line Ga; the gate of the driving transistor T1 may be the first capacitor electrode CE1. The first reset transistor T4 may be a thin film transistor with a dual-gate structure, and the two gates are the portions where the reset signal line Re overlaps with the semiconductor layer.

[0106] In the display substrate provided in some embodiments of the present disclosure, a first interlayer insulating layer is formed on the first conductive layer to protect the first conductive layer.

[0107] Fig.7D 4 shows a second conductive layer of the pixel circuit 400. For example, Fig.7DAs shown, the second conductive layer of the pixel circuit 400 includes a second capacitor electrode CE2 of the storage capacitor Cst and an initial signal line Vinit. The second capacitor electrode CE2 at least partially overlaps with the first capacitor electrode CE1 to form the storage capacitor Cst.

[0108] In some embodiments, the second conductive layer may further include a first light shielding portion Co1 and a second light shielding portion Co2. The orthographic projection of the first light shielding portion Co1 on the substrate covers the active layer of the data writing transistor T2, the drain of the threshold compensation transistor T3 and the active layer between the drain of the first reset transistor T4, thereby preventing external light from affecting the active layer of the data writing transistor T2, the threshold compensation transistor T3 and the first reset transistor T4. The orthographic projection of the second light shielding portion Co2 on the substrate covers the active layer between the two gates of the threshold compensation transistor T3, thereby preventing external light from affecting the active layer of the threshold compensation transistor T3. The first light shielding portion Co1 may be an integral structure with the second light shielding portion Co2 of the adjacent pixel driving circuit, and is electrically connected to the first power line VDD through a via that penetrates the second interlayer insulating layer.

[0109] In the display substrate provided in some embodiments of the present disclosure, a second interlayer insulating layer is formed on the second conductive layer to protect the second conductive layer.

[0110] Fig. 7E 4 shows the third conductive layer of the pixel circuit 400. For example, Fig. 7E As shown, the third conductive layer of the pixel circuit 400 includes a data line Vda and a first power line VDD. Fig. 7A and Fig. 7E As shown, the data line Vda is connected to the source region of the data writing transistor T2 in the semiconductor layer through at least one via hole VH1 in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer. The first power line VDD is connected to the source region of the corresponding first light emission control transistor T5 in the semiconductor layer through at least one via hole VH2 in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer. The first power line VDD is connected to the second capacitor electrode CE2 in the second conductive layer through at least one via hole VH3 in the second interlayer insulating layer.

[0111] For example, the third conductive layer further includes a first connection portion CP1, a second connection portion CP2, and a third connection portion CP3. One end of the first connection portion CP1 is connected to the drain region of the corresponding threshold compensation transistor T3 in the semiconductor layer through at least one via hole VH4 in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer, and the other end of the first connection portion CP1 is connected to the gate of the driving transistor T1 in the first conductive layer through at least one via hole VH5 in the first interlayer insulating layer and the second interlayer insulating layer. One end of the second connection portion CP2 is connected to the initialization line Vinit through a via hole VH6 in the second interlayer insulating layer, and the other end of the second connection portion CP2 is connected to the source region of the second reset transistor T7 in the semiconductor layer and the source region of the first reset transistor T4 through at least one via hole VH7 in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer. The third connection portion CP3 is connected to the drain region of the second light-emitting control transistor T6 in the semiconductor layer through at least one via hole VH8 in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer.

[0112] In the display substrate provided in some embodiments of the present disclosure, a third interlayer insulating layer is formed on the third conductive layer to protect the third conductive layer.

[0113] For example, the first and second wirings are located on a side of the plurality of first voltage lines VDD away from the substrate. For example, a fourth conductive layer may be provided on the third interlayer insulating layer, and the first and second wirings may be located on the fourth conductive layer.

[0114] Figure 7F FIG. 4 shows a fourth conductive layer of the pixel circuit 400, and the fourth conductive layer is located on a side of the third interlayer insulating layer away from the third conductive layer. Figure 7F As shown, the fourth conductive layer of the pixel circuit 400 includes a switching electrode L22.

[0115] In the display substrate provided in some embodiments of the present disclosure, a fourth interlayer insulating layer is formed on the fourth conductive layer to protect the fourth conductive layer.

[0116] Figure 7G FIG. 4 shows a fifth conductive layer of the pixel circuit 400. For example, Figure 7G As shown, the fifth conductive layer is located on a side of the fourth interlayer insulating layer away from the fourth conductive layer, and the fifth conductive layer includes a first wiring L1 extending along a first direction Y and at least two connecting electrodes L21 extending along a second direction X. It should be noted that the first wiring L1 and the connecting electrode L21 belong to different connecting wirings, for example, the first wiring L1 belongs to a wiring connected to Figure 3The connection line of the third row of pixel units shown in the figure, the connection electrode L21 belongs to the connection line connected to the first row of pixel units. In order to avoid the first line L1 from crossing with the second line of another connection line, the second line is divided into at least two connection electrodes L21, and the first line L1 passes through the gap between two adjacent connection electrodes L21.

[0117] For example, the transfer electrode L22 may be connected to at least two connection electrodes L21 through a via hole penetrating the fourth interlayer insulating layer to form a second wiring.

[0118] Figure 7H Schematic diagram showing the stacking position relationship of the semiconductor layer, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer. Figure 7H As shown, the orthographic projection of the first wiring L1 on the base substrate at least partially overlaps with the orthographic projection of the first voltage line VDD on the base substrate. The orthographic projection of the connecting electrode L21 on the base substrate at least partially overlaps with the initial signal line Vinit. The orthographic projection of the switching electrode L22 on the base substrate at least partially overlaps with the orthographic projection of the connecting electrode L21 on the base substrate, and the switching electrode L22 is connected to the connecting electrode L21 in the fifth conductive layer through the vias VH9 and V10 of the fourth interlayer insulating layer.

[0119] In the display substrate provided in some embodiments of the present disclosure, a protective layer is formed on the fifth conductive layer to protect the fifth conductive layer. The first display electrode (eg, anode) of the light emitting element in the pixel unit may be disposed on the protective layer.

[0120] For example, in some other examples, the fourth conductive layer can be on the same layer as other conductive layers except the fifth conductive layer, that is, the switching electrode L22 can be arranged on other conductive layers except the fifth conductive layer, and the specific arrangement depends on the wiring layout of each layer, which is not limited by the embodiments of the present disclosure.

[0121] For example, in some other examples, the fourth conductive layer can also be arranged on the side of the fifth conductive layer away from the base substrate, that is, the transfer electrode L22 can be arranged on the side of the connecting electrode L21 away from the base substrate. It can be flexibly arranged according to the specific situation, and the embodiments of the present disclosure are not limited to this.

[0122] In other examples of the present disclosure, any one or more of the transistors T1-T7 may be of an oxide semiconductor thin film transistor (Oxide TFT), for example, the first reset transistor T4 may be an oxide semiconductor thin film transistor, such as an indium gallium zinc oxide (IGZO) thin film transistor. Oxide semiconductor thin film transistors have the characteristics of good hysteresis characteristics and low leakage current (below 1e-14A), and low mobility. Oxide semiconductor thin film transistors can be used to ensure the stability of the gate voltage of the driving transistor. The types of the remaining transistors T1-T3 and T5-T7 may be polycrystalline silicon thin film transistors, for example, low temperature polycrystalline silicon (LTPS) thin film transistors. The oxide semiconductor thin film transistors and polycrystalline silicon thin film transistors are located in different film layers, so the active layer A4 of the first reset transistor T4 is located in different layers from the active layers A1-A3 and A5-A7 of the transistors T1-T3 and T5-T7.

[0123] Figure 8 A partial cross-sectional schematic diagram of another stacked structure of a pixel circuit provided by an embodiment of the present disclosure is shown. Figure 8 The schematic diagram includes three cross-sections: part AA`, part BB` and part CC`, wherein part AA` is a schematic diagram of the cross-sectional structure corresponding to the second light-emitting control transistor T6, part BB` is a schematic diagram of the cross-sectional structure corresponding to the first reset transistor T4, and part CC` is a schematic diagram of the cross-sectional structure corresponding to the storage capacitor Cst.

[0124] For example, the stacked structure may include a first semiconductor layer 410 , a first conductive layer 420 , a second conductive layer 430 , a second semiconductor layer 440 , a third conductive layer 450 , a source-drain metal layer 460 , a fourth conductive layer 470 , a fifth conductive layer 480 , and a sixth conductive layer 490 .

[0125] For example, the first semiconductor layer 410 may include active layers A1-A3 and A5-A7 of transistors T1-T3 and T5-T7, the first conductive layer 420 may include a gate scan signal line Ga, a light emitting control signal line EM and a first capacitor electrode CE1, the second conductive layer 430 may include a second capacitor electrode CE2 and a first reset sub-signal line Re1, the second semiconductor layer 440 may include an active layer A4 of a first reset transistor T4, the third conductive layer 450 may include a second reset sub-signal line Re2, the source-drain metal layer 460 may include an initial signal line Vinit and the source and drain of transistors T1-T7, the fourth conductive layer 470 may include a data line Vda and a first voltage line VDD, the fifth conductive layer 480 may include a transfer electrode L22, and the sixth conductive layer 490 may include a first routing line L1 and a connecting electrode L21.

[0126] For example, in some examples, the switching electrode L22 is used to connect adjacent connection electrodes L21. The orthographic projection of each switching electrode L22 on the base substrate at least partially overlaps with the orthographic projections of two adjacent connection electrodes L21 on the base substrate. In another embodiment, the switching electrode L22 can be disposed on other conductive layers.

[0127] For example, at least one insulating layer may be disposed between each two adjacent layers of the first semiconductor layer 410, the first conductive layer 420, the second conductive layer 430, the second semiconductor layer 440, the third conductive layer 450, the source-drain metal layer 460, the fourth conductive layer 470, the fifth conductive layer 480, and the anode layer (not shown). Figure 8 As shown, there is a first insulating layer 410 between the first semiconductor layer 410 and the first conductive layer 420, a second insulating layer 520 between the first conductive layer 420 and the second conductive layer 430, a third insulating layer 430 and a buffer layer 440 between the second conductive layer 430 and the second semiconductor layer 440, a fourth insulating layer 450 between the second semiconductor layer 440 and the third conductive layer 450, a fifth insulating layer 460 between the third conductive layer 450 and the source-drain metal layer 460, a sixth insulating layer 570 between the source-drain metal layer 460 and the fourth conductive layer 470, a seventh insulating layer 580 between the fourth conductive layer 470 and the fifth conductive layer 480, an eighth insulating layer 590 between the fifth conductive layer 480 and the sixth conductive layer 490, and a planarization layer 511 between the sixth conductive layer 490 and the anode layer.

[0128] For example, Figure 8As shown in the AA' portion of FIG. 4 , the sixth source S6 and the sixth drain D6 of the second light emission control transistor T6 are located in the source-drain metal layer 460, and the sixth source S6 and the sixth drain D6 are connected to the active layer A6 of the second light emission control transistor T4 in the first active semiconductor layer 410 through a via hole penetrating the insulating layer (for example, penetrating the first insulating layer 550 to the fifth insulating layer 560 and the buffer layer 540). The sixth drain D6 is connected to the anode of the light emitting element 500 through a via hole penetrating the insulating layer (for example, penetrating the sixth insulating layer 560 to the eighth insulating layer 590 and the planarization layer 511). The gate of the second light emission control transistor T6 is formed integrally with the light emission control signal line EM.

[0129] For example, Figure 8 As shown in the BB' portion of FIG. 1 , the initial signal line Vinit is formed integrally with the fourth source S4 of the first reset transistor T4, and is connected to the active layer A4 of the first reset transistor T4 in the second active semiconductor layer 440 through a via hole penetrating the insulating layer (e.g., penetrating the fourth insulating layer 550 and the fifth insulating layer 560). The fourth drain D4 of the first reset transistor T4 is connected to the active layer A4 of the first reset transistor T4 in the second active semiconductor layer 440 through a via hole penetrating the insulating layer (e.g., penetrating the fourth insulating layer 550 and the fifth insulating layer 560).

[0130] For example, Figure 8 As shown in the BB` part, the first reset transistor T4 can be a dual-gate structure with a first gate and a second gate, the first reset sub-signal line Re1 is formed integrally with the first gate of the first reset transistor T4, and the second reset sub-signal line Re2 is formed integrally with the second gate of the first reset transistor T4.

[0131] For example, Figure 8 As shown in the BB' portion, in the direction perpendicular to the substrate, the connection electrode L21 of the second wiring at least partially overlaps with the initial signal line Vinit.

[0132] For example, Figure 8 As shown in the CC' portion of FIG. 4 , the first voltage line VDD is located in the fourth conductive layer 470, and the first voltage line VDD is connected to the second capacitor electrode CE2 in the second conductive layer 420 through a via hole penetrating the insulating layer (for example, penetrating the third insulating layer 530 to the sixth insulating layer 570 and the buffer layer 540), and the first capacitor electrode CE1 is connected to the gate of the driving transistor T1 through the fourth connecting portion CP4, that is, connected to the drain D4 of the first reset transistor T4. The fourth connecting portion CP4 is connected to the first capacitor electrode CE1 through a via hole penetrating the insulating layer (for example, penetrating the second insulating layer 520 to the sixth insulating layer 570 and the buffer layer 540).

[0133] For example, Figure 8As shown in the CC' portion of FIG. 1 , in a direction perpendicular to the substrate, the first wiring L1 at least partially overlaps with the first voltage line VDD.

[0134] For example, in addition to the pixel circuit with a 7T1C structure in the above embodiment, the pixel circuit may also be a pixel circuit with other structures, for example, it may be a pixel circuit with 8T1C, 5T1C, 6T2C or 4T2C, and the embodiments of the present disclosure are not limited to this.

[0135] It should be noted that the introduction of the first gate driving circuit and the second gate driving circuit can refer to the specific description of the structure and working principle in the art, and will not be repeated here. For example, in the embodiment of the present disclosure, the size of the shift register unit (for example, the size of the transistor and the capacitor) in the first gate driving circuit and the second gate driving circuit located in the second peripheral sub-area is compressed accordingly, so that the second peripheral sub-area can be arranged to drive the pixel units of all rows of the display area.

[0136] At least one embodiment of the present disclosure further provides a display device. Fig. 9 Schematic diagram of a display device provided by at least one embodiment of the present disclosure. Fig. 9 As shown, the display device 60 includes a display substrate 1 provided by any embodiment of the present disclosure, for example, the display substrate 1 shown in FIG. 1 .

[0137] For example, the display device 60 may be a liquid crystal display device or an organic light emitting diode (OLED) display device. For example, when the display device 60 is a liquid crystal display device, the display substrate 1 may be an array substrate or a color filter substrate. When the display device 60 is an organic light emitting diode display device, the display substrate 1 may be an array substrate.

[0138] For example, the display device 60 may include a rectangular panel, a circular panel, an elliptical panel, a polygonal panel, etc. In addition, the display device 60 may include not only a flat panel but also a curved panel or even a spherical panel.

[0139] For example, the display device 60 may also have a touch function, that is, the display device 60 may be a touch display device.

[0140] For example, the display device 60 can be applied to any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

[0141] For example, the display device 60 may be a flexible display device, so as to meet various practical application requirements. For example, the display device 60 may be applied to a curved screen, etc.

[0142] It should be noted that the display device 60 may also include other components, such as a data drive circuit, a timing controller, etc., which are not limited in the embodiments of the present disclosure. For the sake of clarity and brevity, the embodiments of the present disclosure do not provide all the components of the display device 60. To achieve the basic functions of the display device 60, those skilled in the art may provide and set other structures not shown according to specific needs, which are not limited in the embodiments of the present disclosure.

[0143] Fig.10 A schematic block diagram of another display device provided in some embodiments of the present disclosure. Fig.10 As shown, the display device 70 includes a display substrate 701 , and the display substrate 701 may be a display substrate provided by any embodiment of the present disclosure.

[0144] For example, Fig.10 As shown, the display device 70 further includes a data driver 710, a gate driver 720, a timing controller 730, a voltage source 740, etc. For example, the gate driver 720 may include the first gate scanning circuit and the second gate scanning circuit in the above-mentioned embodiment of the display substrate, that is, it may be directly prepared on the substrate through a semiconductor process; the voltage source 740 may include the first voltage source 181 in the above-mentioned embodiment of the display substrate 1, for example, it may be implemented as a power management circuit.

[0145] For example, in one example, a plurality of pixel units P (such as the pixel unit 130 in the above embodiment of the display substrate 1) are arranged in an array in the display area of ​​the display substrate 701, and each pixel unit P receives a data signal provided by the data driver 710 through a data line Vda, and receives a voltage signal provided by the voltage source 740 through a first voltage line VDD. For example, the power line VDD may include the first power line 183 in the above embodiment of the display substrate 1.

[0146] For example, the data driver 710 converts the digital image data RGB input from the timing controller 730 into a data signal according to the data control signal DCS provided by the timing controller 730. For example, the data driver 710 converts the data signal into an analog voltage signal according to the data control signal DCS provided by the timing controller 730, and performs processing such as operational amplification on the analog voltage signal, and then provides the corresponding data signal to each pixel unit P through the data line Vda. For example, the data driver 710 can be implemented as a semiconductor chip.

[0147] For example, the gate driver 720 is electrically connected to each pixel unit P through the gate scanning signal line SL to provide a gate scanning signal to each pixel unit P. For example, the gate driver 720 provides a gating signal according to a plurality of scanning control signals GCS provided by the timing controller 730. For example, the gate driver 720 can be implemented as a semiconductor chip, or can be integrated in the display device 70 to form a GOA circuit, such as the first gate driving circuit and the second gate driving circuit in the above-mentioned embodiment of the display substrate 1.

[0148] For example, the timing controller 730 is used to process the image data RGB input from outside the display device 70, provide the processed image data RGB to the data driver 710, and provide the data control signal DCS and the scan control signal GCS to the data driver 710 and the gate driver 720 to control the data driver 710 and the gate driver 720.

[0149] For example, the timing controller 730 processes the externally input image data RGB to match the size and resolution of the display device 70, and then provides the processed image data RGB to the data driver 710. The timing controller 730 generates a scan control signal GCS and a data control signal DCS using a synchronization signal SYNC (e.g., a dot clock DCLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync) input from the outside of the display device 70. The timing controller 730 provides the generated data control signal DCS and the scan control signal GCS to the data driver 710 and the gate driver 720, respectively, for control of the data driver 710 and the gate driver 720.

[0150] The structure, function, technical effect, etc. of the display device 60 and the display device 70 provided in the embodiments of the present disclosure may refer to the corresponding description in the display substrate 1 provided in the above embodiments of the present disclosure, and will not be repeated here.

[0151] For example, the display device 60 and the display device 70 provided in the embodiment of the present disclosure may be an organic light emitting diode display device. Alternatively, the display device 60 and the display device 70 provided in the embodiment of the present disclosure may also be a device with a display function such as a quantum dot light emitting diode display device, an electronic paper display device, or other types of display devices, which are not limited in the embodiment of the present disclosure.

[0152] For example, the display device 60 and the display device 70 provided in the embodiments of the present disclosure may be a display substrate, a display panel, electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function, and the embodiments of the present disclosure are not limited to this.

[0153] There are a few points to note about this disclosure:

[0154] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0155] (2) For the sake of clarity, the thickness and size of layers or structures are exaggerated in the drawings used to describe the embodiments of the present invention. It is understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element, or there may be intervening elements.

[0156] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0157] The above description is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A display substrate, comprising: A substrate, comprising a display area and a peripheral area located on at least one side of the display area, The display area includes a plurality of rows and columns of pixel units arranged in an array, a plurality of gate scanning signal lines respectively connected to the plurality of rows of pixel units, and a plurality of connecting wires located at different layers from the plurality of gate scanning signal lines; The peripheral area includes a first peripheral sub-area and a second peripheral sub-area, and the display area includes a first display sub-area corresponding to the first peripheral sub-area and a second display sub-area corresponding to the second peripheral sub-area and different from the first display sub-area; The second peripheral sub-region includes a first gate driving circuit, and the first gate driving circuit is configured to be connected to a plurality of gate scanning signal lines located in the first display sub-region through the plurality of connecting lines located in the display region, so as to provide gate scanning signals to a plurality of rows of pixel units located in the first display sub-region respectively; The first peripheral sub-region does not include the first gate driving circuit, Each of the plurality of connecting lines further comprises a first line extending along a first direction and a second line extending along a second direction, the first direction and the second direction intersecting; The first gate driving circuit is connected to the first routing line through the second routing line, and the first routing line is connected to the corresponding gate scanning signal line located in the first display sub-area through a via hole penetrating the insulating layer to provide the gate scanning signal to the corresponding gate scanning signal line. When the second routing line overlaps with a first routing line among other connecting routing lines, the second routing line includes at least one switching electrode and a plurality of connecting electrodes, and the at least one switching electrode and the first routing line of the other connecting routing lines at least partially overlap in a direction perpendicular to the substrate.

2. The display substrate according to claim 1, wherein: The second peripheral sub-region further includes a second gate driving circuit, and the second gate driving circuit is configured to be connected to a plurality of gate scanning signal lines located in the second display sub-region to respectively provide the gate scanning signals to a plurality of rows of pixel units located in the second display sub-region; The first peripheral sub-region also does not include the second gate driving circuit.

3. The display substrate according to claim 1, wherein: The orthographic projection of the second wiring on the base substrate is located between the orthographic projections of two adjacent rows of pixel units in the display area on the base substrate.

4. The display substrate according to claim 1, wherein: The connecting electrode and the first wiring are located in the same layer, and the at least one switching electrode and the plurality of connecting electrodes are located in different layers; The plurality of connection electrodes are connected to the at least one transfer electrode through via holes penetrating the insulating layer to form the second routing line.

5. The display substrate according to claim 3 or 4, wherein: The orthographic projection of the first wiring on the base substrate is located between the orthographic projections of two adjacent columns of pixel units in the display area on the base substrate.

6. The display substrate according to claim 4, wherein: The display area further includes a plurality of first voltage lines, which are respectively connected to the plurality of columns of pixel units and extend along the first direction to respectively provide a first voltage to the plurality of columns of pixel units. The orthographic projection of the first wiring on the substrate and the orthographic projection of the corresponding first voltage line on the substrate at least partially overlap.

7. The display substrate according to claim 6, wherein: The display area further includes a plurality of initial signal lines, which are respectively connected to the plurality of rows of pixel units and extend along the second direction to respectively provide initial voltages to the plurality of rows of pixel units. The orthographic projection of the second trace on the substrate at least partially overlaps with the orthographic projection of the corresponding initial signal line on the substrate.

8. The display substrate according to claim 7, wherein: Each of the plurality of rows and columns of pixel units comprises a light emitting element and a pixel circuit for driving the light emitting element to emit light, wherein the pixel circuit comprises a driving subcircuit, a data writing subcircuit, a threshold compensation subcircuit and a reset subcircuit; The driving subcircuit includes a control terminal, a first terminal and a second terminal, and is configured to control a driving current flowing through the light emitting element. The data writing subcircuit is connected to the first end of the driving subcircuit, the data line and the gate scanning signal line, and is configured to write the data signal provided by the data line into the first end of the driving subcircuit in response to the gate scanning signal provided by the gate scanning signal line; The threshold compensation subcircuit is connected to the control terminal and the second terminal of the driving subcircuit, the first voltage line and the gate scanning signal line, and is configured to compensate the driving subcircuit in response to the gate scanning signal provided by the gate scanning signal line and the written data signal; The reset subcircuit is connected to the second end of the driving subcircuit, the initial signal line and the reset signal line, and is configured to apply an initial voltage provided by the initial signal line to the second end of the driving subcircuit in response to a reset signal provided by the reset signal line.

9. The display substrate according to claim 8, further comprising a semiconductor layer, a first conductive layer, a second conductive layer and a third conductive layer sequentially stacked in a direction perpendicular to the base substrate; in, The pixel circuit includes a thin film transistor and a storage capacitor; The thin film transistor comprises a gate, a source, a drain and source-drain regions corresponding to the source and the drain, and the storage capacitor comprises a first capacitor electrode and a second capacitor electrode opposite to the first capacitor electrode in a direction perpendicular to the plate surface of the substrate; The semiconductor layer includes the source and drain regions; The first conductive layer includes the gate of the thin film transistor, the first capacitor electrode of the storage capacitor and the gate scanning signal line, The second conductive layer includes the initial signal line and a second capacitor electrode of the storage capacitor; The third conductive layer includes the first voltage line, the source electrode and the drain electrode of the thin film transistor.

10. The display substrate according to claim 9, further comprising a fourth conductive layer, wherein: The fourth conductive layer includes the at least one switching electrode.

11. The display substrate according to claim 9, further comprising a fifth conductive layer; in, The fifth conductive layer includes the first routing line and the second routing line.

12. The display substrate according to any one of claims 3 to 4, wherein: The pixel units in each row of the first display sub-area are arranged in a step-like manner in a first direction.

13. The display substrate according to any one of claims 1 to 4, wherein: The number of pixel units in each row in the first display sub-area is less than or equal to the number of pixel units in each row in the second display sub-area.

14. A display device, comprising the display substrate according to any one of claims 1 to 13.

15. The display device according to claim 14, wherein: The peripheral area of ​​the display substrate further includes a third peripheral sub-area, The first peripheral sub-region is located between the second peripheral sub-region and the third peripheral sub-region; The second peripheral sub-region has a first straight edge portion extending along a first direction, the third peripheral sub-region has a second straight edge portion extending along a second direction, and the first peripheral sub-region has a corner edge portion connecting the first straight edge portion and the second straight edge portion; The first direction and the second direction intersect.

16. The display device according to claim 15, wherein: The display substrate has a display side and a non-display side. The first straight edge portion and the second straight edge portion are configured to be bendable toward the non-display side.

17. The display device according to claim 15, wherein: The corner edge portion includes an arc-shaped edge portion.

18. The display device according to any one of claims 15 to 17, wherein: The display substrate has a display side and a non-display side. The corner edge portion is configured to be bendable toward the non-display side.

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