Driving circuit, driving method, driving module and display device

Abstract

The present invention provides a driving circuit, a driving method, a driving module and a display device. The driving circuit includes a light-emitting control signal generating circuit and a gate driving circuit; the gate driving circuit is used to control the gate driving signal output terminal to output a gate driving signal according to a first clock signal provided by a first clock signal terminal and a first voltage signal provided by a first voltage terminal under the control of the potential of a first node, a first input signal provided by a first input terminal and a reset signal provided by a reset terminal. The present invention can generate a gate driving signal while generating a light-emitting control signal, can simplify the driving scheme, reduce the number of signals, and narrow the border.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a driving circuit, a driving method, a driving module and a display device. Background Art

[0002] In the related art, two driving circuits are required to generate a light-emitting control signal and a gate driving signal respectively, which cannot simplify the driving scheme and is not conducive to narrowing the frame. Summary of the invention

[0003] The main purpose of the present invention is to provide a driving circuit, a driving method, a driving module and a display device to solve the problem that the existing driving circuit cannot generate a light-emitting control signal and a gate driving signal at the same time, thereby failing to simplify the driving scheme and being unfavorable for narrowing the frame.

[0004] In one aspect, an embodiment of the present invention provides a driving circuit, including a light emitting control signal generating circuit and a gate driving circuit; the light emitting control signal generating circuit includes a first node control circuit, a second node control circuit, a third node control circuit and a light emitting control output circuit;

[0005] The first node control circuit is used to control the potential of the first node;

[0006] The second node control circuit is used to control the potential of the second node;

[0007] The third node control circuit is used to control the potential of the third node;

[0008] The light emitting control output circuit is used to control the light emitting control signal output terminal to output a light emitting control signal according to the potential of the second node and the potential of the third node;

[0009] The gate drive circuit is used to control the gate drive signal output terminal to output a gate drive signal according to the first clock signal provided by the first clock signal terminal and the first voltage signal provided by the first voltage terminal under the control of the potential of the first node, the first input signal provided by the first input terminal and the reset signal provided by the reset terminal.

[0010] Optionally, the gate driving circuit includes a fourth node control circuit and a gate output circuit;

[0011] The fourth node control circuit is used to control the fourth node to be connected or disconnected from the reset terminal under the control of the potential of the first node, and to control the fourth node to be connected or disconnected from the first voltage terminal under the control of the first input signal provided by the first input terminal;

[0012] The gate output circuit is used to control the connection or disconnection between the gate drive signal output terminal and the first clock signal terminal under the control of the potential of the fourth node, and to control the connection or disconnection between the gate drive signal output terminal and the first voltage terminal under the control of the first input signal, and is used to control the gate drive signal provided by the gate drive signal output terminal according to the potential of the fourth node.

[0013] Optionally, the driving circuit described in at least one embodiment of the present invention further includes a gate reset circuit;

[0014] The gate reset circuit is used to control the connection or disconnection between the gate drive signal output terminal and the first voltage terminal under the control of the potential of the first node.

[0015] Optionally, the fourth node control circuit includes a first transistor and a second transistor;

[0016] The control electrode of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the reset terminal, and the second electrode of the first transistor is electrically connected to the fourth node;

[0017] The control electrode of the second transistor is electrically connected to the first input terminal, the first electrode of the second transistor is electrically connected to the fourth node, and the second electrode of the second transistor is electrically connected to the first voltage terminal.

[0018] Optionally, the gate output circuit includes a third transistor, a fourth transistor and a first capacitor;

[0019] The control electrode of the third transistor is electrically connected to the fourth node, the first electrode of the third transistor is electrically connected to the first clock signal terminal, and the second electrode of the third transistor is electrically connected to the gate drive signal output terminal;

[0020] The control electrode of the fourth transistor is electrically connected to the first input terminal, the first electrode of the fourth transistor is electrically connected to the gate drive signal output terminal, and the second electrode of the fourth transistor is electrically connected to the first voltage terminal;

[0021] A first end of the first capacitor is electrically connected to the fourth node, and a second end of the first capacitor is electrically connected to the gate driving signal output end.

[0022] Optionally, the gate reset circuit includes a fifth transistor;

[0023] The control electrode of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the gate driving signal output terminal, and the second electrode of the fifth transistor is electrically connected to the first voltage terminal.

[0024] Optionally, the first node control circuit includes a fifth node control subcircuit and a first node control subcircuit;

[0025] The fifth node control subcircuit is used to control the connection or disconnection between the fifth node and the second voltage terminal under the control of the first clock signal provided by the first clock signal terminal, and to control the connection or disconnection between the fifth node and the first clock signal terminal under the control of the potential of the third node;

[0026] The first node control subcircuit is used to control the potential of the first node according to the potential of the fifth node and the second clock signal provided by the second clock signal terminal.

[0027] Optionally, the fifth node control subcircuit includes a sixth transistor and a seventh transistor;

[0028] The control electrode of the sixth transistor is electrically connected to the first clock signal terminal, the first electrode of the sixth transistor is electrically connected to the second voltage terminal, and the second electrode of the sixth transistor is electrically connected to the fifth node;

[0029] The control electrode of the seventh transistor is electrically connected to the third node, the first electrode of the seventh transistor is electrically connected to the first clock signal terminal, and the second electrode of the seventh transistor is electrically connected to the fifth node.

[0030] Optionally, the first node control subcircuit is used to control the connection or disconnection between the first node and the second clock signal terminal under the control of the potential of the fifth node, and is used to control the potential of the first node according to the potential of the fifth node.

[0031] Optionally, the first node control subcircuit includes an eighth transistor and a second capacitor;

[0032] A control electrode of the eighth transistor is electrically connected to the fifth node, a first electrode of the eighth transistor is electrically connected to the second clock signal terminal, and a second electrode of the eighth transistor is electrically connected to the first node;

[0033] A first end of the second capacitor is electrically connected to the fifth node, and a second end of the second capacitor is electrically connected to the first node.

[0034] Optionally, the driving circuit described in at least one embodiment of the present invention further includes a conduction control circuit; the conduction control circuit is used to control the connection or disconnection between the fifth node and the sixth node under the control of the second voltage signal provided by the second voltage terminal;

[0035] The first node control subcircuit is used to control the connection or disconnection between the first node and the second clock signal terminal under the control of the potential of the sixth node, and is used to control the potential of the first node according to the potential of the sixth node.

[0036] Optionally, the first node control subcircuit includes an eighth transistor and a second capacitor, and the conduction control circuit includes a first conduction control transistor;

[0037] The control electrode of the first conduction control transistor is electrically connected to the second voltage terminal, the first electrode of the first conduction control transistor is electrically connected to the fifth node, and the second electrode of the first conduction control transistor is electrically connected to the sixth node;

[0038] The control electrode of the eighth transistor is electrically connected to the sixth node, the first electrode of the eighth transistor is electrically connected to the second clock signal terminal, and the second electrode of the eighth transistor is electrically connected to the first node;

[0039] A first end of the second capacitor is electrically connected to the sixth node, and a second end of the second capacitor is electrically connected to the first node.

[0040] Optionally, the second node control circuit is used to control the connection or disconnection between the first node and the second node under the control of a second clock signal provided by a second clock signal terminal, and is used to control the connection or disconnection between the second node and the first voltage terminal under the control of the potential of the third node, and is used to maintain the potential of the second node.

[0041] Optionally, the second node control circuit includes a ninth transistor, a tenth transistor and a control capacitor;

[0042] The control electrode of the ninth transistor is electrically connected to the second clock signal terminal, the first electrode of the ninth transistor is electrically connected to the first node, and the second electrode of the ninth transistor is electrically connected to the second node;

[0043] The control electrode of the tenth transistor is electrically connected to the third node, the first electrode of the tenth transistor is electrically connected to the first voltage terminal, and the second electrode of the tenth transistor is electrically connected to the second node;

[0044] The first end of the control capacitor is electrically connected to the second node, and the second end of the control capacitor is connected to the first voltage end.

[0045] Optionally, the third node control circuit is used to control the connection or disconnection between the third node and the second input terminal under the control of the first clock signal provided by the first clock signal terminal, and to control the connection or disconnection between the third node and the first voltage terminal under the control of the potential of the fifth node and the second clock signal, and to control the potential of the third node according to the second clock signal.

[0046] Optionally, the third node control circuit includes an eleventh transistor, a twelfth transistor, a thirteenth transistor and a third capacitor;

[0047] The control electrode of the eleventh transistor is electrically connected to the first clock signal terminal, the first electrode of the eleventh transistor is electrically connected to the second input terminal, and the second electrode of the eleventh transistor is electrically connected to the third node;

[0048] The control electrode of the twelfth transistor is electrically connected to the fifth node, and the first electrode of the twelfth transistor is electrically connected to the first voltage terminal;

[0049] The control electrode of the thirteenth transistor is electrically connected to the second clock signal terminal, the first electrode of the thirteenth transistor is electrically connected to the second electrode of the twelfth transistor, and the second electrode of the thirteenth transistor is electrically connected to the third node;

[0050] A first end of the third capacitor is electrically connected to the second clock signal end, and a second end of the third capacitor is electrically connected to the third node.

[0051] Optionally, the third node control circuit includes a seventh node control subcircuit and a third node control subcircuit;

[0052] The seventh node control subcircuit is used to control the seventh node to be connected or disconnected with the first voltage terminal under the control of the potential of the fifth node, and to control the seventh node to be connected or disconnected with the second clock signal terminal under the control of the potential of the third node;

[0053] The third node control subcircuit is used to control the potential of the third node according to the potential of the seventh node, and control the connection or disconnection between the third node and the second input terminal under the control of the first clock signal provided by the first clock signal terminal.

[0054] Optionally, the third node control subcircuit includes an eleventh transistor and a third capacitor; the seventh node control subcircuit includes a twelfth transistor and a thirteenth transistor;

[0055] The control electrode of the eleventh transistor is electrically connected to the first clock signal terminal, the first electrode of the eleventh transistor is electrically connected to the second input terminal, and the second electrode of the eleventh transistor is electrically connected to the third node;

[0056] A control electrode of the twelfth transistor is electrically connected to the fifth node, a first electrode of the twelfth transistor is electrically connected to the first voltage terminal, and a second electrode of the twelfth transistor is electrically connected to the seventh node;

[0057] The control electrode of the thirteenth transistor is electrically connected to the third node, the first electrode of the thirteenth transistor is electrically connected to the second clock signal terminal, and the second electrode of the thirteenth transistor is electrically connected to the seventh node;

[0058] A first end of the third capacitor is electrically connected to the seventh node, and a second end of the third capacitor is electrically connected to the third node.

[0059] Optionally, the light emitting control output circuit includes a conduction subcircuit; the third node control circuit includes a third node control subcircuit, a seventh node control subcircuit and an eighth node control subcircuit;

[0060] The conduction subcircuit is used to control the connection or disconnection between the third node and the eighth node under the control of the second voltage signal provided by the second voltage terminal;

[0061] The third node control subcircuit is used to control the connection or disconnection between the third node and the second input terminal under the control of the first clock signal provided by the first clock signal terminal;

[0062] The seventh node control subcircuit is used to control the seventh node to be connected or disconnected with the first voltage terminal under the control of the potential of the fifth node, and to control the seventh node to be connected or disconnected with the second clock signal terminal under the control of the potential of the eighth node;

[0063] The eighth-node control subcircuit is used to control the potential of the eighth node according to the potential of the seventh node.

[0064] Optionally, the conduction subcircuit includes a second conduction control transistor, the third node control subcircuit includes an eleventh transistor, the seventh node control subcircuit includes a twelfth transistor and a thirteenth transistor; and the eighth node control subcircuit includes a third capacitor;

[0065] The control electrode of the second conduction control transistor is electrically connected to the second voltage terminal, the first electrode of the second conduction control transistor is electrically connected to the third node, and the second electrode of the second conduction control transistor is electrically connected to the eighth node;

[0066] The control electrode of the eleventh transistor is electrically connected to the first clock signal terminal, the first electrode of the eleventh transistor is electrically connected to the second input terminal, and the second electrode of the eleventh transistor is electrically connected to the third node;

[0067] A control electrode of the twelfth transistor is electrically connected to the fifth node, a first electrode of the twelfth transistor is electrically connected to the first voltage terminal, and a second electrode of the twelfth transistor is electrically connected to the seventh node;

[0068] The control electrode of the thirteenth transistor is electrically connected to the eighth node, the first electrode of the thirteenth transistor is electrically connected to the second clock signal terminal, and the second electrode of the thirteenth transistor is electrically connected to the seventh node;

[0069] A first end of the third capacitor is electrically connected to the seventh node, and a second end of the third capacitor is electrically connected to the eighth node.

[0070] Optionally, the light emitting control output circuit includes a first output transistor and a second output transistor;

[0071] The control electrode of the first output transistor is electrically connected to the third node, the first electrode of the first output transistor is electrically connected to the second voltage terminal, and the second electrode of the first output transistor is electrically connected to the light emission control signal output terminal;

[0072] The control electrode of the second output transistor is electrically connected to the second node, the first electrode of the second output transistor is electrically connected to the light emitting control signal output terminal, and the second electrode of the second output transistor is electrically connected to the first voltage terminal.

[0073] Optionally, the light emission control output circuit includes a second conduction control transistor, a first output transistor and a second output transistor;

[0074] The control electrode of the second conduction control transistor is electrically connected to the second voltage terminal, the first electrode of the second conduction control transistor is electrically connected to the third node, and the second electrode of the second conduction control transistor is electrically connected to the eighth node;

[0075] The control electrode of the first output transistor is electrically connected to the eighth node, the first electrode of the first output transistor is electrically connected to the second voltage terminal, and the second electrode of the first output transistor is electrically connected to the light emitting control signal output terminal;

[0076] The control electrode of the second output transistor is electrically connected to the second node, the first electrode of the second output transistor is electrically connected to the light emitting control signal output terminal, and the second electrode of the second output transistor is electrically connected to the first voltage terminal.

[0077] In a second aspect, the present invention further provides a driving method, which is applied to the above-mentioned driving circuit, and the driving method comprises:

[0078] The gate drive circuit controls the gate drive signal output terminal to output the gate drive signal according to the first clock signal provided by the first clock signal terminal and the first voltage signal provided by the first voltage terminal, under the control of the potential of the first node, the first input signal provided by the first input terminal and the reset signal provided by the reset terminal.

[0079] Optionally, the driving cycle includes a first input stage, a second input stage, a third input stage and a first reset stage which are arranged in sequence; and the driving method includes:

[0080] In the first input stage, the fourth node control circuit controls the fourth node to be disconnected from the reset terminal under the control of the potential of the first node, and controls the fourth node to be disconnected from the first voltage terminal under the control of the first input signal; the gate output circuit controls the gate drive signal output terminal to be disconnected from the first clock signal terminal under the control of the potential of the fourth node, and controls the gate drive signal output terminal to be disconnected from the first voltage terminal under the control of the first input signal, so that the gate drive signal output terminal maintains outputting the first voltage signal;

[0081] In the second input stage, the fourth node control circuit controls the fourth node to be connected to the reset terminal under the control of the potential of the first node; the gate output circuit controls the gate drive signal output terminal to be connected to the first clock signal terminal under the control of the potential of the fourth node, so that the gate drive signal output terminal outputs the first voltage signal;

[0082] In the third input stage, the fourth node control circuit controls the fourth node to be disconnected from the reset terminal under the control of the potential of the first node; the gate output circuit controls the gate drive signal output terminal to be connected to the first clock signal terminal under the control of the potential of the fourth node, so that the gate drive signal output terminal outputs the second voltage signal;

[0083] In the first reset stage, the fourth node control circuit controls the connection between the fourth node and the reset terminal under the control of the potential of the first node, and controls the connection between the fourth node and the first voltage terminal under the control of the first input signal; the gate output circuit controls the gate drive signal output terminal to be disconnected from the first clock signal terminal under the control of the potential of the fourth node, and controls the gate drive signal output terminal to be connected to the first voltage terminal under the control of the first input signal, so that the gate drive signal output terminal outputs the first voltage signal.

[0084] Optionally, the driving circuit further includes a gate reset circuit; and the driving method further includes:

[0085] In the first input stage, the gate reset circuit controls the gate drive signal output terminal to be disconnected from the first voltage terminal under the control of the potential of the first node;

[0086] In the second input stage, the gate reset circuit controls the gate drive signal output terminal to be connected to the first voltage terminal under the control of the potential of the first node;

[0087] In the third input stage, the gate reset circuit controls the gate drive signal output terminal to be disconnected from the first voltage terminal under the control of the potential of the first node;

[0088] In the first reset stage, the gate reset circuit controls the gate drive signal output terminal to be connected to the first voltage terminal under the control of the potential of the first node.

[0089] In a third aspect, the present invention further provides a driving module, comprising multiple levels of the above-mentioned driving circuits.

[0090] Optionally, the second input terminal of the driving circuit is electrically connected to the light emitting control signal output terminal of an adjacent upper-level driving circuit.

[0091] Optionally, the first input terminal of the driving circuit is electrically connected to the light-emitting control signal output terminal of the adjacent upper-level driving circuit; or, the first input terminal of the driving circuit is electrically connected to the light-emitting control signal output terminal of the driving circuit.

[0092] Optionally, the reset terminal of the driving circuit is electrically connected to the light-emitting control signal output terminal of the adjacent next-stage driving circuit; or, the reset terminal is electrically connected to the gate driving signal output terminal of the adjacent previous-stage driving circuit.

[0093] In a fourth aspect, an embodiment of the present invention provides a display device, comprising the above-mentioned driving module.

[0094] The driving circuit, driving method, driving module and display device described in the embodiments of the present invention can generate a gate driving signal while generating a light-emitting control signal, thereby simplifying the driving scheme, reducing the number of signals, and narrowing the frame. BRIEF DESCRIPTION OF THE DRAWINGS

[0095] Figure 1 is a structural diagram of a driving circuit according to an embodiment of the present invention;

[0096] Figure 2 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0097] Figure 3 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0098] Figure 4 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0099] Figure 5 yes Figure 4 An operation timing diagram of at least one embodiment of the driving circuit shown;

[0100] Figure 6 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0101] Figure 7 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0102] Figure 8 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0103] Fig. 9 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0104] Fig.10 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0105] Fig.11 The present invention is Fig.10 An operation timing diagram of at least one embodiment of the driving circuit;

[0106] Fig. 12A The present invention is Fig.10 A schematic diagram of the working state of at least one embodiment of the driving circuit in the first preparation stage t01;

[0107] Fig. 12B The present invention is Fig.10 A schematic diagram of the working state of at least one embodiment of the driving circuit in the second preparation stage t02;

[0108] Fig. 12C The present invention is Fig.10 A schematic diagram of the working state of at least one embodiment of the driving circuit in the first input stage t1;

[0109] Fig.12D The present invention is Fig.10 A schematic diagram of the working state of at least one embodiment of the driving circuit in the second input stage t2;

[0110] Fig.12E The present invention is Fig.10 A schematic diagram of the working state of at least one embodiment of the driving circuit in the third input stage t3;

[0111] Fig.12F The present invention is Fig.10 A schematic diagram of the working state of at least one embodiment of the driving circuit in the first reset stage t4;

[0112] Figure 12G The present invention is Fig.10 A schematic diagram of the working state of at least one embodiment of the driving circuit in the second reset stage t5;

[0113] Fig.12H The present invention is Fig.10 A schematic diagram of the working state of at least one embodiment of the driving circuit in the third reset stage t6;

[0114] Fig.13 is a waveform diagram of a light emitting control signal and a gate driving signal provided by a driving circuit according to at least one embodiment of the present invention;

[0115] Fig.14 is a waveform diagram of a light emitting control signal and a gate driving signal provided by a driving circuit according to at least one embodiment of the present invention;

[0116] Fig.15 is a waveform diagram of a light emitting control signal and a gate driving signal provided by a driving circuit according to at least one embodiment of the present invention;

[0117] Fig.16 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0118] Fig.17 The present invention is Fig.16 An operation timing diagram of at least one embodiment of the driving circuit;

[0119] Fig.18 FIG. 1 is a structural diagram of a gate driving circuit provided by at least one embodiment of the present invention;

[0120] Fig.19 is a structural diagram of at least one embodiment of the gate drive circuit;

[0121] Fig. 20 is a structural diagram of at least one embodiment of the gate drive circuit;

[0122] Fig.21 is a circuit diagram of at least one embodiment of the gate drive circuit;

[0123] Fig. 22 is a working timing diagram of at least one embodiment of the gate driving circuit. DETAILED DESCRIPTION

[0124] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0125] The transistors used in all embodiments of the present invention may be triodes, thin film transistors, field effect transistors or other devices with the same characteristics. In the embodiments of the present invention, in order to distinguish the two electrodes of the transistor except the control electrode, one of the electrodes is called the first electrode and the other is called the second electrode.

[0126] In actual operation, when the transistor is a triode, the control electrode may be a base, the first electrode may be a collector, and the second electrode may be an emitter; or, the control electrode may be a base, the first electrode may be an emitter, and the second electrode may be a collector.

[0127] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode can be a gate, the first electrode can be a drain, and the second electrode can be a source; or, the control electrode can be a gate, the first electrode can be a source, and the second electrode can be a drain.

[0128] like Figure 1 As shown, the driving circuit according to the embodiment of the present invention includes a light emitting control signal generating circuit and a gate driving circuit 10; the light emitting control signal generating circuit includes a first node control circuit 11, a second node control circuit 12, a third node control circuit 13 and a light emitting control output circuit 14;

[0129] The first node control circuit 11 is electrically connected to the first node PU1 and is used to control the potential of the first node PU1;

[0130] The second node control circuit 12 is electrically connected to the second node PU and is used to control the potential of the second node PU;

[0131] The third node control circuit 13 is electrically connected to the third node PD1 and is used to control the potential of the third node PD1;

[0132] The light emitting control output circuit 14 is electrically connected to the second node PU, the third node PD1 and the light emitting control signal output terminal E1 respectively, and is used to control the light emitting control signal output terminal E1 to output a light emitting control signal according to the potential of the second node PU and the potential of the third node PD1;

[0133] The gate drive circuit 10 is electrically connected to the first node PU1, the first input terminal I1, the reset terminal R1, the first clock signal terminal K1, the first voltage terminal V1 and the gate drive signal output terminal G1, respectively, and is used to control the gate drive signal output terminal G1 to output a gate drive signal according to the first clock signal provided by the first clock signal terminal K1 and the first voltage signal provided by the first voltage terminal V1, under the control of the potential of the first node PU1, the first input signal provided by the first input terminal I1 and the reset signal provided by the reset terminal R1.

[0134] In the driving circuit described in the embodiment of the present invention, a gate driving circuit for generating a gate driving signal is added, and a signal obtained by performing an "OR" operation on the reset signal provided by the reset terminal R1 and the voltage signal of the first node PU1 of the row is used as an input / reset function. That is, when the reset signal and the voltage signal of the first node PU1 of the row are both valid voltage signals, the input function is realized, and when the voltage signal of the first node PU1 of the row is a valid voltage signal and the reset signal is an invalid voltage signal, the reset function is realized. When the first input signal provided by I1 is a valid voltage signal, G1 is denoised, so that the driving circuit described in the embodiment of the present invention can generate a gate driving signal while generating a light-emitting control signal, which can simplify the driving scheme, reduce the number of signals, and narrow the border.

[0135] like Figure 2As shown, the driving circuit according to the embodiment of the present invention includes a light emitting control signal generating circuit and a gate driving circuit; the light emitting control signal generating circuit includes a first node control circuit 11, a second node control circuit 12, a third node control circuit 13 and a light emitting control output circuit 14; the gate driving circuit includes a fourth node control circuit 21 and a gate output circuit 23;

[0136] The first node control circuit 11 is electrically connected to the first node PU1 and is used to control the potential of the first node PU1;

[0137] The second node control circuit 12 is electrically connected to the second node PU and is used to control the potential of the second node PU;

[0138] The third node control circuit 13 is electrically connected to the third node PD1 and is used to control the potential of the third node PD1;

[0139] The light emitting control output circuit 14 is electrically connected to the second node PU, the third node PD1 and the light emitting control signal output terminal E1 respectively, and is used to control the light emitting control signal output terminal E1 to output a light emitting control signal according to the potential of the second node PU and the potential of the third node PD1;

[0140] The fourth node control circuit 21 is electrically connected to the first node PU1, the fourth node PPU, the reset terminal R1, the first input terminal I1 and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the fourth node PPU and the reset terminal R1 under the control of the potential of the first node PU1, and control the connection or disconnection between the fourth node PPU and the first voltage terminal V1 under the control of the first input signal provided by the first input terminal I1;

[0141] The gate output circuit 23 is electrically connected to the fourth node PPU, the gate drive signal output terminal G1, the first clock signal terminal K1, the first input terminal I1 and the first voltage terminal V1, respectively, and is used to control the connection or disconnection between the gate drive signal output terminal G1 and the first clock signal terminal K1 under the control of the potential of the fourth node PPU, and control the connection or disconnection between the gate drive signal output terminal G1 and the first voltage terminal V1 under the control of the first input signal provided by the first input terminal I1, and is used to control the gate drive signal provided by the gate drive signal output terminal G1 according to the potential of the fourth node PPU.

[0142] In the driving circuit described in the embodiment of the present invention, a gate driving circuit for generating a gate driving signal is added, and a signal obtained by performing an "OR" operation on the reset signal provided by the reset terminal R1 and the voltage signal of the first node PU1 of the row is used as an input / reset function. That is, when the reset signal and the voltage signal of the first node PU1 of the row are both valid voltage signals, the input function is realized (input for the fourth node PPU), and when the voltage signal of the first node PU1 of the row is a valid voltage signal and the reset signal is an invalid voltage signal, the reset function is realized (resetting the fourth node PPU), and when the first input signal provided by I1 is a valid voltage signal, the fourth node PPU and G1 are denoised, so that the driving circuit described in the embodiment of the present invention can generate a gate driving signal while generating a light-emitting control signal, which can simplify the driving scheme, reduce the number of signals, and narrow the border.

[0143] In at least one embodiment of the present invention, when the transistors included in the driving circuit are p-type transistors, the effective voltage signal can be a low voltage signal, and the invalid voltage signal can be a high voltage signal; when the transistors included in the driving circuit are n-type transistors, the effective voltage signal can be a high voltage signal, and the invalid voltage signal can be a low voltage signal.

[0144] When the driving circuit of the embodiment of the present invention is working, the pulse width of the light-emitting control signal generated is adjustable, and the light-emitting control signal can be a signal with a low voltage validity, and the gate driving signal generated can be a signal with a low voltage validity. In addition, the time for which the potential of the light-emitting control signal continues to be a high voltage can be greater than or equal to 2H (the pulse width of the light-emitting control signal is adjustable), and the time for which the gate driving signal continues to be a low voltage can be less than or equal to 1H.

[0145] Among them, 1H is the theoretical charging time of one row of pixels, 1H=1 / frame refresh frequency / number of rows.

[0146] Optionally, the first voltage terminal may be a high voltage terminal.

[0147] The present invention Figure 2 When the embodiment of the driving circuit shown is in operation, the driving cycle may include a first input stage, a second input stage, a third input stage and a first reset stage which are arranged in sequence;

[0148] In the first input stage, the fourth node control circuit 21 controls the fourth node PPU to be disconnected from the reset terminal R1 under the control of the potential of the first node PU1, and controls the fourth node PPU to be disconnected from the first voltage terminal V1 under the control of the first input signal; the gate output circuit 23 controls the gate drive signal output terminal G1 to be disconnected from the first clock signal terminal K1 under the control of the potential of the fourth node PPU, and controls the gate drive signal output terminal G1 to be disconnected from the first voltage terminal V1 under the control of the first input signal, so that the gate drive signal output terminal G1 maintains to output the first voltage signal;

[0149] In the second input stage, the fourth node control circuit 21 controls the fourth node PPU to be connected to the reset terminal R1 under the control of the potential of the first node PU1; the gate output circuit 23 controls the gate drive signal output terminal G1 to be connected to the first clock signal terminal K1 under the control of the potential of the fourth node PPU, so that the gate drive signal output terminal G1 outputs the first voltage signal;

[0150] In the third input stage, the fourth node control circuit 21 controls the fourth node PPU to be disconnected from the reset terminal R1 under the control of the potential of the first node PU1; the gate output circuit 23 controls the gate drive signal output terminal G1 to be connected to the first clock signal terminal K1 under the control of the potential of the fourth node PPU, so that the gate drive signal output terminal G1 outputs the second voltage signal;

[0151] In the first reset stage, the fourth node control circuit 21 controls the connection between the fourth node PPU and the reset terminal R1 under the control of the potential of the first node PU1, and controls the connection between the fourth node PPU and the first voltage terminal V1 under the control of the first input signal; the gate output circuit 23 controls the disconnection between the gate drive signal output terminal G1 and the first clock signal terminal K1 under the control of the potential of the fourth node PPU, and controls the connection between the gate drive signal output terminal G1 and the first voltage terminal V1 under the control of the first input signal, so that the gate drive signal output terminal G1 outputs the first voltage signal.

[0152] In at least one embodiment of the present invention, the first voltage signal may be a high voltage signal, and the second voltage signal may be a low voltage signal.

[0153] Optionally, the first input terminal may be electrically connected to the light-emitting control signal output terminal of an adjacent upper-level driving circuit; or, the first input terminal of the driving circuit may be electrically connected to the light-emitting control signal output terminal of the driving circuit.

[0154] Optionally, the reset terminal of the driving circuit is electrically connected to the light-emitting control signal output terminal of the adjacent next-stage driving circuit; or, the reset terminal is electrically connected to the gate driving signal output terminal of the adjacent previous-stage driving circuit.

[0155] like Figure 3 As shown, in Figure 2 Based on the embodiment of the driving circuit shown, the driving circuit according to at least one embodiment of the present invention may further include a gate reset circuit 24;

[0156] The gate reset circuit 24 is electrically connected to the first node PU1, the gate drive signal output terminal G1 and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the gate drive signal output terminal G1 and the first voltage terminal V1 under the control of the potential of the first node PU1.

[0157] In a specific implementation, in order to prevent the potential of the first input signal provided by I1 from remaining an invalid voltage for too long and failing to reset G1 in time, the gate reset circuit 24 is added to control the gate drive signal output terminal to output a first voltage signal under the control of the potential of the first node PU1 to reset G1.

[0158] The present invention Figure 3 At least one embodiment of the driving circuit shown in the figure is in operation.

[0159] In the first input stage, the gate reset circuit 24 controls the gate drive signal output terminal G1 to be disconnected from the first voltage terminal V1 under the control of the potential of the first node PU1;

[0160] In the second input stage, the gate reset circuit 24 controls the gate drive signal output terminal G1 to be connected to the first voltage terminal V1 under the control of the potential of the first node PU1;

[0161] In the third input stage, the gate reset circuit 24 controls the gate drive signal output terminal G1 to be disconnected from the first voltage terminal V1 under the control of the potential of the first node PU1;

[0162] In the first reset stage, the gate reset circuit 24 controls the connection between the gate driving signal output terminal G1 and the first voltage terminal V1 under the control of the potential of the first node PU1 to reset G1.

[0163] Optionally, the fourth node control circuit includes a first transistor and a second transistor;

[0164] The control electrode of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the reset terminal, and the second electrode of the first transistor is electrically connected to the fourth node;

[0165] The control electrode of the second transistor is electrically connected to the first input terminal, the first electrode of the second transistor is electrically connected to the fourth node, and the second electrode of the second transistor is electrically connected to the first voltage terminal.

[0166] Optionally, the gate output circuit includes a third transistor, a fourth transistor and a first capacitor;

[0167] The control electrode of the third transistor is electrically connected to the fourth node, the first electrode of the third transistor is electrically connected to the first clock signal terminal, and the second electrode of the third transistor is electrically connected to the gate drive signal output terminal;

[0168] The control electrode of the fourth transistor is electrically connected to the first input terminal, the first electrode of the fourth transistor is electrically connected to the gate drive signal output terminal, and the second electrode of the fourth transistor is electrically connected to the first voltage terminal;

[0169] A first end of the first capacitor is electrically connected to the fourth node, and a second end of the first capacitor is electrically connected to the gate driving signal output end.

[0170] In at least one embodiment of the present invention, the first capacitor is used to couple the fourth node, so that the transistor whose control electrode is electrically connected to the fourth node is turned on more fully, thereby outputting a waveform to the gate drive signal output terminal.

[0171] Optionally, the gate reset circuit includes a fifth transistor;

[0172] The control electrode of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the gate driving signal output terminal, and the second electrode of the fifth transistor is electrically connected to the first voltage terminal.

[0173] like Figure 4 As shown, in Figure 3 Based on at least one embodiment of the driving circuit shown, the fourth node control circuit 21 includes a first transistor M1 and a second transistor M2;

[0174] The gate of the first transistor M1 is electrically connected to the first node PU1, the first electrode of the first transistor M1 is electrically connected to the reset terminal R1, and the second electrode of the first transistor M1 is electrically connected to the fourth node PPU;

[0175] The gate of the second transistor M2 is electrically connected to the first input terminal I1, the first electrode of the second transistor M2 is electrically connected to the fourth node PPU, and the second electrode of the second transistor M2 is electrically connected to the high voltage terminal V01;

[0176] The gate output circuit 23 includes a third transistor M3, a fourth transistor M4 and a first capacitor C1;

[0177] The gate of the third transistor M3 is electrically connected to the fourth node PPU, the first electrode of the third transistor M3 is electrically connected to the first clock signal terminal K1, and the second electrode of the third transistor M3 is electrically connected to the gate drive signal output terminal G1;

[0178] The gate of the fourth transistor M4 is electrically connected to the first input terminal I1, the first electrode of the fourth transistor M4 is electrically connected to the gate drive signal output terminal G1, and the second electrode of the fourth transistor M4 is electrically connected to the high voltage terminal V01;

[0179] The gate reset circuit 24 includes a fifth transistor M5;

[0180] The gate of the fifth transistor M5 is electrically connected to the first node PU1, the first electrode of the fifth transistor M5 is electrically connected to the gate drive signal output terminal G1, and the second electrode of the fifth transistor M5 is electrically connected to the high voltage terminal V01;

[0181] A first end of the first capacitor C1 is electrically connected to the fourth node PPU, and a second end of the first capacitor C1 is electrically connected to the gate driving signal output terminal G1.

[0182] exist Figure 4 In at least one embodiment of the driving circuit shown, each transistor is a p-type transistor.

[0183] like Figure 5 As shown, the present invention is Figure 4 When at least one embodiment of the driving circuit shown is in operation, the driving cycle includes a first preparation phase t01, a second preparation phase t02, a first input phase t1, a second input phase t2, a third input phase t3, a first reset phase t4, a second reset phase t5 and a third reset phase t6, which are arranged in sequence;

[0184] In the first preparation stage t01, K1 provides a low voltage signal, I1 provides a low voltage signal, R1 provides a low voltage signal, the potential of PU1 is a high voltage, the potential of PPU is a high voltage, M1 is turned off, M2 is turned on, M3 is turned off, M4 is turned on, M5 is turned off, and G1 outputs a high voltage signal;

[0185] In the second preparation stage t01, K1 provides a high voltage signal, I1 provides a low voltage signal, R1 provides a low voltage signal, the potential of PU1 is a high voltage, the potential of PPU is a high voltage, M1 is off, M2 is on, M3 is off, M4 is on, M5 is off, and G1 outputs a high voltage signal;

[0186] In the first input stage t1, K1 provides a low voltage signal, I1 provides a high voltage signal, R1 provides a low voltage signal, the potential of PU1 is a high voltage, the potential of PPU is a high voltage, M1, M2, M3, M4 and M5 are all turned off, and G1 continuously outputs a high voltage signal;

[0187] In the second input stage t2, K1 provides a high voltage signal, I1 provides a high voltage signal, R1 provides a low voltage signal, the potential of PU1 is a low voltage, the potential of PPU is pulled low, M1 is turned on, M2 is turned off, M3 is turned on, M4 is turned off, M5 is turned on, and G1 provides a high voltage signal;

[0188] In the third input stage t3, K1 provides a low voltage signal, I1 provides a high voltage signal, R1 provides a high voltage signal, the potential of PU1 is a high voltage, the potential of PPU is further pulled down, M1 and M2 are turned off, M3 is turned on, M4 is turned off, M5 is turned off, and G1 provides a low voltage signal;

[0189] In the first reset stage t4, K1 provides a high voltage signal, I1 provides a low voltage signal, R1 provides a high voltage signal, the potential of PU1 is a low voltage, the potential of PPU is a high voltage, M1 and M2 are turned on, M3 is turned off, M4 is turned on, M5 is turned on, and G1 provides a high voltage signal to reset G1;

[0190] In the second reset stage t5, K1 provides a low voltage signal, I1 provides a low voltage signal, R1 provides a high voltage signal, the potential of PU1 is a high voltage, the potential of PPU is a high voltage, M1 is turned off, M2 is turned on, M3 is turned off, M4 is turned on, M5 is turned off, and G1 provides a high voltage signal;

[0191] In the third reset stage t6, K1 provides a high voltage signal, I1 provides a low voltage signal, R1 provides a low voltage signal, the potential of PU1 is a high voltage, the potential of PPU is a high voltage, M1 is turned off, M2 is turned on, M3 is turned off, M4 is turned on, M5 is turned off, and G1 provides a high voltage signal.

[0192] like Figure 5 As shown, the potential of the light emitting control signal provided by E1 continues to be a high voltage for 3 hours, and the potential of the gate driving signal provided by G1 continues to be a low voltage for 1 hour.

[0193] Figure 5 The light emitting control signal and gate driving signal shown in the figure are driving signals in actual application, and the duty cycle is less than 50%. The effective width is less than 1H, and the period is 2H, so the duty cycle is less than 50%, resulting in gaps between each stage in the figure separated by dotted lines.

[0194] In at least one embodiment of the present invention, Figure 6 As shown, in Figure 4Based on at least one embodiment of the driving circuit shown, the first node control circuit may include a fifth node control subcircuit 51 and a first node control subcircuit 52;

[0195] The fifth node control subcircuit 51 is electrically connected to the first clock signal terminal K1, the fifth node PD2, the second voltage terminal V2 and the third node PD1 respectively, and is used to control the connection or disconnection between the fifth node PD2 and the second voltage terminal V2 under the control of the first clock signal provided by the first clock signal terminal K1, and control the connection or disconnection between the fifth node PD2 and the first clock signal terminal K1 under the control of the potential of the third node PD1;

[0196] The first node control subcircuit 52 is electrically connected to the fifth node PD2, the second clock signal terminal K2 and the first node PU1, respectively, and is used to control the potential of the first node PU1 according to the potential of the fifth node PD2 and the second clock signal provided by the second clock signal terminal K2.

[0197] In at least one embodiment of the present invention, the first node control subcircuit 52 can be used to control the connection or disconnection between the first node PU1 and the second clock signal terminal K2 under the control of the potential of the fifth node PD2, and to control the potential of the first node PU1 according to the potential of the fifth node PD2.

[0198] Optionally, the fifth node control subcircuit includes a sixth transistor and a seventh transistor;

[0199] The control electrode of the sixth transistor is electrically connected to the first clock signal terminal, the first electrode of the sixth transistor is electrically connected to the second voltage terminal, and the second electrode of the sixth transistor is electrically connected to the fifth node;

[0200] The control electrode of the seventh transistor is electrically connected to the third node, the first electrode of the seventh transistor is electrically connected to the first clock signal terminal, and the second electrode of the seventh transistor is electrically connected to the fifth node.

[0201] Optionally, the first node control subcircuit includes an eighth transistor and a second capacitor;

[0202] A control electrode of the eighth transistor is electrically connected to the fifth node, a first electrode of the eighth transistor is electrically connected to the second clock signal terminal, and a second electrode of the eighth transistor is electrically connected to the first node;

[0203] A first end of the second capacitor is electrically connected to the fifth node, and a second end of the second capacitor is electrically connected to the first node.

[0204] The driving circuit according to at least one embodiment of the present invention may further include a conduction control circuit; the conduction control circuit is used to control the connection or disconnection between the fifth node and the sixth node under the control of the second voltage signal provided by the second voltage terminal;

[0205] The first node control subcircuit is used to control the connection or disconnection between the first node and the second clock signal terminal under the control of the potential of the sixth node, and is used to control the potential of the first node according to the potential of the sixth node.

[0206] In a specific implementation, the driving circuit described in at least one embodiment of the present invention may include a conduction control circuit, which controls the connection or disconnection between the fifth node and the sixth node, and the first node control subcircuit controls the potential of the first node under the control of the potential of the sixth node.

[0207] like Figure 7 As shown, in Figure 3 Based on at least one embodiment of the driving circuit shown in the figure, the driving circuit according to at least one embodiment of the present invention may further include a conduction control circuit 60; the first node control circuit may include a fifth node control subcircuit 51 and a first node control subcircuit 52;

[0208] The conduction control circuit 60 is electrically connected to the second voltage terminal V2, the fifth node PD2 and the sixth node PD22 respectively, and is used to control the connection or disconnection between the fifth node PD2 and the sixth node PD22 under the control of the second voltage signal provided by the second voltage terminal V2;

[0209] The fifth node control subcircuit 51 is electrically connected to the first clock signal terminal K1, the fifth node PD2, the second voltage terminal V2 and the third node PD1 respectively, and is used to control the connection or disconnection between the fifth node PD2 and the second voltage terminal V2 under the control of the first clock signal provided by the first clock signal terminal K1, and control the connection or disconnection between the fifth node PD2 and the first clock signal terminal K1 under the control of the potential of the third node PD1;

[0210] The first node control subcircuit 52 is electrically connected to the sixth node PD22, the first node PU1 and the second clock signal terminal K2, respectively, and is used to control the connection or disconnection between the first node PU1 and the second clock signal terminal K2 under the control of the potential of the sixth node PD22, and is used to control the potential of the first node PU1 according to the potential of the sixth node PD22.

[0211] exist Figure 7In at least one embodiment of the driving circuit shown, the conduction control circuit 60 controls the connection or disconnection between PD2 and PD22 under the control of the second voltage signal, the fifth node control subcircuit 51 controls the potential of the fifth node PD2, and the first node control subcircuit 52 controls the potential of the first node PU1.

[0212] Optionally, the first node control subcircuit includes an eighth transistor and a second capacitor, and the conduction control circuit includes a first conduction control transistor;

[0213] The control electrode of the first conduction control transistor is electrically connected to the second voltage terminal, the first electrode of the first conduction control transistor is electrically connected to the fifth node, and the second electrode of the first conduction control transistor is electrically connected to the sixth node;

[0214] The control electrode of the eighth transistor is electrically connected to the sixth node, the first electrode of the eighth transistor is electrically connected to the second clock signal terminal, and the second electrode of the eighth transistor is electrically connected to the first node;

[0215] A first end of the second capacitor is electrically connected to the sixth node, and a second end of the second capacitor is electrically connected to the first node.

[0216] In at least one embodiment of the present invention, the second node control circuit is electrically connected to the second clock signal terminal K2, the first node PU1, the second node PU, the third node PD1 and the first voltage terminal V1, respectively, and is used to control the connection or disconnection between the first node PU1 and the second node PU under the control of the second clock signal provided by the second clock signal terminal K2, and is used to control the connection or disconnection between the second node PU and the first voltage terminal V1 under the control of the potential of the third node PD1, and is used to maintain the potential of the second node PU.

[0217] Optionally, the second node control circuit includes a ninth transistor, a tenth transistor and a control capacitor;

[0218] The control electrode of the ninth transistor is electrically connected to the second clock signal terminal, the first electrode of the ninth transistor is electrically connected to the first node, and the second electrode of the ninth transistor is electrically connected to the second node;

[0219] The control electrode of the tenth transistor is electrically connected to the third node, the first electrode of the tenth transistor is electrically connected to the first voltage terminal, and the second electrode of the tenth transistor is electrically connected to the second node;

[0220] The first end of the control capacitor is electrically connected to the second node, and the second end of the control capacitor is connected to the first voltage end.

[0221] In at least one embodiment of the present invention, Figure 7As shown, the third node control circuit is electrically connected to the first clock signal terminal K1, the third node PD1, the second input terminal I2, the fifth node PD2, the second clock signal terminal K2 and the first voltage terminal V1, respectively, and is used to control the connection or disconnection between the third node PD1 and the second input terminal I2 under the control of the first clock signal provided by the first clock signal terminal K1, and to control the connection or disconnection between the third node PD1 and the first voltage terminal V1 under the control of the potential of the fifth node PD2 and the second clock signal provided by the second clock signal terminal K2, and is used to control the potential of the third node PD1 according to the second clock signal.

[0222] Optionally, the third node control circuit includes an eleventh transistor, a twelfth transistor, a thirteenth transistor and a third capacitor;

[0223] The control electrode of the eleventh transistor is electrically connected to the first clock signal terminal, the first electrode of the eleventh transistor is electrically connected to the second input terminal, and the second electrode of the eleventh transistor is electrically connected to the third node;

[0224] The control electrode of the twelfth transistor is electrically connected to the fifth node, and the first electrode of the twelfth transistor is electrically connected to the first voltage terminal;

[0225] The control electrode of the thirteenth transistor is electrically connected to the second clock signal terminal, the first electrode of the thirteenth transistor is electrically connected to the second electrode of the twelfth transistor, and the second electrode of the thirteenth transistor is electrically connected to the third node;

[0226] A first end of the third capacitor is electrically connected to the second clock signal end, and a second end of the third capacitor is electrically connected to the third node.

[0227] like Figure 8 As shown, in Figure 6 Based on at least one embodiment of the driving circuit shown in FIG. 1 , the second node control circuit 12 is electrically connected to the second clock signal terminal K2, the first node PU1, the second node PU, the third node PD1 and the first voltage terminal V1, respectively, and is used to control the connection or disconnection between the first node PU1 and the second node PU under the control of the second clock signal provided by the second clock signal terminal K2, and is used to control the connection or disconnection between the second node PU and the first voltage terminal V1 under the control of the potential of the third node PD1;

[0228] The third node control circuit 13 is electrically connected to the first clock signal terminal K1, the third node PD1, the second input terminal I2, the fifth node PD2, the second clock signal terminal K2 and the first voltage terminal V1, respectively, and is used to control the connection or disconnection between the third node PD1 and the second input terminal I2 under the control of the first clock signal provided by the first clock signal terminal K1, and to control the connection or disconnection between the third node PD1 and the first voltage terminal V1 under the control of the potential of the fifth node PD2 and the second clock signal provided by the second clock signal terminal K2, and to control the potential of the third node PD1 according to the second clock signal.

[0229] exist Figure 8 In at least one embodiment of the driving circuit shown, the second node control circuit 12 controls the potential of the second node PU, and the third node control circuit 13 controls the potential of the third node PD1.

[0230] In at least one embodiment of the present invention, the third node control circuit may include a seventh node control subcircuit and a third node control subcircuit;

[0231] The seventh node control subcircuit is used to control the seventh node to be connected or disconnected with the first voltage terminal under the control of the potential of the fifth node, and to control the seventh node to be connected or disconnected with the second clock signal terminal under the control of the potential of the third node;

[0232] The third node control subcircuit is used to control the potential of the third node according to the potential of the seventh node, and control the connection or disconnection between the third node and the second input terminal under the control of the first clock signal provided by the first clock signal terminal.

[0233] Optionally, the third node control subcircuit includes an eleventh transistor and a third capacitor;

[0234] The seventh node control subcircuit includes a twelfth transistor and a thirteenth transistor;

[0235] The control electrode of the eleventh transistor is electrically connected to the first clock signal terminal, the first electrode of the eleventh transistor is electrically connected to the second input terminal, and the second electrode of the eleventh transistor is electrically connected to the third node;

[0236] A control electrode of the twelfth transistor is electrically connected to the fifth node, a first electrode of the twelfth transistor is electrically connected to the first voltage terminal, and a second electrode of the twelfth transistor is electrically connected to the seventh node;

[0237] The control electrode of the thirteenth transistor is electrically connected to the third node, the first electrode of the thirteenth transistor is electrically connected to the second clock signal terminal, and the second electrode of the thirteenth transistor is electrically connected to the seventh node;

[0238] A first end of the third capacitor is electrically connected to the seventh node, and a second end of the third capacitor is electrically connected to the third node.

[0239] Optionally, the light emitting control output circuit includes a first output transistor and a second output transistor;

[0240] The control electrode of the first output transistor is electrically connected to the third node, the first electrode of the first output transistor is electrically connected to the second voltage terminal, and the second electrode of the first output transistor is electrically connected to the light emission control signal output terminal;

[0241] The control electrode of the second output transistor is electrically connected to the second node, the first electrode of the second output transistor is electrically connected to the light emitting control signal output terminal, and the second electrode of the second output transistor is electrically connected to the first voltage terminal.

[0242] like Fig. 9 As shown, in Figure 7 Based on at least one embodiment of the driving circuit shown, the light emitting control output circuit may include a conduction subcircuit 70 and a light emitting control output subcircuit 71; the third node control circuit includes a third node control subcircuit 80, a seventh node control subcircuit 81 and an eighth node control subcircuit 82;

[0243] The conduction subcircuit 70 is electrically connected to the first voltage terminal V2, the third node PD1 and the eighth node PD11 respectively, and is used to control the connection or disconnection between the third node PD1 and the eighth node PD11 under the control of the second voltage signal provided by the first voltage terminal V2;

[0244] The light-emitting control output subcircuit 71 is electrically connected to the second node PU, the eighth node PD11, the light-emitting control signal output terminal E1, the high voltage terminal V01 and the low voltage terminal V02, respectively, and is used to control the connection or disconnection between the light-emitting control signal output terminal E1 and the low voltage terminal V02 under the control of the potential of the eighth node PD11, and to control the connection or disconnection between the light-emitting control signal output terminal E1 and the high voltage terminal V01 under the control of the potential of the second node PU;

[0245] The third node control subcircuit 80 is electrically connected to the first clock signal terminal K1, the second input terminal I2 and the third node PD1 respectively, and is used to control the connection or disconnection between the second input terminal I2 and the third node PD1 under the control of the first clock signal provided by the first clock signal terminal K1;

[0246] The seventh node control subcircuit 81 is electrically connected to the fifth node PD2, the eighth node PD11, the seventh node N1, the first voltage terminal V1 and the second clock signal terminal K2 respectively, and is used to control the seventh node N1 to be connected or disconnected from the first voltage terminal V1 under the control of the potential of the fifth node PD2, and to control the seventh node N1 to be connected or disconnected from the second clock signal terminal K2 under the control of the potential of the eighth node PD11;

[0247] The eighth node control sub-circuit 82 is electrically connected to the seventh node N1 and the eighth node PD11, respectively, and is used to control the potential of the eighth node PD11 according to the potential of the seventh node N1.

[0248] exist Fig. 9 In at least one embodiment of the driving circuit shown, the conduction subcircuit 70 controls the connection or disconnection between PD1 and PD11 under the control of the second voltage signal, the third node control subcircuit 81 controls the potential of the third node PD1, the seventh node control subcircuit 81 controls the potential of the seventh node N1, and the eighth node control subcircuit 82 controls the potential of the eighth node PD11.

[0249] Optionally, the conduction subcircuit includes a second conduction control transistor, the third node control subcircuit includes an eleventh transistor; the seventh node control subcircuit includes a twelfth transistor and a thirteenth transistor; the eighth node control subcircuit includes a third capacitor;

[0250] The control electrode of the second conduction control transistor is electrically connected to the second voltage terminal, the first electrode of the second conduction control transistor is electrically connected to the third node, and the second electrode of the second conduction control transistor is electrically connected to the eighth node;

[0251] The control electrode of the eleventh transistor is electrically connected to the first clock signal terminal, the first electrode of the eleventh transistor is electrically connected to the second input terminal, and the second electrode of the eleventh transistor is electrically connected to the third node;

[0252] A control electrode of the twelfth transistor is electrically connected to the fifth node, a first electrode of the twelfth transistor is electrically connected to the first voltage terminal, and a second electrode of the twelfth transistor is electrically connected to the seventh node;

[0253] The control electrode of the thirteenth transistor is electrically connected to the eighth node, the first electrode of the thirteenth transistor is electrically connected to the second clock signal terminal, and the second electrode of the thirteenth transistor is electrically connected to the seventh node;

[0254] A first end of the third capacitor is electrically connected to the seventh node, and a second end of the third capacitor is electrically connected to the eighth node.

[0255] Optionally, the light emission control output circuit includes a second conduction control transistor, a first output transistor and a second output transistor;

[0256] The control electrode of the second conduction control transistor is electrically connected to the second voltage terminal, the first electrode of the second conduction control transistor is electrically connected to the third node, and the second electrode of the second conduction control transistor is electrically connected to the eighth node;

[0257] The control electrode of the first output transistor is electrically connected to the eighth node, the first electrode of the first output transistor is electrically connected to the second voltage terminal, and the second electrode of the first output transistor is electrically connected to the light emitting control signal output terminal;

[0258] The control electrode of the second output transistor is electrically connected to the second node, the first electrode of the second output transistor is electrically connected to the light emitting control signal output terminal, and the second electrode of the second output transistor is electrically connected to the first voltage terminal.

[0259] like Fig.10 As shown, in the driving circuit described in at least one embodiment of the present invention, Figure 8 Based on at least one embodiment of the driving circuit shown,

[0260] The fifth node control subcircuit 51 includes a sixth transistor M6 and a seventh transistor M7;

[0261] The gate of the sixth transistor M6 is electrically connected to the first clock signal terminal K1, the first electrode of the sixth transistor M6 is electrically connected to the low voltage terminal V02, and the second electrode of the sixth transistor M6 is electrically connected to the fifth node PD2;

[0262] The gate of the seventh transistor M7 is electrically connected to the third node PD1, the first electrode of the seventh transistor M7 is electrically connected to the first clock signal terminal K1, and the second electrode of the seventh transistor M7 is electrically connected to the fifth node PD2;

[0263] The first node control subcircuit 52 includes an eighth transistor M8 and a second capacitor C2;

[0264] A gate of the eighth transistor M8 is electrically connected to the fifth node PD2, a first electrode of the eighth transistor M8 is electrically connected to the second clock signal terminal K2, and a second electrode of the eighth transistor M8 is electrically connected to the first node PU1;

[0265] A first end of the second capacitor C2 is electrically connected to the fifth node PD2, and a second end of the second capacitor C2 is electrically connected to the first node PU1;

[0266] The second node control circuit 12 includes a ninth transistor M9, a tenth transistor M10 and a control capacitor C0;

[0267] A gate of the ninth transistor M9 is electrically connected to the second clock signal terminal K2, a first electrode of the ninth transistor M9 is electrically connected to the first node PU1, and a second electrode of the ninth transistor M9 is electrically connected to the second node PU;

[0268] A gate of the tenth transistor M10 is electrically connected to the third node PD1, a first electrode of the tenth transistor M10 is electrically connected to the high voltage terminal V01, and a second electrode of the tenth transistor M10 is electrically connected to the second node PU;

[0269] A first end of the control capacitor C0 is electrically connected to the second node PU, and a second end of the control capacitor C0 is electrically connected to the high voltage terminal V01;

[0270] The third node control circuit 13 includes an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13 and a third capacitor C3;

[0271] A gate of the eleventh transistor M11 is electrically connected to the first clock signal terminal K1, a first electrode of the eleventh transistor M11 is electrically connected to the second input terminal I2, and a second electrode of the eleventh transistor M11 is electrically connected to the third node PD1;

[0272] A gate of the twelfth transistor M12 is electrically connected to the fifth node PD2, and a first electrode of the twelfth transistor M12 is electrically connected to the high voltage terminal V01;

[0273] A gate of the thirteenth transistor M13 is electrically connected to the second clock signal terminal K2, a first electrode of the thirteenth transistor M13 is electrically connected to the second electrode of the twelfth transistor M12, and a second electrode of the thirteenth transistor M13 is electrically connected to the third node PD1;

[0274] A first end of the third capacitor C3 is electrically connected to the second clock signal terminal K2, and a second end of the third capacitor C3 is electrically connected to the third node PD1;

[0275] The light emission control output circuit 14 includes a first output transistor M01 and a second output transistor M02;

[0276] The gate of the first output transistor M01 is electrically connected to the third node PD1, the first electrode of the first output transistor M01 is electrically connected to the low voltage terminal V02, and the second electrode of the first output transistor M01 is electrically connected to the light emitting control signal output terminal E1;

[0277] A gate of the second output transistor M02 is electrically connected to the second node PU, a first electrode of the second output transistor M02 is electrically connected to the light emitting control signal output terminal E1, and a second electrode of the second output transistor M02 is electrically connected to the high voltage terminal V02.

[0278] exist Fig.10In at least one embodiment of the driving circuit shown, I1 and I2 are both electrically connected to the light-emitting control signal output terminal of the adjacent previous-stage driving circuit, and R1 is electrically connected to the light-emitting control signal output terminal of the adjacent next-stage driving circuit.

[0279] Optionally, I1 can be replaced by being electrically connected to the light emitting control signal output terminal of the driving circuit.

[0280] Optionally, R1 can be replaced by being electrically connected to the gate drive signal output terminal of the adjacent previous-stage drive circuit.

[0281] exist Fig.10 In at least one embodiment of the driving circuit shown, all transistors are p-type transistors, but the present invention is not limited thereto.

[0282] like Fig.11 As shown, Fig.10 When at least one embodiment of the driving circuit shown is in operation, the driving cycle includes a first preparation phase t01, a second preparation phase t02, a first input phase t1, a second input phase t2, a third input phase t3, a first reset phase t4, a second reset phase t5 and a third reset phase t6, which are arranged in sequence;

[0283] In the first preparation stage t01, K1 provides a low voltage signal, K2 provides a high voltage signal, I1 and I2 provide a low voltage signal, and R1 provides a low voltage signal, such as Fig. 12A As shown, M11 is turned on, M6 is turned on, M13 is turned off, the potential of PD1 is a low voltage, M7 is turned on, the potential of PD2 is a low voltage, M8 is turned on, the potential of PU1 is a high voltage, M9 is turned off, M6 is turned on, the potential of PU is a high voltage, M01 is turned on, M02 is turned off, and E1 outputs a low voltage signal; M1 is turned off, M2 is turned on, M3 is turned off, M4 is turned on, M5 is turned off, the potential of PPU is maintained at a high voltage, and G1 outputs a high voltage signal;

[0284] In the second preparation stage t02, K1 provides a high voltage signal, K2 provides a low voltage signal, I1 and I2 provide a low voltage signal, and R1 provides a low voltage signal, such as Fig. 12B As shown, M11 is turned off, M6 is turned off, and since the potential of the second clock signal provided by K2 is reduced, the potential of PD1 is further reduced due to coupling, M7 is turned on, the potential of PD2 is a high voltage, M12 is turned off, M8 is turned off, the potential of PU1 is a high voltage, M9 is turned on, M10 is turned on, the potential of PU is a high voltage, M01 is turned on, M02 is turned off, and E1 outputs a low voltage signal; M1 is turned off, M2 is turned on, M3 is turned off, M4 is turned on, M5 is turned off, the potential of PPU is a high voltage, and G1 outputs a high voltage signal;

[0285] In the first input stage t1, K1 provides a low voltage signal, K2 provides a high voltage signal, I1 and I2 provide high voltage signals, and R1 provides a low voltage signal, such as Fig. 12C As shown, M11 is turned on, M6 is turned on, M13 is turned off, the potential of PD1 is a high voltage, M7 is turned off, the potential of PD2 is a low voltage, M8 is turned on, the potential of PU1 is a high voltage, M9 is turned off, M10 is turned off, the potential of PU is maintained at a high voltage, M01 and M02 are both turned off, and E1 maintains the output of a low voltage signal; M1 is turned off, M2 is turned off, M3 is turned off, M4 is turned off, and M5 is turned off, the potential of PPU is maintained at a high voltage, and G1 continues to output a high voltage signal;

[0286] In the second input stage t2, K1 provides a high voltage signal, K2 provides a low voltage signal, I1 and I2 provide a high voltage signal, and R1 provides a low voltage signal, such as Fig.12D As shown, M11 and M6 are turned off, the potential of PD2 is maintained at a low voltage, M13 and M12 are turned on, the potential of PD1 is a high voltage, M8 is turned on, the potential of PU1 is a low voltage, M9 is turned on, the potential of PU is a low voltage, M01 is turned off, M02 is turned on, and E1 outputs a high voltage signal; M1 is turned on, M2 is turned off, M3 is turned on, M4 is turned off, M5 is turned on, the potential of PPU is a low voltage, and G1 outputs a high voltage signal;

[0287] In the third input stage t3, K1 provides a low voltage signal, K2 provides a high voltage signal, I1 and I2 provide high voltage signals, and R1 provides a high voltage signal, such as Fig.12E As shown, M11 and M6 are turned on, the potential of PD1 is a high voltage, M7 is turned off, the potential of PD2 is a low voltage, M13 is turned off, M8 is turned on, the potential of PU1 is a high voltage signal, M9 is turned off, M10 is turned off, the potential of PU is maintained at a low voltage, M01 is turned off, M02 is turned on, and E1 outputs a high voltage signal; M1 is turned off, M2 is turned off, M3 is turned on, M4 is turned off, M5 is turned off, G1 outputs a low voltage signal, and the potential of PPU is reduced to a lower voltage due to coupling;

[0288] In the first reset phase t4, K1 provides a high voltage signal, K2 provides a low voltage signal, I1 and I2 provide low voltage signals, and R1 provides a high voltage signal. Fig.12F As shown, M11 and M6 are turned off, the potential of PD2 is maintained at a low voltage, M12 and M13 are both turned on, the potential of PD1 is a high voltage, M8 is turned on, the potential of PU1 is a low voltage, M10 is turned off, the potential of PU is a low voltage, M01 is turned off, M02 is turned on, and E1 outputs a high voltage signal; M1 is turned on, M2 is turned on, M3 is turned off, M4 is turned on, M5 is turned on, the potential of PPU is a high voltage, and G1 outputs a high voltage signal;

[0289] In the second reset phase t5, K1 provides a low voltage signal, K2 provides a high voltage signal, I1 and I2 provide low voltage signals, and R1 provides a high voltage signal. Figure 12G As shown, M11 and M6 are turned on, M11 is turned off, the potential of PD1 is a low voltage, M10 is turned on, M9 is turned off, the potential of PU is a high voltage, M7 is turned on, the potential of PD2 is a low voltage, M8 is turned on, the potential of PU1 is a high voltage, M01 is turned on, M02 is turned off, and E1 outputs a low voltage signal; M1 is turned off, M2 is turned on, M3 is turned off, M4 is turned on, M5 is turned off, the potential of PPU is a high voltage, and G1 outputs a high voltage signal;

[0290] In the third reset stage t6, K1 provides a high voltage signal, K2 provides a low voltage signal, I1 and I2 provide low voltage signals, and R1 provides a low voltage signal, such as Fig.12H As shown, M11 and M6 are turned off. Since the potential of the second clock signal provided by K2 is reduced from a high voltage to a low voltage, the potential of PD1 is further reduced due to coupling, M7 is turned on, the potential of PD2 is a high voltage, M12 is turned off, M8 is turned off, the potential of PU1 is maintained at a high voltage, M9 is turned on, M10 is turned on, the potential of PU is a high voltage, M01 is turned on, M02 is turned off, and E1 outputs a low voltage signal; M1 is turned off, M2 is turned on, M3 is turned off, M4 is turned on, M5 is turned off, the potential of PPU is a high voltage, and G1 outputs a high voltage signal.

[0291] The driving circuit described in at least one embodiment of the present invention can output a light-emitting control signal and a gate driving signal simultaneously when in operation, and the pulse width of the light-emitting control signal is adjustable.

[0292] like Fig.13 As shown, the time during which the potential of the light-emitting control signal output by the driving circuit according to at least one embodiment of the present invention continues to be a high voltage (ie, the pulse width of the light-emitting control signal) is 7H.

[0293] like Fig.14 As shown, the time during which the potential of the light-emitting control signal output by the driving circuit according to at least one embodiment of the present invention continues to be a high voltage (ie, the pulse width of the light-emitting control signal) is 5H.

[0294] like Fig.15 As shown, the time during which the potential of the light-emitting control signal output by the driving circuit described in at least one embodiment of the present invention continues to be a high voltage (ie, the pulse width of the light-emitting control signal) is 3H.

[0295] like Fig.16 As shown, in Fig. 9 Based on at least one embodiment of the driving circuit shown,

[0296] The fifth node control subcircuit 51 includes a sixth transistor M6 and a seventh transistor M7;

[0297] The gate of the sixth transistor M6 is electrically connected to the first clock signal terminal K1, the first electrode of the sixth transistor M6 is electrically connected to the low voltage terminal V02, and the second electrode of the sixth transistor M6 is electrically connected to the fifth node PD2;

[0298] The gate of the seventh transistor M7 is electrically connected to the third node PD1, the first electrode of the seventh transistor M7 is electrically connected to the first clock signal terminal K1, and the second electrode of the seventh transistor M7 is electrically connected to the fifth node PD2;

[0299] The first node control subcircuit 52 includes an eighth transistor M8 and a second capacitor C2, and the conduction control circuit 60 includes a first conduction control transistor M21;

[0300] The gate of the first conduction control transistor M21 is electrically connected to the low voltage terminal V02, the first electrode of the first conduction control transistor M21 is electrically connected to the fifth node PD2, and the second electrode of the first conduction control transistor M21 is electrically connected to the sixth node PD22;

[0301] The gate of the eighth transistor M8 is electrically connected to the sixth node PD22, the first electrode of the eighth transistor M8 is electrically connected to the second clock signal terminal K2, and the second electrode of the eighth transistor M8 is electrically connected to the first node PU1;

[0302] A first end of the second capacitor C2 is electrically connected to the sixth node PD22, and a second end of the second capacitor C2 is electrically connected to the first node PU1;

[0303] The second node control circuit 12 includes a ninth transistor M9, a tenth transistor M10 and a control capacitor C0;

[0304] A gate of the ninth transistor M9 is electrically connected to the second clock signal terminal K2, a first electrode of the ninth transistor M9 is electrically connected to the first node PU1, and a second electrode of the ninth transistor M9 is electrically connected to the second node PU;

[0305] A gate of the tenth transistor M10 is electrically connected to the third node PD1, a first electrode of the tenth transistor M10 is electrically connected to the high voltage terminal V01, and a second electrode of the tenth transistor M10 is electrically connected to the second node PU;

[0306] A first end of the control capacitor C0 is electrically connected to the second node PU, and a second end of the control capacitor C0 is electrically connected to the high voltage terminal V01;

[0307] The conduction subcircuit 70 includes a second conduction control transistor M22, the third node control subcircuit 80 includes an eleventh transistor M11; the seventh node control subcircuit 81 includes a twelfth transistor M12 and a thirteenth transistor M13; the eighth node control subcircuit 82 includes a third capacitor C3;

[0308] The gate of the second conduction control transistor M22 is electrically connected to the low voltage terminal V02, the first electrode of the second conduction control transistor M22 is electrically connected to the third node PD1, and the second electrode of the second conduction control transistor M22 is electrically connected to the eighth node PD11;

[0309] A gate of the eleventh transistor M11 is electrically connected to the first clock signal terminal K1, a first electrode of the eleventh transistor M11 is electrically connected to the second input terminal I2, and a second electrode of the eleventh transistor M11 is electrically connected to the third node PD1;

[0310] A gate of the twelfth transistor M12 is electrically connected to the fifth node PD2, a first electrode of the twelfth transistor M12 is electrically connected to the high voltage terminal V01, and a second electrode of the twelfth transistor M12 is electrically connected to the seventh node N1;

[0311] A gate of the thirteenth transistor M13 is electrically connected to the eighth node PD11, a first electrode of the thirteenth transistor M13 is electrically connected to the second clock signal terminal K2, and a second electrode of the thirteenth transistor M13 is electrically connected to the seventh node N1;

[0312] A first end of the third capacitor C3 is electrically connected to the seventh node N1, and a second end of the third capacitor C3 is electrically connected to the eighth node PD11;

[0313] The light emitting control output subcircuit 71 includes a first output transistor M01 and a second output transistor M02;

[0314] The gate of the first output transistor M01 is electrically connected to the eighth node PD11, the first electrode of the first output transistor M01 is electrically connected to the low voltage terminal V02, and the second electrode of the first output transistor M01 is electrically connected to the light emitting control signal output terminal E1;

[0315] A gate of the second output transistor M02 is electrically connected to the second node PU, a first electrode of the second output transistor M02 is electrically connected to the light emitting control signal output terminal E1, and a second electrode of the second output transistor M02 is electrically connected to the high voltage terminal V02.

[0316] exist Fig.16 In at least one embodiment of the driving circuit shown, I1 and I2 are both electrically connected to the light-emitting control signal output terminal of the adjacent previous-stage driving circuit, and R1 is electrically connected to the light-emitting control signal output terminal of the adjacent next-stage driving circuit.

[0317] exist Fig.16 In at least one embodiment of the driving circuit shown, all transistors are p-type transistors, but the present invention is not limited thereto.

[0318] exist Fig.16 In at least one embodiment of the driving circuit shown, M21 and M22 may not be provided.

[0319] exist Fig.16 In at least one embodiment of the driving circuit shown, the benefits of adding M21 are as follows: stabilizing the potential of PD22, reducing the influence of M7 leakage, and thus stabilizing the control of M8;

[0320] The benefits of adding M22 are as follows: it can stabilize the low potential of PD11 and reduce the influence of the leakage of M11 on the potential of PD11.

[0321] like Fig.17 As shown, the present invention is Fig.16 When at least one embodiment of the driving circuit shown is in operation, the driving cycle includes a first input stage t1, a second input stage t2, a third input stage t3, a first reset stage t4, a second reset stage t5 and a third reset stage t5 which are arranged in sequence;

[0322] In the first input stage t1, K1 provides a low voltage signal, K2 provides a high voltage signal, I1 and I2 provide high voltage signals, M11 and M6 are turned on, the potential of PD1 is a high voltage, M22 is turned on, the potential of PD11 is a high voltage, the potential of PD2 is a low voltage, M21 is turned on, the potential of PD22 is a low voltage, M8 is turned on, the potential of PU1 is a high voltage, M9 is turned off, the potential of PU is maintained at a high voltage, M10 is turned off, M13 is turned off, M12 is turned on, the potential of N1 is a high voltage, M01 and M02 are both turned off, and E1 continues to output a low voltage signal;

[0323] In the second input stage t2, K1 provides a high voltage signal, K2 provides a low voltage signal, I1 and I2 provide high voltage signals, M11 and M6 are turned off, M7 is turned off, the potential of PD2 is maintained at a low voltage, M12 is turned on, the potential of N1 is a high voltage, the potential of PD11 is a high voltage, the potential of PD1 is a high voltage, M21 and M22 are turned on, the potential of PD22 is coupled to a lower voltage, M8 is turned on, the potential of PU1 is a low voltage, M9 is turned on, the potential of PU is a low voltage, M01 is turned off, M02 is turned on, and E1 outputs a high voltage signal;

[0324] In the third input stage t3, K1 provides a low voltage signal, K2 provides a high voltage signal, I1 and I2 provide high voltage signals, M11 and M6 are turned on, M22 is turned on, the potential of PD1 and the potential of PD11 are both high voltages, the potential of PD2 is low voltage, M21 is turned on, the potential of PD22 is low voltage, M12 is turned on, M13 is turned off, the potential of N1 is high voltage, M8 is turned on, the potential of PU1 is high voltage, M9 is turned off, M10 is turned off, the potential of PU is maintained at a low voltage, M01 is turned off, M02 is turned on, and E1 outputs a high voltage signal;

[0325] In the first reset stage t4, K1 provides a high voltage signal, K2 provides a low voltage signal, I1 and I2 provide low voltage signals, M11 and M6 are turned off, the potential of PD1 is a high voltage, M7 is turned off, the potential of PD2 is maintained at a low voltage, M21 is turned on, the potential of PD22 is further pulled down, M8 is turned on, the potential of PU1 is a low voltage, M9 is turned on, the potential of PU is a low voltage, M12 is turned on, M13 is turned off, the potential of N1 is a high voltage, the potential of PD11 is a high voltage, M01 is turned off, M02 is turned on, and E1 outputs a high voltage signal;

[0326] In the second reset stage t5, K1 provides a low voltage signal, K2 provides a high voltage signal, I1 and I2 provide low voltage signals, M11 and M6 are turned on, the potential of PD1 is a low voltage, M7 is turned on, the potential of PD2 is a low voltage, M12 is turned on, M22 is turned on, the potential of PD11 is a low voltage, M13 is turned on, the potential of N1 is a high voltage, M21 is turned on, the potential of PD22 is a low voltage, M8 is turned on, the potential of PU1 is a high voltage, M9 is turned off, M10 is turned on, the potential of PU is a high voltage, M01 is turned on, M02 is turned off, and E1 outputs a low voltage signal;

[0327] In the third reset stage t6, K1 provides a high voltage signal, K2 provides a low voltage signal, I1 and I2 provide low voltage signals, M11 and M6 are turned off, the potential of PD1 is a low voltage, M7 is turned on, the potential of PD2 is a high voltage, M12 is turned off, M22 is turned on, the potential of PD11 is a low voltage, M13 is turned on, the potential of N1 is a low voltage, the potential of PD11 is further pulled down, M10 is turned on, the potential of PU is a high voltage, M01 is turned on, M02 is turned off, and E1 provides a low voltage signal.

[0328] In at least one embodiment of the present invention, Fig.18As shown, a gate drive circuit 10 is provided, and the gate drive circuit 10 is electrically connected to the control node L1, the first input terminal I1, the reset terminal R1, the first clock signal terminal K1, the first voltage terminal V1 and the gate drive signal output terminal G1, respectively, and is used to control the gate drive signal output terminal G1 to output a gate drive signal according to the first clock signal provided by the first clock signal terminal K1 and the first voltage signal provided by the first voltage terminal V1 under the control of the potential of the control node L1, the first input signal provided by the first input terminal I1 and the reset signal provided by the reset terminal R1.

[0329] The gate driving circuit provided by at least one embodiment of the present invention uses the signal obtained by performing an "OR" operation on the reset signal provided by the reset terminal R1 and the voltage signal of the first node PU1 of the row as the input / reset function, that is, when the reset signal and the voltage signal of the first node PU1 of the row are both valid voltage signals, the input function is realized, and when the voltage signal of the first node PU1 of the row is a valid voltage signal and the reset signal is an invalid voltage signal, the reset function is realized, and when the first input signal provided by I1 is a valid voltage signal, G1 is denoised, so that the gate driving circuit 10 provided by at least one embodiment of the present invention can generate a gate driving signal.

[0330] Optionally, the control node L1 may be a first node in a light emitting control signal generating circuit; the structure of the light emitting control signal generating circuit may not be limited to the circuit structure provided in the embodiment of the present invention.

[0331] like Fig.19 As shown, in Fig.18 Based on at least one embodiment of the gate driving circuit shown, at least one embodiment of the gate driving circuit may include a fourth node control circuit 21 and a gate output circuit 23;

[0332] The fourth node control circuit 21 is electrically connected to the control node L1, the fourth node PPU, the reset terminal R1, the first input terminal I1 and the first voltage terminal V1 respectively, and is used to control the fourth node PPU to be connected or disconnected from the reset terminal R1 under the control of the potential of the control node L1, and to control the fourth node PPU to be connected or disconnected from the first voltage terminal V1 under the control of the first input signal provided by the first input terminal I1;

[0333] The gate output circuit 23 is electrically connected to the fourth node PPU, the gate drive signal output terminal G1, the first clock signal terminal K1, the first input terminal I1 and the first voltage terminal V1, respectively, and is used to control the connection or disconnection between the gate drive signal output terminal G1 and the first clock signal terminal K1 under the control of the potential of the fourth node PPU, and control the connection or disconnection between the gate drive signal output terminal G1 and the first voltage terminal V1 under the control of the first input signal provided by the first input terminal I1, and is used to control the gate drive signal provided by the gate drive signal output terminal G1 according to the potential of the fourth node PPU.

[0334] Fig.19 When at least one embodiment of the gate driving circuit shown is in operation, a driving cycle may include a first input stage, a second input stage, a third input stage and a first reset stage which are arranged in sequence;

[0335] In the first input stage, the fourth node control circuit 21 controls the fourth node PPU to be disconnected from the reset terminal R1 under the control of the potential of the control node L1, and controls the fourth node PPU to be disconnected from the first voltage terminal V1 under the control of the first input signal; the gate output circuit 23 controls the gate drive signal output terminal G1 to be disconnected from the first clock signal terminal K1 under the control of the potential of the fourth node PPU, and controls the gate drive signal output terminal G1 to be disconnected from the first voltage terminal V1 under the control of the first input signal, so that the gate drive signal output terminal G1 maintains to output the first voltage signal;

[0336] In the second input stage, the fourth node control circuit 21 controls the fourth node PPU to be connected to the reset terminal R1 under the control of the potential of the control node L1; the gate output circuit 23 controls the gate drive signal output terminal G1 to be connected to the first clock signal terminal K1 under the control of the potential of the fourth node PPU, so that the gate drive signal output terminal G1 outputs the first voltage signal;

[0337] In the third input stage, the fourth node control circuit 21 controls the fourth node PPU to be disconnected from the reset terminal R1 under the control of the potential of the control node L1; the gate output circuit 23 controls the gate drive signal output terminal G1 to be connected to the first clock signal terminal K1 under the control of the potential of the fourth node PPU, so that the gate drive signal output terminal G1 outputs the second voltage signal;

[0338] In the first reset stage, the fourth node control circuit 21 controls the connection between the fourth node PPU and the reset terminal R1 under the control of the potential of the control node L1, and controls the connection between the fourth node PPU and the first voltage terminal V1 under the control of the first input signal; the gate output circuit 23 controls the disconnection between the gate drive signal output terminal G1 and the first clock signal terminal K1 under the control of the potential of the fourth node PPU, and controls the connection between the gate drive signal output terminal G1 and the first voltage terminal V1 under the control of the first input signal, so that the gate drive signal output terminal G1 outputs the first voltage signal.

[0339] like Fig. 20 As shown, in Fig.19 Based on at least one embodiment of the gate driving circuit shown, the driving circuit according to at least one embodiment of the present invention may further include a gate reset circuit 24;

[0340] The gate reset circuit 24 is electrically connected to the control node L1, the gate drive signal output terminal G1 and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the gate drive signal output terminal G1 and the first voltage terminal V1 under the control of the potential of the control node L1.

[0341] In a specific implementation, in order to prevent the potential of the first input signal provided by I1 from being an invalid voltage for too long and failing to reset G1 in time, the gate reset circuit 24 is added to control the potential of the control node L11 to control the gate drive signal output terminal to output a first voltage signal to reset G1.

[0342] The present invention Fig. 20 At least one embodiment of the driving circuit shown in the figure is in operation.

[0343] In the first input stage, the gate reset circuit 24 controls the gate drive signal output terminal G1 to be disconnected from the first voltage terminal V1 under the control of the potential of the control node L1;

[0344] In the second input stage, the gate reset circuit 24 controls the gate drive signal output terminal G1 to be connected to the first voltage terminal V1 under the control of the potential of the control node L1;

[0345] In the third input stage, the gate reset circuit 24 controls the gate drive signal output terminal G1 to be disconnected from the first voltage terminal V1 under the control of the potential of the control node L1;

[0346] In the first reset stage, the gate reset circuit 24 controls the connection between the gate driving signal output terminal G1 and the first voltage terminal V1 under the control of the potential of the control node L1 to reset G1.

[0347] like Fig.21 As shown, in Fig. 20 Based on at least one embodiment of the gate driving circuit shown, the fourth node control circuit 21 includes a first transistor M1 and a second transistor M2;

[0348] The gate of the first transistor M1 is electrically connected to the control node L1, the first electrode of the first transistor M1 is electrically connected to the reset terminal R1, and the second electrode of the first transistor M1 is electrically connected to the fourth node PPU;

[0349] The gate of the second transistor M2 is electrically connected to the first input terminal I1, the first electrode of the second transistor M2 is electrically connected to the fourth node PPU, and the second electrode of the second transistor M2 is electrically connected to the high voltage terminal V01;

[0350] The gate output circuit 23 includes a third transistor M3, a fourth transistor M4 and a first capacitor C1;

[0351] The gate of the third transistor M3 is electrically connected to the fourth node PPU, the first electrode of the third transistor M3 is electrically connected to the first clock signal terminal K1, and the second electrode of the third transistor M3 is electrically connected to the gate drive signal output terminal G1;

[0352] The gate of the fourth transistor M4 is electrically connected to the first input terminal I1, the first electrode of the fourth transistor M4 is electrically connected to the gate drive signal output terminal G1, and the second electrode of the fourth transistor M4 is electrically connected to the high voltage terminal V01;

[0353] A first end of the first capacitor C1 is electrically connected to the fourth node PPU, and a second end of the first capacitor C1 is electrically connected to the gate driving signal output terminal G1.

[0354] exist Fig.21 In at least one embodiment of the gate driving circuit shown, each transistor is a p-type transistor.

[0355] exist Fig.21 In at least one embodiment of the gate driving circuit shown, the control node L1 may be a first node in the light emitting control signal generating circuit.

[0356] like Fig. 22 As shown, Fig.21 When at least one embodiment of the gate driving circuit shown is in operation, the driving cycle includes a first preparation stage t01, a second preparation stage t02, a first input stage t1, a second input stage t2, a third input stage t3, a first reset stage t4, a second reset stage t5 and a third reset stage t6, which are arranged in sequence;

[0357] In the first preparation stage t01, K1 provides a low voltage signal, I1 provides a low voltage signal, R1 provides a low voltage signal, the potential of L1 is a high voltage, the potential of PPU is a high voltage, M1 is turned off, M2 is turned on, M3 is turned off, M4 is turned on, M5 is turned off, and G1 outputs a high voltage signal;

[0358] In the second preparation stage t01, K1 provides a high voltage signal, I1 provides a low voltage signal, R1 provides a low voltage signal, the potential of L1 is a high voltage, the potential of PPU is a high voltage, M1 is turned off, M2 is turned on, M3 is turned off, M4 is turned on, M5 is turned off, and G1 outputs a high voltage signal;

[0359] In the first input stage t1, K1 provides a low voltage signal, I1 provides a high voltage signal, R1 provides a low voltage signal, the potential of L1 is a high voltage, the potential of PPU is a high voltage, M1, M2, M3, M4 and M5 are all turned off, and G1 continuously outputs a high voltage signal;

[0360] In the second input stage t2, K1 provides a high voltage signal, I1 provides a high voltage signal, R1 provides a low voltage signal, the potential of L1 is a low voltage, the potential of PPU is pulled low, M1 is turned on, M2 is turned off, M3 is turned on, M4 is turned off, M5 is turned on, and G1 provides a high voltage signal;

[0361] In the third input stage t3, K1 provides a low voltage signal, I1 provides a high voltage signal, R1 provides a high voltage signal, the potential of L1 is a high voltage, the potential of PPU is further pulled down, M1 and M2 are turned off, M3 is turned on, M4 is turned off, M5 is turned off, and G1 provides a low voltage signal;

[0362] In the first reset stage t4, K1 provides a high voltage signal, I1 provides a low voltage signal, R1 provides a high voltage signal, the potential of L1 is a low voltage, the potential of PPU is a high voltage, M1 and M2 are turned on, M3 is turned off, M4 is turned on, M5 is turned on, and G1 provides a high voltage signal to reset G1;

[0363] In the second reset stage t5, K1 provides a low voltage signal, I1 provides a low voltage signal, R1 provides a high voltage signal, the potential of L1 is a high voltage, the potential of PPU is a high voltage, M1 is turned off, M2 is turned on, M3 is turned off, M4 is turned on, M5 is turned off, and G1 provides a high voltage signal;

[0364] In the third reset stage t6, K1 provides a high voltage signal, I1 provides a low voltage signal, R1 provides a low voltage signal, the potential of L1 is a high voltage, the potential of PPU is a high voltage, M1 is turned off, M2 is turned on, M3 is turned off, M4 is turned on, M5 is turned off, and G1 provides a high voltage signal. The driving method described in the embodiment of the present invention is applied to the above-mentioned driving circuit, and the driving method includes:

[0365] The gate drive circuit controls the gate drive signal output terminal to output the gate drive signal according to the first clock signal provided by the first clock signal terminal and the first voltage signal provided by the first voltage terminal, under the control of the potential of the first node, the first input signal provided by the first input terminal and the reset signal provided by the reset terminal.

[0366] By adopting the driving method described in the embodiment of the present invention, the driving circuit can generate a gate driving signal while generating a light-emitting control signal, thereby simplifying the driving scheme, reducing the number of signals, and narrowing the frame.

[0367] The driving method described in at least one embodiment of the present invention is applied to the above-mentioned driving circuit, wherein the driving cycle includes a first input stage, a second input stage, a third input stage and a first reset stage which are arranged in sequence; the driving method includes:

[0368] In the first input stage, the fourth node control circuit controls the fourth node to be disconnected from the reset terminal under the control of the potential of the first node, and controls the fourth node to be disconnected from the first voltage terminal under the control of the first input signal; the gate output circuit controls the gate drive signal output terminal to be disconnected from the first clock signal terminal under the control of the potential of the fourth node, and controls the gate drive signal output terminal to be disconnected from the first voltage terminal under the control of the first input signal, so that the gate drive signal output terminal maintains outputting the first voltage signal;

[0369] In the second input stage, the fourth node control circuit controls the fourth node to be connected to the reset terminal under the control of the potential of the first node; the gate output circuit controls the gate drive signal output terminal to be connected to the first clock signal terminal under the control of the potential of the fourth node, so that the gate drive signal output terminal outputs the first voltage signal;

[0370] In the third input stage, the fourth node control circuit controls the fourth node to be disconnected from the reset terminal under the control of the potential of the first node; the gate output circuit controls the gate drive signal output terminal to be connected to the first clock signal terminal under the control of the potential of the fourth node, so that the gate drive signal output terminal outputs the second voltage signal;

[0371] In the first reset stage, the fourth node control circuit controls the connection between the fourth node and the reset terminal under the control of the potential of the first node, and controls the connection between the fourth node and the first voltage terminal under the control of the first input signal; the gate output circuit controls the gate drive signal output terminal to be disconnected from the first clock signal terminal under the control of the potential of the fourth node, and controls the gate drive signal output terminal to be connected to the first voltage terminal under the control of the first input signal, so that the gate drive signal output terminal outputs the first voltage signal.

[0372] In at least one embodiment of the present invention, the driving circuit further includes a gate reset circuit; and the driving method further includes:

[0373] In the first input stage, the gate reset circuit controls the gate drive signal output terminal to be disconnected from the first voltage terminal under the control of the potential of the first node;

[0374] In the second input stage, the gate reset circuit controls the gate drive signal output terminal to be connected to the first voltage terminal under the control of the potential of the first node;

[0375] In the third input stage, the gate reset circuit controls the gate drive signal output terminal to be disconnected from the first voltage terminal under the control of the potential of the first node;

[0376] In the first reset stage, the gate reset circuit controls the gate drive signal output terminal to be connected to the first voltage terminal under the control of the potential of the first node.

[0377] In a specific implementation, in order to prevent the potential of the first input signal provided by the first input terminal from being an invalid voltage for too long and thus failing to reset the gate drive signal output terminal in time, a gate reset circuit is added to control the gate drive signal output terminal to output a first voltage signal under the control of the potential of the first node, so as to reset the gate drive signal output terminal.

[0378] The driving module described in the embodiment of the present invention includes multiple stages of the above-mentioned driving circuits.

[0379] In a specific implementation, the second input terminal of the driving circuit may be electrically connected to the light emitting control signal output terminal of the adjacent upper-level driving circuit.

[0380] Optionally, the first input terminal of the driving circuit is electrically connected to the light-emitting control signal output terminal of the adjacent upper-level driving circuit; or, the first input terminal of the driving circuit is electrically connected to the light-emitting control signal output terminal of the driving circuit.

[0381] Optionally, the reset terminal of the driving circuit is electrically connected to the light-emitting control signal output terminal of the adjacent next-stage driving circuit; or, the reset terminal is electrically connected to the gate driving signal output terminal of the adjacent previous-stage driving circuit.

[0382] The display device described in the embodiment of the present invention includes the above-mentioned driving module.

[0383] The display device provided in the embodiment of the present invention can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

[0384] The display device provided in at least one embodiment of the present invention may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or the like.

[0385] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A driving circuit, characterized in that: It includes a light emitting control signal generating circuit and a gate driving circuit; the light emitting control signal generating circuit includes a first node control circuit, a second node control circuit, a third node control circuit and a light emitting control output circuit; The first node control circuit is used to control the potential of the first node; The second node control circuit is used to control the potential of the second node; The third node control circuit is used to control the potential of the third node; The light emitting control output circuit is used to control the light emitting control signal output terminal to output a light emitting control signal according to the potential of the second node and the potential of the third node; The gate driving circuit is used to control the gate driving signal output terminal to output a gate driving signal according to the first clock signal provided by the first clock signal terminal and the first voltage signal provided by the first voltage terminal under the control of the potential of the first node, the first input signal provided by the first input terminal and the reset signal provided by the reset terminal; The first node control circuit includes a fifth node control subcircuit and a first node control subcircuit; The fifth node control subcircuit is used to control the connection or disconnection between the fifth node and the second voltage terminal under the control of the first clock signal provided by the first clock signal terminal, and to control the connection or disconnection between the fifth node and the first clock signal terminal under the control of the potential of the third node; The first node control subcircuit is used to control the potential of the first node according to the potential of the fifth node and the second clock signal provided by the second clock signal terminal.

2. The driving circuit according to claim 1, characterized in that: The gate driving circuit includes a fourth node control circuit and a gate output circuit; The fourth node control circuit is used to control the fourth node to be connected or disconnected from the reset terminal under the control of the potential of the first node, and to control the fourth node to be connected or disconnected from the first voltage terminal under the control of the first input signal provided by the first input terminal; The gate output circuit is used to control the connection or disconnection between the gate drive signal output terminal and the first clock signal terminal under the control of the potential of the fourth node, and to control the connection or disconnection between the gate drive signal output terminal and the first voltage terminal under the control of the first input signal, and is used to control the gate drive signal provided by the gate drive signal output terminal according to the potential of the fourth node.

3. The driving circuit according to claim 2, characterized in that: Also included is a gate reset circuit; The gate reset circuit is used to control the connection or disconnection between the gate drive signal output terminal and the first voltage terminal under the control of the potential of the first node.

4. The driving circuit according to claim 2, characterized in that: The fourth node control circuit includes a first transistor and a second transistor; The control electrode of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the reset terminal, and the second electrode of the first transistor is electrically connected to the fourth node; The control electrode of the second transistor is electrically connected to the first input terminal, the first electrode of the second transistor is electrically connected to the fourth node, and the second electrode of the second transistor is electrically connected to the first voltage terminal.

5. The driving circuit according to claim 2, characterized in that: The gate output circuit includes a third transistor, a fourth transistor and a first capacitor; The control electrode of the third transistor is electrically connected to the fourth node, the first electrode of the third transistor is electrically connected to the first clock signal terminal, and the second electrode of the third transistor is electrically connected to the gate drive signal output terminal; The control electrode of the fourth transistor is electrically connected to the first input terminal, the first electrode of the fourth transistor is electrically connected to the gate drive signal output terminal, and the second electrode of the fourth transistor is electrically connected to the first voltage terminal; A first end of the first capacitor is electrically connected to the fourth node, and a second end of the first capacitor is electrically connected to the gate driving signal output end.

6. The driving circuit according to claim 3, characterized in that: The gate reset circuit includes a fifth transistor; The control electrode of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the gate driving signal output terminal, and the second electrode of the fifth transistor is electrically connected to the first voltage terminal.

7. The driving circuit according to any one of claims 1 to 6, characterized in that: The fifth node control subcircuit includes a sixth transistor and a seventh transistor; The control electrode of the sixth transistor is electrically connected to the first clock signal terminal, the first electrode of the sixth transistor is electrically connected to the second voltage terminal, and the second electrode of the sixth transistor is electrically connected to the fifth node; The control electrode of the seventh transistor is electrically connected to the third node, the first electrode of the seventh transistor is electrically connected to the first clock signal terminal, and the second electrode of the seventh transistor is electrically connected to the fifth node.

8. The driving circuit according to any one of claims 1 to 6, characterized in that: The first node control subcircuit is used to control the connection or disconnection between the first node and the second clock signal terminal under the control of the potential of the fifth node, and is used to control the potential of the first node according to the potential of the fifth node.

9. The driving circuit according to claim 8, characterized in that: The first node control subcircuit includes an eighth transistor and a second capacitor; The control electrode of the eighth transistor is electrically connected to the fifth node, the first electrode of the eighth transistor is electrically connected to the second clock signal terminal, and the second electrode of the eighth transistor is electrically connected to the first node; A first end of the second capacitor is electrically connected to the fifth node, and a second end of the second capacitor is electrically connected to the first node.

10. The driving circuit according to any one of claims 1 to 6, characterized in that: It also includes a conduction control circuit; the conduction control circuit is used to control the connection or disconnection between the fifth node and the sixth node under the control of the second voltage signal provided by the second voltage terminal; The first node control subcircuit is used to control the connection or disconnection between the first node and the second clock signal terminal under the control of the potential of the sixth node, and is used to control the potential of the first node according to the potential of the sixth node.

11. The driving circuit according to claim 10, characterized in that: The first node control subcircuit includes an eighth transistor and a second capacitor, and the conduction control circuit includes a first conduction control transistor; The control electrode of the first conduction control transistor is electrically connected to the second voltage terminal, the first electrode of the first conduction control transistor is electrically connected to the fifth node, and the second electrode of the first conduction control transistor is electrically connected to the sixth node; The control electrode of the eighth transistor is electrically connected to the sixth node, the first electrode of the eighth transistor is electrically connected to the second clock signal terminal, and the second electrode of the eighth transistor is electrically connected to the first node; A first end of the second capacitor is electrically connected to the sixth node, and a second end of the second capacitor is electrically connected to the first node.

12. The driving circuit according to any one of claims 1 to 6, characterized in that: The second node control circuit is used to control the connection or disconnection between the first node and the second node under the control of the second clock signal provided by the second clock signal terminal, and is used to control the connection or disconnection between the second node and the first voltage terminal under the control of the potential of the third node, and is used to maintain the potential of the second node.

13. The driving circuit according to claim 12, characterized in that: The second node control circuit includes a ninth transistor, a tenth transistor and a control capacitor; The control electrode of the ninth transistor is electrically connected to the second clock signal terminal, the first electrode of the ninth transistor is electrically connected to the first node, and the second electrode of the ninth transistor is electrically connected to the second node; The control electrode of the tenth transistor is electrically connected to the third node, the first electrode of the tenth transistor is electrically connected to the first voltage terminal, and the second electrode of the tenth transistor is electrically connected to the second node; The first end of the control capacitor is electrically connected to the second node, and the second end of the control capacitor is connected to the first voltage end.

14. The driving circuit according to any one of claims 1 to 6, characterized in that: The third node control circuit is used to control the connection or disconnection between the third node and the second input terminal under the control of the first clock signal provided by the first clock signal terminal, and to control the connection or disconnection between the third node and the first voltage terminal under the control of the potential of the fifth node and the second clock signal, and to control the potential of the third node according to the second clock signal.

15. The driving circuit according to claim 14, characterized in that: The third node control circuit includes an eleventh transistor, a twelfth transistor, a thirteenth transistor and a third capacitor; The control electrode of the eleventh transistor is electrically connected to the first clock signal terminal, the first electrode of the eleventh transistor is electrically connected to the second input terminal, and the second electrode of the eleventh transistor is electrically connected to the third node; The control electrode of the twelfth transistor is electrically connected to the fifth node, and the first electrode of the twelfth transistor is electrically connected to the first voltage terminal; The control electrode of the thirteenth transistor is electrically connected to the second clock signal terminal, the first electrode of the thirteenth transistor is electrically connected to the second electrode of the twelfth transistor, and the second electrode of the thirteenth transistor is electrically connected to the third node; A first end of the third capacitor is electrically connected to the second clock signal end, and a second end of the third capacitor is electrically connected to the third node.

16. The driving circuit according to any one of claims 1 to 6, characterized in that: The third node control circuit includes a seventh node control subcircuit and a third node control subcircuit; The seventh node control subcircuit is used to control the seventh node to be connected or disconnected with the first voltage terminal under the control of the potential of the fifth node, and to control the seventh node to be connected or disconnected with the second clock signal terminal under the control of the potential of the third node; The third node control subcircuit is used to control the potential of the third node according to the potential of the seventh node, and control the connection or disconnection between the third node and the second input terminal under the control of the first clock signal provided by the first clock signal terminal.

17. The driving circuit according to claim 16, characterized in that: The third node control subcircuit includes an eleventh transistor and a third capacitor; the seventh node control subcircuit includes a twelfth transistor and a thirteenth transistor; The control electrode of the eleventh transistor is electrically connected to the first clock signal terminal, the first electrode of the eleventh transistor is electrically connected to the second input terminal, and the second electrode of the eleventh transistor is electrically connected to the third node; A control electrode of the twelfth transistor is electrically connected to the fifth node, a first electrode of the twelfth transistor is electrically connected to the first voltage terminal, and a second electrode of the twelfth transistor is electrically connected to the seventh node; The control electrode of the thirteenth transistor is electrically connected to the third node, the first electrode of the thirteenth transistor is electrically connected to the second clock signal terminal, and the second electrode of the thirteenth transistor is electrically connected to the seventh node; A first end of the third capacitor is electrically connected to the seventh node, and a second end of the third capacitor is electrically connected to the third node.

18. The driving circuit according to any one of claims 1 to 6, characterized in that: The light emitting control output circuit includes a conduction subcircuit; the third node control circuit includes a third node control subcircuit, a seventh node control subcircuit and an eighth node control subcircuit; The conduction subcircuit is used to control the connection or disconnection between the third node and the eighth node under the control of the second voltage signal provided by the second voltage terminal; The third node control subcircuit is used to control the connection or disconnection between the third node and the second input terminal under the control of the first clock signal provided by the first clock signal terminal; The seventh node control subcircuit is used to control the seventh node to be connected or disconnected with the first voltage terminal under the control of the potential of the fifth node, and to control the seventh node to be connected or disconnected with the second clock signal terminal under the control of the potential of the eighth node; The eighth-node control subcircuit is used to control the potential of the eighth node according to the potential of the seventh node.

19. The driving circuit according to claim 18, characterized in that: The conduction subcircuit includes a second conduction control transistor, the third node control subcircuit includes an eleventh transistor, the seventh node control subcircuit includes a twelfth transistor and a thirteenth transistor; the eighth node control subcircuit includes a third capacitor; The control electrode of the second conduction control transistor is electrically connected to the second voltage terminal, the first electrode of the second conduction control transistor is electrically connected to the third node, and the second electrode of the second conduction control transistor is electrically connected to the eighth node; The control electrode of the eleventh transistor is electrically connected to the first clock signal terminal, the first electrode of the eleventh transistor is electrically connected to the second input terminal, and the second electrode of the eleventh transistor is electrically connected to the third node; A control electrode of the twelfth transistor is electrically connected to the fifth node, a first electrode of the twelfth transistor is electrically connected to the first voltage terminal, and a second electrode of the twelfth transistor is electrically connected to the seventh node; The control electrode of the thirteenth transistor is electrically connected to the eighth node, the first electrode of the thirteenth transistor is electrically connected to the second clock signal terminal, and the second electrode of the thirteenth transistor is electrically connected to the seventh node; A first end of the third capacitor is electrically connected to the seventh node, and a second end of the third capacitor is electrically connected to the eighth node.

20. The driving circuit according to any one of claims 1 to 6, characterized in that: The light emission control output circuit includes a first output transistor and a second output transistor; The control electrode of the first output transistor is electrically connected to the third node, the first electrode of the first output transistor is electrically connected to the second voltage terminal, and the second electrode of the first output transistor is electrically connected to the light emission control signal output terminal; The control electrode of the second output transistor is electrically connected to the second node, the first electrode of the second output transistor is electrically connected to the light emitting control signal output terminal, and the second electrode of the second output transistor is electrically connected to the first voltage terminal.

21. The driving circuit according to any one of claims 1 to 6, characterized in that: The light emission control output circuit includes a second conduction control transistor, a first output transistor and a second output transistor; The control electrode of the second conduction control transistor is electrically connected to the second voltage terminal, the first electrode of the second conduction control transistor is electrically connected to the third node, and the second electrode of the second conduction control transistor is electrically connected to the eighth node; The control electrode of the first output transistor is electrically connected to the eighth node, the first electrode of the first output transistor is electrically connected to the second voltage terminal, and the second electrode of the first output transistor is electrically connected to the light emitting control signal output terminal; The control electrode of the second output transistor is electrically connected to the second node, the first electrode of the second output transistor is electrically connected to the light emitting control signal output terminal, and the second electrode of the second output transistor is electrically connected to the first voltage terminal.

22. A driving method, applied to the driving circuit according to any one of claims 1 to 21, characterized in that: The driving method comprises: The gate driving circuit controls the gate driving signal output terminal to output the gate driving signal according to the first clock signal provided by the first clock signal terminal and the first voltage signal provided by the first voltage terminal under the control of the potential of the first node, the first input signal provided by the first input terminal and the reset signal provided by the reset terminal; The fifth node control subcircuit controls the connection or disconnection between the fifth node and the second voltage terminal under the control of the first clock signal, and the fifth node control subcircuit controls the connection or disconnection between the fifth node and the first clock signal terminal under the control of the potential of the third node; The first node control subcircuit controls the potential of the first node according to the potential of the fifth node and the second clock signal.

23. The driving method according to claim 22, characterized in that: The driving circuit further includes a fourth node control circuit and a gate output circuit; the driving cycle includes a first input stage, a second input stage, a third input stage and a first reset stage which are arranged in sequence; the driving method includes: In the first input stage, the fourth node control circuit controls the fourth node to be disconnected from the reset terminal under the control of the potential of the first node, and controls the fourth node to be disconnected from the first voltage terminal under the control of the first input signal; the gate output circuit controls the gate drive signal output terminal to be disconnected from the first clock signal terminal under the control of the potential of the fourth node, and controls the gate drive signal output terminal to be disconnected from the first voltage terminal under the control of the first input signal, so that the gate drive signal output terminal maintains outputting the first voltage signal; In the second input stage, the fourth node control circuit controls the fourth node to be connected to the reset terminal under the control of the potential of the first node; the gate output circuit controls the gate drive signal output terminal to be connected to the first clock signal terminal under the control of the potential of the fourth node, so that the gate drive signal output terminal outputs the first voltage signal; In the third input stage, the fourth node control circuit controls the fourth node to be disconnected from the reset terminal under the control of the potential of the first node; the gate output circuit controls the gate drive signal output terminal to be connected to the first clock signal terminal under the control of the potential of the fourth node, so that the gate drive signal output terminal outputs the second voltage signal; In the first reset stage, the fourth node control circuit controls the connection between the fourth node and the reset terminal under the control of the potential of the first node, and controls the connection between the fourth node and the first voltage terminal under the control of the first input signal; the gate output circuit controls the gate drive signal output terminal to be disconnected from the first clock signal terminal under the control of the potential of the fourth node, and controls the gate drive signal output terminal to be connected to the first voltage terminal under the control of the first input signal, so that the gate drive signal output terminal outputs the first voltage signal.

24. The driving method according to claim 23, characterized in that: The driving circuit further includes a gate reset circuit; and the driving method further includes: In the first input stage, the gate reset circuit controls the gate drive signal output terminal to be disconnected from the first voltage terminal under the control of the potential of the first node; In the second input stage, the gate reset circuit controls the gate drive signal output terminal to be connected to the first voltage terminal under the control of the potential of the first node; In the third input stage, the gate reset circuit controls the gate drive signal output terminal to be disconnected from the first voltage terminal under the control of the potential of the first node; In the first reset stage, the gate reset circuit controls the gate drive signal output terminal to be connected to the first voltage terminal under the control of the potential of the first node.

25. A driving module, characterized in that: The driving circuit comprises a plurality of stages as claimed in any one of claims 1 to 21.

26. The driving module according to claim 25, characterized in that: The second input terminal of the driving circuit is electrically connected to the light emitting control signal output terminal of the adjacent upper-level driving circuit.

27. The driving module according to claim 25 or 26, characterized in that: The first input terminal of the driving circuit is electrically connected to the light-emitting control signal output terminal of the adjacent upper-level driving circuit; or, the first input terminal of the driving circuit is electrically connected to the light-emitting control signal output terminal of the driving circuit.

28. The driving module according to claim 25 or 26, characterized in that: The reset terminal of the driving circuit is electrically connected to the light-emitting control signal output terminal of the adjacent next-stage driving circuit; or, the reset terminal is electrically connected to the gate driving signal output terminal of the adjacent previous-stage driving circuit.

29. A display device, characterized in that: Comprising a drive module as described in claim 25 or 28.

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