A chip packaging structure, electronic device

Abstract

The embodiments of the present application provide a chip packaging structure and an electronic device, which relate to the field of chip packaging technology and are used to improve the thermal contact reliability between the thermal interface material and the chip and the heat dissipation cover. The chip packaging structure includes a packaging substrate, at least one chip, at least one internal thermal interface layer and a heat dissipation cover. The heat dissipation cover includes an upper cover and a plurality of side walls. The upper cover includes at least one boss structure and a first connecting structure. A boss structure is in contact with at least one internal thermal interface layer and is connected to the side wall through the first connecting structure. The maximum thickness of the boss structure is greater than the maximum thickness of the first connecting structure, and the boss structure is away from the surface of the chip and protrudes from the surface of the first connecting structure away from the chip. The boss structure can reduce the gap between the heat dissipation cover and the heat dissipation device, so that the heat dissipation device can effectively exert pressure on the boss structure, reducing the probability of delamination between the internal thermal interface layer and the chip.

Description

Technical Field

[0001] The present application relates to the field of chip packaging technology, and in particular to a chip packaging structure and electronic equipment. Background Art

[0002] With the continuous development of semiconductor technology, electronic devices are developing in a multifunctional direction, and chip bandwidth and computing power are constantly improving, which makes the chip package size larger and larger. Based on this, the chip will experience large temperature changes during packaging, installation of the heat sink and operation, which will cause the larger package substrate to warp due to the different coefficients of thermal expansion (CTE) between the materials of different layers inside it. In this way, within the operating temperature range, the above-mentioned warping phenomenon will increase the probability of separation between the thermal interface material (TIM) on the surface of the chip and the chip, reduce the thermal contact reliability between the thermal interface material and the chip and the heat sink, and lead to reduced heat dissipation effect. Summary of the invention

[0003] The embodiments of the present application provide a chip packaging structure and an electronic device for improving the thermal contact reliability between a thermally conductive interface material and a chip and a heat dissipation cover.

[0004] In order to achieve the above objectives, this application adopts the following technical solutions:

[0005] In one aspect of an embodiment of the present application, a chip packaging structure is provided. The chip packaging structure includes a packaging substrate, at least one chip, at least one internal heat-conducting interface layer and a heat dissipation cover. The packaging substrate has a first surface. The chip is arranged on the first surface of the packaging substrate. At least one internal heat-conducting interface layer covers the surface of at least one chip away from the packaging substrate. The heat dissipation cover includes an upper cover and a plurality of side walls. The plurality of side walls are arranged end to end around the upper cover and connected to the first surface. A receiving cavity for accommodating at least one chip is formed between the heat dissipation cover and the packaging substrate. The upper cover includes at least one boss structure and a first connection structure. Each boss structure of the at least one boss structure is in contact with at least one of the internal heat-conducting interface layers. Moreover, each boss structure of the at least one boss structure is connected to the side wall through the first connection structure. The maximum thickness D1_max of the boss structure is greater than the maximum thickness D2_max of the first connection structure, and the boss structure is away from the surface of the chip and protrudes from the surface of the first connection structure away from the chip. In the embodiment of the present application, the direction of the thickness is perpendicular to the direction of the first surface. Based on this, during the service process of the chip packaging structure, the packaging substrate warps due to the increase in temperature. This warping phenomenon will cause the gap between the heat sink cover and the heat sink to tend to increase. However, since the heat sink cover has a boss structure. The maximum thickness D1_max of the boss structure is greater than the maximum thickness D2_max of the first connection structure, and the boss structure is away from the surface of the chip and protrudes from the surface of the first connection structure away from the chip. Therefore, the boss structure can reduce the gap between the heat sink cover and the heat sink. In this way, it is possible to avoid a large change in the gap between the heat sink cover and the heat sink due to the deformation of the external thermal interface layer, and thus the heat sink fixed on the circuit board can still effectively exert pressure on the boss structure, reducing the probability of delamination between the solidified internal thermal interface layer and the chip, and improving the thermal contact reliability between the internal thermal interface layer and the chip and the heat sink cover, thereby reducing the probability of high-temperature power failure in the chip packaging structure.

[0006] Optionally, the surface of the boss structure close to the chip protrudes from the surface of the first connection structure close to the chip. In this way, both the upper and lower surfaces of the boss structure protrude from the first connection structure, which is conducive to increasing the thickness and rigidity of the boss structure, so that the heat dissipation device can more effectively apply pressure to the boss structure in the heat dissipation cover, reducing the probability of delamination of the internal thermal interface layer.

[0007] Optionally, the surface of the boss structure close to the chip is flush with the surface of the first connection structure close to the chip. In this way, the surface of the upper cover in the heat dissipation cover close to the chip can have a higher flatness, achieving the purpose of simplifying the mold structure for making the heat dissipation cover.

[0008] Optionally, the thickness of the first connection structure gradually decreases along the direction from the boss structure to the side wall. In this way, the rigidity of the first connection structure near the side wall can be reduced, so that when the heat sink applies pressure to the heat sink cover, the first connection structure near the side wall is easily deformed. Therefore, when the heat sink applies pressure to the heat sink cover, the pressure is more concentrated on the boss structure with greater thickness and rigidity, and then transmitted to the chip through the boss structure in the heat sink cover, reducing the probability of delamination of the internal thermal interface layer.

[0009] Optionally, the surface of the first connection structure close to the chip is a plane. In this case, in order to ensure that the thickness of the first connection structure gradually decreases along the direction from the boss structure to the side wall, the surface of the first connection structure close to the chip is an inclined surface or an arc surface. Alternatively, the surface of the first connection structure away from the chip is a plane. In this case, in order to ensure that the thickness of the first connection structure gradually decreases along the direction from the boss structure to the side wall, the surface of the first connection structure away from the chip is an inclined surface or an arc surface.

[0010] Optionally, the side surface of the side wall away from the package substrate is the upper reference surface, and the side surface of the inner thermal interface layer away from the package substrate is the lower reference surface. There is a reference thickness D0 between the upper reference surface and the lower reference surface. The minimum thickness D2_min of the first connection structure is less than the reference thickness D0. In this way, the purpose of reducing the rigidity of the first connection structure can be achieved by reducing the thickness of the first connection structure. Therefore, when the heat sink applies pressure to the heat sink cover, the pressure applied by the heat sink to the heat sink cover can be more concentrated on the boss structure, reducing the probability of delamination of the inner thermal interface layer.

[0011] Optionally, 20%×D0≤D2_min≤80%×D0. When the minimum thickness D2_min of the first connection structure is less than 20%×D0, the thickness of the first connection structure 311 is too thin, resulting in too little rigidity of the first connection structure, which reduces the ability of the heat dissipation cover to control the warping of the package substrate 102. In addition, when the minimum thickness D2_min of the first connection structure is greater than 80%×D0, the thickness of the first connection structure is too large and the rigidity is too strong, so when the heat dissipation device applies pressure to the heat dissipation cover, it is not conducive to transferring the pressure applied by the heat dissipation device to the heat dissipation cover to the chip.

[0012] Optionally, the surface of the boss structure away from the chip has a maximum distance L_max from the upper reference surface. L_max<D0. In this way, the portion of the boss structure located in the accommodating cavity, that is, the portion of the boss structure where the reference thickness D0 is located, can be made thicker, while the portion of the boss structure located outside the accommodating cavity, that is, the portion of the boss structure where the maximum distance L_max is located, can be made thinner. Thus, when the maximum thickness D1_max of the boss structure meets the design requirements, the maximum distance L_max of the boss structure does not need to be too large, which is beneficial to improving the filling degree of the outer thermal interface layer between the heat sink and the heat dissipation cover 103.

[0013] Optionally, 0.01mm≤L_max≤0.2mm. When the maximum distance L_max is less than 0.01mm, the protrusion of the boss structure is small, and the effect of the boss structure on reducing the distance between the heat sink cover and the heat sink is not obvious, and the pressure effect of the heat sink on the boss structure cannot be effectively improved. When L_max is greater than 0.02mm, the protrusion of the boss structure is too large, so that the gap between the boss structure and the heat sink is too small, and the effective coverage area of ​​the external thermal interface layer on the upper surface of the heat sink cover is small, thereby reducing the filling amount of the external thermal interface layer between the heat sink and the heat sink cover. In addition, the thickness of the external thermal interface layer cannot absorb the thickness of the boss structure well, so that the contact flatness with the surface of the heat sink facing the packaging substrate is reduced.

[0014] Optionally, the surface of the boss structure away from the chip is a first curved surface, and the portion of the surface of the first connection structure away from the chip close to the first curved surface is a second curved surface. The curvature of the second curved surface is the same as that of the first curved surface, and the second curved surface is connected to the first curved surface. In addition, the vertical projection of the chip corresponding to the boss structure on the first surface is located within the range of the vertical projection of the first curved surface and the second curved surface on the first surface. In this way, not only the surface of the boss structure away from the chip in the upper cover is raised, but also the surface of the first connection structure away from the chip is raised at the position where the second curved surface is located, so that the size of the raised portion of the surface of the upper cover away from the chip can be appropriately increased. Therefore, when the heat dissipation device applies pressure to the heat dissipation cover, the pressure can more effectively act on the pressure of the raised portion of the upper cover to be transmitted to the chip, so that the thermal interface layer and the chip are more closely attached. On this basis, the side of the second curved surface away from the first curved surface has a first contour on the vertical projection of the first surface. The chip corresponding to the boss structure has a second contour on the vertical projection of the first surface. The maximum spacing Hmax between the first contour and the second contour satisfies: Hmax≤2mm. When Hmax>2mm, the size of the raised portion of the upper cover away from the chip is too large, so that the gap between the upper cover and the heat sink is too small, and the external thermal interface layer can only cover the area where the boss structure in the upper cover is located, thereby reducing the filling amount of the external thermal interface layer between the heat sink and the heat sink.

[0015] Optionally, at least a portion of the surface of the boss structure away from the chip is a third curved surface. The vertical projection of the third curved surface on the first surface is within the range of the vertical projection of the chip corresponding to the boss structure on the first surface. On this basis, the vertical projection of the third curved surface on the first surface has a third contour. The vertical projection of the chip corresponding to the boss structure on the first surface has a second contour. The maximum spacing Hmax between the third contour and the second contour satisfies: Hmax≤2mm. When Hmax>2mm, the size of the boss structure is too small, and when the heat sink applies pressure to the heat sink cover, the area of ​​the action surface of the heat sink cover on the chip is too small, which is not conducive to the heat sink to effectively apply pressure to the chip.

[0016] Optionally, the surface of the boss structure away from the chip is a first curved surface. The vertical projection of the first curved surface on the first surface completely overlaps with the vertical projection of the chip corresponding to the boss structure on the first surface. In this way, the boss structure can completely cover the chip, so that when the heat dissipation device applies pressure to the heat dissipation cover, the force acting on the boss structure can be more effectively transmitted to the chip.

[0017] Optionally, the vertical projection of the contact surface between the boss structure and the inner thermal interface layer on the first surface completely overlaps with the vertical projection of the chip connected to the boss structure on the first surface. In this way, the contact surface between the boss structure and the inner thermal interface layer can completely cover the chip, so that when the heat dissipation device applies pressure to the heat dissipation cover, the force acting on the boss structure can be more effectively transmitted to the chip.

[0018] Optionally, the upper cover further comprises at least one first groove, and the first groove is provided on a side surface of the first connection structure close to the chip. The first groove is located at an end of the first connection structure away from the boss structure. Thus, by providing the first groove at an end of the first connection structure away from the boss structure, the rigidity of the first connection structure close to the side wall can be further reduced, which is conducive to concentrating the pressure applied by the heat dissipation device to the heat dissipation cover on the boss structure.

[0019] Optionally, the first groove is an annular groove surrounding at least one chip, so that the rigidity of the first connection structure located around the boss structure is reduced.

[0020] Optionally, the depth S1 of the first groove satisfies: 20%×D2_max≤S1≤80%×D2_max; the groove width L1 of the first groove satisfies: 0.1mm≤L1≤20mm. When the depth S1 of the first groove is less than 20%×D2_max and the width L1 is less than 0.1mm, the requirements for the manufacturing accuracy of the first groove are high, which is not conducive to reducing the manufacturing cost. And the size of the first groove is too small, and the effect of reducing the rigidity of the first connection structure is not obvious. In addition, when the depth S1 of the first groove is greater than 80%×D2_max and the width L1 is greater than 20mm, the size of the first groove is too large, resulting in the first connection structure being too small, which reduces the heat dissipation cover's ability to control the warping of the packaging substrate.

[0021] Optionally, the at least one chip includes a first chip and a second chip. The at least one internal thermal interface layer includes a first internal thermal interface layer covering the first chip and a second internal thermal interface layer covering the second chip. The surface of the first internal thermal interface layer away from the packaging substrate is flush with the surface of the second internal thermal interface layer away from the packaging substrate. In addition, the at least one boss structure includes a first boss structure and a second boss structure, the first boss structure is in contact with the first internal thermal interface layer, and the second boss structure is in contact with the second internal thermal interface layer. The upper cover also includes a second connecting structure, the second connecting structure is located between the first boss structure and the second boss structure, and is connected to the first boss structure and the second boss structure. In this case, the chip packaging structure is a multi-chip sealed structure.

[0022] Optionally, the upper cover also includes at least one second groove, and the second groove is opened on the side surface of the second connection structure close to the packaging substrate. The size setting method of the second groove can be the same as the setting method of the first groove, which will not be repeated here. In addition, in the case where the above-mentioned packaging substrate is a redistribution layer, the packaging substrate is prone to deformation during temperature changes. At this time, when the second groove and the first groove on the upper cover of the heat dissipation cover can weaken the rigidity of the upper cover, so that when the packaging substrate is deformed, there is a certain decoupling effect between the movement of the packaging substrate and the movement of the heat dissipation cover, reducing the chip from being constrained when following the movement of the packaging substrate. Thereby, the cracking of the molding layer between two adjacent chips can be reduced.

[0023] Optionally, the at least one chip includes a first chip and a second chip. The at least one internal thermal interface layer includes a first internal thermal interface layer covering the first chip and a second internal thermal interface layer covering the second chip. The surface of the first internal thermal interface layer away from the packaging substrate is flush with the surface of the second internal thermal interface layer away from the packaging substrate. A boss structure is in contact with the first internal thermal interface layer and the second internal thermal interface layer. In this case, the chip packaging structure is a multi-chip sealed structure. When the heat dissipation device applies pressure to the heat dissipation cover, the pressure can be transmitted to the first chip and the second chip through the same boss structure, thereby simplifying the structure of the heat dissipation cover.

[0024] Another aspect of the embodiment of the present application provides an electronic device, including a heat sink, an external heat-conducting interface layer, a circuit board, and any one of the chip packaging structures described above disposed on the circuit board. The external heat-conducting interface layer is located between the heat sink and the heat dissipation cover in the chip packaging structure, and is connected to the heat sink and the heat dissipation cover. The heat sink is also connected to the circuit board. The electronic device has the same technical effects as the chip packaging structure provided in the aforementioned embodiment, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of a portion of the structure of an electronic device provided in an embodiment of the present application;

[0026] Figure 2a for Figure 1 A schematic diagram of a chip packaging structure;

[0027] Figure 2b for Figure 2a A schematic structural diagram of the side wall of the middle heat dissipation cover;

[0028] Figure 3a for Figure 1 Another structural schematic diagram of the chip packaging structure;

[0029] Figure 3b for Figure 1 Another structural schematic diagram of the chip packaging structure;

[0030] Figure 4 A schematic diagram of a warping of a chip packaging structure provided in an embodiment of the present application;

[0031] Figure 5 A schematic diagram of a structure in which a chip packaging structure provided in an embodiment of the present application is connected to a heat dissipation device;

[0032] Figure 6a for Figure 1 Another structural schematic diagram of the chip packaging structure;

[0033] Figure 6bfor Figure 1 Another structural schematic diagram of the chip packaging structure;

[0034] Figure 7a for Figure 1 Another structural schematic diagram of the chip packaging structure;

[0035] Figure 7b for Figure 1 Another structural schematic diagram of the chip packaging structure;

[0036] Figure 8 for Figure 1 Another structural schematic diagram of the chip packaging structure;

[0037] Figure 9a for Figure 1 Another structural schematic diagram of the chip packaging structure;

[0038] Figure 9b for Figure 9a Schematic diagram of the top view of the mid-mount structure and the chip;

[0039] Fig.9c for Figure 1 Another structural schematic diagram of the chip packaging structure;

[0040] Figure 9d for Fig.9c Schematic diagram of the top view of the platform structure and the chip;

[0041] Fig.9e for Figure 1 Another structural schematic diagram of the chip packaging structure;

[0042] Fig.10 for Figure 1 Another structural schematic diagram of the chip packaging structure;

[0043] Fig.11a A schematic diagram of the structure of a heat dissipation cover provided in an embodiment of the present application;

[0044] Fig.11b A schematic diagram of the structure of another heat dissipation cover provided in an embodiment of the present application;

[0045] Fig.12a A schematic diagram of a multi-chip package structure provided in an embodiment of the present application;

[0046] Figure 12b A schematic diagram of another multi-chip package structure provided in an embodiment of the present application;

[0047] Fig.12c A schematic diagram of another multi-chip package structure provided in an embodiment of the present application;

[0048] Fig.13 A schematic diagram of another multi-chip package structure provided in an embodiment of the present application.

[0049] Reference numerals:

[0050] 01-electronic device; 10-chip packaging structure; 11-heat dissipation device; 12-PCB; 13-solder ball array; 101-chip; 102-packaging substrate; 103-heat dissipation cover; 110-inner thermal interface layer; 120-outer thermal interface layer; 20-accommodating cavity; 31-upper cover; 310-boss structure; 311-first connecting structure; 32-side wall; 40-adhesive layer; 312-first groove; 313-second connecting structure; 314-second groove; 101a-first chip; 101b-second chip; 110a-first inner thermal interface layer; 110b-second inner thermal interface layer; 310a-first boss structure; 310b-second boss structure; 400-molding material. DETAILED DESCRIPTION

[0051] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0052] In the following, the terms "first", "second", etc. are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the features.

[0053] In addition, in the present application, directional terms such as "upper" and "lower" are defined relative to the orientation of the components in the drawings. It should be understood that these directional terms are relative concepts. They are used for relative description and clarification, and they can change accordingly according to the changes in the orientation of the components in the drawings.

[0054] In this application, unless otherwise specified or limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium. In addition, the term "electrical connection" can be a direct electrical connection or an indirect electrical connection through an intermediate medium.

[0055] The embodiment of the present application provides an electronic device. The electronic device may include a mobile phone, a tablet computer (pad), a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device and other devices. The above-mentioned electronic device may also be an electric car, a small household appliance (e.g., a soymilk machine, a sweeping robot), an unmanned aerial vehicle and other electronic devices, or an electronic device used in a pan-network. The embodiment of the present application does not impose any special restrictions on the specific form of the above-mentioned electronic device.

[0056] The electronic device 01, such as Figure 1 As shown, it may include a chip package structure 10 and a printed circuit board (PCB) 12. The chip package structure 10 may be electrically connected to the PCB 12 via a ball grid array (BGA) 13 or a land grid array (LGA).

[0057] The chip package structure 10 may include at least one chip 101 and a package substrate 102. The package substrate 102 has a first surface A1 and a second surface A2 that are arranged opposite to each other. The chip 101 is arranged on the first surface A1 of the package substrate 102, and the solder ball array 13 is arranged on the second surface A2 of the package substrate 102. The chip 101 can realize signal transmission with other chips or chip package structures on the PCB 12 through the package substrate 102 and the solder ball array 13.

[0058] The chip 101 generates heat during operation, and in order to diffuse the heat, the performance of the chip 101 is not affected. Figure 1 As shown, the chip packaging structure 10 further includes at least one inner thermal interface layer 110 and a heat dissipation cover (lid) 103. The at least one inner thermal interface layer 110 covers the surface of the at least one chip 101 away from the packaging substrate 102. The heat dissipation cover 103 is connected to the inner thermal interface layer 110 and the packaging substrate 102, and a receiving cavity 20 for receiving the at least one chip 101 is formed between the heat dissipation cover 103 and the packaging substrate 102.

[0059] It should be noted that Figure 1The description is made by taking a chip 101 encapsulated in a chip packaging structure 10 as an example. In other embodiments of the present application, the chip packaging structure 10 may also be a multi-chip package structure (multi chip module, MCM). In this case, the chip packaging structure 10 may encapsulate at least two chips 101. At this time, each chip 101 may be covered with an inner thermal interface layer 110 on a side surface away from the packaging substrate 102.

[0060] In some embodiments of the present application, the chip 101 may be a bare chip (single die). Alternatively, in other embodiments, the chip 101 may be a structure in which the bare chip is disposed on an interposer using chip on wafer on substrate (COWOS) technology including a silicon carrier. Alternatively, in other embodiments, the chip 101 may be a structure in which the bare chip is disposed on a redistribution layer (RDL) using fan out package (FOP) technology.

[0061] In addition, if Figure 1 As shown, the electronic device 01 further includes a heat sink 11 and an external heat conduction interface layer 120. The external heat conduction interface layer 120 is connected to the heat sink 11 and the heat dissipation cover 103 in the chip packaging structure 10. The heat sink 11 can also be connected to the PCB 12 by screws.

[0062] In some embodiments of the present application, the heat dissipation device 11 may be a radiator or a liquid cooling plate. In this case, the heat generated by the chip 101 as a heat source during operation can be transferred to the heat dissipation cover 103 as a heat dissipation device through the inner thermal conductive interface layer 110. The inner thermal conductive interface layer 110 can reduce the contact thermal resistance between the chip 101 and the heat dissipation cover 103 to improve the heat dissipation performance of the heat dissipation cover 103. Next, the heat dissipation cover 103 acts as a heat source, and the heat on the heat dissipation cover 103 can be transferred to the heat dissipation device 11 as a heat dissipation device through the outer thermal conductive interface layer 120 to dissipate heat through the heat dissipation device 11. The outer thermal conductive interface layer 120 is used to reduce the contact thermal resistance between the heat dissipation device 11 and the heat dissipation cover 103 to improve the heat dissipation performance of the heat dissipation device 11.

[0063] Based on this, the materials of the inner thermal interface layer 110 and the outer thermal interface layer 120 may include thermally conductive silicone. As can be seen from the above, the contact thermal resistance between the heat source surface and the heat sink can be reduced by the inner thermal interface layer 110 and the outer thermal interface layer 120. In addition, the inner thermal interface layer 110 and the outer thermal interface layer 120 can also fill the gap between the heat source and the heat sink well, squeeze out the air between the two, and avoid the air, which is a poor thermal conductor, from hindering the transfer of heat between the heat source and the heat sink. Moreover, the inner thermal interface layer 110 and the outer thermal interface layer 120 can also make the contact between the heat source and the heat sink more sufficient, and have the function of bonding the heat source and the heat sink. In addition, the material constituting the heat dissipation cover 103 can be a metal material with good thermal conductivity, such as copper, aluminum, etc.

[0064] On this basis, in some embodiments of the present application, the heat dissipation cover 103 is as follows Figure 2a As shown, the upper cover 31 and the plurality of side walls 32 may be included. The plurality of side walls 32 are arranged around the upper cover 31 and may be connected to the first surface A1 of the package substrate 102 through an adhesive layer 40. The bonding position between the side wall 32 and the package substrate 102 may be referred to as a footprint. When the plurality of side walls 32 are arranged around the upper cover 31, as shown in FIG. Figure 2b As shown, a plurality of side walls 32 are connected end to end in sequence to form a frame structure, and the hollow portion of the frame structure is the area where the above-mentioned accommodating cavity 20 is located.

[0065] It should be noted that the embodiment of the present application is described by taking the heat dissipation cover 103 including four side walls 32, and the frame structure formed by the four side walls 32 connected end to end in sequence as an example. The present application does not limit the number of side walls 32 in the heat dissipation cover 103 and the shape of the frame structure formed by the multiple side walls 32 connected end to end, and will not be described one by one here.

[0066] In addition, if Figure 2a As shown, the upper cover 31 may include at least one boss structure 310 and a first connection structure 311. Each boss structure 310 of the at least one boss structure 310 may be in contact with at least one inner thermal interface layer 110. For example, Figure 2aAs shown, when the upper cover 31 has a boss structure 310 and the chip package structure 10 includes an inner thermal interface layer 110, the boss structure 310 is in contact with the inner thermal interface layer 110. Alternatively, when the upper cover 31 has a boss structure 310 and the chip package structure 10 includes multiple inner thermal interface layers 110, the boss structure 310 can be in contact with all of the multiple inner thermal interface layers 110 at the same time. Alternatively, when the upper cover 31 has multiple boss structures 310 and the chip package structure 10 includes multiple inner thermal interface layers 110, each of the multiple boss structures 310 can be in contact with one inner thermal interface layer 110 respectively.

[0067] Furthermore, each of the at least one boss structure 310 may be connected to the side wall 32 via a first connection structure 311. In this case, the portion of the upper cover 31 used for contacting the inner thermal interface layer 110 is the boss structure 310, and the portion of the upper cover 31 used for connecting the boss structure 310 to the side wall 32 is the first connection structure 311.

[0068] It should be noted that the boss structure 310 and the first connecting structure 311 in the upper cover 31 can be made of the same material and be an integral structure. In the process of manufacturing the heat dissipation cover 103, the above-mentioned four side walls 32, as well as the boss structure 310 and the first connecting structure 311 in the upper cover 31 can be prepared simultaneously through the same process flow. In addition, since the boss structure 310 and the first connecting structure 311 are an integral structure, the following embodiments distinguish between the boss structure 310 and the first connecting structure 311 for the convenience of explanation. For example, in the vertical projection of the first surface A1 of the packaging substrate 102 in the upper cover 31, the portion corresponding to the vertical projection of at least one chip 101 on the first surface A is the boss structure 310. For example, Figure 2a As shown, when the upper cover 31 has a boss structure 310 and a chip 101 is packaged in the chip package structure 10, the vertical projection of the boss structure 310 on the first surface A1 can completely overlap with the vertical projection of the chip 101 on the first surface A1. Alternatively, when the upper cover 31 has a boss structure 310 and a plurality of chips 101 are packaged in the chip package structure 10, the vertical projections of the plurality of chips 101 on the first surface A1 can all be located within the range of the vertical projection of the boss structure 310 on the first surface A1. Alternatively, when the upper cover 31 has a plurality of boss structures 310 and a plurality of chips 101 are packaged in the chip package structure 10, the vertical projection of each boss structure 310 on the first surface A1 can completely overlap with the vertical projection of a chip 101 on the first surface A1. In addition, the portion of the vertical projection of the upper cover 31 on the first surface A that is located outside the vertical projection of the chip 101 on the first surface A is the first connection structure 311.

[0069] In addition, the maximum thickness D1_max of the boss structure 310 is greater than the maximum thickness D2_max of the first connection structure 311, and the boss structure 310 is away from the surface of the chip 101 and protrudes beyond the surface of the first connection structure 311 away from the chip 101. Figure 2a The description is made by taking the surface of the protrusion structure 310 away from the chip 101 as a step. In other embodiments of the present application, Figure 3a As shown, the surface of the boss structure 310 away from the chip 101 may be an arc surface that bulges away from the packaging substrate 102 .

[0070] It should be noted that the maximum thickness D1_max of the boss structure 310 refers to the thickest portion of the boss structure 310 along a direction perpendicular to the first surface A1. Similarly, the maximum thickness D2_max of the first connection structure 311 refers to the thickest portion of the first connection structure 311 along a direction perpendicular to the first surface A1.

[0071] Figure 3a The structure of the side wall 32 is described by taking the side wall 32 of the heat dissipation cover 103 as being perpendicular to the first surface A1 of the packaging substrate 102 as an example. Figure 3b As shown, the side wall 32 of the heat dissipation cover 103 may have an acute angle α with the package substrate 102. Figure 3a The scheme shown is relative to Figure 3b As for the scheme shown, since the side wall 32 is arranged perpendicular to the first surface A1 of the packaging substrate 102, the layout area of ​​the entire heat dissipation cover 103 on the packaging substrate 102 can be reduced, which is beneficial to saving component space on the packaging substrate 102, so that more chips 101 or other electronic components can be arranged on the packaging substrate 102.

[0072] It should be noted that in the implementation of the present application, the thickness of the boss structure 310 and the thickness of the first connection structure 311 are perpendicular to the direction of the first surface A1, that is, along Figure 3a In this case, the maximum thickness D1_max of the boss structure 310 refers to the maximum distance between the upper and lower surfaces of the boss structure 310 along the Y direction. The maximum thickness D2_max of the first connecting structure 311 refers to the maximum distance between the upper and lower surfaces of the first connecting structure 311 along the Y direction.

[0073] As can be seen from the above, the chip package structure 10 with the heat dissipation cover 103 can be arranged on the PCB 12, an outer heat conduction interface layer 120 can be formed on the upper surface of the heat dissipation cover 103, and the heat dissipation device 11 can be arranged on the surface of the heat dissipation cover 103 away from the PCB 12. Then, the four corners of the heat dissipation device 11 are fixed to the PCB 12 by threaded connectors, such as screws.

[0074] Based on this, on the one hand, in the chip packaging structure 10, when the chip 101 is in service (ie, working), the packaging substrate 102 undergoes the following changes due to the increase in temperature: Figure 4 The warping phenomenon shown. The warping phenomenon will cause the gap between the heat dissipation cover 103 and the heat dissipation device 11 to tend to increase. However, since the heat dissipation cover 103 has a boss structure 310. The maximum thickness D1_max of the boss structure 310 is greater than the maximum thickness D2_max of the first connection structure 311, and the boss structure 310 is away from the surface of the chip 101 and protrudes from the surface of the first connection structure 311 away from the chip 101. Therefore, the boss structure 310 can reduce the gap between the heat dissipation cover 103 and the heat dissipation device 11.

[0075] In this way, it is possible to avoid a large change in the gap between the heat dissipation cover 103 and the heat dissipation device 11 due to the deformation of the outer thermal conductive interface layer 120, so that the heat dissipation device 11 fixed on the PCB 12 can still effectively exert pressure on the boss structure 310, thereby reducing the probability of delamination between the solidified inner thermal conductive interface layer 110 and the chip 101, and improving the thermal contact reliability between the inner thermal conductive interface layer 110 and the chip 101 and the heat dissipation cover 103, thereby reducing the probability of high-temperature power failure in the chip packaging structure 10.

[0076] On this basis, Figure 4 It can be seen that when the package substrate 102 in the chip package structure 10 is deformed, the area of ​​the package substrate 102 corresponding to the center of the chip 101 is deformed greatly, which easily causes the inner thermal interface layer 110 to be delaminated at the portion in contact with the center of the chip 101. In order to solve the above problem, the portion of the boss structure 310 of the heat dissipation cover 103 with the maximum thickness D1_max can be located at the center of the chip 101.

[0077] In this way, most of the pressure applied by the heat sink 11 to the chip 101 through the boss structure 310 can be applied to the center of the chip 101, avoiding the pressure applied by the heat sink 11 to the chip 101 from being offset, and reducing the probability of delamination of the inner thermal interface layer 110 in contact with the center of the chip 101.

[0078] On the other hand, when the upper surface of the heat dissipation cover 103 is a plane, the surface will be concave and present a "smiley face" state at the service temperature or higher, making it difficult for the external force to be effectively transmitted to the chip 101 through the heat dissipation cover 103. In the embodiment of the present application, since the heat dissipation cover 103 has the above-mentioned boss structure 310, it is better in contact with the external thermal interface layer 120, so that the heat dissipation device 11 can more effectively apply pressure to the chip 101.

[0079] On the other hand, in the embodiment of the present application, the boss structure 310 is used as a part of the heat dissipation cover 103, and the preparation of the boss structure 310 can be completed while manufacturing the heat dissipation cover 103. The current mass production processing technology can make the tolerance of the heat dissipation cover 103 much smaller than the whole machine level tolerance of manufacturing the heat dissipation device 11. Therefore, compared with the solution of manufacturing the boss structure 310 on the heat dissipation device 11, the boss structure 310 is used as a part of the heat dissipation cover 103, and the thickness of the boss structure 310 does not need to be large, which is conducive to the outer thermal interface layer 120 absorbing the thickness of the boss structure 310, and can avoid the boss structure 310 being too thick, resulting in the outer thermal interface layer 120 can only cover the area where the boss structure 310 is located in the upper cover 31, thereby improving the filling degree of the outer thermal interface layer 120 between the heat dissipation device 11 and the heat dissipation cover 103.

[0080] In some embodiments of the present application, Figure 5 As shown, the side surface of the side wall 32 of the heat dissipation cover 103 away from the package substrate 102 can be used as the upper reference surface B1. In order to make the boss structure 310 away from the surface of the chip 101, the first connecting structure 311 protrudes away from the surface of the chip 101, as shown in FIG. Figure 5 As shown, the boss structure 310 is away from the surface of the chip 101 and protrudes from the upper reference plane B1, and there is a maximum distance L_max between the surface of the boss structure 310 away from the chip 101 and the upper reference plane B1. For example, 0.01mm≤L_max≤0.2mm.

[0081] It should be noted that, in the embodiment of the present application, the side surface of the side wall 32 of the heat dissipation cover 103 away from the packaging substrate 102 can be used as the upper reference plane B1. When at least a portion of the side surface of the side wall 32 of the heat dissipation cover 103 away from the packaging substrate 102 is a plane, this portion can be used as the above-mentioned upper reference plane B1.

[0082] In this case, when the maximum distance L_max is less than 0.01 mm, the protrusion of the boss structure 310 is small, and the boss structure 310 has an insignificant effect on reducing the distance between the heat dissipation cover 103 and the heat dissipation device 11, and cannot effectively improve the pressure effect of the heat dissipation device 11 on the boss structure 310. When L_max is greater than 0.2 mm, the protrusion of the boss structure 310 is too large, so that the gap between the boss structure 310 and the heat dissipation device 11 is too small, and the external thermal interface layer 120 can only cover the area where the boss structure 310 is located in the upper cover 31, thereby reducing the filling amount of the external thermal interface layer 120 between the heat dissipation device 11 and the heat dissipation cover 103. In addition, the thickness of the external thermal interface layer 120 (for example, 0.12 mm to 0.3 mm) cannot well absorb the thickness of the boss structure 310, so that the contact flatness with the surface of the heat dissipation device 11 facing the packaging substrate 102 is reduced.

[0083] Therefore, when the maximum distance L_max satisfies 0.01mm≤L_max≤0.2mm, the surface where the outer thermal interface layer 120 contacts the heat sink 11 can be a plane, which is beneficial to improving the contact performance between the outer thermal interface layer 120 and the heat sink 11. In addition, the filling degree of the outer thermal interface layer 120 between the heat sink 11 and the heat sink cover 103 can meet the requirements, thereby maintaining the temperature equalization capability of the heat sink cover 103 and the heat sink 11. For example, the above maximum distance L_max can be 0.05mm, 0.06mm, 0.08mm, 0.10mm, 0.15mm.

[0084] In addition, when performing the surface mounting (SMT) process, since the tolerance level of the heat dissipation cover 103 is much higher than the tolerance level of the SMT suction nozzle, although the boss structure 310 is far away from the surface of the chip 101 and protrudes from the surface of the first connection structure 311 far away from the chip 101, the protruding part of the surface of the boss structure 310 far away from the chip 101 can be considered to be a smooth transition in macroscopic terms. In this way, when the SMT suction nozzle adsorbs the chip packaging structure 10, it can be closely attached to the heat dissipation cover 103.

[0085] Other configurations of the boss structure 310 are described below by way of example.

[0086] In some embodiments of the present application, Figure 6aAs shown, the maximum thickness D1_max of the boss structure 310 is greater than the maximum thickness D2_max of the first connection structure 311. The boss structure 310 is far from the surface (upper surface) of the chip 101 and protrudes from the surface of the first connection structure 311 far from the chip 101. In addition, the boss structure 310 is close to the surface (lower surface) of the chip 101 and protrudes from the surface of the first connection structure 311 close to the chip 101.

[0087] In this way, the upper and lower surfaces of the boss structure 310 both protrude from the first connecting structure 311, which is beneficial to increase the thickness and rigidity of the boss structure 310, so that the heat dissipation device 11 can more effectively apply pressure to the boss structure 310 in the heat dissipation cover 103, reducing the probability of delamination of the inner thermal interface layer 110.

[0088] In addition, since the boss structure 310 is close to the surface (lower surface) of the chip 101 and protrudes from the surface of the first connection structure 311 close to the chip 101, when the maximum thickness D1_max of the boss structure 310 meets the design requirements, the maximum distance L_max between the surface (upper surface) of the boss structure 310 away from the chip 101 and the upper reference plane B1 may not need to be too large, for example, L_max = 0.06mm. Thus, the thickness of the outer thermal interface layer 120 covering the upper surface of the boss structure 310 (for example, 0.12mm to 0.3mm) can well absorb the thickness of the boss structure 310, which is conducive to improving the filling degree of the outer thermal interface layer 120 between the heat sink 11 and the heat dissipation cover 103.

[0089] In addition, if Figure 6a As shown, along the direction from the boss structure 310 to the side wall 32 ( Figure 6a In the X direction in FIG. 1 , the thickness D2 of the first connection structure 311 gradually decreases. In this way, the rigidity of the first connection structure 311 at one end close to the side wall 32 can be reduced, so that when the heat sink 11 applies pressure to the heat sink cover 103, the first connection structure 311 at one end close to the side wall 32 is easily deformed. Therefore, when the heat sink 11 applies pressure to the heat sink cover 103, the first connection structure 311 is more likely to move in the downward pressing direction of the heat sink 11, so that the pressure applied by the heat sink 11 to the heat sink cover 103 is more concentrated on the boss structure 310 with greater thickness and rigidity, and the pressure of the heat sink 11 can be more effectively transmitted to the chip structure 101 through the boss structure 310 in the heat sink cover 103, thereby reducing the probability of delamination of the internal thermal interface layer 110.

[0090] It should be noted that Figure 6a The structure of the side wall 32 is described by taking the side wall 32 of the heat dissipation cover 103 as being perpendicular to the packaging substrate 102 as an example. Figure 6bAs shown, the side wall 32 of the heat dissipation cover 103 may have an acute angle α with the package substrate 102 .

[0091] In addition, in the direction from the boss structure 310 to the side wall 32 ( Figure 6a In the X direction), when the thickness D2 of the first connecting structure 311 gradually decreases, Figure 6a and Figure 6b The explanation is made by taking as an example that the surface (upper surface) of the boss structure 310 away from the chip 101 and the surface (lower surface) close to the chip 101, and the surface (upper surface) of the first connecting structure 311 away from the chip 101 and the surface (lower surface) close to the chip 101 are all non-planar surfaces protruding outward.

[0092] In other embodiments of the present application, Figure 7a As shown, the surface (upper surface) of the first connecting structure 311 away from the chip 101 is a plane. Figure 7a The thickness D2 of the first connection structure 311 gradually decreases, and the first connection structure 311 is close to the surface (lower surface) of the chip 101 and is an inclined surface or an arc surface.

[0093] Or, in other embodiments of the present application, Figure 7b As shown, the surface (lower surface) of the first connection structure 311 close to the chip 101 is a plane. In this case, the surface (lower surface) of the boss structure 310 close to the chip 101 can be flush with the surface (lower surface) of the first connection structure 311 close to the chip 101. In this way, the surface of the upper cover 31 in the heat dissipation cover 103 close to the chip 101 can have a higher flatness, thereby achieving the purpose of simplifying the mold structure for manufacturing the heat dissipation cover 103.

[0094] In addition, in order to ensure that the direction from the boss structure 310 to the side wall 32 ( Figure 7b The thickness D2 of the first connection structure 311 gradually decreases, and the surface (upper surface) of the first connection structure 311 away from the chip 101 is an inclined surface or an arc surface. In this case, when the surfaces (upper surfaces) of the boss structure 310 and the first connection structure 311 away from the chip 101 are both arc surfaces, the curvatures of the surfaces (upper surfaces) of the boss structure 310 and the first connection structure 311 away from the chip 101 can be the same. In this way, the structure of the mold for making the heat dissipation cover 103 can be simple, and the manufacturing process can be simplified.

[0095] Similarly, Figure 7a and Figure 7bIn the embodiment, the side wall 32 of the heat dissipation cover 103 may have an acute angle α with the package substrate 102, which will not be described in detail. For the convenience of description, the following description is based on the example that the side wall 32 of the heat dissipation cover 103 is perpendicular to the first surface A1 of the package substrate 102.

[0096] In addition, when the thickness D2 of the first connecting structure 311 gradually decreases along the direction from the boss structure 310 to the side wall 32, in some embodiments of the present application, such as Figure 8 As shown, the side surface (upper surface) of the side wall 32 away from the package substrate 102 is the upper reference surface B1, and the side surface (upper surface) of the inner thermal conductive interface layer 110 away from the package substrate 102 is the lower reference surface B2. Based on this, there is a reference thickness D0 between the upper reference surface B1 and the lower reference surface B2. The minimum thickness D2_min of the first connection structure 311 can be less than the reference thickness D0.

[0097] In this way, the purpose of reducing the rigidity of the first connection structure 311 can be achieved by reducing the thickness of the first connection structure 311. Therefore, when the heat sink 11 applies pressure to the heat sink cover 103, the first connection structure 311 can more easily move in the downward pressing direction of the heat sink 11, so that the pressure applied by the heat sink 11 to the heat sink cover 103 is more concentrated on the boss structure 310, reducing the probability of delamination of the inner thermal interface layer 110.

[0098] It should be noted that, as can be seen from the above, the thickness D2 of the first connecting structure 311 gradually decreases along the direction from the boss structure 310 to the side wall 32, so the minimum thickness D2_min of the first connecting structure 311 is the thickness of one end of the first connecting structure 311 close to the side wall 32 (or the above footprint).

[0099] For example, the minimum thickness D2_min of the first connection structure 311 and the reference thickness D0 may satisfy: 20%×D0≤D2_min≤80%×D0. For example, the minimum thickness D2_min of the first connection structure 311 may be 25%×D0, 30%×D0, 35%×D0, 40%×D0, 45%×D0, 50%×D0, 60%×D0 or 70%×D0. In some embodiments of the present application, the reference thickness D0 may be in the range of 1 mm to 2 mm. For example, when D0=1 mm, the range of the minimum thickness D2_min is 0.2 mm≤D2_min≤0.8 mm.

[0100] When the minimum thickness D2_min of the first connection structure 311 is less than 20%×D0, the thickness of the first connection structure 311 is too thin, resulting in too little rigidity of the first connection structure 311, which reduces the ability of the heat dissipation cover 103 to control the warping of the package substrate 102. In addition, when the minimum thickness D2_min of the first connection structure 311 is greater than 80%×D0, the thickness of the first connection structure 311 is too large and the rigidity is too strong, so that when the heat dissipation device 11 applies pressure to the heat dissipation cover 103, the first connection structure 311 is not easy to move with the downward pressing direction of the heat dissipation device 11, which is not conducive to concentrating the pressure applied by the heat dissipation device 11 to the heat dissipation cover 103 on the boss structure 310.

[0101] On this basis, it can be known from the above that the surface (upper surface) of the boss structure 310 away from the chip 101 has a maximum distance L_max from the upper reference plane B1. In some embodiments of the present application, L_max<D0. In this way, the portion of the boss structure 310 located in the accommodating cavity 20, that is, the portion of the boss structure 310 where the reference thickness D0 is located, can be made thicker, while the portion of the boss structure 310 located outside the accommodating cavity 20, that is, the portion of the boss structure 310 where the maximum distance L_max is located, can be made thinner. Therefore, when the maximum thickness D1_max of the boss structure 310 meets the design requirements, the maximum distance L_max of the boss structure 310 does not need to be too large, which is beneficial to improve the filling degree of the external thermal interface layer 120 between the heat sink 11 and the heat dissipation cover 103.

[0102] In addition, in some embodiments of the present application, Figure 9a As shown, the surface of the boss structure 310 away from the chip 101 is the first curved surface S1, and the portion of the surface of the first connecting structure 311 away from the chip 101 close to the first curved surface S1 is the second curved surface S2. The second curved surface S1 has the same curvature as the first curved surface S2, and the second curved surface S2 is connected to the first curved surface S1. In addition, the vertical projection of the chip 101 corresponding to the boss structure 310 on the first surface A1 is located within the range of the vertical projection of the first curved surface S1 and the second curved surface S2 on the first surface A1. In this way, not only the surface of the boss structure 310 away from the chip 101 in the upper cover 31 is raised, but also the surface of the first connecting structure 311 away from the chip 101 is raised at the position where the second curved surface S2 is located, so that the size of the raised portion of the surface of the upper cover 31 away from the chip 101 can be appropriately increased. Therefore, when the heat sink 11 applies pressure to the heat dissipation cover 103 , the pressure can be more effectively applied to the raised portion of the upper cover 31 and transferred to the chip 101 , thereby making the thermal interface layer 110 and the chip 101 fit more closely.

[0103] On this basis, the vertical projection of one side of the second curved surface S2 away from the first curved surface S1 on the first surface A1 has the following shape: Figure 9b (along Figure 9a The chip 101 corresponding to the boss structure 310 has a second profile T2 in the vertical projection of the first surface A1. The maximum spacing Hmax between the first profile T1 and the second profile T2 satisfies: Hmax≤2mm. When Hmax>2mm, the size of the raised portion of the surface of the upper cover 31 away from the chip 101 is too large, so that the gap between the upper cover 31 and the heat sink 11 is too small, and the external thermal interface layer 120 can only cover the area where the boss structure 310 is located in the upper cover 31, thereby reducing the filling amount of the external thermal interface layer 120 between the heat sink 11 and the heat sink 103.

[0104] It should be noted that, in the embodiment of the present application, the chip 101 corresponding to the boss structure 310 refers to the chip 101 connected to the boss structure 310 through the inner thermal conductive interface layer 110 .

[0105] Or, in other embodiments of the present application, Fig.9c As shown, at least a portion of the surface of the boss structure 310 away from the chip 101 is a third curved surface S3. The vertical projection of the third curved surface S3 on the first surface A1 is located within the range of the vertical projection of the chip 101 corresponding to the boss structure 310 on the first surface A1. On this basis, the vertical projection of the third curved surface S3 on the first surface A1 has the following Figure 9d (along Fig.9c The third profile T3 is shown in the top view obtained by the arrow Y direction in FIG. The vertical projection of the chip 101 corresponding to the boss structure 310 has a second profile T2 on the first surface A1. The maximum spacing Hmax between the third profile T3 and the second profile T2 satisfies: Hmax≤2mm. When Hmax>2mm, the size of the boss structure 310 is too small, and when the heat sink 11 applies pressure to the heat sink cover 103, the area of ​​the action surface of the heat sink 103 on the chip 101 is too small, which is not conducive to the heat sink 11 to effectively apply pressure to the chip 101.

[0106] Alternatively, in other embodiments of the present application, Fig.9e As shown, the surface of the boss structure 310 away from the chip 101 is a first curved surface S1. The vertical projection of the first curved surface S1 on the first surface A1 completely overlaps with the vertical projection of the chip 101 corresponding to the boss structure 310 on the first surface A1. In this way, the boss structure 310 can completely cover the chip 101, so that when the heat dissipation device 11 applies pressure to the heat dissipation cover 103, the force acting on the boss structure 310 can be more effectively transmitted to the chip 101.

[0107] In addition, in order to further reduce the thickness D2 of the first connecting structure 311 in the upper cover 31 of the heat dissipation cover 103, as shown in FIG. Fig.10 As shown, the upper cover 31 may also include at least one first groove 312. The first groove 312 is provided on a side surface of the first connection structure 311 close to the chip 101. The first groove 312 may be located at an end of the first connection structure 311 away from the boss structure 310. In this way, by providing the first groove 312 at an end of the first connection structure 311 away from the boss structure 310, the rigidity of the first connection structure 311 close to the side wall 32 (or the footprint) may be further reduced, which is conducive to concentrating the pressure applied by the heat sink 11 to the heat dissipation cover 103 on the boss structure 310.

[0108] In some embodiments of the present application, Fig.10 As shown, the depth S1 of the first groove 312 can satisfy: 20%×D2_max≤S1≤80%×D2_max. The groove width L1 of the first groove 312 can satisfy: 0.1mm≤L1≤20mm. When the depth S1 of the first groove 312 is less than 20%×D2_max (for example, when the maximum thickness D2_max of the first connection structure 311 is 1mm, S1 is less than 0.2mm), and the width L1 is less than 0.1mm, the manufacturing accuracy of the first groove 312 is high, which is not conducive to reducing the manufacturing cost. In addition, the size of the first groove 312 is too small, and the effect of reducing the rigidity of the first connection structure 311 is not obvious. In addition, when the depth S1 of the first groove 312 is greater than 80%×D2_max (for example, when the maximum thickness D2_max of the first connecting structure 311 is 2.7 mm, S1 is greater than 2.1 mm) and the width L1 is greater than 20 mm, the size of the first groove 312 is too large, which causes the first connecting structure 311 to be too small, thereby reducing the heat dissipation cover 103's ability to control the warping of the packaging substrate 102.

[0109] For example, the depth S1 of the first groove 312 can be 0.5 mm, 0.8 mm, 1.0 mm or 1.5 mm. The width L1 of the first groove 312 can be 0.5 mm, 1 mm, 2 mm, 4 mm, 8 mm, 15 mm or 18 mm. In this way, the control capability of the heat dissipation cover 103 on the warping of the package substrate 102 can be avoided while reducing the rigidity of the first connection structure 311.

[0110] On this basis, in some embodiments of the present application, Fig.11a As shown in (the side surface of the heat dissipation cover 103 close to the chip 101), the first groove 312 can be around at least one chip 101 ( Fig.11aThe position of the middle chip is indicated by a dotted line) and a circular groove is formed around the boss structure 310, thereby reducing the rigidity of the first connection structure around the boss structure 310.

[0111] Alternatively, in some other embodiments of the present application, taking the chip 101 as a rectangle as an example, the upper cover 31 may include four Fig.11b The first grooves shown (on one side of the heat dissipation cover 103 close to the chip 101) are respectively the first groove 312a, the first groove 312b, the first groove 312c and the first groove 312d. Among them, the first groove 312a and the first groove 312b are respectively located on two opposite sides of the chip 101. The first groove 312c and the first groove 312d are respectively located on two other opposite sides of the chip 101. In this case, the bottom of any one of the first grooves 312a, the first groove 312b, the first groove 312c and the first groove 312d can penetrate the first connection structure 311.

[0112] The above descriptions are all based on an example in which a chip package structure 10 is provided with a chip 101 . The following descriptions are based on an example in which two chips are provided in a chip package structure 10 to illustrate the structure of the heat dissipation cover 103 .

[0113] In some embodiments of the present application, Fig.12a As shown, at least one chip in the chip package structure 10 may include a first chip 101a and a second chip 101b. In this case, in order to ensure that the surface of each chip 101a away from the package substrate 102 is covered with an inner thermal interface layer, the at least one inner thermal interface layer may include a first inner thermal interface layer 110a covering the first chip 101a and a second inner thermal interface layer 110b covering the second chip 101b.

[0114] In order to ensure that the heat dissipation cover 103 is stably bonded to the first chip 101a and the second chip 101b, the surface of the first inner thermal interface layer 110a away from the package substrate 102 is flush with the surface of the second inner thermal interface layer 110b away from the package substrate 102. Fig.12a As shown, when the first chip 101a and the second chip 101b are chips with different functions or types and their thicknesses may be different, the thicknesses of the first inner thermal conductive interface layer 110a and the second inner thermal conductive interface layer 110b may be different, so that the thickness difference between the first chip 101a and the second chip 101b may be compensated by the thickness difference between the first inner thermal conductive interface layer 110a and the second inner thermal conductive interface layer 110b.

[0115] On this basis, in order to make the pressure applied by the heat dissipation device 11 to the heat dissipation cover 103 effectively act on the first chip 101a and the second chip 101b when the heat dissipation device 11 applies pressure to the heat dissipation cover 103, as shown in FIG. Fig.12a As shown, the at least one boss structure in the upper cover 31 may include a first boss structure 310a and a second boss structure 310b, wherein the first boss structure 310a contacts the first inner thermal interface layer 110a, and the second boss structure 310b contacts the second inner thermal interface layer 110b.

[0116] The configuration of the first boss structure 310a and the second boss structure 310b is the same as described above. Fig.12a As shown, the surface (upper surface) of the first boss structure 310a and the second boss structure 310b away from the package substrate 102 may protrude from the surface of the first connection structure 311 away from the chip 101. The surface (lower surface) of the first boss structure 310a and the second boss structure 310b close to the package substrate 102 may be a plane. In this case, Fig.12a As shown, the contact surface between the first boss structure 310a and the first inner thermal interface layer 110a can completely cover the first chip 101a. Similarly, the contact surface between the second boss structure 310b and the second inner thermal interface layer 110b can completely cover the second chip 101b.

[0117] Or, for example, Figure 12b As shown, the surface (upper surface) of the first platform structure 310a and the second platform structure 310b away from the package substrate 102 can protrude from the surface of the first connection structure 311 away from the chip 101. In addition, the surface (lower surface) of the first platform structure 310a and the second platform structure 310b close to the chip 101 protrudes from the surface of the first connection structure 311 close to the chip 101. In this case, Figure 12b As shown, the vertical projection of the contact surface between the first boss structure 310a and the first inner thermal conductive interface layer 110a on the package substrate 102 may be within the range of the vertical projection of the first chip 101a on the package substrate 102. Similarly, the vertical projection of the contact surface between the second boss structure 310b and the second inner thermal conductive interface layer 110b on the package substrate 102 may be within the range of the vertical projection of the second chip 101b on the package substrate 102.

[0118] On this basis, the upper cover 31 may also include Fig.12a or Figure 12b The second connecting structure 313 is shown. The second connecting structure 313 is located between the first boss structure 310a and the second boss structure 310b, and is connected to the first boss structure 310a and the second boss structure 310b.

[0119] Based on this, in order to effectively act on the first boss structure 310a and the second boss structure 310b when the heat sink 11 applies pressure to the heat sink 103, the upper cover 31 further includes at least one second groove 314, which is opened on the side surface of the second connection structure 313 close to the package substrate 102. The size setting method of the second groove 314 can be the same as the setting method of the first groove 312, which will not be repeated here.

[0120] In addition, when the package substrate 102 is a rewiring layer, the package substrate 102 is easily deformed during temperature changes. At this time, when the first groove 312 and the second groove 314 are set on the upper cover 31 of the heat dissipation cover 103, the rigidity of the upper cover 31 is weakened, so that when the package substrate 102 is deformed, there is a certain decoupling effect between the movement of the package substrate 102 and the movement of the heat dissipation cover 103, which reduces the constraint of the chip when it follows the package substrate 102. In this way, the distance between two adjacent chips, such as the first chip 101a and the second chip 101b, can be reduced. Fig.12c The molding material 400 shown is cracked. In the embodiment of the present application, the molding material 400 in some drawings is not shown.

[0121] In addition, in some other embodiments of the present application, when the chip package structure 10 includes the first chip 101a and the second chip 101b, as shown in FIG. Fig.13 As shown, the first chip 101a and the second chip 101b can be connected to the same boss structure 310 through the first inner thermal interface layer 110a and the second inner thermal interface layer 110b respectively. The boss structure 310 is in contact with both the first inner thermal interface layer 110a and the second inner thermal interface layer 110b. The arrangement of the boss structure 310 is the same as described above and will not be repeated here. When the heat sink 11 applies pressure to the heat dissipation cover 103, the pressure can be transmitted to the first chip 101a and the second chip 101b through the same boss structure 310, thereby simplifying the structure of the heat dissipation cover 103.

[0122] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A chip packaging structure, characterized in that: include: A packaging substrate having a first surface; At least one chip is disposed on the first surface of the packaging substrate; at least one inner thermally conductive interface layer; The at least one inner thermal conductive interface layer respectively covers a surface of the at least one chip away from the packaging substrate; A heat dissipation cover, comprising an upper cover and a plurality of side walls; the plurality of side walls are sequentially arranged end to end around a circumference of the upper cover and connected to the first surface; a receiving cavity for receiving the at least one chip is formed between the heat dissipation cover and the packaging substrate; Wherein, the upper cover includes at least one boss structure and a first connecting structure; each boss structure in the at least one boss structure is in contact with at least one of the inner thermal conductive interface layers, and each boss structure in the at least one boss structure is connected to the side wall through the first connecting structure; the maximum thickness D1_max of the boss structure is greater than the maximum thickness D2_max of the first connecting structure, and the boss structure is away from the surface of the chip and protrudes from the surface of the first connecting structure away from the chip; the direction of the thickness is perpendicular to the direction of the first surface; the upper cover also includes at least one first groove, which is opened on a side surface of the first connecting structure close to the chip; the first groove is located at one end of the first connecting structure away from the boss structure.

2. The chip packaging structure according to claim 1, characterized in that: The boss structure is close to the surface of the chip and protrudes from the surface of the first connecting structure close to the chip.

3. The chip packaging structure according to claim 1, characterized in that: The surface of the boss structure close to the chip is flush with the surface of the first connecting structure close to the chip.

4. The chip packaging structure according to claim 1, characterized in that: Along the direction from the boss structure to the side wall, the thickness D2 of the first connecting structure gradually decreases.

5. The chip packaging structure according to claim 4, characterized in that: The surface of the first connecting structure close to the chip or the surface away from the chip is a plane.

6. The chip packaging structure according to claim 4, characterized in that: The side surface of the side wall away from the packaging substrate is an upper reference surface, and the side surface of the inner thermal conductive interface layer away from the packaging substrate is a lower reference surface; A reference thickness D0 is provided between the upper reference surface and the lower reference surface; and a minimum thickness D2_min of the first connection structure is smaller than the reference thickness D0.

7. The chip packaging structure according to claim 6, characterized in that: 20%×D0≤D2_min≤80%×D0.

8. The chip packaging structure according to claim 6, characterized in that: There is a maximum distance L_max between the surface of the boss structure away from the chip and the upper reference surface; L_max<D0.

9. The chip packaging structure according to claim 8, characterized in that: 0.01mm≤L_max≤0.2mm.

10. The chip packaging structure according to claim 4, characterized in that: The surface of the boss structure away from the chip is a first curved surface; Among the surfaces of the first connection structure away from the chip, the portion close to the first curved surface is a second curved surface, the second curved surface has the same curvature as the first curved surface, and the second curved surface is connected to the first curved surface; the vertical projection of the chip corresponding to the boss structure on the first surface is located within the range of the vertical projection of the first surface by the first curved surface and the second curved surface; The vertical projection of the side of the second curved surface away from the first curved surface on the first surface has a first contour; the vertical projection of the chip corresponding to the boss structure on the first surface has a second contour; A maximum distance Hmax between the first contour and the second contour satisfies: Hmax≤2 mm.

11. The chip packaging structure according to any one of claims 1 to 9, characterized in that: At least a portion of the surface of the boss structure away from the chip is a third curved surface; The vertical projection of the third curved surface on the first surface is located within the range of the vertical projection of the chip corresponding to the boss structure on the first surface; The vertical projection of the third curved surface on the first surface has a third contour; the vertical projection of the chip corresponding to the boss structure on the first surface has a second contour; A maximum distance Hmax between the third contour and the second contour satisfies: Hmax≤2 mm.

12. The chip packaging structure according to any one of claims 1 to 9, characterized in that: The surface of the boss structure away from the chip is a first curved surface; A vertical projection of the first curved surface on the first surface completely overlaps with a vertical projection of a chip corresponding to the boss structure on the first surface.

13. The chip packaging structure according to claim 1, characterized in that: The first groove is an annular groove surrounding the at least one chip.

14. The chip packaging structure according to claim 1 or 13, characterized in that: The depth S1 of the first groove satisfies: 20%×D2_max≤S1≤80%×D2_max; the groove width L1 of the first groove satisfies: 0.1mm≤L1≤20mm.

15. The chip packaging structure according to any one of claims 1 to 9, characterized in that: The at least one chip comprises a first chip and a second chip; the at least one inner thermal conductive interface layer comprises a first inner thermal conductive interface layer covering the first chip and a second inner thermal conductive interface layer covering the second chip; a surface of the first inner thermal conductive interface layer away from the packaging substrate is flush with a surface of the second inner thermal conductive interface layer away from the packaging substrate; The at least one boss structure comprises a first boss structure and a second boss structure, the first boss structure is in contact with the first inner thermal conductive interface layer, and the second boss structure is in contact with the second inner thermal conductive interface layer; The upper cover also includes a second connecting structure, which is located between the first boss structure and the second boss structure and connected to the first boss structure and the second boss structure.

16. The chip packaging structure according to claim 15, characterized in that: The upper cover further includes at least one second groove, and the second groove is formed on a surface of the second connection structure on one side close to the packaging substrate.

17. The chip packaging structure according to any one of claims 1 to 9, characterized in that: The at least one chip comprises a first chip and a second chip; the at least one inner thermal conductive interface layer comprises a first inner thermal conductive interface layer covering the first chip and a second inner thermal conductive interface layer covering the second chip; The surface of the first inner thermal conductive interface layer away from the packaging substrate is flush with the surface of the second inner thermal conductive interface layer away from the packaging substrate; One of the boss structures is in contact with the first inner thermal conductive interface layer and the second inner thermal conductive interface layer.

18. An electronic device, characterized in that: A chip packaging structure comprising a heat dissipation device, an external heat-conducting interface layer, a circuit board, and a chip packaging structure according to any one of claims 1 to 17 arranged on the circuit board; The outer heat-conducting interface layer is located between the heat sink and the heat-dissipating cover in the chip packaging structure, and is connected to the heat sink and the heat-dissipating cover; the heat sink is also connected to the circuit board.

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