Display device

Abstract

A display device according to an embodiment of the present application includes a first silicon transistor including a first semiconductor layer and a first gate electrode overlapping the first semiconductor layer, wherein the first semiconductor layer includes a silicon-based semiconductor; a first oxide transistor spaced apart from the first semiconductor layer and including a second semiconductor layer and a second gate electrode, wherein the second semiconductor layer includes an oxide-based semiconductor; an upper insulating layer disposed on the first semiconductor layer and the second semiconductor layer; and a first connection electrode disposed on the upper insulating layer and electrically connected to the first semiconductor layer and the second semiconductor layer through first and second contact holes passing through the upper insulating layer, respectively. The second semiconductor layer includes a channel region and a source region and a drain region disposed on respective sides of the channel region, wherein a first distance between the channel region of the second semiconductor layer and the first contact hole is about 2 μm or more.

Description

TECHNICAL FIELD

[0001] One or more embodiments relate to a display device. BACKGROUND

[0002] Unlike liquid crystal display devices, light emitting diode display devices are a kind of display device that displays an image and self-emits. Thus, since a separate light source is not required, the thickness and weight of the light emitting diode display device can be reduced. In addition, the organic light emitting diode display device can have high quality characteristics such as low power consumption, high brightness, and high response speed. SUMMARY

[0003] DETAILED DESCRIPTION

[0004] TECHNICAL PROBLEM

[0005] One or more embodiments include a display device that displays a high quality image.

[0006] SOLUTION TO PROBLEM

[0007] According to one or more embodiments, a display device can include a first silicon transistor including a first semiconductor layer including a silicon-based semiconductor, and a first gate electrode overlapping the first semiconductor layer, a first oxide transistor including a second semiconductor layer spaced apart from the first semiconductor layer and including an oxide-based semiconductor, and a second gate electrode, an upper insulating layer disposed on the first semiconductor layer and the second semiconductor layer, the upper insulating layer including a first contact hole and a second contact hole, and a first connection electrode disposed on the upper insulating layer, electrically connected to the first semiconductor layer through the first contact hole, and electrically connected to the second semiconductor layer through the second contact hole, wherein the second semiconductor layer can include a channel region, a source region, and a drain region, the source region and the drain region are arranged at opposite sides of the channel region, and a first distance between the channel region of the second semiconductor layer and the first contact hole can be about 2 μm or more.

[0008] A hydrogen concentration of the source region or the drain region of the second semiconductor layer can be about 1.1 × 10 21 atom / cm 3 or more.

[0009] The display device can further include an insulating layer disposed between the first semiconductor layer and the second semiconductor layer.

[0010] The first semiconductor layer can include a channel region, a source region, and a drain region, the source region and the drain region of the first semiconductor layer being disposed at opposite sides of the channel region of the first semiconductor layer, and the channel region of the first semiconductor layer can include a curved shape.

[0011] The display device can further include a node connection line electrically connecting the first gate electrode of the first silicon transistor to the first oxide transistor.

[0012] The display device can further include a second oxide transistor including a third semiconductor layer and a third gate electrode, the third semiconductor layer including an oxide-based semiconductor.

[0013] The third semiconductor layer of the second oxide transistor and the second semiconductor layer of the first oxide transistor can be integral with each other.

[0014] The display device can further include an initialization voltage line, a first signal line extending in the same direction as the initialization voltage line, and a second connection electrode disposed on the third semiconductor layer of the second oxide transistor and the initialization voltage line, the second connection electrode electrically connecting the initialization voltage line to the third semiconductor layer.

[0015] The upper insulating layer can further include a third contact hole through which the second connection electrode can be electrically connected to the initialization voltage line, and a second distance between the channel region of the third semiconductor layer and the third contact hole can be about 2 µm or more.

[0016] The first signal line can include a first conductive layer overlapping the third semiconductor layer, a second conductive layer disposed below the third semiconductor layer, and an insulating layer disposed between the first conductive layer and the second conductive layer and including a contact hole, wherein the first conductive layer can be electrically connected to the second conductive layer through the contact hole of the insulating layer.

[0017] A width of the contact hole of the insulating layer can be about 2.2 µm or less.

[0018] A third distance between a channel region of the third semiconductor layer and the contact hole of the insulating layer can be about 2.4 µm or more.

[0019] The insulating layer can include a lateral surface forming the contact hole, and an inclination angle of the lateral surface can be about 86° or less.

[0020] The display device can further include a first capacitor electrically connected to the first silicon transistor, and a second capacitor electrically connected to the first oxide transistor.

[0021] The electrode of the second capacitor and the second semiconductor layer can include the same material.

[0022] According to one or more embodiments, a display device can include a silicon-based semiconductor layer including a first semiconductor layer of a first silicon transistor, an oxide-based semiconductor layer spaced apart from the silicon-based semiconductor layer, the oxide-based semiconductor layer including a second semiconductor layer of a first oxide transistor, an upper insulating layer disposed on the silicon-based semiconductor layer and the oxide-based semiconductor layer, the upper insulating layer including a first contact hole and a second contact hole, and a first connection electrode disposed on the upper insulating layer, electrically connected to the first semiconductor layer through the first contact hole, and electrically connected to the second semiconductor layer through the second contact hole, wherein the oxide-based semiconductor layer can include a channel region of the first oxide transistor, and a first distance between the channel region and the first contact hole can be about 2 µm or more.

[0023] The oxide-based semiconductor layer can further include a third semiconductor layer of a second oxide transistor, and the second semiconductor layer and the third semiconductor layer can be integral with each other.

[0024] The second semiconductor layer can include the channel region, and a source region and a drain region arranged at opposite sides of the channel region, respectively, wherein the third semiconductor layer can include a channel region, and a source region and a drain region arranged at opposite sides of the channel region of the third semiconductor layer, respectively, and wherein a hydrogen concentration of the source region or the drain region of each of the second semiconductor layer and the third semiconductor layer can be about 1.1 × 1019 atoms / cm3 or more. 21 3

[0025] The display device can further include an initialization voltage line to which an initialization voltage can be supplied to the second oxide transistor, and a second connection electrode disposed on the third semiconductor layer of the second oxide transistor and the initialization voltage line, and electrically connecting the initialization voltage line to the third semiconductor layer.

[0026] The upper insulating layer can further include a third contact hole, the second connection electrode can be electrically connected to the initialization voltage line through the third contact hole, and a second distance between the channel region of the third semiconductor layer and the third contact hole can be about 2 µm or more.

[0027] ​​The display device may further include: a first signal line overlapping the second semiconductor layer of the first oxide transistor; and a second signal line overlapping the third semiconductor layer of the second oxide transistor, wherein the first signal line or the second signal line may include a first conductive layer overlapping the oxide-based semiconductor layer; a second conductive layer disposed below the oxide-based semiconductor layer; and an insulating layer disposed between the first conductive layer and the second conductive layer and including a contact hole, wherein the first conductive layer may be electrically connected to the second conductive layer through the contact hole.

[0028] The width of the contact hole can be approximately 2.2 μm or less.

[0029] The third distance between the channel region of the third semiconductor layer and the contact hole of the insulating layer can be approximately 2.4 μm or greater.

[0030] The insulating layer may include a lateral surface forming the contact hole, and the tilt angle of the lateral surface may be approximately 86° or less.

[0031] The display device may further include an insulating layer disposed between the silicon-based semiconductor layer and the oxide-based semiconductor layer.

[0032] These and / or other aspects will become apparent and more readily understood from the following description of the embodiments and the accompanying drawings.

[0033] Effects of the present invention

[0034] According to embodiments, the transmittance of the transmission region can be adequately ensured through a simple process. Such effects are exemplary, and therefore the scope of this disclosure is not limited thereto. Attached Figure Description

[0035] Brief description of the attached figures

[0036] Figure 1 This is a plan view of a display device according to an embodiment.

[0037] Figure 2 This is an equivalent circuit diagram of a light-emitting diode and a pixel circuit electrically connected to the light-emitting diode in a display device according to an embodiment.

[0038] Figure 3 This is a plan view of pixel circuits arranged in the Nth row of a display device according to an embodiment.

[0039] Figure 4 It is along Figure 3 A schematic cross-sectional view of the pixel circuit and the light-emitting diodes arranged on the pixel circuit, taken by line A-A'.

[0040] Figure 5 is a plan view of a portion or a region of a pixel circuit of a display device according to an embodiment.

[0041] Figure 6 is a schematic cross-sectional view taken along Figure 5 line B-B' of FIG. 11A.

[0042] Figure 7 is a schematic cross-sectional view taken along Figure 5 line C-C' of FIG. 11B.

[0043] Figure 8 is a graph showing transfer curves of a third transistor according to an embodiment and a comparative example.

[0044] Figure 9 is a graph showing hydrogen concentration measured by secondary ion mass spectrometry (SIMS) for a third transistor according to an embodiment and a comparative example.

[0045] Figure 10 is a plan view of a portion of a display device according to an embodiment.

[0046] Figure 11 is a schematic cross-sectional view taken along Figure 10 line D-D' of FIG. 12A.

[0047] Figure 12 is a graph showing transfer curves of a fourth transistor according to an embodiment and a comparative example.

[0048] Figure 13 is a plan view of a portion or a region of a display device according to an embodiment. DETAILED DESCRIPTION

[0049] BEST MODE FOR CARRYING OUT THE INVENTION

[0050] According to one or more embodiments, a display device can include a first silicon transistor including a first semiconductor layer including a silicon-based semiconductor, and a first gate electrode overlapping the first semiconductor layer, a first oxide transistor including a second semiconductor layer spaced apart from the first semiconductor layer and including an oxide-based semiconductor, and a second gate electrode, an upper insulating layer disposed on the first semiconductor layer and the second semiconductor layer, the upper insulating layer including a first contact hole and a second contact hole, and a first connection electrode disposed on the upper insulating layer, electrically connected to the first semiconductor layer through the first contact hole, and electrically connected to the second semiconductor layer through the second contact hole, wherein the second semiconductor layer can include a channel region, a source region, and a drain region, the source region and the drain region are arranged at opposite sides of the channel region, and a first distance between the channel region of the second semiconductor layer and the first contact hole can be about 2 µm or more.

[0051] Embodiments of the present invention

[0052] Since the present disclosure allows various changes and numerous embodiments, embodiments will be illustrated in the accompanying drawings and described in detail in the written description. Through the following description of the embodiments and the drawings, the effects and features of the present disclosure will become apparent and more readily understood. However, the present disclosure is not limited to the following embodiments and can be implemented in various forms.

[0053] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. When described with reference to the drawings, the same reference numerals are assigned to the same or corresponding elements, and repetitive description thereof can be omitted.

[0054] In the following embodiments, it will be understood that, although terms such as "first", "second", etc. can be used herein to describe various components, these components should not be limited by these terms. These components are only used to distinguish one component from another.

[0055] In the following embodiments, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0056] In the following embodiments, it will be understood that the terms "include" and / or "including", "contain" and / or "containing", "have" and / or "having" used herein designate the presence of stated features or components, but do not exclude the presence or addition of one or more other features or components.

[0057] In the following embodiments, it will be understood that when a layer, a region or an element is referred to as being "formed on" another layer, region or element, it can be "directly formed or connected on" the other layer, region or element, or an intervening layer, region or element can be present. That is, for example, an intervening layer, region or element can be present.

[0058] The size of the elements in the drawings can be exaggerated or reduced for the sake of explanation. In other words, since the size and thickness of the components in the drawings are arbitrarily shown for the sake of explanation, the following embodiments are not limited thereto.

[0059] The order of the processes can be different from the described order. For example, two processes described in succession can be executed substantially simultaneously or in the reverse order to the described order.

[0060] In the following embodiments, it will be understood that when a layer, a region or an element is referred to as being "connected to" another layer, region or element, it can be "directly connected to" the other layer, region or element, or can be "indirectly connected to" the other layer, region or element, with other layers, regions or elements intervening therebetween. For example, it will be understood that when a layer, a region or an element is referred to as being "electrically connected to" another layer, region or element, it can be "directly electrically connected to" the other layer, region or element, or can be "indirectly electrically connected to" the other layer, region or element, with other layers, regions or elements intervening therebetween.

[0061] Figure 1 is a plan view of a display device 1 according to an embodiment.

[0062] As Figure 1 As shown in FIG. 1A, the display device 1 can include a display area DA and a non-display area NDA surrounding (or adjacent to) the display area DA.

[0063] The display area DA can display an image. The display area DA can include pixels. Each pixel can include a light emitting element, for example, a light emitting diode. Each light emitting diode can be electrically connected to circuit elements including a transistor and a capacitor. The circuit elements can be arranged or disposed in the display area DA.

[0064] The non-display area NDA can be an area in which an image can not be displayed. The non-display area NDA can completely surround the display area DA or can be adjacent to the display area DA. For example, a driver can be arranged or disposed in the non-display area NDA, the driver can provide an electrical signal or power to the circuit elements and / or the light emitting diodes arranged or disposed in the display area DA. The non-display area NDA can include a pad, for example, the pad can be a region or area to which an electronic element or a printed circuit board can be electrically connected.

[0065] Although the display device 1 and the display area DA are shown as being approximately quadrangular in Figure 1 , this is provided as an example. According to another example, the display device 1 and / or the display area DA can be substantially circular, substantially elliptical, or can have various substantially polygonal shapes.

[0066] Figure 2 is an equivalent circuit diagram of a light emitting diode LED of a display device according to an embodiment and a pixel circuit PC electrically connected to the light emitting diode LED.

[0067] Referring to Figure 2 , the pixel circuit PC electrically connected to the light emitting diode LED can include transistors and capacitors. The pixel circuit PC can include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, a storage capacitor Cst, and a boost capacitor Cbt.

[0068] Some or a predetermined number of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be N-channel metal oxide semiconductor field effect transistors (MOSFETs), and the remaining transistors of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-channel metal oxide semiconductor field effect transistors (MOSFETs). As an example, the third transistor T3 and the fourth transistor T4 can be N-channel MOSFETs (NMOS), and the remaining transistors can be P-channel MOSFETs (PMOS). In one embodiment, the third transistor T3, the fourth transistor T4, and the seventh transistor T7 can be NMOS, and the remaining transistors can be PMOS. Only one transistor of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be NMOS, and the remaining transistors can be PMOS.

[0069] The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7, the storage capacitor Cst, and the boost capacitor Cbt can be electrically connected to a signal line.

[0070] The signal lines can include a first scan line SL1, a second scan line SL2, a previous scan line SLp, an emission control line 133, a next scan line SLn, and a data line 171, the first scan line SL1 can transmit a first scan signal Sn, the second scan line SL2 can transmit a second scan signal Sn', the previous scan line SLp can transmit a previous scan signal Sn-1, the emission control line 133 can transmit an emission control signal En, the next scan line SLn can transmit a next scan signal Sn+1, and the data line 171 intersecting or crossing the first scan line SL1 can transmit a data signal Dm.

[0071] The driving voltage line 175 can transmit a driving voltage (or a first power voltage) ELVDD to the first transistor T1, and the first initialization voltage line 145 and the second initialization voltage line 165 can transmit an initialization voltage Vint.

[0072] The first transistor T1 can be a driving transistor T1. A first gate electrode (or a first control electrode) of the first transistor T1 can be electrically connected to the storage capacitor Cst, a first electrode of the driving transistor T1 can be electrically connected to the driving voltage line 175 through the fifth transistor T5, and a second electrode of the first transistor T1 can be electrically connected to a pixel electrode (or a first electrode) of the light emitting diode LED through the sixth transistor T6. One of the first electrode and the second electrode of the first transistor T1 can be a source electrode, and the other of the first electrode and the second electrode of the first transistor T1 can be a drain electrode. The first transistor T1 can receive the data signal Dm according to a switching operation of the second transistor T2, and transmit a driving current I d to the light emitting diode LED. The light emitting diode LED can emit light having a predetermined brightness by using the driving current I d .

[0073] The second transistor T2 can be a switching transistor. A second gate electrode (or a second control electrode) of the second transistor T2 can be electrically connected to the first scan line SL1, a first electrode of the second transistor T2 can be electrically connected to the data line 171, and a second electrode of the second transistor T2 can be electrically connected to the first electrode of the first transistor T1 and simultaneously electrically connected to the driving voltage line 175 through the fifth transistor T5. One of the first electrode and the second electrode of the second transistor T2 can be a source electrode, and the other of the first electrode and the second electrode of the second transistor T2 can be a drain electrode. The second transistor T2 can be turned on according to the first scan signal Sn transmitted through the first scan line SL1, and can perform a switching operation of transmitting the data signal Dm transmitted through the data line 171 to the first electrode of the first transistor T1.

[0074] The third transistor T3 can be a compensation transistor that can compensate for a threshold voltage of the first transistor T1. A third gate electrode (or a compensation control electrode) of the third transistor T3 can be electrically connected to the second scan line SL2. A first electrode of the third transistor T3 can be electrically connected to the first electrode CE1 of the storage capacitor Cst and the first gate electrode of the first transistor T1 through the node connection line 166. The first electrode of the third transistor T3 can be electrically connected to a second electrode of the fourth transistor T4. A second electrode of the third transistor T3 can be electrically connected to the second electrode of the first transistor T1 and, at the same time, to the pixel electrode of the light emitting diode LED through the sixth transistor T6. One of the first and second electrodes of the third transistor T3 can be a source electrode, and the other of the first and second electrodes of the third transistor T3 can be a drain electrode.

[0075] The third transistor T3 is turned on according to the second scan signal Sn' transmitted through the second scan line SL2 and diode-connects the first transistor T1 by electrically connecting the first gate electrode of the first transistor T1 to the second electrode of the first transistor T1.

[0076] The fourth transistor T4 can be a first initialization transistor that can initialize the first gate electrode of the first transistor T1. A fourth gate electrode (or a fourth control electrode) of the fourth transistor T4 can be electrically connected to the previous scan line SLp. A first electrode of the fourth transistor T4 can be electrically connected to the first initialization voltage line 145. A second electrode of the fourth transistor T4 can be electrically connected to the first electrode CE1 of the storage capacitor Cst, the first electrode of the third transistor T3, and the first gate electrode of the first transistor T1. One of the first and second electrodes of the fourth transistor T4 can be a source electrode, and the other of the first and second electrodes of the fourth transistor T4 can be a drain electrode. The fourth transistor T4 can be turned on according to the previous scan signal Sn-1 and can perform an initialization operation of initializing a voltage of the first gate electrode of the first transistor T1 by transmitting the initialization voltage Vint to the first gate electrode of the first transistor T1.

[0077] The fifth transistor T5 can be an operation control transistor. A fifth gate electrode (or a fifth control electrode) of the fifth transistor T5 can be electrically connected to the emission control line 133, a first electrode of the fifth transistor T5 can be electrically connected to the driving voltage line 175, and a second electrode of the fifth transistor T5 can be electrically connected to the first electrode of the first transistor T1 and the second electrode of the second transistor T2. One of the first and second electrodes of the fifth transistor T5 can be a source electrode, and the other of the first and second electrodes of the fifth transistor T5 can be a drain electrode.

[0078] The sixth transistor T6 can be an emission control transistor. A sixth gate electrode (or a sixth control electrode) of the sixth transistor T6 can be electrically connected to the emission control line 133, a first electrode of the sixth transistor T6 is connected to the second electrode of the first transistor T1 and the second electrode of the third transistor T3, and a second electrode of the sixth transistor T6 can be electrically connected to the second electrode of the seventh transistor T7 and the pixel electrode of the light emitting diode LED. One of the first electrode and the second electrode of the sixth transistor T6 can be a source electrode, and the other of the first electrode and the second electrode of the sixth transistor T6 can be a drain electrode.

[0079] The fifth transistor T5 and the sixth transistor T6 can be simultaneously turned on according to the emission control signal En transmitted through the emission control line 133, and can allow the driving voltage ELVDD to be transmitted to the light emitting diode LED, and thus allow the driving current I d to flow through the light emitting diode LED.

[0080] The seventh transistor T7 can be a second initialization transistor that can initialize the pixel electrode of the light emitting diode LED. A seventh gate electrode (or a seventh control electrode) of the seventh transistor T7 can be electrically connected to the next scan line SLn. A first electrode of the seventh transistor T7 can be electrically connected to the second initialization voltage line 165. A second electrode of the seventh transistor T7 can be electrically connected to the second electrode of the sixth transistor T6 and the pixel electrode of the light emitting diode LED. The seventh transistor T7 can be turned on according to the next scan signal Sn+1 transmitted through the next scan line SLn to initialize the pixel electrode of the light emitting diode LED. Although it is shown in FIG. 1 that the seventh transistor T7 can be electrically connected to the next scan line SLn, the seventh transistor T7 can be electrically connected to the emission control line 133 and driven according to the emission control signal En. Figure 2

[0081] The storage capacitor Cst can include a first electrode CE1 and a second electrode CE2. The first electrode CE1 of the storage capacitor Cst can be electrically connected to the first gate electrode of the first transistor T1, and the second electrode CE2 of the storage capacitor Cst can be electrically connected to the driving voltage line 175. The storage capacitor Cst can store a charge corresponding to a difference between the voltage of the first gate electrode of the first transistor T1 and the driving voltage ELVDD.

[0082] ​The boost capacitor Cbt can include a third electrode CE3 and a fourth electrode CE4. The third electrode CE3 can be electrically connected to the second gate electrode of the second transistor T2 and the first scan line SL1, and the fourth electrode CE4 can be electrically connected to the first electrode of the third transistor T3 and the node connection line 166. In a case where the first scan signal Sn supplied to the first scan line SL1 is cut off, the boost capacitor Cbt can raise the voltage of the first node N1. In a case where the voltage of the first node N1 is raised, black gray scale can be clearly expressed.

[0083] The first node N1 can include a portion or region electrically connected to the first gate electrode of the first transistor T1, the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the fourth electrode CE4 of the boost capacitor Cbt.

[0084] As an embodiment, Figure 2 It is described that the third transistor T3 and the fourth transistor T4 are NMOS, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are PMOS. The first transistor T1 directly affecting the brightness of the display device can include a semiconductor layer including polysilicon having high reliability. Thereby, a display device of high resolution can be implemented.

[0085] For example, since the oxide-based semiconductor can have high carrier mobility and low leakage current, the voltage drop can not be large even if the driving time is long. For example, even during low-frequency driving, the image color change according to the voltage drop can not be large, and thus the transistor including the oxide-based semiconductor can be driven at low frequency. Since the oxide-based semiconductor can have the advantage of small leakage current, the third transistor T3 and the fourth transistor T4 each electrically connected to the first gate electrode G1 of the first transistor T1 can include the oxide-based semiconductor to prevent the leakage current that can flow to the first gate electrode G1 and at the same time reduce power consumption. In an embodiment, each of the third transistor T3, the fourth transistor T4, and the seventh transistor T7 can be an oxide transistor including the oxide-based semiconductor.

[0086] Figure 3 is a plan view of a pixel circuit PC according to an embodiment or disposed in an Nth row of a display device.

[0087] Referring to Figure 3The pixel circuit PC can include a first scan line SL1, a second scan line SL2, a previous scan line SLp, a next scan line SLn, an emission control line 133, a first initialization voltage line 145, and a second initialization voltage line 165 each extending in a first direction (e.g., an x direction), and include a data line 171 and a drive voltage line 175 each extending in a second direction (e.g., a y direction) intersecting the first direction.

[0088] As described above with reference to Figure 2 The pixel circuit PC can include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, a storage capacitor Cst, and a boost capacitor Cbt.

[0089] In an embodiment, each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be a silicon transistor including a silicon-based semiconductor. For example, each of the third transistor T3 and the fourth transistor T4 can be an oxide transistor including an oxide-based semiconductor.

[0090] The semiconductor layer A1 of the first transistor T1, the semiconductor layer A2 of the second transistor T2, the semiconductor layer A5 of the fifth transistor T5, the semiconductor layer A6 of the sixth transistor T6, and the semiconductor layer A7 of the seventh transistor T7 can be arranged or disposed on the same layer, can include the same or similar material, and can be electrically connected to each other to be integral with each other. The semiconductor layer A1 of the first transistor T1, the semiconductor layer A2 of the second transistor T2, the semiconductor layer A5 of the fifth transistor T5, the semiconductor layer A6 of the sixth transistor T6, and the semiconductor layer A7 of the seventh transistor T7 can include, for example, polysilicon.

[0091] Each of the semiconductor layer A1 of the first transistor T1, the semiconductor layer A2 of the second transistor T2, the semiconductor layer A5 of the fifth transistor T5, the semiconductor layer A6 of the sixth transistor T6, and the semiconductor layer A7 of the seventh transistor T7 can include a channel region, a first region, and a second region, and the first region and the second region are at opposite sides of the channel region, respectively. The first region and the second region can include an impurity region, and include an N-type impurity or a P-type impurity. One of the first region and the second region can be a source region, and the other of the first region and the second region can be a drain region. As described above with reference to Figure 1 The first region can correspond to a first electrode (a source region or a drain region) of the relevant transistor, and the second region can correspond to a second electrode (a drain region or a source region) of the relevant transistor, as described above with reference to

[0092] The semiconductor layer A3 of the third transistor T3 and the semiconductor layer A4 of the fourth transistor T4 can be arranged or disposed on the same layer, can include the same or similar material, and can be electrically connected to each other to be integral with each other. The semiconductor layer A3 of the third transistor T3 and the semiconductor layer A4 of the fourth transistor T4 can include a zinc oxide-based material, for example, zinc oxide, indium zinc oxide, and gallium indium zinc oxide. In an embodiment, the semiconductor layer A3 of the third transistor T3 and the semiconductor layer A4 of the fourth transistor T4 can include an In-Ga-Zn-O (IGZO), In-Sn-Zn-O (ITZO), or In-Ga-Sn-Zn-O (IGTZO) semiconductor including a metal such as at least one of indium (In), gallium (Ga), and tin (Sn) in ZnO.

[0093] Each of the semiconductor layer A3 of the third transistor T3 and the semiconductor layer A4 of the fourth transistor T4 can include a channel region, a first region, and a second region, and the first region and the second region are at opposite sides of the channel region, respectively. Each of the first region and the second region can include a conductive region, and can be formed by adjusting a carrier concentration of an oxide semiconductor and making a source region and a drain region conductive. For example, the conductive region can be formed by increasing the carrier concentration by performing a plasma treatment that can use a hydrogen (H)-based gas, a fluorine (F)-based gas, or a combination of these gases on the oxide-based semiconductor of the third transistor T3 and the fourth transistor T4.

[0094] The first region of each of the semiconductor layer A3 of the third transistor T3 and the semiconductor layer A4 of the fourth transistor T4 can correspond to the first electrode (source electrode or drain electrode) described above with reference to Figure 2 and the second region of each of the semiconductor layer A3 of the third transistor T3 and the semiconductor layer A4 of the fourth transistor T4 can correspond to the second electrode (drain electrode or source electrode).

[0095] As shown in Figure 3 The silicon-based semiconductor layer SSL including the semiconductor layer A1 of the first transistor T1, the semiconductor layer A2 of the second transistor T2, the semiconductor layer A5 of the fifth transistor T5, the semiconductor layer A6 of the sixth transistor T6, and the semiconductor layer A7 of the seventh transistor T7 can be separated (or spaced apart) from the oxide-based semiconductor layer OSL including the semiconductor layer A3 of the third transistor T3 and the semiconductor layer A4 of the fourth transistor T4.

[0096] The silicon-based semiconductor layer SSL can be bent into various shapes, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be arranged or disposed along the bent shape of the silicon-based semiconductor layer SSL.

[0097] The semiconductor layer A1 of the first transistor T1 can include a portion of the silicon-based semiconductor layer SSL, and can include a channel region, a first region B1, and a second region C1, the channel region overlaps with the first gate electrode G1 of the first transistor T1, and the first region B1 and the second region C1 are at opposite sides of the channel region, respectively. The channel region of the first transistor T1 can have a substantially curved shape. As an example, although it is shown in FIG. 1 that the channel region of the first transistor T1 can have a substantially letter S shape, in an embodiment, the channel region of the first transistor T1 can have a shape that can be curved multiple times, like an omega or a substantially letter C shape. Since the channel region of the first transistor T1 can have a substantially curved shape, a long channel length can be formed on a narrow plane, and a driving range of a gate voltage applied to the first gate electrode G1 is enlarged, and thus a gray scale of light emitted from the light emitting diode LED (see FIG. 1) can be controlled more finely, and display quality can be improved. The first gate electrode G1 of the first transistor T1 can be formed to have a solitary configuration or an island-like configuration. Figure 3 Figure 2

[0098] The semiconductor layer A2 of the second transistor T2 can include a portion of the silicon-based semiconductor layer SSL, and can include a channel region, a first region B2, and a second region C2, the channel region overlaps with the second gate electrode G2 of the second transistor T2, and the first region B2 and the second region C2 are at opposite sides of the channel region, respectively. The second gate electrode G2 of the second transistor T2 can include a portion of the first scan line SL1 extending in the first direction. The first region B2 of the second transistor T2 can be electrically connected to the data line 171 through a contact hole of the insulating layer between the semiconductor layer A2 of the second transistor T2 and the data line 171. As an example, since the intermediary metal 163 between the semiconductor layer A2 of the second transistor T2 and the data line 171 is electrically connected to the semiconductor layer A2 through the eighth contact hole CNT8, and the data line 171 is electrically connected to the intermediary metal 163 through the tenth contact hole CNT10, the semiconductor layer A2 of the second transistor T2 can be electrically connected to the data line 171 through the intermediary metal 163. In an embodiment, the semiconductor layer A2 of the second transistor T2 can be directly electrically connected to the data line 171 through a contact hole between the semiconductor layer A2 and the data line 171 without the intermediary metal. The second region C2 of the second transistor T2 can be electrically connected to the first region B1 of the first transistor T1.

[0099] The semiconductor layer A3 of the third transistor T3 can include a portion of the oxide-based semiconductor layer OSL, and can include a channel region, a first region B3, and a second region C3, the channel region overlaps with the third gate electrode G3, and the first region B3 and the second region C3 are at opposite sides of the channel region, respectively.

[0100] ​​The channel region of the third transistor T3 can overlap the second scan line SL2. The third gate electrode G3 of the third transistor T3 can include a portion of the second scan line SL2 extending in the first direction. The second scan line SL2 can include a first conductive layer 143 and a second conductive layer 153 arranged or disposed on different layers, respectively, and electrically connected to each other. The first conductive layer 143 can be arranged or disposed under the semiconductor layer A3 of the third transistor T3. The second conductive layer 153 can be arranged or disposed over the semiconductor layer A3 of the third transistor T3. The portion of the first conductive layer 143 overlapping the semiconductor layer A3 of the third transistor T3 and the portion of the second conductive layer 153 overlapping the semiconductor layer A3 of the third transistor T3 can correspond to the bottom gate electrode and the top gate electrode, respectively. For example, the third gate electrode G3 of the third transistor T3 can have a dual gate structure.

[0101] The first region B3 of the semiconductor layer A3 of the third transistor T3 can be electrically connected to the semiconductor layer A4 of the fourth transistor T4 and to the first gate electrode G1 of the first transistor T1 through a node connection line 166. As an example, the node connection line 166 can be electrically connected to the first gate electrode G1 through a fourth contact hole CNT4 and can be electrically connected to the first region B3 of the semiconductor layer A3 of the third transistor T3 through a fifth contact hole CNT5. The fourth contact hole CNT4 can pass through an insulating layer between the first gate electrode G1 and the node connection line 166, and the fifth contact hole CNT5 can pass through an insulating layer between the oxide-based semiconductor layer OSL and the node connection line 166. A second electrode CE2 of a storage capacitor Cst described below can include an opening SOP corresponding to the fourth contact hole CNT4.

[0102] The second region C3 of the semiconductor layer A3 of the third transistor T3 can be electrically connected to a first connection electrode 168. As an example, the first connection electrode 168 can be electrically connected to a portion of the silicon-based semiconductor layer SSL (e.g., the second region C1 of the semiconductor layer A1 of the first transistor T1) through a first contact hole CNT1 and to a portion of the oxide-based semiconductor layer OSL (e.g., the second region C3 of the semiconductor layer A3 of the third transistor T3) through a second contact hole CNT2. The first contact hole CNT1 can pass through an insulating layer between the silicon-based semiconductor layer SSL and the first connection electrode 168. The second contact hole CNT2 can pass through an insulating layer between the oxide-based semiconductor layer OSL and the first connection electrode 168.

[0103] The first region B3 and the second region C3 of the semiconductor layer A3 of the third transistor T3 can be made conductive by using a gas including hydrogen. Accordingly, the first region B3 and the second region C3 of the semiconductor layer A3 can include hydrogen.

[0104] The semiconductor layer A4 of the fourth transistor T4 can include a portion of the oxide-based semiconductor layer OSL and include a channel region, a first region B4, and a second region C4, the channel region overlaps with the fourth gate electrode G4, and the first region B4 and the second region C4 are respectively at opposite sides of the channel region.

[0105] The channel region of the fourth transistor T4 can overlap with a previous scan line SLp, and the fourth gate electrode G4 can include a portion of the previous scan line SLp. The previous scan line SLp can include a plurality of conductive layers which are respectively arranged or disposed on different layers and electrically connected to each other. As an example, the previous scan line SLp can include a third conductive layer 141 and a fourth conductive layer 151. The third conductive layer 141 can be arranged or disposed below the semiconductor layer A4 of the fourth transistor T4. The fourth conductive layer 151 can be arranged or disposed above the semiconductor layer A4 of the fourth transistor T4. A portion of the third conductive layer 141 which overlaps with the semiconductor layer A4 of the fourth transistor T4 and a portion of the fourth conductive layer 151 which overlaps with the semiconductor layer A4 of the fourth transistor T4 can respectively correspond to a bottom gate electrode and a top gate electrode.

[0106] The first region B4 of the semiconductor layer A4 of the fourth transistor T4 can be electrically connected to the first initialization voltage line 145 through a second connection electrode 161. The second region C4 can be electrically connected to the third semiconductor layer A3 of the third transistor T3. The second connection electrode 161 can be electrically connected to the first initialization voltage line 145 through a third contact hole CNT3 and electrically connected to the first region B4 of the fourth transistor T4 through a ninth contact hole CNT9. The third contact hole CNT3 can be formed in an insulating layer between the first initialization voltage line 145 and the second connection electrode 161. The ninth contact hole CNT9 can be formed in an insulating layer between the oxide-based semiconductor layer OSL and the second connection electrode 161.

[0107] The first region B4 and the second region C4 of the semiconductor layer A4 of the fourth transistor T4 can be electrically conductive by using a gas including hydrogen. Accordingly, the first region B4 and the second region C4 can include hydrogen. Alternatively, the first region B4 and the second region C4 of the fourth transistor T4 can include fluorine or both hydrogen and fluorine.

[0108] The semiconductor layer A5 of the fifth transistor T5 can include a portion of the silicon-based semiconductor layer SSL and include a channel region, a first region B5, and a second region C5, the channel region overlaps with the fifth gate electrode G5 of the fifth transistor T5, and the first region B5 and the second region C5 are respectively at opposite sides of the channel region.

[0109] The fifth gate electrode G5 of the fifth transistor T5 can include a portion of the emission control line 133 extending in the first direction. The first region B5 of the fifth transistor T5 can be electrically connected to the driving voltage line 175. The second region C5 can be electrically connected to the semiconductor layer A1 of the first transistor T1.

[0110] The semiconductor layer A6 of the sixth transistor T6 can include a portion of the silicon-based semiconductor layer SSL and include a channel region overlapping the sixth gate electrode G6 of the sixth transistor T6, and a first region B6 and a second region C6 at opposite sides of the channel region, respectively.

[0111] The sixth gate electrode G6 of the sixth transistor T6 can include a portion of the emission control line 133. The first region B6 of the sixth transistor T6 can be electrically connected to the semiconductor layer A1 of the first transistor T1, and the second region C2 can be electrically connected to the third connection electrode 167. The third connection electrode 167 can be electrically connected to the fourth connection electrode 177 disposed or provided thereon. The third connection electrode 167 and the fourth connection electrode 177 can be disposed or provided between the sixth transistor T6 and the pixel electrode of the light emitting diode LED to electrically connect the sixth transistor T6 to the pixel electrode.

[0112] The semiconductor layer A7 of the seventh transistor T7 can include a portion of the silicon-based semiconductor layer SSL and include a channel region overlapping the seventh gate electrode G7, and a first region B7 and a second region C7 at opposite sides of the channel region, respectively.

[0113] The channel region of the seventh transistor T7 can overlap the next scan line SLn. The seventh gate electrode G7 can include a portion of the next scan line SLn extending in the first direction.

[0114] The second region C7 of the seventh transistor T7 can be electrically connected to the semiconductor layer A6 of the sixth transistor T6, and the first region B7 can be electrically connected to the second initialization voltage line 165. In an embodiment, it is shown in Figure 3 that the second initialization voltage line 165 can extend in the first direction and can include branches extending in the second direction, and the branches of the second initialization voltage line 165 can be electrically connected to the first region B7 of the seventh transistor T7 through the sixth contact hole CNT6. In an embodiment, the second initialization voltage line 165 can not include branches.

[0115] The storage capacitor Cst may include a first electrode CE1 and a second electrode CE2. The first electrode CE1 and the second electrode CE2 may overlap with the first transistor T1. As an example, the first electrode CE1 and the second electrode CE2 may overlap with the semiconductor layer A1 or the channel region of the first transistor T1. In an embodiment, the first gate electrode G1 of the first transistor T1 may include the first electrode CE1.

[0116] The second electrode CE2 of the storage capacitor Cst may include a portion of the lateral wiring HL extending in the first direction, and the drive voltage line 175 may be electrically connected to the second electrode CE2 and / or the lateral wiring HL through the seventh contact hole CNT7. The drive voltage line 175 may directly contact the second electrode CE2 and / or the lateral wiring HL through the seventh contact hole CNT7, or may be electrically connected to the second electrode CE2 and / or the lateral wiring HL through the connection metal below the drive voltage line 175.

[0117] The boost capacitor Cbt may include a third electrode CE3 and a fourth electrode CE4. The third electrode CE3 may include a portion of the first scan line SL1. In other words, a portion of the first scan line SL1 may include the third electrode CE3. The third electrode CE3 may be integral with the second gate electrode G2. The fourth electrode CE4 of the boost capacitor Cbt overlaps with the third electrode CE3 and may include an oxide-based semiconductor. As an example, a portion of the oxide-based semiconductor layer OSL may include the fourth electrode CE4 of the boost capacitor Cbt.

[0118] In an embodiment, the display device may have wherein Figure 3 The pixel circuits PC shown are arranged or configured repeatedly in both the row and column directions. Alternatively, the display device may have a flip structure in which... Figure 3 Two adjacent pixel circuits in the image are horizontally symmetrical with respect to a virtual axis arranged or positioned between the two pixel circuits in a second direction (e.g., the y-direction).

[0119] Figure 4 This is a schematic cross-sectional view of a display device according to an embodiment. Specifically, Figure 4 It is along Figure 3 A schematic cross-sectional view of the pixel circuit PC and the light-emitting diodes (LEDs) arranged or disposed on the pixel circuit PC, taken by line A-A'.

[0120] Reference Figure 4 The pixel circuit PC may include a reference. Figure 3The structures described and can be arranged or disposed over a substrate 100. The substrate 100 can include glass or a polymer resin. The polymer resin can include polyether sulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), cellulose triacetate (TAC), and cellulose acetate propionate (CAP).

[0121] The buffer layer 111 can prevent impurities from penetrating into a semiconductor layer (e.g., a silicon-based semiconductor layer SSL) of the pixel circuit PC. The buffer layer 111 can include an inorganic insulating material such as silicon oxide, silicon oxynitride, and silicon nitride, and can include a single layer or multiple layers including the above-described materials.

[0122] The silicon-based semiconductor layer SSL can be arranged or disposed on the buffer layer 111. In this regard, Figure 4 A semiconductor layer A1 of the first transistor T1, which can be a part or a region of the silicon-based semiconductor layer SSL, is illustrated. The semiconductor layer A1 of the first transistor T1 can include a channel region D1 overlapping with the first gate electrode G1 and a plurality of impurity regions respectively at opposite sides of the channel region D1.

[0123] The first insulating layer 112 can be arranged or disposed on the silicon-based semiconductor layer SSL. The first insulating layer 112 can correspond to a gate insulating layer that can insulate a semiconductor layer arranged or disposed on the silicon-based semiconductor layer SSL from a relevant gate electrode overlapping with the relevant semiconductor layer. A portion of the first insulating layer 112 can correspond to a gate insulating layer that can electrically insulate the semiconductor layer A1 of the first transistor T1 from the first gate electrode G1. Similarly, the first insulating layer 112 can be arranged or disposed between the semiconductor layers A2, A5, A6, and A7 (see Figure 3 ) arranged or disposed along the silicon-based semiconductor layer SSL and a plurality of gate electrodes (e.g., Figure 3 the second gate electrode G2, the fifth gate electrode G5, the sixth gate electrode G6, and the seventh gate electrode G7) respectively corresponding to the plurality of relevant semiconductor layers. The first insulating layer 112 can include an inorganic insulating material such as silicon oxide, silicon oxynitride, and silicon nitride, and can include a single layer or multiple layers including the above-described materials.

[0124] The first gate electrode G1 and the other gate electrodes (e.g., the second gate electrode G2 (see Figure 3 ), the fifth gate electrode G5 (see Figure 3 ), the sixth gate electrode G6 (see Figure 3 ), and the seventh gate electrode G7 (see Figure 3)) can include a low-resistance conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and include a single-layer structure or a multi-layer structure including the above-described material.

[0125] The first electrode CE1 of the storage capacitor Cst can be arranged or disposed on the first insulating layer 112, and the second electrode CE2 can be arranged or disposed on the second insulating layer 113 on the first insulating layer 112. In an embodiment, in a case where the storage capacitor Cst overlaps with the first transistor T1, the first electrode CE1 of the storage capacitor Cst can include a portion of the first gate electrode G1, and the second electrode CE2 can include an opening SOP for electrically connecting between the node connection line 166 and the first gate electrode G1. The second insulating layer 113 can include an inorganic insulating material such as silicon oxide, silicon oxynitride, and silicon nitride, and can include a single layer or a multi-layer including the above-described material.

[0126] The first electrode CE1 and / or the second electrode CE2 can include a low-resistance conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and include a single-layer structure or a multi-layer structure including the above-described material.

[0127] The third insulating layer 114 can be arranged or disposed on the storage capacitor Cst. The third insulating layer 114 can include an inorganic insulating material such as silicon oxide, silicon oxynitride, and silicon nitride, and include a single layer or a multi-layer including the above-described material.

[0128] The oxide-based semiconductor layer OSL can be arranged or disposed on the third insulating layer 114. Regarding this, Figure 4 The semiconductor layer A4 of the fourth transistor T4 is shown, which can be a portion or a region of the oxide-based semiconductor layer OSL. The semiconductor layer A4 of the fourth transistor T4 can include a channel region D4, a first region B4, and a second region C4, which are respectively at opposite sides of the channel region D4.

[0129] The fourth gate electrode G4 of the fourth transistor T4 can include a bottom gate electrode G4a and a top gate electrode G4b which are respectively disposed under or below and on the channel region D4. Figure 4 The bottom gate electrode G4a of the fourth transistor T4 can include a portion of the third conductive layer 141 described with reference to Figure 3 The top gate electrode G4b of the fourth transistor T4 can include a portion of the fourth conductive layer 151 described with reference to Figure 3 The top gate electrode G4b of the fourth transistor T4 can include a portion of the fourth conductive layer 151 described with reference to

[0130] The bottom gate electrode G4a can be below the channel region D4 of the fourth transistor T4 and can overlap the channel region D4 of the fourth transistor T4 with the third insulating layer 114 between the bottom gate electrode G4a and the channel region D4 of the fourth transistor T4. The top gate electrode G4b can be above the channel region D4 of the fourth transistor T4 with the fourth insulating layer 115 between the top gate electrode G4b and the channel region D4 of the fourth transistor T4. The fourth insulating layer 115 can not be formed or disposed entirely over the substrate 100, but rather is locally patterned. The fourth insulating layer 115 can include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride, and can include a single layer or multiple layers containing the above-described materials.

[0131] Although not shown, the structure of the semiconductor layer A3 and the third gate electrode G3 of the third transistor T3 described above can be the same as the structure of the semiconductor layer A4 and the fourth gate electrode G4 of the fourth transistor T4 shown in FIG. 6. Figure 3 Figure 4 The structure of the semiconductor layer A3 and the third gate electrode G3 of the third transistor T3 described above can be the same as the structure of the semiconductor layer A4 and the fourth gate electrode G4 of the fourth transistor T4 shown in FIG. 6.

[0132] The fifth insulating layer 116 can be disposed or arranged over a transistor including an oxide-based semiconductor (e.g., the fourth transistor T4 and the third transistor T3 (see FIG. 6). Figure 3 The fifth insulating layer 116 can include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride, and can include a single layer or multiple layers containing the above-described materials.

[0133] The third electrode CE3 of the boost capacitor Cbt can be on the first insulating layer 112, and the fourth electrode CE4 can be on the third insulating layer 114. The third electrode CE3 and / or the fourth electrode CE4 can include a low-resistance conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and can include a single-layer structure or a multi-layer structure containing the above-described materials.

[0134] The node connection line 166 can be on the fifth insulating layer 116. The node connection line 166 can be electrically connected to the first gate electrode G1 and the oxide-based semiconductor layer OSL through the fourth contact hole CNT4 and the fifth contact hole CNT5. The node connection line 166 can include aluminum (Al), copper (Cu), and / or titanium (Ti), and can include a single-layer structure or a multi-layer structure containing the above-described materials. As an example, the node connection line 166 can have a three-layer structure of a Ti layer / Al layer / Ti layer.

[0135] The sixth insulating layer 118 can be on the node connection line 166. The sixth insulating layer 118 can include inorganic insulating materials and / or organic insulating materials. The organic insulating materials can include benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO).

[0136] ​The data line 171 and the driving voltage line 175 can be disposed or arranged on the sixth insulating layer 118. The data line 171 and / or the driving voltage line 175 can include aluminum (Al), copper (Cu), and / or titanium (Ti), and include a single layer or a multi-layer structure including the above-described materials. As an example, the data line 171 and / or the driving voltage line 175 can have a three-layer structure of a Ti layer / Al layer / Ti layer.

[0137] Although the data line 171 and the driving voltage line 175 are shown as being disposed or arranged on the sixth insulating layer 118 in Figure 4 , in an embodiment, the data line 171 and / or the driving voltage line 175 can be disposed or arranged on the fifth insulating layer 116, or can include an auxiliary line disposed or arranged on the fifth insulating layer 116 and electrically connected to the data line 171 and / or the driving voltage line 175.

[0138] The seventh insulating layer 119 can be disposed or arranged on the pixel circuit PC. The seventh insulating layer 119 can include an organic insulating layer such as benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO).

[0139] The light emitting diode LED can include a pixel electrode 310, an emission layer 320, and an opposite electrode 330.

[0140] An edge of the pixel electrode 310 can be covered or overlapped with the upper insulating layer 120. The emission layer 320 can overlap the pixel electrode 310 through an opening formed in the upper insulating layer 120.

[0141] The pixel electrode 310 can include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. The pixel electrode 310 can include the reflective layer and a transparent conductive layer disposed on and / or under or below the reflective layer. The transparent conductive layer can include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum-doped zinc oxide (AZO). In an embodiment, the pixel electrode 310 can have a three-layer structure of an ITO layer / Ag layer / ITO layer.

[0142] In an embodiment, the emission layer 320 can include an organic material. The emission layer 320 can include a material emitting light having a predetermined color (e.g., red, green, or blue), and include a fluorescent material or a phosphorescent material.

[0143] The counter electrode 330 can include a metal having a relatively small work function. For example, the counter electrode 330 can include a thin layer including silver (Ag), magnesium (Mg), aluminum (Al), nickel (Ni), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof. In an embodiment, the counter electrode 330 can include a transmissive electrode including silver (Ag) and magnesium (Mg).

[0144] Although it is described in Figure 4 that the light emitting diode LED can include an organic light emitting diode including an organic material, in an embodiment, the light emitting diode LED can include an inorganic light emitting diode including an inorganic material. The inorganic light emitting diode can include a PN junction diode including an inorganic material semiconductor base material. In a case where a voltage can be applied to the PN junction diode in a forward direction, holes and electrons are injected into the PN junction diode, and by converting energy generated by recombination of the holes and the electrons into light energy, light having a preset color can be emitted. The inorganic light emitting diode can have a width of about several micrometers to about several hundred micrometers. In an embodiment, the inorganic light emitting diode can be represented by a micro light emitting diode.

[0145] Figure 5 is a plan view of a portion or region of a pixel circuit PC of a display device according to an embodiment, Figure 6 is a schematic cross-section taken along the line B-B' of Figure 5 , and Figure 7 is a schematic cross-section taken along the line C-C' of Figure 5 .

[0146] Figure 5 shows a portion or region of the pixel circuit PC shown in Figure 4 , for example, an oxide-based semiconductor layer OSL and a structure surrounding the oxide-based semiconductor layer OSL, and shows that a third transistor T3 (see Figure 6 ) and a fourth transistor T4 (see Figure 7 ) can be formed or disposed along the oxide-based semiconductor layer OSL.

[0147] Referring to Figure 5 and Figure 6 , a semiconductor layer A3 of the third transistor T3 can include a channel region D3, a first region B3, and a second region C3, the first region B3 and the second region C3 being at opposite sides of the channel region D3, respectively. A third gate electrode G3 of the third transistor T3 can include a bottom gate electrode G3a and a top gate electrode G3b, the bottom gate electrode G3a being below the channel region D3 of the third transistor T3, and the top gate electrode G3b being above the channel region D3 of the third transistor T3.

[0148] The channel region D3 of the third transistor T3 may include a region overlapping with the top gate electrode G3b and / or the bottom gate electrode G3a. In an embodiment, if the third transistor T3 may include a single gate electrode, the channel region D3 may be defined as the region overlapping with said single gate electrode. In an embodiment, if the third transistor T3 may include a top gate electrode G3b and a bottom gate electrode G3a, the channel region D3 may be defined as the region overlapping with the top gate electrode G3b.

[0149] The first connection electrode 168 may be arranged or disposed above the third transistor T3. For example, the first connection electrode 168 may be arranged or disposed above the top gate electrode G3b of the third transistor T3, and the fifth insulating layer 116 may be between the first connection electrode 168 and the top gate electrode G3b.

[0150] The first connection electrode 168 can electrically connect the oxide-based semiconductor layer OSL to the silicon-based semiconductor layer SSL, which is located below the oxide-based semiconductor layer OSL. As an example, the first connection electrode 168 can electrically connect the semiconductor layer A3 of the third transistor T3 to... Figure 4 The semiconductor layer A1 of the first transistor T1 is shown. A portion of the first connection electrode 168 can be electrically connected to a conductive region (e.g., the second region C3) of the third transistor T3 through a second contact hole CNT2 defined in the fifth insulating layer 116 on the third transistor T3. Another portion of the first connection electrode 168 can be electrically connected to the second region C1 of the first transistor T1 through or extending through the first contact hole CNT1 through the first insulating layer 112, the second insulating layer 113, the third insulating layer 114, and the fifth insulating layer 116.

[0151] like Figure 5 As shown, the channel region D3 of the third transistor T3 can maintain a first distance DS1 from the first contact hole CNT1 in one direction or another direction (e.g., in the second direction). The first distance DS1 can be 2 μm or greater. For example, the first distance DS1 can be 2.0 μm ≤ DS1 ≤ 10 μm, 2.0 μm ≤ DS1 ≤ 8 μm, or 2.0 μm ≤ DS1 ≤ 7 μm. If the first distance DS1 deviates from the above lower limit, the characteristics of the semiconductor layer A3 of the third transistor T3 may deteriorate and stains may appear.

[0152] The hydrogen concentration in the conductive region of the third transistor T3 (e.g., region B3 in the first region or region C3 in the second region) can be 1.1 × 10⁻⁶. 21 atom / cm 3or more. The increase in the hydrogen concentration means that the carrier in the first region B3 or the second region C3 increases and the characteristics of the third transistor T3 improve. In the case where the hydrogen concentration of the first region B3 or the second region C3 deviates from the lower limit, it can be difficult to expect normal operation of the third transistor T3.

[0153] Referring to Figure 5 and Figure 7 The semiconductor layer A4 of the fourth transistor T4 can include a channel region D4, a first region B4, and a second region C4, the first region B4 and the second region C4 being at opposite sides of the channel region D4, respectively. The fourth gate electrode G4 of the fourth transistor T4 can include a bottom gate electrode G4a and a top gate electrode G4b, the bottom gate electrode G4a being below the channel region D4 of the fourth transistor T4, and the top gate electrode G4b being above the channel region D4 of the fourth transistor T4.

[0154] The channel region D4 of the fourth transistor T4 can include a region overlapping with the top gate electrode G4b and / or the bottom gate electrode G4a. In an embodiment, in the case where the fourth transistor T4 can include one gate electrode, the channel region D4 can be defined as a region overlapping with the one gate electrode. In an embodiment, in the case where the fourth transistor T4 can include the top gate electrode G4b and the bottom gate electrode G4a, the channel region D4 can be defined as a region overlapping with the top gate electrode G4b.

[0155] The second connection electrode 161 can be arranged or disposed over the fourth transistor T4. The second connection electrode 161 can be disposed over the fifth insulating layer 116, and the top gate electrode G4b of the fourth transistor T4 can be disposed under or below the fifth insulating layer 116. For example, the second connection electrode 161 can be arranged or disposed over the top gate electrode G4b of the fourth transistor T4, and the fifth insulating layer 116 is disposed between the second connection electrode 161 and the top gate electrode G4b.

[0156] The second connection electrode 161 can electrically connect the oxide-based semiconductor layer OSL to a line under the oxide-based semiconductor layer OSL. As an example, the second connection electrode 161 can electrically connect the semiconductor layer A4 of the fourth transistor T4 to the first initialization voltage line 145. A portion of the second connection electrode 161 can be electrically connected to a conductive region (e.g., the second region C4) of the fourth transistor T4 through a ninth contact hole CNT9 formed in the fifth insulating layer 116. Another portion of the second connection electrode 161 can be electrically connected to the first initialization voltage line 145 through a third contact hole CNT3 passing through or extending through the third insulating layer 114 and the fifth insulating layer 116.

[0157] As Figure 5As shown in FIG. 6, the channel region D4 of the fourth transistor T4 can be kept at a second distance DS2 from the third contact hole CNT3 in one direction or a direction (e.g., in the second direction). The second distance DS2 can be 2 pm or more. For example, the second distance DS2 can be 2.0 pm ≤ DS2 ≤ 10 pm, 2.0 pm ≤ DS2 ≤ 8 pm, or 2.0 pm ≤ DS2 ≤ 7 pm. In a case where the second distance DS2 deviates from the lower limit described above, the characteristics of the semiconductor layer A4 of the fourth transistor T4 can be deteriorated.

[0158] The hydrogen concentration of the conductive region (e.g., the first region B4 or the second region C4) of the fourth transistor T4 can be approximately 1.1 x 1019 atoms / cm3 or more. In a case where the above range is satisfied, the fourth transistor T4 can operate normally. 21 atom / cm 3 or more. In a case where the above range is satisfied, the fourth transistor T4 can operate normally.

[0159] Figure 8 is a graph showing the transfer curve of the third transistor according to the embodiment and the comparative example. In Figure 8 , Ids represents the drain-source current, and Vgs represents the gate-source voltage.

[0160] According to Figure 8 the comparative example, the pixel circuit corresponds to a case where the first distance DS1 described with reference to Figure 5 is formed to be less than approximately 2 pm (e.g., approximately 1.6 pm), which indicates that the current deviation between the current in the SD forward direction and the current in the DS reverse direction is large. In contrast, according to the embodiment, in a case where the first distance DS1 can be formed to be approximately 2 pm or more, as shown in Figure 8 , the current deviation between the current in the SD forward direction and the current in the DS reverse direction can be very small.

[0161] As described above, the conductive region of the oxide-based semiconductor layer OSL (see Figure 5 ) can be formed by plasma treatment, which can use a hydrogen (H)-based gas, a fluorine (F)-based gas, and / or a combination thereof. During a process (e.g., a process of forming a contact hole and an annealing process) performed after the plasma treatment, elements contained in the conductive region can be reduced, and thus the characteristics of the transistor can be deteriorated. As an example, due to dehydrogenation caused by heat applied during the annealing process, the characteristics of the third transistor T3 (see Figure 6 ) formed or provided along the oxide-based semiconductor layer OSL can be deteriorated, and a stain can occur in an image displayed by the display device, which deteriorates the display quality. In contrast, according to the embodiment, by the above-described structure, the characteristics of the third transistor T3 can be improved, and the occurrence of the stain can be minimized.

[0162] The conductive region of the third transistor T3 (e.g., Figure 6 The hydrogen concentration in the first region B3 or the second region C3 shown can be 1.1 × 10⁻⁶. 21 atom / cm 3 Or even higher. Within the aforementioned range, the characteristics of the third transistor T3 can be improved. An increase in hydrogen concentration means an increase in charge carriers within the first region B3 or the second region C3, and thus an improvement in the characteristics of the third transistor T3.

[0163] Figure 9 This is a graph showing the hydrogen concentration measured by secondary ion mass spectrometry (SIMS) for a third transistor according to the embodiments and comparative examples. Figure 4 and Figure 6 As shown, since the conductive regions of the oxide-based semiconductor layer OSL can be arranged or disposed between the third insulating layer 114 and the fifth insulating layer 116, the hydrogen concentration of the fifth insulating layer 116 and the third insulating layer 114 can also be adjusted as shown in the diagram, since a SIMS can be performed on a display device having the relevant structure. Figure 9 As shown in the measurement, the fifth insulating layer 116 and the third insulating layer 114 are disposed above and below the first region B3 and / or the second region C3 of the third transistor T3.

[0164] The comparative example shows the hydrogen concentration in the conductive region of the third transistor in a pixel circuit smaller than approximately 2 μm, as described above, and the hydrogen concentration in the conductive region (e.g., the central portion tc of the first region B3) in the thickness direction, which can be approximately 1.03 × 10⁻⁶. 21 atom / cm 3 Or even higher. In contrast, according to an embodiment, the hydrogen concentration in the conductive region (e.g., the central portion tc of the first region B3) in the thickness direction can be approximately 1.4 × 10⁻⁶. 21 atom / cm 3 Or larger, for example, approximately 1.42 × 10 21 atom / cm 3 .

[0165] Figure 10 This is a plan view of a portion of the display device according to an embodiment, and Figure 11 It is along Figure 10 A schematic cross-sectional view taken by line D-D'. Because Figure 10 The display device shown may include reference Figure 5 to Figure 9 All the features described, therefore omitting the descriptions of... Figure 10 Among the multiple structures shown, the one with Figure 5 The structure shown is the same as the description of the structure.

[0166] Reference Figure 10The preceding scan line SLp may extend in a first direction to intersect or cross with the oxide-based semiconductor layer OSL, and may include multiple layers arranged or disposed on different layers. As an example, such as... Figure 10 As shown, the previous scan line SLp may include a third conductive layer 141 and a fourth conductive layer 151. The third conductive layer 141 may be disposed below the oxide-based semiconductor layer OSL, and the fourth conductive layer 151 may be disposed above the oxide-based semiconductor layer OSL. The third conductive layer 141 and the fourth conductive layer 151 on different layers can be electrically connected to each other through the eleventh contact hole CNT11.

[0167] The eleventh contact hole CNT11 can be connected to the fourth transistor T4 (see...). Figure 7 The channel region D4 of the fourth transistor T4 is separated from the eleventh contact hole CNT11. The third distance DS3 in the first direction between the channel region D4 of the fourth transistor T4 and the eleventh contact hole CNT11 can be 2.4 μm or greater. If the third distance DS3 is less than the lower limit mentioned above, the characteristics of the fourth transistor T4 may deteriorate, and therefore the display quality may be degraded.

[0168] Reference Figure 11 The third conductive layer 141 may be disposed on or on the second insulating layer 113, and the fourth conductive layer 151 may be disposed on or above the third conductive layer 141, with the third insulating layer 114 located between the fourth conductive layer 151 and the third conductive layer 141. The third insulating layer 114 may include an eleventh contact hole CNT11 that may overlap with a portion of the third conductive layer 141, and the fourth conductive layer 151 may be electrically connected to the third conductive layer 141 through the eleventh contact hole CNT11.

[0169] The lateral surface defining the eleventh contact hole CNT11 of the third insulating layer 114 may include a sloped surface. The slope of the sloped surface (i.e., the angles (also referred to as slope angles) α1 and α2 formed between the sloped surface and the top surface of the third conductive layer 141 (or the top surface of the substrate 100) may be approximately 86° or less. By forming angles α1 and α2 of approximately 86° or less, the thickness of the portion of the fourth conductive layer 151 that may be disposed or set on the sloped surface can be prevented from decreasing.

[0170] The dimensions of the eleventh contact hole CNT11 (e.g., the width w of the eleventh contact hole CNT11) can be formed to be approximately 2.2 μm or smaller. When the width w of the eleventh contact hole CNT11 meets the above conditions, the characteristics of the fourth transistor T4 can be improved.

[0171] Figure 12 This is a graph showing the transfer curve of the fourth transistor according to the embodiment and comparative example.

[0172] Figure 12 The comparative example of FIG. 10 shows the case where the first distance DS1 is about 2.2 pm and the width w of the eleventh contact hole CNT11 is about 2.6 pm. Figure 10 The third distance DS3 described with reference to Figure 11 The width w of the eleventh contact hole CNT11 described with reference to Figure 12 The comparative example of FIG. 10 makes it difficult to predict the transfer curve of the fourth transistor T4. In contrast, according to the embodiments, for example, in the case where the third distance DS3 is about 2.4 pm and the width w of the eleventh contact hole CNT11 is about 2.2 pm, this indicates that the operation of the fourth transistor T4 is excellent.

[0173] The structure described with reference to Figure 10 and Figure 11 is applicable between the second scan line SL2 and the third transistor T3 (see Figure 3 ). Figure 13 is a plan view of a portion or region of a display device according to an embodiment. As shown in Figure 13 , the first conductive layer 143 and the second conductive layer 153 of the second scan line SL2 can be electrically connected to each other by a twelfth contact hole CNT12.

[0174] The twelfth contact hole CNT12 can have the same structure and width as the structure and width of the eleventh contact hole CNT11 described with reference to Figure 13 and Figure 10 and Figure 11 As described above, the distance in the first direction between the twelfth contact hole CNT12 and the channel region D3 of the third transistor T3 can be 2.4 pm or more. For example, the inclination angle of the lateral surface of the insulating layer arranged or provided between the first conductive layer 143 and the second conductive layer 153 and defining the twelfth contact hole CNT12 can also have the inclination angles al and a2 of the lateral surface of the third insulating layer 114 described with reference to Figure 11 .

[0175] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as being applicable to other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the attached drawings, it will be evident for those skilled in the art that various changes can be made in form and details without departing from the spirit and scope of the application as defined by the following claims.

Claims

1. A display device, comprising: The first silicon transistor includes: The first semiconductor layer includes a silicon-based semiconductor; and The first gate electrode overlaps with the first semiconductor layer; A first oxide transistor, comprising: A second semiconductor layer, spaced apart from the first semiconductor layer and comprising an oxide-based semiconductor; and Second gate electrode; An upper insulating layer is disposed on the first semiconductor layer and the second semiconductor layer, the upper insulating layer including a first contact hole and a second contact hole; and A first connecting electrode is disposed on the upper insulating layer, electrically connected to the first semiconductor layer through the first contact hole, and electrically connected to the second semiconductor layer through the second contact hole, wherein... The second semiconductor layer includes a channel region, a source region, and a drain region, wherein the source region and the drain region are disposed on opposite sides of the channel region, and The first distance between the channel region of the second semiconductor layer and the first contact hole is 2 μm or greater.

2. The display device according to claim 1, wherein, The hydrogen concentration in the source or drain region of the second semiconductor layer is 1.1 × 10⁻⁶. 21 atom / cm 3 Or larger.

3. The display device according to claim 1 further includes an insulating layer disposed between the first semiconductor layer and the second semiconductor layer.

4. The display device according to claim 1, wherein, The first semiconductor layer includes a channel region, a source region, and a drain region. The source region and the drain region of the first semiconductor layer are disposed on opposite sides of the channel region of the first semiconductor layer. The channel region of the first semiconductor layer includes a curved shape.

5. The display device according to claim 1, further comprising a node connection line, the node connection line electrically connecting the first gate electrode of the first silicon transistor to the first oxide transistor.

6. The display device according to claim 1 further includes a second oxide transistor, the second oxide transistor including a third semiconductor layer and a third gate electrode, the third semiconductor layer including an oxide-based semiconductor.

7. The display device according to claim 6, wherein, The third semiconductor layer of the second oxide transistor and the second semiconductor layer of the first oxide transistor are integral with each other.

8. The display device according to claim 6, further comprising: Initialize the voltage lines; The first signal line extends in the same direction as the initialization voltage line; as well as A second connection electrode is disposed on the third semiconductor layer of the second oxide transistor and the initialization voltage line, and the second connection electrode electrically connects the initialization voltage line to the third semiconductor layer.

9. The display device according to claim 8, wherein, The upper insulating layer also includes a third contact hole. The second connection electrode is electrically connected to the initialization voltage line through the third contact hole, and The second distance between the channel region of the third semiconductor layer and the third contact hole is 2 μm or greater.

10. The display device according to claim 8, wherein, The first signal line includes: A first conductive layer overlaps with the third semiconductor layer; and A second conductive layer is disposed below the third semiconductor layer. The first conductive layer is electrically connected to the second conductive layer through a contact hole in an insulating layer disposed between the first conductive layer and the second conductive layer.

11. The display device according to claim 10, wherein, The width of the contact hole in the insulating layer is 2.2 μm or less.

12. The display device according to claim 10, wherein, The third distance between the channel region of the third semiconductor layer and the contact hole of the insulating layer is 2.4 μm or greater.

13. The display device according to claim 10, wherein, The insulating layer includes a lateral surface forming the contact hole, and The tilt angle of the lateral surface is 86° or less.

14. The display device according to claim 1, further comprising: A first capacitor is electrically connected to the first silicon transistor; as well as The second capacitor is electrically connected to the first oxide transistor.

15. The display device according to claim 14, wherein, The electrodes of the second capacitor and the second semiconductor layer are made of the same material.

16. A display device, comprising: A silicon-based semiconductor layer, including a first semiconductor layer of a first silicon transistor; An oxide-based semiconductor layer, spaced apart from the silicon-based semiconductor layer, the oxide-based semiconductor layer comprising a second semiconductor layer of a first oxide transistor; An upper insulating layer is disposed on the silicon-based semiconductor layer and the oxide-based semiconductor layer, the upper insulating layer including a first contact hole and a second contact hole; as well as A first connecting electrode is disposed on the upper insulating layer, electrically connected to the first semiconductor layer through the first contact hole, and electrically connected to the second semiconductor layer through the second contact hole, wherein... The oxide-based semiconductor layer includes the channel region of the first oxide transistor, and The first distance between the channel area and the first contact hole is 2 μm or greater.

17. The display device according to claim 16, wherein, The oxide-based semiconductor layer further includes a third semiconductor layer for the second oxide transistor, and The second semiconductor layer and the third semiconductor layer are integral to each other.

18. The display device according to claim 17, wherein, The second semiconductor layer includes: The trench area; and The source and drain regions are respectively located on opposite sides of the channel region. The third semiconductor layer includes: Channel area; and The source and drain regions are respectively located on opposite sides of the channel region of the third semiconductor layer, and Wherein, the hydrogen concentration in the source region or the drain region of each of the second semiconductor layer and the third semiconductor layer is 1.1 × 10⁻⁶. 21 atom / cm 3 Or larger.

19. The display device according to claim 17, further comprising: Initialize the voltage line to provide an initialization voltage to the second oxide transistor; as well as The second connection electrode is disposed on the third semiconductor layer of the second oxide transistor and the initialization voltage line, and the initialization voltage line is electrically connected to the third semiconductor layer.

20. The display device according to claim 19, wherein, The upper insulating layer also includes a third contact hole. The second connection electrode is electrically connected to the initialization voltage line through the third contact hole, and The second distance between the channel region of the third semiconductor layer and the third contact hole is 2 μm or greater.

21. The display device according to claim 19, further comprising: The first signal line overlaps with the second semiconductor layer of the first oxide transistor; as well as The second signal line overlaps with the third semiconductor layer of the second oxide transistor. Wherein, the first signal line or the second signal line includes: A first conductive layer overlaps with the oxide-based semiconductor layer; and A second conductive layer is disposed beneath the oxide-based semiconductor layer. The first conductive layer is electrically connected to the second conductive layer through a contact hole in an insulating layer disposed between the first conductive layer and the second conductive layer.

22. The display device according to claim 21, wherein, The width of the contact hole in the insulating layer is 2.2 μm or less.

23. The display device according to claim 21, wherein, The third distance between the channel region of the third semiconductor layer and the contact hole of the insulating layer is 2.4 μm or greater.

24. The display device according to claim 21, wherein, The insulating layer includes a lateral surface forming the contact hole, and The tilt angle of the lateral surface is 86° or less.

25. The display device according to claim 16, further comprising an insulating layer disposed between the silicon-based semiconductor layer and the oxide-based semiconductor layer.

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