Light emitting device and light emitting method

Abstract

The present disclosure provides a light emitting device and a light emitting method. The light emitting device includes a plurality of sub-pixels. Each sub-pixel displays a grayscale during a frame. The frame includes N sub-frames. Each sub-frame includes a scanning period and an emission period. Each sub-pixel includes a pixel circuit and a light emitter. The pixel circuit includes a current control circuit and a pulse width modulation (PWM) circuit. The current control circuit receives an analog signal and outputs a driving current according to the analog signal. The PWM circuit receives M digital signals and M reference pulse signals, and outputs PWM pulses according to the M digital signals and the M reference pulse signals. The light emitter receives a driving current and a PWM pulse during the emission period of each of the N sub-frames. The light emitting device and the light emitting method disclosed in the present disclosure can provide a good display effect.

Description

Technical Field

[0001] The present disclosure relates to a light emitting device; in particular, the present disclosure relates to a light emitting device and a light emitting method. Background Art

[0002] Current control is often used to generate various currents for pixels to display multiple levels of grayscale. However, as the requirements for grayscale levels increase, the scale of the driving circuit also increases. Summary of the invention

[0003] The present disclosure relates to a light emitting device and a light emitting method capable of providing good display effects.

[0004] In the present disclosure, the light emitting device may include a plurality of sub-pixels. Each of the plurality of sub-pixels is configured to display grayscale during a frame. The frame may include N sub-frames. Each sub-frame may include a scanning period and an emission period. Each of the plurality of sub-pixels may include a pixel circuit and a light emitter. The pixel circuit may include a current control circuit and a pulse width modulation (PWM) circuit. The current control circuit is configured to receive an analog signal during the scanning period, and output a drive current according to the analog signal during the emission period. The PWM circuit is configured to receive M digital signals and M reference pulse signals, and output PWM pulses according to the M digital signals and the M reference pulse signals. The light emitter is configured to receive the drive current and the PWM pulse during the emission period of each of the N sub-frames. N and M are integers greater than 1.

[0005] In the present disclosure, the light emission method may include the following steps: receiving an analog signal through the current control circuit during the scanning period; outputting a driving current through the current control circuit according to the analog signal during the emission period; receiving M digital signals and M reference pulse signals through the PWM circuit; outputting PWM pulses through the PWM circuit according to the M digital signals and the M reference pulse signals; and receiving the driving current and the PWM pulses by the light emitter during the emission period of each of the N subframes. N and M are integers greater than 1.

[0006] Based on the above, according to the light emitting device and light emitting method of the present disclosure, various gray scales can be formed according to various combinations of the amount of driving current and the width of PWM pulse. In addition, as the requirements for gray scale levels increase, the scale of the driving circuit of the present disclosure can be maintained relatively small.

[0007] In order to make the above contents easier to understand, several embodiments attached with the drawings will be described in detail below. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure.

[0009] Figure 1A is a schematic block diagram of a light emitting device according to an embodiment of the present disclosure;

[0010] Figure 1B is a schematic block diagram of a sub-pixel according to an embodiment of the present disclosure;

[0011] Figure 2 is a schematic circuit diagram of a sub-pixel according to an embodiment of the present disclosure;

[0012] Figure 3 is a schematic signal timing chart according to the first embodiment of the present disclosure;

[0013] Figure 4 is a schematic signal timing chart according to the second embodiment of the present disclosure;

[0014] Figure 5A is a schematic signal timing chart according to the third embodiment of the present disclosure;

[0015] Figure 5B is a schematic signal timing chart according to the third embodiment of the present disclosure;

[0016] Figure 5C is a schematic signal timing chart according to the third embodiment of the present disclosure;

[0017] Fig. 6A is a schematic signal timing chart according to a fourth embodiment of the present disclosure;

[0018] Figure 6B is a schematic signal timing chart according to a fourth embodiment of the present disclosure;

[0019] Figure 6C is a schematic signal timing chart according to a fourth embodiment of the present disclosure;

[0020] Fig.6D is a schematic sub-pixel arrangement according to a fourth embodiment of the present disclosure;

[0021] Fig. 6E is a schematic sub-pixel arrangement according to a fourth embodiment of the present disclosure;

[0022] Fig. 6F is a schematic sub-pixel arrangement according to a fourth embodiment of the present disclosure;

[0023] Fig. 7A is a schematic sub-pixel arrangement according to a fifth embodiment of the present disclosure;

[0024] Figure 7B is a schematic sub-pixel arrangement according to a fifth embodiment of the present disclosure;

[0025] Figure 7C is a schematic sub-pixel arrangement according to a fifth embodiment of the present disclosure;

[0026] Figure 8 is a schematic signal timing chart according to a sixth embodiment of the present disclosure;

[0027] Fig. 9 is a schematic gray level chart according to a seventh embodiment of the present disclosure;

[0028] Fig.10 is a schematic grayscale chart according to an eighth embodiment of the present disclosure;

[0029] Fig.11 is a schematic flowchart of a light emission method according to an embodiment of the present disclosure.

[0030] [Explanation of Symbols]

[0031] 1 / 63: width / shortest width;

[0032] 2 / 63, 4 / 63, 8 / 63, 16 / 63: width;

[0033] 32 / 63: width / longest width;

[0034] 100: light emitting device;

[0035] 110. P_2~P_(K-1): sub-pixel;

[0036] 120: pixel circuit;

[0037] 121: current control circuit;

[0038] 122: Pulse Width Modulation (PWM) circuit;

[0039] 130: optical transmitter;

[0040] 910, 920: line;

[0041] A, B, C: mode;

[0042] A1, A2: AND gate;

[0043] C11, C21, C22: capacitors;

[0044] DT_D1, DT_D2, DT_D3~DT_DM: digital signal;

[0045] DT_A: analog signal;

[0046] F1, F2, F3: frames;

[0047] I_D: driving current;

[0048] N1: NOR gate;

[0049] P_1: sub-pixel / first sub-pixel;

[0050] P_K: sub-pixel / Kth sub-pixel;

[0051] P_PWM: pulse;

[0052] P11, P11', P11_A, P12_B, P21, P21', P21_A, P22_B, P31, P31', P31_A, P32_B, P41, P41', P51, P61, P71, P81, P91: scan cycle;

[0053] P11_B, P12, P12', P12_A, P21_B, P22, P22', P22_A, P31_B, P32, P32', P32_A, P41_B, P42, P42', P52, P62, P72, P82, P92: emission period;

[0054] PVDD, PVSS: voltage source;

[0055] RP1, RP2~RPM, RP1_A, RP1_B, RP1_D, RP2_A, RP2_B, RP2_D: reference pulse signals;

[0056] S1110, S1120, S1130, S1140, S1150: steps;

[0057] SCAN, SCAN(1), SCAN(2)~SCAN(K-1): scanning signal;

[0058] SCAN(K): scan signal / Kth scan signal;

[0059] SF1, SF2, SF3: subframe;

[0060] T11, T12, T21, T22, T23: transistors;

[0061] t_11, t_11', t_12, t_12', t_21, t_21', t_22, t_22', t_31, t_31', t_32, t_32', t_41, t_41', t_42, t_42', t_51, t_51', t_52, t_61, t_62, t_71, t_72, t_81, t_82, t_92: time. DETAILED DESCRIPTION

[0062] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like components.

[0063] Throughout the specification and claims of the present disclosure, certain terms are used to refer to specific components. It should be understood by those skilled in the art that electronic device manufacturers may use different names to refer to the same component. It is not intended herein to distinguish between components that have the same function but different names. In the following description and claims, words such as "comprise" and "include" are open-ended terms and should be interpreted as "including but not limited to ..."

[0064] The term "coupling (coupling) (or connection (connection))" used throughout the entire specification of the present application (including the attached claims) may refer to any direct or indirect connection mode. For example, if the text states that a first device is coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or certain connection modes. The terms "first (first)", "second (second)" and similar terms mentioned throughout the entire specification of the present application (including the attached claims) are only used to name discrete elements or to distinguish different embodiments or scopes. Therefore, the terms should not be regarded as limiting the upper or lower limits of the number of elements and should not be used to limit the arrangement sequence of elements. In addition, whenever possible, the same reference number is used in the drawings and embodiments to represent the same or similar parts. In different embodiments, the same reference number or the same term can be used to refer to the relevant description of the element / component / step.

[0065] The light emitting device of the present disclosure may be applicable to liquid crystal, light emitting diode, quantum dot (QD), fluorescence, phosphor, other suitable display medium or combination of the foregoing materials, but the present disclosure is not limited thereto. The light emitting diode may include, for example, an organic light emitting diode (OLED), a sub-millimeter light emitting diode (Mini LED), a micro light emitting diode (Micro LED) or a quantum dot light emitting diode (QLED) or other suitable materials. The materials may be arranged and combined arbitrarily, but the present disclosure is not limited thereto. The light emitting device of the present disclosure may include peripheral systems, such as a drive system, a control system, a light source system, a shelf system and the like, to support the light emitting device.

[0066] It should be noted that in the following embodiments, without departing from the spirit of the present disclosure, the technical features of several different embodiments may be replaced, recombined and mixed to complete other embodiments. As long as the features of each embodiment do not violate the spirit of the present disclosure or conflict with each other, the features may be mixed and used together at will.

[0067] Figure 1A is a schematic block diagram of a light emitting device according to an embodiment of the present disclosure. Figure 1A , the light emitting device 100 may include a plurality of sub-pixels P_1 to P_K, where K is an integer greater than 1. Each of the sub-pixels P_1 to P_K is configured to display a grayscale during a frame. In addition, the frame may include N sub-frames, where N is an integer greater than 1. In addition, each of the N sub-frames may include a scanning period and an emission period, but the present disclosure is not limited thereto. In an embodiment, the light emitting device 100 may be particularly suitable for an active matrix LED (AM-LED) display, for example.

[0068] Figure 1B is a schematic block diagram of a sub-pixel according to an embodiment of the present disclosure. Figure 1A and Figure 1B, the sub-pixel 110 is an exemplary embodiment of the sub-pixels P_1 to P_K. Specifically, the sub-pixel 110 may include a pixel circuit 120 and a light emitter 130. In addition, the pixel circuit 120 may include a current control circuit 121 and a pulse width modulation (PWM) circuit 122. The current control circuit 121 is configured to receive an analog signal DT_A during a scanning period, and output a driving current I_D according to the analog signal DT_A during an emission period. The PWM circuit 122 is configured to receive M digital signals DT_D1 to DT_DM and M reference pulse signals RP1 to RPM, and output a PWM pulse P_PWM according to the M digital signals DT_D1 to DT_DM and the M reference pulse signals RP1 to RPM. M is an integer greater than 1. The light emitter 130 is configured to receive a driving current I_D and a PWM pulse P_PWM during an emission period. That is, a variety of gray scales can be formed according to a variety of combinations of the amount of the driving current I_D and the width of the PWM pulse P_PWM. Therefore, as the requirements for grayscale levels increase, the scale of the drive circuit remains relatively small.

[0069] Figure 2 is a schematic circuit diagram of a sub-pixel according to an embodiment of the present disclosure. Figure 1A to Figure 2 In one embodiment, the sub-pixel 110 may be Figure 2 As shown, but the present disclosure is not limited to this. For example, assume that N is 3, and assume that M is 2, but the present disclosure is not limited to this. That is, the sub-pixel 110 is configured to display grayscale during one frame and the frame may include three sub-frames. Each of the three sub-frames may include a scanning period and an emission period. In addition, the PWM circuit 122 is configured to receive two digital signals DT_D1, DT_D2 and two reference pulse signals RP1, RP2. In addition, the PWM circuit 122 is configured to output PWM pulses P_PWM according to the two digital signals DT_D1, DT_D2 and the two reference pulse signals RP1, RP2.

[0070] Specifically, the current control circuit 121 may include a transistor T11, a transistor T12, and a capacitor C11. The first terminal of the transistor T11 is coupled to the analog signal DT_A, and the control terminal of the transistor T11 is coupled to the scan signal SCAN. The control terminal of the transistor T12 is coupled to the second terminal of the transistor T11, and the first terminal of the transistor T12 is coupled to the voltage source PVDD. The first terminal of the capacitor C11 is coupled to the control terminal of the transistor T12, and the second terminal of the capacitor C11 is coupled to the first terminal of the transistor T12. In an embodiment, the control terminal may be a gate terminal of the transistors T11 and T12, and the first terminal and the second terminal may be a source terminal and a drain terminal, respectively, but the present disclosure is not limited thereto. The scan signal SCAN is provided to each of the K sub-pixels P_1 to P_K to determine the light emission sequence of the K sub-pixels P_1 to P_K. That is, the current control circuit 121 is configured to receive the analog signal DT_A during the scan period, and output the drive current I_D according to the analog signal DT_A during the emission period.

[0071] In addition, the PWM circuit 122 may include a transistor T21, a transistor T22, a transistor T23, a capacitor C21, a capacitor C22, an AND gate A1, an AND gate A2, and a NOR gate N1. The first terminal of the transistor T21 is coupled to the digital signal DT_D1, and the control terminal of the transistor T21 is coupled to the scan signal SCAN. The first terminal of the transistor T22 is coupled to the digital signal DT_D2, and the control terminal of the transistor T22 is coupled to the scan signal SCAN. The first terminal of the capacitor C21 is coupled to the second terminal of the transistor T21, and the second terminal of the capacitor C21 is coupled to the ground voltage. The first terminal of the capacitor C22 is coupled to the second terminal of the transistor T22, and the second terminal of the capacitor C22 is coupled to the ground voltage. The first input terminal of the AND gate A1 is coupled to the reference pulse signal RP1, and the second input terminal of the AND gate A1 is coupled to the second terminal of the transistor T21. The first input terminal of the AND gate A2 is coupled to the reference pulse signal RP2, and the second input terminal of the AND gate A2 is coupled to the second terminal of the transistor T22. The first input terminal of the NOR gate N1 is coupled to the output terminal of the AND gate A1, and the second input terminal is coupled to the output terminal of the AND gate A2. The control terminal of the transistor T23 is coupled to the output terminal of the NOR gate N1, and the first terminal of the transistor T23 is coupled to the second terminal of the transistor T12. Specifically, the transistor T21 is configured to receive the digital signal DT_D1 and output the digital signal DT_D1 to the AND gate A1. The transistor T22 is configured to receive the digital signal DT_D2 and output the digital signal DT_D2 to the AND gate A2.

[0072] In an embodiment, the two digital signals DT_D1, DT_D2 and the two reference pulse signals RP1, RP2 may include a plurality of reference pulses. The reference pulses may include different widths and different voltage levels. When the voltage level of the digital signal DT_D1 and the voltage level of the reference pulse signal RP1 are both at a high level, the AND gate A1 may output a logic operation result to the NOR gate N1. When the voltage level of the digital signal DT_D1 and the voltage level of the reference pulse signal RP1 are not both at a high level, the AND gate A1 may not output a logic operation result to the NOR gate N1. Therefore, the PWM circuit 122 may output a pulse P_PWM according to the digital signal DT_D1 and the reference pulse signal RP1. Similarly, when the voltage level of the digital signal DT_D2 and the voltage level of the reference pulse signal RP2 are both at a high level, the AND gate A2 may output a logic operation result to the NOR gate N1. When the voltage level of the digital signal DT_D2 and the voltage level of the reference pulse signal RP2 are not both at a high level, the AND gate A2 may not output a logic operation result to the NOR gate N1. Therefore, the PWM circuit 122 can output the pulse P_PWM according to the digital signal DT_D2 and the reference pulse signal RP2. In this way, the PWM circuit 122 is configured to output the PWM pulse P_PWM according to the two digital signals DT_D1 and DT_D2 and the two reference pulse signals RP1 and RP2.

[0073] In addition, the first terminal of the light emitter 130 is coupled to the second terminal of the transistor T23, and the second terminal of the light emitter 130 is coupled to the voltage source PVSS. Therefore, the light emitter 130 is configured to receive the drive current I_D and the PWM pulse P_PWM during the emission period. That is, a variety of gray scales can be formed according to various combinations of the amount of the drive current I_D and the width of the PWM pulse P_PWM. Therefore, as the requirements for gray scale levels increase, the scale of the drive circuit remains relatively small.

[0074] Figure 3 is a schematic signal timing chart according to an embodiment of the present disclosure. Figures 1A to 3 , assuming that N is 3, and assuming that M is 2, but the present disclosure is not limited thereto. That is, each of the K sub-pixels P_1 to P_K is configured to display grayscale during frame F1, and frame F1 may include 3 sub-frames SF1 to SF3. Each of the 3 sub-frames SF1 to SF3 may include scanning periods P11, P21, and P31, respectively, and emission periods P12, P22, and P32, respectively.

[0075] Specifically, during the scanning periods P11, P21, P31, the current control circuit 121 of each of the K sub-pixels P_1 to P_K is configured to receive the analog signal DT_A and the scanning signal SCAN during the scanning periods P11, P21, P31. In an embodiment, the scanning signal SCAN may include scanning signals SCAN(1), SCAN(2), ... SCAN(K-1) and SCAN(K). The scanning signals SCAN(1), SCAN(2), ... SCAN(K-1) and SCAN(K) are provided to the first sub-pixel P_1, the second sub-pixel, ..., the (K-1)th sub-pixel and the Kth sub-pixel P_K, respectively. For example, at times t_11, t_21, t_31, t_41, the scanning signal SCAN(1) is provided to the first sub-pixel P_1. Before time t_12, t_22, t_32, the K-th scan signal SCAN(K) is provided to the K-th sub-pixel P_K. In addition, the current control circuit 121 is configured to output the drive current I_D according to the analog signal DT_A during the emission period P12, P22, P32. That is, the amount of the drive current I_D can be determined by the analog signal DT_A. During the emission period P12, P22, P32, the PWM circuit 122 is configured to output the PWM pulse P_PWM according to the two digital signals DT_D1, DT_D2 and the two reference pulse signals RP1, RP2. That is, the width of the PWM pulse P_PWM can be determined by the two digital signals DT_D1, DT_D2 and the two reference pulse signals RP1, RP2. In this way, a variety of gray scales can be formed according to a variety of combinations of the amount of the drive current I_D and the width of the PWM pulse P_PWM. Therefore, as the requirements for gray scale levels increase, the scale of the drive circuit remains relatively small.

[0076] For example, it is assumed that the width 1 of the PWM pulse P_PWM is used to display the highest gray scale. That is, when the width of the PWM pulse P_PWM is 1, for a 256-level gray scale display, the gamma value of the gray scale may be 255. When the width of the PWM pulse P_PWM is 0, for a 256-level gray scale display, the gamma value of the gray scale may be 0. In an embodiment, the width of the PWM pulse P_PWM may be determined by the width of the reference pulse of the reference pulse signals RP1 and RP2.

[0077] In an embodiment, during the emission periods P12, P22, P32, each of the emission periods P12, P22, P32 may include two separate reference pulses according to the two reference pulse signals RP1, RP2, respectively. For example, the emission period P12 may include a reference pulse with a width of 32 / 63 and a reference pulse with a width of 1 / 63. The emission period P22 may include a reference pulse with a width of 16 / 63 and a reference pulse with a width of 2 / 63. The emission period P32 may include a reference pulse with a width of 8 / 63 and a reference pulse with a width of 4 / 63. In an embodiment, a sub-grayscale is defined as the grayscale of each of the subframes SF1, SF2, SF3. In an embodiment, the sum of the widths of the reference pulses is 1 (32 / 63+16 / 63+8 / 63+4 / 63+2 / 63+1 / 63=63 / 63). Therefore, during the emission periods P12, P22, and P32, a gray scale with a gamma value of 1 is formed by superposition of the sub-gray scales of one sub-pixel. Different gray scales are provided by changing the width of the reference pulse during the emission periods P12, P22, and P32. In other words, the reference pulse signals PR1 and PR2 during different emission periods P12, P22, and P32 of each of the sub-frames SF1, SF2, and SF3 may correspond to different PWM pulses P_PWM. In this way, a variety of gray scales may be formed according to a variety of combinations of the amount of the drive current I_D and the width of the PWM pulse P_PWM. Therefore, as the requirements for the gray scale level increase, the scale of the drive circuit remains relatively small.

[0078] In an embodiment, the PWM signal is defined as a combination of PWM pulses P_PWM corresponding to each of the transmission periods P12, P22, and P32 of the frame F1. In an embodiment, the PWM circuit 122 may output N×M bits of the PWM signal corresponding to a single frame F1. That is, during different transmission periods P12, P22, and P32 of the subframes SF1, SF2, and SF3, the reference pulse signals PR1 and PR2 may correspond to different PWM pulses P_PWM. For example, during the transmission period P12, according to the reference pulse of the reference pulse signal RP1 with a width of 32 / 63, the PWM pulse P_PWM may correspond to the PWM pulse P_PWM with a width of 32 / 63. During the transmission period P22, according to the reference pulse of the reference pulse signal RP1 with a width of 16 / 63, the PWM pulse P_PWM may correspond to the PWM pulse P_PWM with a width of 16 / 63. During the transmission period P32, according to the reference pulse of the reference pulse signal RP1 having a width of 8 / 63, the PWM pulse P_PWM may correspond to the PWM pulse P_PWM having a width of 8 / 63. It should be noted that the width of the reference pulse is not limited thereto.

[0079] In one embodiment, one of the reference pulse signals RP1 and the other of the reference pulse signals RP2 corresponding to the same transmission period of the transmission periods P12, P22, and P32 may correspond to the longest one of the plurality of PWM pulses P_PWM and the shortest one of the PWM pulses P_PWM, respectively. For example, during the transmission period P12, according to the reference pulse whose longest width is 32 / 63 of the reference pulse signal RP1, the PWM pulse P_PWM may correspond to the PWM pulse P_PWM whose longest width is 32 / 63. In addition, according to the reference pulse whose shortest width is 1 / 63 of the reference pulse signal RP2, the PWM pulse P_PWM may correspond to the PWM pulse P_PWM whose shortest width is 1 / 63. It should be noted that the width of the reference pulse is not limited thereto.

[0080] Figure 4 is a schematic signal timing chart according to an embodiment of the present disclosure. Figure 1A , Figure 1B and Figure 4 In an embodiment, the plurality of sub-pixels P_1 to P_K include two sub-pixels 110 arranged adjacent to each other along a row direction. In addition, the sequences of scanning periods P11_A, P21_A, P31_A, P12_B, P22_B, P32_B and emission periods P12_A, P22_A, P32_A, P11_B, P21_B, P31_B corresponding to the two sub-pixels 110 are different. Specifically, the two sub-pixels 110 may correspond to reference pulse signals RP1_A, RP2_A and reference pulse signals RP1_B, RP2_B, respectively. For example, from time t_11 to time t_12, reference pulse signals RP1_A, RP2_A may correspond to scanning period P11_A, and reference pulse signals RP1_B, RP2_B may correspond to emission period P11_B. That is, the scanning periods P11_A, P21_A, and P31_A may correspond to the emission periods P11_B, P21_B, P31_B, and P41_B. The emission periods P12_A, P22_A, and P32_A may correspond to the scanning periods P12_B, P22_B, and P32_B.

[0081] In another embodiment, the plurality of sub-pixels P_1 to P_K include two sub-pixels 110 arranged adjacent to each other along the column direction. In addition, the sequences of the scanning periods P11_A, P21_A, P31_A, P12_B, P22_B, P32_B and the emission periods P12_A, P22_A, P32_A, P11_B, P21_B, P31_B corresponding to the two sub-pixels 110 are different. Specifically, the two sub-pixels 110 may correspond to the reference pulse signals RP1_A, RP2_A and the reference pulse signals RP1_B, RP2_B, respectively. For example, from time t_11 to time t_12, the reference pulse signals RP1_A, RP2_A may correspond to the scanning period P11_A, and the reference pulse signals RP1_B, RP2_B may correspond to the emission period P11_B. That is, the scanning periods P11_A, P21_A, and P31_A may correspond to the emission periods P11_B, P21_B, P31_B, and P41_B. The emission periods P12_A, P22_A, and P32_A may correspond to the scanning periods P12_B, P22_B, and P32_B.

[0082] Figure 5A is a schematic signal timing chart according to the third embodiment of the present disclosure. Figure 5B is a schematic signal timing chart according to the third embodiment of the present disclosure. Figure 5C is a schematic signal timing chart according to the third embodiment of the present disclosure. Figure 1A to Figure 1B and FIG. 5A to FIG. 5C , FIG. 5A to FIG. 5C Corresponding to three consecutive frames F1 to F3 of each of the sub-pixels P_1 to P_K. That is, the emission period P32 of frame F1 may end at time t_41, and the scanning period of frame F2 may start at time t_41. The emission period P62 of frame F2 may end at time t_71, and the scanning period of frame F3 may start at time t_71. Specifically, the scanning periods P11, P21, P31, P41, P51, P61, P71, P81, P91 may start at time t_11, t_21, t_31, t_41, t_51, t_61, t_71, t_81, t_91, respectively. The emission periods P12, P22, P32, P42, P52, P62, P72, P82, and P92 may start at times t_12, t_22, t_32, t_42, t_52, t_62, t_72, t_82, and t_92, respectively.

[0083] Reference Figure 5A, during frame F1, emission period P12 may include a reference pulse with a width of 32 / 63 and a reference pulse with a width of 1 / 63. Emission period P22 may include a reference pulse with a width of 16 / 63 and a reference pulse with a width of 2 / 63. Emission period P32 may include a reference pulse with a width of 8 / 63 and a reference pulse with a width of 4 / 63. In an embodiment, the reference pulse sequence during frame F1 is defined as mode A.

[0084] Reference Figure 5B , during frame F2, emission period P42 may include a reference pulse with a width of 8 / 63 and a reference pulse with a width of 4 / 63. Emission period P52 may include a reference pulse with a width of 32 / 63 and a reference pulse with a width of 1 / 63. Emission period P62 may include a reference pulse with a width of 16 / 63 and a reference pulse with a width of 2 / 63. In an embodiment, the reference pulse sequence during frame F2 is defined as mode B.

[0085] Reference Figure 5C , during frame F3, emission period P72 may include a reference pulse with a width of 16 / 63 and a reference pulse with a width of 2 / 63. Emission period P82 may include a reference pulse with a width of 8 / 63 and a reference pulse with a width of 4 / 63. Emission period P92 may include a reference pulse with a width of 32 / 63 and a reference pulse with a width of 1 / 63. In an embodiment, the reference pulse sequence during frame F3 is defined as mode C.

[0086]

[0087]

[0088] Table 1

[0089] Referring to Table 1 shown above, modes A, B, and C may include similar reference pulse signals RP1 and RP2 with different reference pulse sequences, but the present disclosure is not limited thereto. That is, at least one of the reference pulse signals RP1 and RP2 has a different PWM pulse sequence during the transmission period corresponding to two consecutive subframes SF1, SF2, and SF3. In one embodiment, modes A, B, and C may include completely different reference pulse signals.

[0090] Fig. 6A is a schematic signal timing chart according to the fourth embodiment of the present disclosure. Figure 6B is a schematic signal timing chart according to the fourth embodiment of the present disclosure. Figure 6C is a schematic signal timing chart according to the fourth embodiment of the present disclosure. Fig.6D is a schematic sub-pixel arrangement according to the fourth embodiment of the present disclosure. Fig. 6E is a schematic sub-pixel arrangement according to the fourth embodiment of the present disclosure. Fig. 6F is a schematic sub-pixel arrangement according to the fourth embodiment of the present disclosure. Figure 1A , FIG. 5A to FIG. 6D As shown in Table 1, the K sub-pixels P_1 to P_K may be arranged in a matrix. The third embodiment differs from the fourth embodiment in that the pattern of the third embodiment varies from one frame to another, but the pattern of the fourth embodiment varies from one sub-pixel 110 to another sub-pixel 110.

[0091] Specifically, a plurality of sub-pixels 110 arranged adjacent to each other along the row direction may include the same pattern of the reference pulse sequence. For example, a row of sub-pixels 110 may include pattern A of reference pulses. In addition, a row of sub-pixels 110 close to a row of sub-pixels 110 including pattern A of reference pulses may include pattern B of reference pulses. In addition, a row of sub-pixels 110 close to a row of sub-pixels 110 including pattern B of reference pulses may include pattern C of reference pulses. In this way, the arrangement of sub-pixels may be repeatedly arranged to form a matrix. In an embodiment, the matrix is ​​formed by a plurality of sub-pixels 110 having patterns A, B, and C. However, the present disclosure is not limited thereto.

[0092] Reference Figure 1A , FIG. 5A to FIG. 6C , Fig. 6E As shown in Table 1, the K sub-pixels P_1 to P_K may be arranged in the form of a matrix. In an embodiment, a plurality of sub-pixels 110 arranged adjacent to each other along the column direction may include the same pattern of the reference pulse sequence. For example, a column of sub-pixels 110 may include pattern A of reference pulses. In addition, a column of sub-pixels 110 close to a column of sub-pixels 110 including pattern A of reference pulses may include pattern B of reference pulses. In addition, a column of sub-pixels 110 close to a column of sub-pixels 110 including pattern B of reference pulses may include pattern C of reference pulses. In this way, the arrangement of sub-pixels may be repeatedly arranged to form a matrix. In an embodiment, a matrix is ​​formed by a plurality of sub-pixels 110 having patterns A, B, and C. However, the present disclosure is not limited thereto.

[0093] Reference Figure 1A , FIG. 5A to FIG. 6C , Fig. 6F As shown in Table 1, the K sub-pixels P_1 to P_K may be arranged in a matrix. The pattern of the plurality of sub-pixels 110 may be repeatedly arranged in a sequence of patterns A, B, and C along a row direction or along a column direction. In an embodiment, a matrix is ​​formed by a plurality of sub-pixels 110 having patterns A, B, and C. However, the present disclosure is not limited thereto.

[0094] Fig. 7A is a schematic sub-pixel arrangement according to the fifth embodiment of the present disclosure. Figure 7B is a schematic sub-pixel arrangement according to the fifth embodiment of the present disclosure. Figure 7C is a schematic sub-pixel arrangement according to the fifth embodiment of the present disclosure. Figure 1A , FIG. 5A to FIG. 7C As shown in Table 1, the K sub-pixels P_1 to P_K may be arranged in a matrix. The fifth embodiment differs from the thirty-fourth embodiment and the fourth embodiment in that the pattern of the fifth embodiment is different not only from one frame to another, but also from one sub-pixel 110 to another sub-pixel 110. In other words, the fifth embodiment is a combination of the third embodiment and the fourth embodiment.

[0095] Specifically, refer to Figure 1A , FIG. 5A to FIG. 6D , Fig. 7A As shown in Table 1, during frame F1, a plurality of sub-pixels 110 adjacently arranged along the row direction may include the same pattern of the reference pulse sequence. For example, the row of sub-pixels 110 may include pattern A of the reference pulse. In addition, the row of sub-pixels 110 close to the row of sub-pixels 110 including pattern A of the reference pulse may include pattern B of the reference pulse. In addition, the row of sub-pixels 110 close to the row of sub-pixels 110 including pattern B of the reference pulse may include pattern C of the reference pulse. In this way, the arrangement of the sub-pixels may be repeatedly arranged to form a matrix. During frame F2 after F1, the pattern of the plurality of sub-pixels 110 is shifted by one row along the column direction. That is, the pattern of each of the plurality of sub-pixels 110 during frame F2 is different from the pattern of each of the plurality of sub-pixels 110 during frame F1. Similarly, during frame F3 after F2, the pattern of the plurality of sub-pixels 110 is shifted by one row along the column direction. That is, the pattern of each of the plurality of sub-pixels 110 during frame F3 is different from the pattern of each of the plurality of sub-pixels 110 during frame F2. In other words, the pattern of the plurality of sub-pixels 110 is different not only from one frame to another, but also from one sub-pixel 110 to another sub-pixel 110. In an embodiment, the matrix is ​​formed by the plurality of sub-pixels 110 having the patterns A, B, C. However, the present disclosure is not limited thereto.

[0096] Reference Figure 1A , FIG. 5A to FIG. 6C , Fig. 6E , Figure 7BAs shown in Table 1, during frame F1, a plurality of sub-pixels 110 adjacently arranged along the column direction may include the same pattern of the reference pulse sequence. For example, the column of sub-pixels 110 may include pattern A of the reference pulse. In addition, a column of sub-pixels 110 close to a column of sub-pixels 110 including pattern A of the reference pulse may include pattern B of the reference pulse. In addition, a column of sub-pixels 110 close to a column of sub-pixels 110 including pattern B of the reference pulse may include pattern C of the reference pulse. In this way, the arrangement of sub-pixels may be repeatedly arranged to form a matrix. During frame F2 after F1, the pattern of the plurality of sub-pixels 110 is shifted by one column along the row direction. That is, the pattern of each of the plurality of sub-pixels 110 during frame F2 is different from the pattern of each of the plurality of sub-pixels 110 during frame F1. Similarly, during frame F3 after F2, the pattern of the plurality of sub-pixels 110 is shifted by one column along the row direction. That is, the pattern of each of the plurality of sub-pixels 110 during frame F3 is different from the pattern of each of the plurality of sub-pixels 110 during frame F2. In other words, the pattern of the plurality of sub-pixels 110 is different not only from one frame to another, but also from one sub-pixel 110 to another sub-pixel 110. In an embodiment, the matrix is ​​formed by the plurality of sub-pixels 110 having the patterns A, B, C. However, the present disclosure is not limited thereto.

[0097] Reference Figure 1A , FIG. 5A to FIG. 6C , Fig. 6F , Figure 7C As shown in Table 1, the K sub-pixels P_1 to P_K may be arranged in a matrix. During frame F1, the pattern of the plurality of sub-pixels 110 may be repeatedly arranged in a sequence of patterns A, B, and C along the row direction or along the column direction. During frame F2 after F1, the pattern of the plurality of sub-pixels 110 is shifted by one column along the row direction or by one row along the column direction. That is, the pattern of each of the plurality of sub-pixels 110 during frame F2 is different from the pattern of each of the plurality of sub-pixels 110 during frame F1. During frame F3 after F2, the pattern of the plurality of sub-pixels 110 is shifted by one column along the row direction or by one row along the column direction. That is, the pattern of each of the plurality of sub-pixels 110 during frame F3 is different from the pattern of each of the plurality of sub-pixels 110 during frame F2. In other words, the pattern of the plurality of sub-pixels 110 is different not only from one frame to another, but also from one sub-pixel 110 to another sub-pixel 110. In an embodiment, the matrix is ​​formed of a plurality of sub-pixels 110 having patterns A, B, C. However, the present disclosure is not limited thereto.

[0098] Figure 8 is a schematic signal timing chart according to the sixth embodiment of the present disclosure. Figure 1A , Figure 1B , Figure 3 and Figure 8 The difference between the first embodiment and the sixth embodiment is that, in the first embodiment, each of the transmission periods P12, P22, P32 includes a reference pulse according to each of the reference pulse signals RP1, RP2, but in the sixth embodiment, each of the transmission periods P12', P22', P32', P42' includes a reference pulse or more than one reference pulse according to each of the reference pulse signals RP1, RP2, RP1_D, RP2_D.

[0099] Specifically, Figure 8 The upper part of Figure 3 The same, and Figure 8 The lower part of the figure shows the main idea of ​​the sixth embodiment. Figure 8 In the upper half of the frame F1, the frame F1 may include three scanning cycles P11, P21, P31 and three transmission cycles P12, P22, P32. That is, the scanning cycles P11, P21, P31 may start at time t_11, t_21, t_31, respectively. The transmission cycles P12, P22, P32 may start at time t_12, t_22, t_32, respectively. A new cycle of the three scanning cycles P11, P21, P31 and the three transmission cycles P12, P22, P32 starts at time t_41. In an embodiment, each of the transmission cycles P12, P22, P32 may include one reference pulse according to each of the reference pulse signals RP1, RP2, and the sum of the widths of the reference pulses is 1 (32 / 63+16 / 63+8 / 63+4 / 63+2 / 63+1 / 63=63 / 63).

[0100] Reference Figure 8 In the lower half of the frame F1, the frame F1 may include four scanning cycles P11', P21', P31', P41' and four emission cycles P12', P22', P32', P42'. That is, the scanning cycles P11', P21', P31', P41' may start at time t_11', t_21', t_31', t_41', respectively. The emission cycles P12', P22', P32', P42' may start at time t_12', t_22', t_32', t_42', respectively. A new cycle of the three scanning cycles P11', P21', P31', P41' and the three emission cycles P12', P22', P32', P42' starts at time t_51'. In an embodiment, each of the transmission periods P12', P22', P32', P42' may include one reference pulse or more than one reference pulse according to each of the reference pulse signals RP1_D, RP2_D. Figure 8, the reference pulse according to the reference pulse signal RP1 during the transmission period P12 having a width of 32 / 63 may be divided into four reference pulses according to the reference pulse signal RP1_D during the transmission periods P12', P32' having a width of (32 / 63) / 4 (e.g., 8 / 63). Similarly, other reference pulses according to the reference pulse signals RP1, RP2 during the transmission periods P12, P22, P32 may maintain the same width, or be divided into more than one reference pulse according to the reference pulse signals RP1_D, RP2_D during the transmission periods P12', P22', P32', P42'. In other words, at least one of the reference pulse signals RP1_D, RP2_D may include two PWM pulses separated in time during the same transmission period or different transmission periods in the transmission periods P12', P22', P32', P42'. In an embodiment, a reference pulse with a width of 32 / 63 during the emission period P12 may be divided into four reference pulses during two different emission periods P12', P32'. In addition, a reference pulse with a width of 16 / 63 during the emission period P22 may be divided into two reference pulses during the same emission period P22'. Note that the sum of the widths of the reference pulses is still 1 ((32 / 63) / 4×4+(16 / 63) / 2×2+(8 / 63) / 2×2+(4 / 63) / 2×2+(2 / 63) / 2×2+1 / 63=63 / 63). Therefore, the grayscale displayed by the sub-pixel 110 according to the reference pulse signals RP1_D, RP2_D may be the same as the grayscale displayed by the sub-pixel 110 according to the reference pulse signals RP1, RP2.

[0101] Fig. 9 is a schematic grayscale diagram according to the seventh embodiment of the present disclosure. Figure 1B and Fig. 9 The difference between the seventh embodiment and the first to sixth embodiments is that in the first to sixth embodiments, only the width of the PWM pulse P_PWM is changed to form a plurality of gray scales, but in the seventh embodiment, both the amount of the driving current I_D and the width of the PWM pulse P_PWM are changed to form a plurality of gray scales.

[0102] For example, for a gamma 1.0 standard with a level of 256, the sub-pixel 110 can display 256 different grayscales. As described above, the PWM circuit 122 can output N×M bits of a PWM signal corresponding to a single frame F1. N is the number of sub-frames in a frame, and M is the number of reference pulse signals. That is, assuming that N is 3 and M is 2, a 6-bit data input can be obtained. In other words, 64 levels (2 6=64). For example, 6 bits may represent a pulse width ratio of 32. 5 bits may represent a pulse width ratio of 16. 4 bits may represent a pulse width ratio of 8. 3 bits may represent a pulse width ratio of 4. 2 bits may represent a pulse width ratio of 2. 1 bit may represent a pulse width ratio of 1. Note that the pulse width ratio is the ratio of the width of the reference pulse to the width of the reference pulse with the shortest width.

[0103] However, since 64-level data input is not enough for the gamma 1.0 standard with a level of 256, the amount of the driving current I_D and the width of the PWM pulse P_PWM are further changed to form 256 gray scales. Specifically, referring to Table 2 shown below, 6 bits can represent a pulse width ratio of 80. 5 bits can represent a pulse width ratio of 30. 4 bits can represent a pulse width ratio of 12. 3 bits can represent a pulse width ratio of 4. 2 bits can represent a pulse width ratio of 2. 1 bit can represent a pulse width ratio of 1. In other words, the 6-bit pulse width ratio is expanded to represent a greater number of gray scales. Referring to Fig. 9 As shown in line 920 and Table 3 below, the pulse width ratio (PWM ratio) may vary as the gray scale (gray level) varies.

[0104] Bit 6 5 4 3 2 1 Pulse Width Ratio 80 30 12 4 2 1

[0105] Table 2

[0106] In addition, the amount of the driving current I_D is further adjusted to provide different levels of the amount of the driving current I_D. Fig. 9 Referring to line 910, instead of providing the driving current I_D at a fixed value, the driving current I_D (current ratio) may vary as the gray scale (gray level) varies.

[0107]

[0108] Table 3

[0109] In this way, the amount of the driving current I_D and the width of the PWM pulse P_PWM are further changed to form 256 gray scales. In other words, 256 gray scales can be represented using 6-bit data input. Therefore, as the requirements for gray scale levels increase, the scale of the driving circuit remains relatively small.

[0110] For example, referring to the above Fig. 9And Table 3, when the pulse width ratio (PWM ratio) is 0 and the current ratio is 0.5, the gray level 0 can be represented by the gray ratio 0. In an embodiment, the minimum value is preferably selected as a value larger than a specific value for accurately controlling the amount of the drive current I_D. Similarly, when the pulse width ratio (PWM ratio) is 129 (1+2+4+12+30+80=129) and the current ratio is 0.988, the gray level 255 can be represented by the gray ratio 127.5. That is, the drive current I_D may include multiple current levels, and the PWM pulse P_PWM may include multiple pulse widths. The gray scale may include multiple gray levels, and the number of gray levels may be determined according to the current level and the pulse width. Note that the number of ratios may be adjusted due to design requirements, and the present disclosure is not limited thereto.

[0111] Fig.10 is a schematic grayscale diagram according to the eighth embodiment of the present disclosure. Figure 1B , Fig. 9 and Fig.10 The eighth embodiment is different from the seventh embodiment in that the seventh embodiment is for the gamma 1.0 standard with a level of 256, and the eighth embodiment is for the gamma 2.2 standard with a level of 256. In the embodiment, referring to the table shown below, 6 bits can represent a pulse width ratio of 384. 5 bits can represent a pulse width ratio of 96. 4 bits can represent a pulse width ratio of 24. 3 bits can represent a pulse width ratio of 6. 2 bits can represent a pulse width ratio of 2. 1 bit can represent a pulse width ratio of 1.

[0112] bit 6 5 4 3 2 1 Pulse Width Ratio 384 96 24 6 2 1

[0113] Table 4

[0114] Due to the characteristics of the drive current I_D, it is easier to adjust the width of the reference pulse of the reference pulse signal RP1, RP2 than to adjust the amount of the drive current. Fig.10 As shown in Table 5, when the gray scale (gray level) changes within a certain range, the current ratio can be maintained at a specific value. For example, for gray levels 192 and 255, the current ratio is 513 (384+96+24+6+2+1=513). In other words, the change from gray level 192 to gray level 255 can be achieved by adjusting the pulse width ratio. However, it is noted that the number of ratios can be adjusted due to design requirements, and the present disclosure is not limited thereto.

[0115]

[0116] Table 5

[0117] Fig.11 is a schematic flow chart of a light emission method according to an embodiment of the present disclosure. Figures 1A to 3 and Fig.11 , Fig.11 The method of the embodiment may be suitable for application on the light emitting device 100. In step S1110, the current control circuit 121 may receive an analog signal during a scanning period. In step S1120, the current control circuit 121 may output a driving current according to the analog signal during an emission period. In step S1130, the PWM circuit 122 may receive M digital signals and M reference pulse signals. In step S1140, the PWM circuit 122 may output PWM pulses according to the M digital signals and the M reference pulse signals. In step S1150, the light emitter 130 may receive a driving current and a PWM pulse during an emission period. Therefore, as the requirements for grayscale levels increase, the scale of the driving circuit remains relatively small. In an embodiment, the execution sequence of step S1110 and step S1130 may be performed simultaneously, or may be performed at different times, and the present disclosure is not limited thereto. In addition, based on FIGS. 1 to 1150, Fig.10 The description of the above-mentioned embodiments, the relevant circuit features, implementation details and related technical features of the light emitting device 100 can obtain sufficient teachings, suggestions and implementation descriptions, and will not be repeated here.

[0118] In summary, according to the light emitting device and light emitting method disclosed in the present invention, through the above circuit design of the current control circuit and the PWM circuit, even if the requirements for the grayscale level increase, the light emitting device disclosed in the present invention can still effectively reduce the scale of the pixel circuit and provide good grayscale display.

[0119] It is obvious to those skilled in the art that various modifications and changes can be made to the disclosed embodiments without departing from the scope or spirit of the present disclosure. In view of the above, the present disclosure is intended to cover modifications and changes within the scope of the above claims and their equivalents.

Claims

1. A light emitting device, characterized in that: include: A plurality of sub-pixels, wherein each of the plurality of sub-pixels is configured to display a gray scale during a frame, wherein the frame includes N sub-frames and N is an integer greater than 1, and each of the N sub-frames includes a scanning period and an emission period, wherein each of the plurality of sub-pixels includes: A pixel circuit, comprising: a current control circuit configured to receive an analog signal during the scanning period, and configured to output a driving current according to the analog signal during the transmitting period; and a pulse width modulation circuit configured to receive M digital signals and M reference pulse signals, and configured to output a pulse width modulation pulse according to the M digital signals and the M reference pulse signals, wherein M is an integer greater than 1; and an optical transmitter configured to receive the driving current and the pulse width modulation pulse during the emission period of each of the N subframes, wherein The pulse width modulation circuit includes M AND gates and NOR gates, wherein the NOR gates are coupled to the M AND gates, and the M AND gates are configured to respectively receive the M digital signals and respectively receive the M reference pulse signals.

2. The light emitting device according to claim 1, characterized in that The pulse width modulation signal is a combination of the pulse width modulation pulses corresponding to each of the transmission periods of the frame, and the pulse width modulation circuit outputs N×M bits of the pulse width modulation signal corresponding to one frame.

3. The light emitting device according to claim 2, characterized in that The M reference pulse signals during different transmission periods of each of the N subframes include different pulse width modulation pulses.

4. The light emitting device according to claim 3, characterized in that: One of the M reference pulse signals and the other of the M reference pulse signals include a longest pulse width modulated pulse and a shortest pulse width modulated pulse, respectively, during a same one of the transmission cycles.

5. The light emitting device according to claim 1, characterized in that At least one of the M reference pulse signals has different pulse width modulation pulse sequences during the transmission periods corresponding to two consecutive ones of the N subframes.

6. The light emitting device according to claim 1, characterized in that The plurality of sub-pixels include two sub-pixels arranged adjacent to each other along a row direction or a column direction, and the reference pulse signals corresponding to the two sub-pixels during a same frame are different.

7. The light emitting device according to claim 6, characterized in that Each of the reference pulse signals has a different pulse width modulation pulse sequence during the transmission period corresponding to two consecutive ones of the N subframes.

8. The light emitting device according to claim 1, characterized in that At least one of the M reference pulse signals includes two pulse width modulated pulses separated in time during different ones of the transmission cycles or during the same transmission cycle.

9. The light emitting device according to claim 1, characterized in that The plurality of sub-pixels include two sub-pixels arranged adjacent to each other along a row direction or a column direction, and sequences of the scanning periods and the emission periods corresponding to the two sub-pixels are different.

10. The light emitting device according to claim 1, characterized in that The driving current includes a plurality of current levels, the pulse width modulation pulse includes a plurality of pulse widths, and the gray scale includes a plurality of gray scale levels, wherein the number of the plurality of gray scale levels is determined according to the plurality of current levels and the plurality of pulse widths.

11. A light emitting method suitable for a light emitting device, characterized in that: The light emitting device comprises a plurality of sub-pixels, a current control circuit, a pulse width modulation circuit and a light emitter, wherein each of the plurality of sub-pixels is configured to display a gray scale during a frame, the frame comprises N sub-frames and N is an integer greater than 1, and each of the N sub-frames comprises a scanning period and an emission period, wherein the light emitting method comprises: During the scanning period, receiving an analog signal through the current control circuit; During the transmission period, outputting a driving current according to the analog signal through the current control circuit; Receiving M digital signals and M reference pulse signals through the pulse width modulation circuit, wherein M is an integer greater than 1; Outputting pulse width modulation pulses according to the M digital signals and the M reference pulse signals through the pulse width modulation circuit; and During the emission period of each of the N subframes, the drive current and the pulse width modulation pulse are received by the optical transmitter, wherein The pulse width modulation circuit includes M AND gates and NOR gates, wherein the NOR gates are coupled to the M AND gates, and the M AND gates are configured to respectively receive the M digital signals and respectively receive the M reference pulse signals.

12. The light emitting method according to claim 11, characterized in that: The M reference pulse signals during different transmission periods of each of the N subframes correspond to different pulse width modulation pulses.

13. The light emitting method according to claim 11, characterized in that: One of the M reference pulse signals and the other of the M reference pulse signals include a longest pulse width modulated pulse and a shortest pulse width modulated pulse, respectively, during a same one of the transmission cycles.

14. The light emitting method according to claim 11, characterized in that: At least one of the M reference pulse signals has different pulse width modulation pulse sequences during the transmission periods corresponding to two consecutive ones of the N subframes.

15. The light emitting method according to claim 11, characterized in that: The plurality of sub-pixels include two sub-pixels arranged adjacent to each other along a row direction or a column direction, and the reference pulse signals corresponding to the two sub-pixels during a same frame are different.

16. The light emitting method according to claim 15, characterized in that: Each of the reference pulse signals has a different pulse width modulation pulse sequence during the transmission period corresponding to two consecutive ones of the N subframes.

17. The light emitting method according to claim 11, characterized in that: At least one of the M reference pulse signals includes two pulse width modulated pulses separated in time during different ones of the transmission cycles or during the same transmission cycle.

18. The light emitting method according to claim 11, characterized in that: The plurality of sub-pixels include two sub-pixels arranged adjacent to each other along a row direction or a column direction, and sequences of the scanning periods and the emission periods corresponding to the two sub-pixels are different.

19. The light emitting method according to claim 11, characterized in that: The driving current includes a plurality of current levels, the pulse width modulation pulse includes a plurality of pulse widths, and the gray scale includes a plurality of gray scale levels, wherein the number of the plurality of gray scale levels is determined according to the plurality of current levels and the plurality of pulse widths.

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