Power saving techniques for layer-to-layer interfaces

Abstract

This document introduces at least one technique to save power in a medium access (MAC) layer interface defined to a physical (PHY) layer. The technique includes receiving a plurality of code blocks (CBs) at the MAC layer, the plurality of CBs forming part of a transport block (TB). The plurality of CBs is associated with an error rate. The error rate indicates a number of missing CBs and / or a plurality of CBs out of order. If the error rate is above a threshold, the MAC layer stores the plurality of CBs in an external memory. If not, the MAC layer processes the plurality of CBs for transmission, for example, to an upper layer. In this way, the PHY layer transmits CBs from a base station to the MAC layer without first storing the CBs in a memory until all CBs of a corresponding TB are received.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Provisional Application No. 63 / 038,665, filed on June 12, 2020, entitled “4G / 5G DOWNLINK MAC / PHY INTERFACECODE BLOCK BASED DIRECT DATAINTERFACE”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The disclosed technology relates to power-saving technology, and more specifically, to power-saving technology for layer-to-layer interfaces in telecommunications equipment. Background Technology

[0004] Due to the ever-increasing demand for wireless communication systems, these systems are constantly being improved. For example, in fifth-generation (5G) technology, spectral efficiency has been improved compared to previous generations. One technique that contributes to improving spectral efficiency is Hybrid Automatic Repeat Request (HARQ) retransmission based on code block groups (CBGs). This technique involves breaking down a transport block (TB) into multiple CBGs, which allows CBGs to be processed through layers of the protocol stack.

[0005] Particularly in the downlink direction, improved 5G technologies can be leveraged to increase the efficiency of network devices. For example, network devices can reduce power consumption due to a finer-grained approach to handling CBG through the protocol stack. However, additional improvements will help to further capitalize on the development of 5G. Attached Figure Description

[0006] This embodiment is shown by way of example and is not intended to be limited to the figures in the accompanying drawings.

[0007] Figure 1 A high-level block diagram of a system with a physical (PHY) layer and a media access (MAC) layer containing memory is shown.

[0008] Figure 2A A high-level block diagram of a hardware-based implementation of the PHY-to-MAC layer interface is shown.

[0009] Figure 2B The interface signals from the PHY layer to the MAC layer are shown.

[0010] Figure 3A high-level block diagram of a software-based implementation of the PHY layer to MAC layer interface is shown.

[0011] Figure 4 This is a flowchart illustrating a method for processing code blocks through the PHY layer to MAC layer interface.

[0012] Figure 5 It is a block diagram illustrating an example form of a machine that is operable to perform aspects of the disclosed technology. Detailed Implementation

[0013] Wireless communication systems are constantly being improved to meet ever-increasing demands for efficiency. In wireless communication devices, efficiency is a broad term that can encompass factors such as power consumption, memory usage, space utilization, and others. Taking these multiple factors into account, there are various methods to improve the efficiency of wireless communication systems.

[0014] For example, fifth-generation (5G) allows hybrid automatic repeat request (HARQ) retransmission. HARQ retransmission allows a transport block (TB) to be broken down into blocks of code (CBG), and a CBG can be further broken down into multiple blocks of code (CB). Therefore, a wireless communication system can process one or more CBs or CBGs at a time, instead of transmitting, receiving, and / or processing the entire TB.

[0015] For example, in the downlink direction, a terminal device (e.g., an iPhone) can connect to a base station. The base station can send multiple CBs to the terminal device. After receiving a CB, the terminal device can store it in external memory until it receives all the CBs in the corresponding TB. Specifically, at the protocol stack level, the Physical (PHY) layer stores the CBs in external memory. Once all the CBs constituting the corresponding TB are received, the PHY layer processes the CBs and transmits them to the Media Access (MAC) layer. A similar process occurs at the MAC layer. The MAC layer stores the CBs in memory until it receives all the CBs from the PHY layer in the corresponding TB.

[0016] However, due to the granular approach developed for HARQ retransmission, for example, if one or more CBGs of a TB are missing during transmission, it is not necessary to retransmit the entire TB. The one or more CBGs can be retransmitted to solve this problem. For example, the PHY layer can indicate to the base station that a specific CBG was missing during transmission. The base station can then retransmit that specific CBG instead of the entire corresponding TB. In this way, HARQ retransmission improves the efficiency of the wireless communication system.

[0017] However, HARQ retransmission technology has not reached its full potential in the aforementioned process. That is, at each layer, the retransmission and storage of CBs in memory leads to at least two problems: power consumption and memory usage. In particular, power consumption is a critical factor in the operation of terminal devices. Given that terminal devices are typically standalone devices, onboard power must be used efficiently. In the described method, power is lost during repeated round trips between the protocol layer and memory, as well as between the layers themselves. For example, the PHY layer may repeatedly send and receive CBs from memory while simultaneously communicating with the base station. Therefore, power is consumed inefficiently.

[0018] Furthermore, the memory at the terminal device is limited. Therefore, memory should be used efficiently. In current HARQ retransmission technology, memory is used to store CBs until all CBs for the corresponding TB have been received. For this purpose, for example, the PHY layer stores the received CBs in memory. Once all CBs have been received, the PHY layer removes the CBs from memory again and transmits them to the MAC layer. At the MAC layer, the CBs are again stored in memory until the MAC layer receives all CBs from the PHY layer. Therefore, memory is heavily used for intermediate storage.

[0019] Other issues have also arisen with the use of current HARQ retransmission technology. For example, additional latency can occur in CB processing due to the waiting time for all CBs from receiving a CB to receiving a TB. Latency caused by communication with memory exacerbates this problem. Another issue is the standby time of each layer of the protocol stack. For example, if the MAC layer processes a previous set of CBs, it must still wait until the PHY layer receives all CBs in the next transmission before it can begin processing the next transmission. Therefore, there are several opportunities to improve the efficiency involved in implementing HARQ retransmission technology.

[0020] Therefore, this paper introduces at least one technique for improving the efficiency of CB transmission between the PHY layer and the MAC layer. Specifically, this technique involves sending CBs from the PHY layer to the MAC layer regardless of whether all CBs of the corresponding TB are received. CBs can be transmitted via a direct hardware interface or a standard bus. In the former option, the PHY layer decoder can interconnect with the PHY-MAC interface. The PHY decoder can transmit CBs via various interface signals. A MAC buffer can be connected to the other end of the PHY-MAC interface. In the latter option, the PHY layer can transmit CBs to the MAC layer via a bus such as an Advanced Microcontroller Bus Architecture (AHB). In this case, data signals and control data signals can be transmitted via the same bus or via different buses.

[0021] In both options described above, the PHY layer does not need to store CBs in memory until it receives all CBs for the corresponding TB from the base station. Instead, when CBs are received from the base station, the PHY layer can send the CBs to the MAC layer. The MAC layer can then determine whether to process the CBs or store them in memory. The MAC layer can make this determination based on, for example, the error rate associated with the CBs. If the error rate is higher than a threshold, the MAC layer can store the CBs in memory and, for example, request transmission. If the error rate is lower than the threshold, the MAC layer can continue processing the CBs. In this way, the aforementioned problem is solved.

[0022] In the following description, examples of terminal devices (e.g., mobile devices) are used for illustrative purposes only to explain various aspects of the technology. For example, a cellular phone may employ the technology used to transmit CB from the PHY layer to the MAC layer. However, it should be noted that the technologies disclosed herein are not limited to applicability to terminal devices or any other particular type of device. Other devices, such as electronic devices or systems (e.g., wireless communication devices), may be suited to these technologies in a similar manner.

[0023] Furthermore, refer to CB and CBG. A CBG is a grouping of multiple CBs. Therefore, in some cases, these terms can be used interchangeably. For example, the PHY layer can transfer a CB to the MAC layer. A CB can also be described as a CBG because a CB can be grouped into one or more CBGs. Additionally, when performing actions, refer to the layers of the protocol stack, such as the PHY layer and the MAC layer. For example, transferring a CB to memory. However, it is important to note that the hardware implementation layer is the component that performs these actions. The terms PHY layer and MAC layer are used merely for descriptive convenience.

[0024] It should also be noted that although the technologies described in this article are within the context of 5G technology, their applicability is not necessarily limited to 5G, or even to wireless telecommunications. Therefore, the technologies described in this article have potential applications in other technical fields beyond those described herein.

[0025] PHY to MAC interface overview

[0026] Figure 1 A high-level block diagram 100 of a physical (PHY) layer and media access (MAC) layer system with memory is shown. Block diagram 100 includes a PHY layer 102, a MAC layer 104, a PHY-MAC layer interface 106, and a memory 108. The PHY layer 102 is interconnected with the MAC layer 104 via the PHY-MAC layer interface 106. Furthermore, the MAC layer 104 is connected to the memory 108. Conversely, the PHY layer 102 is optionally connected to the memory 108.

[0027] PHY layer 102 is optionally connected to memory 108 because PHY layer 102 does not need to communicate with memory 108. Specifically, PHY layer 102 does not need to store CBs in memory 108 until all CBs of the corresponding TB are received. Instead, when CBs are received from the base station, PHY layer 102 can send these CBs to MAC layer 104. However, other wireless communication operations may require communication with memory 108. Therefore, in the context of the technology described herein, the connection to memory 108 is optional.

[0028] In some embodiments, PHY layer 102 may receive CBs from a base station (e.g., 5G NR) (not shown). A CB may be, for example, a portion of a CBG and / or a TB. For example, PHY layer 102 may receive a given number of CBs from a base station. This given number of CBs may form a CBG and a portion of a corresponding TB. In another example, a given number of CBs may constitute a portion of a CBG, which in turn constitutes a portion of a corresponding TB. In yet another example, the number of CBs may form multiple CBGs, which together constitute the entirety of a corresponding TB.

[0029] Regardless of the number of CBs, PHY layer 102 can transmit CBs to MAC layer 104 via PHY layer-MAC layer interface 106. Once MAC layer 104 receives these CBs, it can determine whether to process the received CBs or store them in memory 108. This determination can be based on, for example, an error rate. The transmission error rate is based on CBs that need to be processed in sequence. Generally, CBs should be received in order. Therefore, MAC layer 104 can determine whether any CBs are missing and whether the CBs were received in the correct order based on the order in which they were received. If CBs are missing and / or CBs are out of order, MAC layer 104 can store the CBs in memory 108. Once the error is resolved, MAC layer 104 can retrieve the CBs from memory 108 for further processing.

[0030] Errors caused by missing CBs can be corrected in several ways. For example, PHY layer 102 can transmit the missing CB in a subsequent transmission. In this case, MAC layer 104 can retrieve the associated CB from memory 108 for further processing. For example, MAC layer 104 may initially receive ten CBs. In the set of ten CBs, two CBs may be missing from the sequence. MAC layer 104 can determine that there are two missing CBs because, in the ten received CBs, two intermediate CBs are missing sequentially. In other words, the set should include twelve CBs, but only ten CBs have been received. Therefore, MAC layer 104 can determine to store the ten CBs in memory 108. Subsequently, PHY layer 102 can transmit the two missing CBs. Once these two CBs are received, MAC layer 104 can retrieve the ten CBs from memory 108 and further process the twelve CBs.

[0031] Similarly, MAC layer 104 can receive CBs out of order. MAC layer 104 can determine whether a CB is out of order based on information such as in the CB header and / or control information received with the CB. If MAC layer 104 determines that a CB is out of order, the CB can be stored in memory 108. While in memory 108, the MAC layer can arrange these CBs in the correct order before further processing them (e.g., for transmission to upper layers).

[0032] In some embodiments, memory 108 can be any external memory device communicatively connected to MAC layer 104. For example, memory 108 can be double data rate (DDR) memory. In this case, "external" can refer to memory located outside the hardware of MAC layer 104 and within the terminal device implementing the elements of block diagram 100. For example, the elements of block diagram 100 can be implemented in a cellular phone (e.g., an iPhone). Memory 108 can be memory serving other components and functions of the device and can therefore be used for a variety of purposes. However, MAC layer 104 can be one of several components of a device that can communicate with memory 108.

[0033] In this way, and by using the components in block diagram 100, PHY layer 102 and MAC layer 104 can interact to optimize HARQ retransmission technology. Furthermore, there are several ways to implement the PHY-MAC layer interface 106. One is a hardware logic-based interface design, and the other is a programmable interface design based on central processing unit (CPU) configuration.

[0034] Hardware logic based interface

[0035] Figure 2AA high-level block diagram of a hardware logic-based implementation 200A for the PHY layer to MAC layer interface is shown. Implementation 200A includes a decoder buffer 202, a downlink (DL) PHY layer decoder 204, a DL MAC layer interface 206, a MAC layer buffer 208, interface signals 210, a decoder direct memory access (DMA) 212, a MAC layer DMA 214, an interconnect 216, a DDR controller 218, and DDR 220. In some embodiments, the decoder buffer 202 and the DL PHY layer decoder 204 may be PHY layer (e.g., ...) Figure 1 The DL MAC layer interface 206 and MAC layer buffer 208 can be part of the MAC layer (e.g., PHY layer 102). Furthermore, the DL MAC layer interface 206 and MAC layer buffer 208 can be part of the MAC layer (e.g., PHY layer 102). Figure 1 It is part of the MAC layer 104.

[0036] The decoder buffer 202 can receive CBs from a base station (not shown) and communicate with the DDR 220. As described above, the connection and components between the decoder buffer 202 and the DDR 220 can be optional. Specifically, in the context of the technology described herein, the (PHY layer) decoder buffer 202 does not need to communicate with the memory device DDR 220. The decoder buffer 202 can also transmit CBs to the DL PHY layer decoder 204, which in turn can transmit CBs to the DL MAC layer interface 206.

[0037] In hardware-based designs, CB can be transmitted via various interface signals 210. Combined with… Figure 2B The interface signal 210 is described in more detail. To initiate communication, the DL PHY layer decoder 204 and the DL MAC layer interface 206 can establish a handshake signal. The handshake signal typically establishes and defines the protocol of the communication link between the two participants in the communication. Once communication begins and the MAC layer receives the CB at the DL MAC layer interface 206 and transmits it to the MAC layer buffer 208, the MAC layer can determine whether to process the CB or store it in the DDR 220, as described above. For example, if the CB needs to be stored in the DDR 220 due to an error rate exceeding a threshold, the MAC layer buffer 208 can store the CB in the DDR 220 via the MAC layer DMA 214, the interconnect 216, and the DDR controller 218.

[0038] In some embodiments, the threshold for the error rate can depend on the type of error. For example, if the error is a missing CB, the threshold error rate can be the ratio of missing CBs to received CBs. For example, the ratio could be 1:5, meaning that one CB might be missing out of every five received CBs. If the ratio is greater than 1:5, the received CBs can be stored in the DDR220 until the error rate is resolved. Alternatively, if the error is due to out-of-order received CBs, the CBs can be stored in the DDR220 by default until they are sorted.

[0039] Figure 2B An example of a 200B PHY-to-MAC layer interface signal is shown. Given... Figure 2A Components in Figure 2B To be understood in the best possible way. That is to say, as Figure 2A As described, transmission occurs between the DL PHY layer decoder 204 and the DL MAC layer interface 206. Figure 2B Signal 200B is shown in the diagram. The initial signal clk is the clock signal. Typically, the clock signal oscillates between high and low levels in cycles and is used to coordinate actions between components. Next, TB_end is a single-cycle pulse indicating the end of the current TB data exchange. CB_start is a single-cycle pulse indicating that the first data cycle of the new CB specified by TB_ID and CB_index will be transmitted. CB_length indicates the length of each CB, represented in bytes, verified by the CB_start signal.

[0040] TB_ID or TB index identifies which TB the current data cycle belongs to. CB_data_valid indicates a valid data cycle has occurred when the signal is high. CB_data is the CB data value associated with the CB identified by TB_ID and CB_index. The CB_data value is valid when CB_data_valid is high. MAC_ready indicates that the MAC layer (e.g., ...) is ready. Figure 1 The MAC layer (104) is checked to see if it is ready to receive data. CB_index is the index of the CB currently being transmitted. Furthermore, the bit width of the CB_index signal indicates the number of CBs in the TB identified by the TB_ID signal.

[0041] CB_in_DDR provides an option for the DL PHY layer decoder 204 to indicate to the DL MAC layer interface 206 that CB has been transferred to intermediate memory (e.g., Figure 2A(DDR 220 in the memory). If CB_in_DDR is high, the MAC layer will have to retrieve CB from intermediate memory. However, as mentioned above, this signal will not be high unless other operation of the device causes the signal to be high. Finally, PHY_error indicates that the PHY layer has an error condition.

[0042] For example, the DL PHY layer decoder 204 can initiate data transmission by activating CB_start. Simultaneously, the DL PHY layer decoder 204 can transmit the identification information of the CB, which may include CB_index, Tb_ID, CB_length, and CB_data. Furthermore, the CB_data_valid signal is activated to indicate that the transmission is valid. Otherwise, data will not be transmitted. The DL PHY layer decoder 204 then transmits the precise amount indicated by CB_length. Afterwards, a new CB transmission can be initiated by activating CB_start again. Once all CBs in the TB have been transmitted, TB_end can be activated.

[0043] Programmable interface design

[0044] Figure 3 A high-level block diagram of a software-based implementation 300 of the PHY-MAC layer interface is shown. Implementation 300 includes components within the PHY layer 302 and MAC layer 304, interfaces 306A-306B, and DDR 308. Interfaces 306A-306B may be, for example, AHB Lite, Open Core Control (OCP) Lite, or any other type of bus. Control information (e.g., TB_ID, CB_index, CB_ID) can be transmitted via another bus, such as the data control interface 306B. Alternatively, data and control information can be transmitted on a single bus (e.g., data interface 306A).

[0045] Similar to combination Figure 2B The described signals, bus registers, and interfaces 306A-306B may include those from... Figure 2B The data indicated by the interface signals described herein is similar to the data in the example. For instance, the first register may include CB information such as CB_ID, TB_ID, CB_Index, and CB_length. The second register may include the CB memory address and control register. As mentioned above, this register may not be used because the PHY layer does not need to store the CB in memory (e.g., DDR 308). The third register may indicate when the session is complete and may include TB_end.

[0046] Furthermore, when CBs are received out of order due to transmission errors, the MAC layer 304 will have to sort them before further processing. For this purpose, the MAC layer 304 can store the CBs in the DDR 308 via the MAC layer DMA 304C. Once a CB is received, the process of sorting the out-of-order CBs may include encoding the first and second registers as described above. Afterward, the MAC layer 304 can transfer the CBs to the DDR 308. Once the CBs are stored in the DDR 308, the third register can be encoded. In this way, the MAC layer 304 transfers the out-of-order CBs to the DDR 308.

[0047] Next, to sort the CBs, MAC layer 304 can use a ring buffer (not shown). Each CB can be represented in the ring buffer at a position indicated by CB_index. The entry may also include a pointer to the memory location where the CB data is stored, an offset value indicating the start of the data in memory (e.g., DDR 308), and a length indicating the remaining length of the data in memory. In memory, each CB can be associated with a header and a trailer. The trailer may contain link information pointing to the next memory location, thus forming links between memory locations. Therefore, MAC layer 304 can examine each memory location to sort the CBs.

[0048] Methodology example

[0049] Figure 4 This is a flowchart illustrating method 400 for processing code blocks through a PHY layer to MAC layer interface. Method 400 can be executed by any wireless communication device having memory and a processor. For example, a terminal device such as a cellular phone (e.g., an iPhone) can implement method 400. Furthermore, the terminal device can operate under new radio (NR) technology or long term evolution (LTE) technology. The terminal device may include a receiver for receiving CBs from network nodes such as base stations. The terminal device may also include a processor for performing at least some of the techniques described herein. Furthermore, at least some of the techniques described herein can be applied when a CB is received in the downlink plane of a telecommunications system.

[0050] In box 402, a layer of the protocol stack (e.g., the PHY layer) can receive multiple CBs from, for example, a base station. These multiple CBs may constitute part of a TB (Transmitter Block), and they are associated with an error rate. In box 404, the multiple CBs can be transmitted to a receive layer (e.g., the MAC layer). Box 404 may also include establishing a handshake signal between the two layers and receiving CBs through multiple hardware interface signals. Alternatively, multiple CBs can be received through a programmable interface such as a data interface bus. In some cases, there may be two interface buses: one bus for control information and a second bus for data.

[0051] In box 406, the receiving layer (e.g., the MAC layer) can determine whether the error rate is below a threshold. The error rate can indicate the number of missing CBs in the TB. If the error rate is not below the threshold, the receiving layer can determine that the error rate is above the threshold when it receives a CB. For example, the ratio between the number of missing CBs and the number of received CBs can be above the threshold. Therefore, in box 408, the MAC layer can store multiple CBs in memory. Alternatively, the MAC layer can determine that the error rate is below the threshold. In this case, in box 410, the MAC layer can further process the CBs for example, to transmit them to an upper layer. For example, once a missing CB is received, the MAC layer can determine that the error rate is below the threshold.

[0052] In some cases, multiple CBs may be received out of order. When this occurs, the receive layer can order the CBs before further processing. For this purpose, the receive layer can use a ring buffer. Furthermore, the receive layer can represent each CB with an entry in the ring buffer indicating identification information (e.g., CB_ID). In this way, layers of the protocol stack (e.g., the PHY layer and the MAC layer) can interact to process CBs regardless of whether all CBs for the corresponding TB have been received.

[0053] Computing system example

[0054] Figure 5This is a block diagram illustrating an example form of a computer system operable to perform aspects of the disclosed technologies. For example, processing system 500 may be an example implementation of a network node or terminal device capable of implementing the technologies described above. At least a portion of processing system 500 may be included in an electronic device (e.g., a computer server) supporting one or more CPNs and / or one or more UPNs. Processing system 500 may include one or more processors 502, main memory 506, non-volatile memory 510, network adapter 512 (e.g., a network interface), display 518, input / output device 520, control device 522 (e.g., a keyboard and pointing device), drive unit 524 including storage medium 526, and signal generation device 530 communicatively connected to bus 516. Bus 516 represents any one or more individual physical buses, point-to-point connections, or any combination thereof connected by suitable bridges, adapters, or controllers. Therefore, bus 516 can include, for example, a system bus, a peripheral component interconnect (PCI) bus or PCI-Express bus, a HyperTransport or industry standard architecture (ISA) bus, a small computer system interface (SCSI) bus, any version of the universal serial bus (USB), an IIC (I2C) bus, or the Institute of Electrical and Electronics Engineers (IEEE) standard 1394 bus, also known as "FireWire". The bus can also be responsible for relaying data packets between components of network devices such as switching engines, network ports, tool ports, etc. (e.g., via full-duplex or half-duplex lines).

[0055] In various embodiments, the processing system 500 operates as a standalone device, although it may be connected (e.g., wired or wirelessly) to other devices. For example, the processing system 500 may include a terminal directly coupled to a network device. As another example, the processing system 500 may be wirelessly coupled to a network device.

[0056] In various embodiments, the processing system 500 may be a server computer, client computer, personal computer (PC), user equipment, tablet PC, laptop computer, personal digital assistant (PDA), cellular phone, iPhone, iPad, Blackberry, processor, telephone, network device, network router, switch or bridge, console, handheld console, (handheld) gaming device, music player, any portable, mobile, handheld device, or any machine capable of executing a set of instructions (sequence or otherwise) specifying the actions to be performed by the processing system 500.

[0057] Although main memory 506, non-volatile memory 510, and storage medium 526 (also referred to as "machine-readable medium") are shown as a single medium, the terms "machine-readable medium" and "storage medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) storing one or more sets of instructions 528. The terms "machine-readable medium" and "storage medium" should also be understood to include any medium capable of storing, encoding, or carrying a set of instructions for execution by processing system 500, and causing processing system 500 to perform any or more of the methods of the currently disclosed embodiments.

[0058] Typically, routines executed to implement the techniques disclosed above can be implemented as part of an operating system or application, component, program, object, module, or sequence of instructions (collectively, a "computer program"). A computer program typically includes one or more instructions (e.g., instruction 504, instruction 508, instruction 528) that are stored in different memories and storage devices in the computer at different times, and when the instructions are read and executed by one or more processing units or processors 502, cause the processing system 500 to operate to perform elements relating to the various aspects of the above disclosure.

[0059] Furthermore, although embodiments have been described in the context of full-featured computers, computer systems and / or other devices, those skilled in the art will understand that various embodiments can be distributed as program products in various forms, and this disclosure applies equally to any particular type of machine or computer-readable medium used for the actual implementation of the distribution.

[0060] Further examples of machine-readable storage media, machine-readable media, or computer-readable (storage) media include recordable media, such as volatile and non-volatile memory devices 510, floppy disks and other removable disks, hard disk drives, optical disks (e.g., compact disk read-only memory, CD ROM, digital versatile disks, DVD) and transport-type media, such as digital communication links and analog communication links.

[0061] Network adapter 512 enables processing system 500 to transmit data in network 514 with entities outside processing system 500 (e.g., network devices) via any known and / or convenient communication protocols supported by processing system 500 and external entities. Network adapter 512 may include one or more of the following: network adapter card, wireless network interface card, router, access point, wireless router, switch, multilayer switch, protocol converter, gateway, bridge, bridge router, hub, digital media receiver, and / or repeater.

[0062] Network adapter 512 may include a firewall, which in some embodiments can govern and / or manage permissions to access / proximize data in a computer network and track different trust levels between different machines and / or applications. The firewall can be any number of modules having any combination of hardware and / or software components capable of enforcing a predetermined set of access permissions between a specific group of machines and applications, between machines, and / or between applications, for example, to regulate traffic and resource sharing between these different entities. The firewall can also manage and / or access access control lists that detail permissions, including, for example, access and operation permissions for individuals, machines, and / or applications on objects, and the context in which the permissions are situated.

[0063] Other network security functions can be implemented or included in the firewall's functionality, including intrusion prevention, intrusion detection, next-generation firewalls, personal firewalls, etc.

[0064] As described above, the techniques described herein are implemented, for example, by programmable circuits (e.g., one or more microprocessors), programmed with software and / or firmware, implemented entirely as dedicated hardwired (i.e., non-programmable) circuits, or a combination thereof. Dedicated circuits can take the form of, for example, one or more application-specific integrated circuits (ASICs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), etc.

[0065] It should be noted that, unless otherwise specified, or if the above embodiments may be mutually exclusive in function and / or structure, any of the embodiments described above can be combined with another embodiment.

[0066] Summary

[0067] The embodiments described herein illustrate the necessary information to enable those skilled in the art to practice the embodiments and demonstrate the best mode for practicing the embodiments. Upon reading the specification with reference to the accompanying drawings, those skilled in the art will understand the concepts of this disclosure and will recognize the application of these concepts, which are not particularly addressed herein. These concepts and applications fall within the scope of this disclosure and the appended claims.

[0068] The above description and accompanying drawings are illustrative and should not be construed as limiting. Many specific details have been described to provide a thorough understanding of this disclosure. However, in some cases, well-known details have not been described to avoid obscuring the description. Furthermore, various modifications may be made without departing from the scope of the embodiments.

[0069] As used herein, unless otherwise specified, terms such as “processing,” “determining,” and “generating” refer to the actions and processes of a computer or similar electronic computing device that manipulates data represented as physical (electronic) quantities in computer memory or registers and converts data represented as physical (electronic) quantities in computer memory or registers into other data represented as physical quantities in computer memory, registers, or other such storage media, transmission, or display devices.

[0070] References to “an embodiment” or “case” herein mean that a particular feature, structure, or characteristic described in connection with that embodiment and / or case is included in at least one embodiment and / or case of this disclosure. The phrases “in an embodiment” and / or “in this case” appearing in different places in the specification do not necessarily refer to the same embodiment and / or case, nor are they separate or alternative embodiments and / or cases that are mutually exclusive with other embodiments and / or cases. Furthermore, various features that may be shown by some embodiments and / or cases but not by others are described. Similarly, various requirements are described, which may be requirements of some embodiments and / or cases but not of others.

[0071] The terms used in this specification generally have their common meaning in the art, in the context of this disclosure, and in the specific context in which each term is used. Some terms used to describe this disclosure are discussed above or elsewhere in the specification to provide additional guidance to those skilled in the art regarding the description of this disclosure. It is understood that the same thing may be expressed in more than one way.

[0072] Therefore, alternative languages ​​and synonyms may be used for any one or more terms discussed herein, and have no particular significance in relation to whether a term is elaborated or discussed herein. Synonyms for certain terms are provided. Listing one or more synonyms does not preclude the use of other synonyms. Examples used anywhere in this specification, including examples of any terms discussed herein, are merely illustrative and are not intended to further limit the scope and meaning of this disclosure or any exemplary terms. Similarly, this disclosure is not limited to the various embodiments given in this specification.

[0073] Without intending to further limit the scope of this disclosure, examples of components and methods according to embodiments of this disclosure and their related results have been given above. It should be noted that headings or subheadings have been used in the examples for the reader's convenience, but these should in no way limit the scope of this disclosure. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. In the event of any conflict, this document, including its limitations, shall prevail.

[0074] In summary, it should be understood that specific embodiments of the invention have been described herein for illustrative purposes, but various modifications may be made without departing from the scope of the invention. Therefore, the invention is not limited except for the appended claims.

Claims

1. A method comprising: At the first layer of the protocol stack, multiple code blocks are received from the base station, wherein the multiple code blocks are part of a transport block and are associated with an error rate; Transmit the plurality of code blocks to the second layer of the protocol stack; and In the second layer, based on the error rate, it is determined whether to (1) store the plurality of code blocks in memory or (2) process the plurality of code blocks; The method further includes: in response to the error rate being higher than a threshold, storing the plurality of code blocks in the memory at the second layer; Wherein, the error rate indicates the number of missing code blocks within the transport block, and the method further includes: In the second layer, the missing code block is received; In response to receiving the missing code block, at the second layer, it is determined that the error rate is below the threshold; and In the second layer, the multiple code blocks are processed.

2. The method according to claim 1, wherein, The multiple code blocks are unordered, and the method further includes: In the second layer, the plurality of code blocks are stored in memory; and In the second layer, the plurality of code blocks are sorted.

3. The method according to claim 1, wherein, The multiple code blocks are unordered, and the method further includes: In the second layer, a ring buffer entry is indicated for each of the plurality of code blocks.

4. The method according to claim 3, wherein, The entry point includes: a pointer to the location where the code block is stored, an offset value, and a length.

5. The method according to claim 1, wherein, The error rate indicates the number of missing code blocks within the transport block.

6. The method according to claim 1, further comprising: In the second layer, it is determined that the error rate is below a threshold; as well as In the second layer, the multiple code blocks are transferred to the upper layer.

7. The method according to claim 1, wherein, The transmission of the plurality of code blocks also includes: A handshake signal is established between the first layer and the second layer, wherein the handshake signal defines a protocol for communication between the first layer and the second layer.

8. The method according to claim 1, wherein, The multiple code blocks are transmitted through multiple hardware interface signals.

9. The method according to claim 1, wherein, The multiple code blocks are transmitted via a data interface bus.

10. The method according to claim 9, wherein, The data interface bus is a first data interface bus, and the method further includes: Control information is received through a second data interface bus, wherein the second data interface bus is different from the first data interface bus.

11. The method according to claim 1, wherein, The first layer is the physical layer, and the second layer is the media access control layer.

12. The method according to claim 1, wherein, The memory is a double data rate (DDR) memory.

13. A method for saving power in a physical PHY layer to media access MAC layer interface, the method comprising: The PHY layer receives a portion of the transport block from the base station; The PHY layer transmits a portion of the transport block to the MAC layer, wherein the portion of the transport block is associated with an error rate; and The PHY layer enables the MAC layer to determine, based on the error rate, whether to (1) store a portion of the transport block in memory or (2) process a portion of the transport block; Wherein, if the error rate is higher than a threshold, the method further includes: The MAC layer stores a portion of the transport block in memory; Wherein, the error rate indicates the number of missing code blocks within the transport block, and the method further includes: The MAC layer receives the missing code block; In response to receiving the missing code block, the MAC layer determines that the error rate is below the threshold; and The MAC layer processes a portion of the transport block.

14. The method according to claim 13, wherein, Transmitting a portion of the transport block also includes: A handshake signal is established between the PHY layer and the MAC layer, wherein the handshake signal defines the protocol for communication between the PHY layer and the MAC layer; and A portion of the transport block is transmitted via multiple hardware interface signals.

15. The method according to claim 13, wherein, Transmitting a portion of the transport block also includes: A portion of the transport block is transmitted via the data interface bus.

16. The method according to claim 13, wherein, A portion of the transport block includes multiple code blocks.

17. A system comprising: processor; as well as The memory stores instructions that, when executed by the processor, cause the system to perform the following operations: At the first layer of the protocol stack, multiple code blocks are received, wherein these multiple code blocks are part of a transport block, and wherein these multiple code blocks are associated with an error rate; and The first layer transmits the plurality of code blocks to the second layer of the protocol stack; In the second layer, based on the error rate, it is determined whether (1) the plurality of code blocks are stored in the memory, or (2) the plurality of code blocks are processed to transfer the plurality of code blocks to the upper layer; In response to the error rate exceeding a threshold, the plurality of code blocks are stored in the memory at the second layer; The error rate indicates the number of missing code blocks within the transport block; the operation further includes: In the second layer, the missing code block is received; In response to receiving the missing code block, at the second layer, it is determined that the error rate is below the threshold; and In the second layer, the multiple code blocks are processed.

Images