A storage unit and related equipment

Abstract

The embodiment of the present application provides a memory cell and related devices, wherein the first electrode of the first MTJ included in the memory cell is connected in series with the first electrode of the second MTJ through a first metal wire, and the first electrode of the first MTJ and the first electrode of the second MTJ are electrodes of the same layer. Wherein, currents of different directions and different magnitudes flowing through the first MTJ and the second MTJ will change the resistance state of the first MTJ and / or the second MTJ. In this way, polymorphic storage can be achieved through the combination of different resistance values ​​of the first MTJ and the second MTJ, thereby improving the storage efficiency of the memory.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of communications, and in particular to a storage unit and related equipment. Background Art

[0002] Memory is an important component of computer architecture and has a decisive impact on computer speed, integration and power consumption.

[0003] Magnetoresistive random access memory (MRAM) is a new type of non-volatile memory technology. It has gradually gained widespread attention from industry insiders for its high speed, low power consumption, and good compatibility with complementary metal oxide semiconductor (CMOS). MRAM has the high-speed read and write capabilities of static random access memory and the high integration of dynamic random access memory, making it a high-quality storage device. Unlike mainstream storage, MRAM uses changes in the direction of magnetic polarization to store information.

[0004] In the existing MRAM storage technology, MRAM can only record two states, 0 and 1, through the high and low resistance difference of the magnetic tunneling junction (MTJ), and the capacity of storing data is limited. Summary of the invention

[0005] The embodiment of the present application provides a memory cell and related devices, where currents of different directions and magnitudes flowing through a first MTJ and a second MTJ change the resistance state of the first MTJ and / or the second MTJ. In this way, polymorphic storage can be achieved through a combination of different resistance values ​​of the first MTJ and the second MTJ, thereby improving the storage efficiency of the memory.

[0006] According to a first aspect of an embodiment of the present application, a storage unit is provided, which includes: a first magnetic tunnel junction MTJ, a second MTJ and a first metal wire; the first MTJ and the second MTJ are connected in series through the first metal wire; the first end of the first metal wire is electrically connected to the first electrode of the first MTJ, the second end of the first metal wire is electrically connected to the first electrode of the second MTJ, and the first electrode of the first MTJ and the first electrode of the second MTJ are both top electrodes or bottom electrodes.

[0007] The embodiment of the present application provides a memory cell, wherein the first electrode of the first MTJ included in the memory cell is connected in series with the first electrode of the second MTJ through a first metal wire, and the first electrode of the first MTJ and the first electrode of the second MTJ are electrodes of the same layer. That is, the first electrode of the first MTJ and the second electrode of the second MTJ are both top electrodes or bottom electrodes. After currents of different directions and sizes flow through the first MTJ and the second MTJ, the resistance state of the first MTJ and / or the second MTJ will be changed. Since the first MTJ and the second MTJ are connected to the same-layer electrodes, with the direction from the bottom electrode to the top electrode of the first MTJ and the second MTJ as the reference direction, the currents in the first MTJ and the second MTJ are equal in magnitude and opposite in direction, and the currents have opposite effects on the magnetic field directions of the free layers of the first MTJ and the second MTJ. Furthermore, polymorphic storage can be achieved by combining different resistance values ​​of the first MTJ and the second MTJ, thereby improving the storage efficiency of the memory.

[0008] In a possible implementation of the first aspect, the first MTJ and the second MTJ are located in the same layer of the film structure and are formed by a single thin film deposition. The first MTJ and the second MTJ have the same thickness, and the first MTJ and the second MTJ have different critical dimensions, so that the resistance values ​​of the first MTJ and the second MTJ can be different, so as to realize polymorphic storage. The first MTJ and the second MTJ are formed by a single thin film deposition, which reduces the processing steps of the first MTJ and the second MTJ and saves the cost of manufacturing the first MTJ and the second MTJ.

[0009] In a possible implementation of the first aspect, the storage unit also includes a first metal connector, a second metal connector and a switching element; the second electrode of the first MTJ is electrically connected to the first end of the switching element through the first metal connector; the second electrode of the second MTJ is electrically connected to the bit line through the second metal connector; the second end of the switching element is connected to the source line; and the control end of the switching element is connected to the word line.

[0010] This possible implementation method provides a possible connection method of a storage unit, thereby improving the feasibility of the solution.

[0011] In a possible implementation of the first aspect, the storage unit also includes a third MTJ, a first metal line, a second metal line, a first metal connector, a second metal connector and a switching element; the second electrode of the first MTJ is electrically connected to the first end of the switching element through the first metal connector; the second MTJ and the third MTJ are connected in series through the second metal line; the first end of the second metal connecting line is electrically connected to the second electrode of the second MTJ, the second end of the second metal connecting line is electrically connected to the first electrode of the third MTJ, and the second electrode of the second MTJ and the first electrode of the third MTJ are both top electrodes or bottom electrodes; the second electrode of the third MTJ is electrically connected to the bit line through the second metal connector; the second end of the switching element is electrically connected to the source line; and the control end of the switching element is electrically connected to the word line.

[0012] In this possible implementation, the memory cell further includes a third MTJ, and the resistance states of the memory cell are increased from 4 resistance states corresponding to 2 MTJs to 8 resistance states corresponding to 3 MTJs, thereby improving the storage efficiency of the memory cell.

[0013] In a possible implementation manner of the first aspect, the angle between the first metal line and the second metal line is an acute angle, and the lines connecting the center of the first MTJ, the center of the second MTJ, and the center of the third MTJ form an acute triangle.

[0014] In this possible implementation, the center of the first MTJ, the center of the second MTJ, and the center of the third MTJ may be arranged in a triangle, thereby reducing the space occupied by the three MTJs when arranged, and further reducing the size of the memory.

[0015] In a possible implementation manner of the first aspect, in the above-mentioned storage unit: the first metal line is parallel to the second metal line, and a line connecting the center of the first MTJ, the center of the second MTJ, and the center of the third MTJ forms a straight line.

[0016] In this possible implementation, the first MTJ, the second MTJ and the third MTJ can be arranged in a straight line. In turn, the space occupied by the three MTJs can be reduced, further reducing the size of the memory. Since the first MTJ, the second MTJ and the third MTJ are connected in series, the current flowing through the first MTJ, the first metal line and the second MTJ is the same as the current flowing through the second MTJ, the second metal line and the third MTJ.

[0017] In a possible implementation of the first aspect, the storage unit also includes a second metal line, a third metal line, a third MTJ, a fourth MTJ, a first metal connector, a second metal connector and a switching element, the second electrode of the first MTJ is electrically connected to the first end of the switching element through the first metal connector; the second MTJ and the third MTJ are connected in series through the second metal line; the first end of the second metal connecting line is electrically connected to the second electrode of the second MTJ, the second end of the second metal connecting line is electrically connected to the first electrode of the third MTJ, and the second electrode of the second MTJ and the first electrode of the third MTJ are both top electrodes or bottom electrodes; the third MTJ and the fourth MTJ are connected in series through the third metal line; the first end of the third metal connecting line is electrically connected to the second electrode of the third MTJ, the second end of the third metal connecting line is electrically connected to the first electrode of the fourth MTJ, and the second electrode of the third MTJ and the first electrode of the fourth MTJ are both top electrodes or bottom electrodes; the second end of the switching element is electrically connected to the source line; and the control end of the switching element is electrically connected to the word line.

[0018] In this possible implementation, the storage unit further includes a third MTJ and a fourth MTJ, and the resistance states of the storage unit are increased from 4 resistance states corresponding to 2 MTJs to 16 resistance states corresponding to 4 MTJs, thereby improving the storage efficiency of the storage unit.

[0019] In a possible implementation manner of the first aspect, lines connecting the center of the first MTJ, the center of the second MTJ, the center of the third MTJ, and the center of the fourth MTJ form a quadrilateral.

[0020] In this possible implementation, the first MTJ, the second MTJ, the third MTJ and the fourth MTJ may be arranged in a quadrilateral manner, thereby reducing the space occupied by the four MTJs when arranged, and further reducing the size of the memory.

[0021] In a possible implementation manner of the first aspect, a line connecting the center of the first MTJ, the center of the second MTJ, the center of the third MTJ, and the center of the fourth MTJ forms a straight line.

[0022] In this possible implementation, the first MTJ, the second MTJ, the third MTJ and the fourth MTJ may be arranged in a straight line, thereby reducing the space occupied by the four MTJs when arranged, and further reducing the size of the memory.

[0023] In a possible implementation manner of the first aspect, the bit line is parallel to the first metal line, the bit line is perpendicular to the word line, and the bit line is perpendicular to the source line.

[0024] In this possible implementation, a possible arrangement of a bit line, a word line, and a source line is provided, where the bit line is parallel to the first metal line, the bit line is perpendicular to the word line, and the bit line is perpendicular to the source line. This can reduce the space occupied by the bit line, the word line, and the source line after arrangement, and further reduce the size of the memory.

[0025] In a possible implementation manner of the first aspect, the bit line is perpendicular to the first metal line, the bit line is perpendicular to the word line, and the bit line is parallel to the source line.

[0026] In this possible implementation, a possible arrangement of a bit line, a word line, and a source line is provided, in which the bit line is perpendicular to the first metal line, the bit line is perpendicular to the word line, and the bit line is parallel to the source line. This can reduce the space occupied by the bit line, the word line, and the source line after the arrangement, and further reduce the size of the memory.

[0027] A second aspect of an embodiment of the present application provides a memory array, which includes: word lines, bit lines, source lines and at least one memory cell, and the memory cell is the memory cell described in the first aspect or any possible implementation of the first aspect.

[0028] A third aspect of an embodiment of the present application provides a memory, the memory comprising a storage unit and a controller;

[0029] The storage unit stores data under the control of the controller, and the storage unit is the storage unit described in the above-mentioned first aspect or any possible implementation manner of the first aspect.

[0030] A fourth aspect of an embodiment of the present application provides a storage computing device, the storage computing device comprising a storage unit and a controller;

[0031] The storage unit stores and / or calculates data under the control of the controller. The storage unit is the storage unit described in the above-mentioned first aspect or any possible implementation manner of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1a is a structural schematic diagram of an MTJ provided in an embodiment of the present application;

[0033] Figure 1b is a schematic diagram of a structure of a memory provided in an embodiment of the present application;

[0034] Figure 2 is a structural schematic diagram of a storage unit provided in an embodiment of the present application;

[0035] Figure 3 is another structural schematic diagram of a storage unit provided in an embodiment of the present application;

[0036] Figure 4 is a schematic diagram of an embodiment of a storage unit provided in an embodiment of the present application;

[0037] Figure 5 is a schematic diagram of another embodiment of a storage unit provided in an embodiment of the present application;

[0038] Figure 6 is a schematic diagram of another embodiment of a storage unit provided in an embodiment of the present application;

[0039] Figure 7 is a schematic diagram of another embodiment of a storage unit provided in an embodiment of the present application;

[0040] Figure 8 is a schematic diagram of another embodiment of a storage unit provided in an embodiment of the present application;

[0041] Fig. 9 is a schematic diagram of another embodiment of a storage unit provided in an embodiment of the present application;

[0042] Fig.10 is a schematic diagram of another embodiment of a storage unit provided in an embodiment of the present application;

[0043] Fig.11 is a schematic diagram of another embodiment of a storage unit provided in an embodiment of the present application;

[0044] Fig.12 is a schematic diagram of another embodiment of a storage unit provided in an embodiment of the present application;

[0045] Fig.13 is a schematic diagram of another embodiment of a storage unit provided in an embodiment of the present application;

[0046] Fig.14 is a schematic diagram of another embodiment of a storage unit provided in an embodiment of the present application;

[0047] Fig.15 is a schematic diagram of another embodiment of a storage unit provided in an embodiment of the present application;

[0048] Fig.16 is a schematic diagram of another embodiment of a storage unit provided in an embodiment of the present application;

[0049] Fig.17 It is a schematic diagram of another embodiment of the storage unit provided in the embodiment of the present application. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solutions and advantages of the present application more clear, the embodiments of the present application are described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. It is known to those skilled in the art that with the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0051] The terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments described here can be implemented in an order other than that illustrated or described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or modules is not necessarily limited to those steps or modules clearly listed, but may include other steps or modules that are not clearly listed or inherent to these processes, methods, products or devices. The naming or numbering of steps in this application does not mean that the steps in the method flow must be executed in the time / logical sequence indicated by the naming or numbering. The process steps that have been named or numbered can change the execution order according to the technical purpose to be achieved, as long as the same or similar technical effects can be achieved.

[0052] "And / or" in this application is only a description of the association relationship of associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. In addition, in the description of this application, unless otherwise specified, "multiple" refers to two or more than two. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0053] Memory is an important component of computer architecture and has a decisive impact on computer speed, integration and power consumption.

[0054] Magnetoresistive random access memory (MRAM) is a new type of non-volatile memory technology. It has gradually gained widespread attention from industry insiders for its high speed, low power consumption, and good compatibility with complementary metal oxide semiconductor (CMOS). MRAM has the high-speed read and write capabilities of static random access memory and the high integration of dynamic random access memory, making it a high-quality storage device. Unlike mainstream storage, MRAM uses changes in the direction of magnetic polarization to store information.

[0055] Figure 1a It is a structural schematic diagram of the MTJ provided in an embodiment of the present application.

[0056] like Figure 1a As shown, the module used for storage in MRAM includes a magnetic tunnel junction (MTJ), wherein the MTJ mainly includes a free layer for storing information, a tunnel layer and a reference layer for fixing the magnetization direction. The magnetism of the reference layer remains unchanged, and the magnetism of the free layer changes with the change of the control current or other magnetic flipping mechanism. The direction of the magnetic field in the reference layer is preset, and the direction of the magnetic field in the reference layer can be upward, and the direction of the magnetic field in the reference layer can be downward, which is not specifically limited here. When the magnetization direction of the reference layer is parallel to that of the free layer, the storage unit exhibits a low resistance. When the magnetization direction of the reference layer is antiparallel to that of the free layer, the storage unit exhibits a high resistance. According to the characteristic that the resistance value of the MTJ can be changed by currents of different directions and sizes, the data can be recorded as 0 or 1 through circuit design. The MTJ also includes a top electrode and a bottom electrode, and the structures of the top electrode and the bottom electrode are different. Optionally, the etching process of the top electrode and the bottom electrode can be different. Optionally, the morphology of the top electrode and the bottom electrode can be different, which is not specifically limited here. Optionally, the direction of the free layer and the reference layer shown in the figure can be that the free layer is above the reference layer and closer to the top electrode, or that the free layer is below the reference layer and closer to the bottom electrode, which is not limited here.

[0057] In the existing MRAM storage technology, MRAM can only record two states, 0 and 1, through the high and low resistance difference of an MTJ, and the capacity for storing data is limited.

[0058] In view of the above-mentioned problems existing in the existing memory, an embodiment of the present application provides a memory cell, and the memory cell included in the memory cell provided in the embodiment of the present application includes a first magnetic tunnel junction MTJ, a second MTJ and a first metal wire, wherein the first MTJ and the second MTJ are formed by a single thin film deposition and the first MTJ and the second MTJ are different in size. The first electrode of the first MTJ is connected in series with the first electrode of the second MTJ through the first metal wire, and the first electrode of the first MTJ and the first electrode of the second MTJ are electrodes of the same layer. Among them, currents of different directions and different sizes flowing through the first MTJ and the second MTJ will change the resistance state of the first MTJ and / or the second MTJ. In this way, polymorphic storage can be achieved by combining different resistance values ​​of the first MTJ and the second MTJ, thereby improving the storage efficiency of the memory.

[0059] The following will be combined with the drawings in the present application to clearly and completely describe the technical solutions in the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. The following specific embodiments can be combined with each other, and the same or similar contents will not be repeated in different embodiments. It should also be noted that the length, width, height (or thickness) of the various components shown in the embodiments of the present application are only exemplary descriptions and are not limitations on the storage unit of the present application.

[0060] Figure 1b It is a structural schematic diagram of a memory provided in an embodiment of the present application.

[0061] See also Figure 1b ,like Figure 1b As shown, the memory 100 provided in the embodiment of the present application includes: a storage unit 101 and a controller 102, wherein the storage unit 101 included in the memory may be one storage unit, or the storage unit 101 may be multiple storage units, which is not specifically limited here.

[0062] The storage unit 101 is electrically connected to the controller 102. The storage unit 101 is a component for storing data in an electronic device integrated with the storage unit 101. The storage unit 101 receives one or more control signals generated by the controller 102, and stores data according to the one or more control signals.

[0063] In the embodiment of the present application, the memory may include one storage unit, and the memory may also include two or more storage units, which is not specifically limited here.

[0064] based on Figure 1a as well as Figure 1b The structural schematic diagram of the described memory describes the storage unit provided in the embodiment of the present application.

[0065] Figure 2 It is a structural schematic diagram of a storage unit provided in an embodiment of the present application.

[0066] See also Figure 2 An embodiment of the present application provides a storage unit, which includes a first magnetic tunnel junction MTJ, a second MTJ and a first metal line, wherein the first MTJ and the second MTJ are located in the same layer of the film layer structure, are formed by a single thin film deposition, and the first MTJ and the second MTJ have different sizes.

[0067] The first electrode of the first MTJ is connected in series with the first electrode of the second MTJ through a first metal line, and the first electrode of the first MTJ and the first electrode of the second MTJ are electrodes of the same layer.

[0068] A first end of the first metal line is electrically connected to a first electrode of the first MTJ, and a second end of the first metal line is electrically connected to a first electrode of the second MTJ.

[0069] Among them, currents of different directions and different sizes flowing through the first MTJ and the second MTJ will change the resistance state of the first MTJ and / or the second MTJ, that is, currents of different directions and different sizes flowing through the first MTJ and the second MTJ will change the resistance state of the first MTJ, or will change the resistance state of the second MTJ, or will change the resistance state of both the first MTJ and the second MTJ, and the specific details are not limited here.

[0070] In the embodiment of the present application, Figure 2 The first MTJ shown to be smaller than the second MTJ is only for illustration. In actual application, the first MTJ may be smaller than the second MTJ, or the second MTJ may be smaller than the first MTJ. The specific details are not limited here.

[0071] Figure 3 It is a schematic diagram of the structure of another storage unit provided in an embodiment of the present application.

[0072] The first electrode of the first MTJ is connected in series with the first electrode of the second MTJ through a first metal line, and the first electrode of the first MTJ and the first electrode of the second MTJ are electrodes of the same layer.

[0073] In the embodiment of the present application, the first electrode of the first MTJ and the first electrode of the second MTJ are the same layer electrodes, which can be used to indicate that the first electrode of the first MTJ and the first electrode of the second MTJ are both top electrodes, or the first electrode of the first MTJ and the first electrode of the second MTJ are both bottom electrodes. The structure of the memory cell provided in the embodiment of the present application can be as follows Figure 2 The structure shown can also be Figure 3 The structure shown in FIG. 1 is not limited here. Figure 2As shown, if the first electrode of the first MTJ and the first electrode of the second MTJ are both top electrodes, the top electrode of the first MTJ and the top electrode of the second MTJ are connected in series through the first metal wire. Figure 3 As shown, if the first electrode of the first MTJ and the first electrode of the second MTJ are both bottom electrodes, the bottom electrode of the first MTJ and the bottom electrode of the second MTJ are connected in series through a first metal wire.

[0074] The first MTJ and the second MTJ are located in the same film layer structure, the first MTJ and the second MTJ are formed by one thin film deposition, and the first MTJ and the second MTJ have different sizes.

[0075] In the embodiment of the present application, Figure 3 The first MTJ shown to be smaller than the second MTJ is only for illustration. In actual application, the first MTJ may be smaller than the second MTJ, or the second MTJ may be smaller than the first MTJ. The specific details are not limited here.

[0076] Figure 4 It is a schematic diagram of an embodiment of a storage unit provided in an embodiment of the present application.

[0077] See also Figure 4 In the embodiment of the present application, in a preferred embodiment, in the process of preparing the first MTJ and the second MTJ, after a film structure is formed on the wafer by a thin film deposition, the first MTJ and the second MTJ are etched at different positions on the film structure, and the material at other positions other than the first MTJ and the second MTJ is a dielectric material. And the size of the first MTJ and the second MTJ is different. For example, if the shape of the first MTJ and the second MTJ is a cylinder, the critical dimension (critical dimention, CD) of the circular surface of the first MTJ and the circular surface of the second MTJ is different. In a preferred embodiment, since the first MTJ and the second MTJ are located in the same layer of thin film, the resistance area product (RA) of the first MTJ and the second MTJ is the same, and the thickness of the MTJ formed from the same film structure is the same, so the thickness of the first MTJ and the second MTJ is the same. Optionally, the shape of the first MTJ and the second MTJ can be a cylinder. When the first MTJ and the second MTJ are cylinders, the diameters on the circular surfaces of the first MTJ and the second MTJ are different. The first MTJ and the second MTJ may be in the shape of an elliptical cylinder. When the first MTJ and the second MTJ are in the shape of an elliptical cylinder, the surface areas of the elliptical surfaces of the first MTJ and the second MTJ may be different. The first MTJ and the second MTJ may also be in other shapes, which are not specifically limited here.

[0078] Currents of different directions and magnitudes flowing through the first MTJ and the second MTJ may change the resistance state of the first MTJ and / or the second MTJ.

[0079] In the embodiment of the present application, Figure 4 The first MTJ shown to be smaller than the second MTJ is only for illustration. In actual application, the first MTJ may be smaller than the second MTJ, or the second MTJ may be smaller than the first MTJ. The specific details are not limited here.

[0080] In the embodiment of the present application, if the shapes of the first MTJ and the second MTJ are both cylindrical, CD can be the diameter of the MTJ. If the shapes of the first MTJ and the second MTJ are elliptical cylinders, CD can be the short axis length of the elliptical surface of the MTJ. If the first MTJ and the second MTJ are other shapes, CD can also be other parameters, which are not specifically limited here.

[0081] In the following, the shapes of the first MTJ and the second MTJ are cylindrical, and the CD of the first MTJ 1 CD with the second MTJ 2 Differently, the first MTJ and the second MTJ are in the same layer of the film structure, and are formed by a single thin film deposition as an example for explanation.

[0082] In the embodiment of the present application, the resistance area product (RA) can usually be tested by the current in-plane tunneling method. RA reflects the thickness and quality of the tunneling layer. Since the first MTJ and the second MTJ are in the same layer of the film structure and are formed by a single thin film deposition, the thickness and quality of the tunneling layer of the first MTJ are the same. Therefore, the RA of the first MTJ 1 With the RA of the second MTJ 2 The resistance R of MTJ and the CD of MTJ have the following relationship: R = 4RA / πCD 2 In the usual design process, since CD is inversely proportional to R, the resistance R can be changed by changing the CD of the MTJ. Figure 2 , Figure 3 As shown, when the RA of the first MTJ 1 With the RA of the second MTJ 2 Same, CD 1 Smaller than CD 2 , R 1 Greater than R 2 Therefore, the initial resistance values ​​of the first MTJ and the second MTJ are different. Since the switching current of the MTJ is positively correlated with its volume, the volume of the first MTJ is smaller than that of the second MTJ, so the switching current I of the first MTJ is 1 Less than the flip current I of the second MTJ 2 .

[0083] In the present application embodiment, Figure 2 , Figure 3 As shown, each MTJ includes a reference layer and a free layer. The reference layer has a fixed magnetization direction, and the magnetization direction will not change due to external influences. The magnetization direction in the free layer can change due to external current. If the magnetization direction of the free layer in the MTJ is the same as that of the reference layer, the resistance of the MTJ is low, and the MTJ is in a low resistance state. If the magnetization direction of the free layer in the MTJ is opposite to that of the reference layer, the resistance of the MTJ is high, and the MTJ is in a high resistance state. The four resistance states can be distinguished according to the different resistance states of two MTJs connected in series.

[0084] The following embodiments will describe the four types of resistance states in detail.

[0085] In the embodiment of the present application, the initial resistance of the first MTJ is different from the initial resistance of the second MTJ. The initial resistance of the first MTJ is the first resistance, the resistance when the first MTJ is in a high resistance state is the second resistance, and the resistance when the first MTJ is in a low resistance state is the third resistance. In this way, the first MTJ has two resistance states, and accordingly, the first MTJ has two storage states. Similarly, the initial resistance of the second MTJ is the fourth resistance, the resistance when the second MTJ is in a high resistance state is the fifth resistance, and the resistance when the second MTJ is in a low resistance state is the sixth resistance. In this way, the second MTJ has two resistance states, and accordingly, the second MTJ has two storage states. After the first MTJ and the second MTJ are connected in series, there can be four resistance states, and correspondingly, there are four storage states.

[0086] Exemplarily, in the embodiment of the present application, the magnetization direction of the reference layer of the first MTJ and the second MTJ is taken as an example to illustrate. In the actual application process, optionally, the magnetization direction of the reference layer of the first MTJ can be the same as the magnetization direction of the reference layer of the second MTJ, and the magnetization direction of the reference layer of the first MTJ can be different from the magnetization direction of the reference layer of the second MTJ, which is not specifically limited here. Optionally, the magnetization direction of the reference layer of the first MTJ can be upward or downward, and the magnetization direction of the reference layer of the second MTJ can be upward or downward, which is not specifically limited here.

[0087] Resistance state 1: first MTJ low resistance state + second MTJ low resistance state.

[0088] Figure 5 It is a schematic diagram of another embodiment of the storage unit provided in the embodiment of the present application.

[0089] like Figure 5As shown, illustratively, taking the example that the top electrodes of the first MTJ and the second MTJ are connected through the first metal wire, the reference layer and the free layer in the first MTJ have the same magnetic field direction, and the first MTJ presents a low resistance state. Similarly, the reference layer and the free layer in the second MTJ have the same magnetic field direction, and the second MTJ presents a low resistance state.

[0090] Resistance state 2: first MTJ high resistance state + second MTJ low resistance state.

[0091] Figure 6 It is a schematic diagram of another embodiment of the storage unit provided in the embodiment of the present application.

[0092] like Figure 6 As shown, for example, taking the example that the top electrodes of the first MTJ and the second MTJ are connected through the first metal wire, the magnetic field directions of the reference layer and the free layer in the first MTJ are opposite, and the first MTJ presents a high resistance state. The magnetic field directions of the reference layer and the free layer in the second MTJ are the same, and the second MTJ presents a low resistance state.

[0093] Resistance state 3: first MTJ low resistance state + second MTJ high resistance state.

[0094] Figure 7 It is a schematic diagram of another embodiment of the storage unit provided in the embodiment of the present application.

[0095] like Figure 7 As shown, for example, the top electrodes of the first MTJ and the second MTJ are connected through the first metal wire. If the magnetic field directions of the reference layer and the free layer in the first MTJ are the same, the first MTJ is in a low resistance state. If the magnetic field directions of the reference layer and the free layer in the second MTJ are opposite, the second MTJ is in a high resistance state.

[0096] Resistance state 4: first MTJ high resistance state + second MTJ high resistance state.

[0097] Figure 8 It is a schematic diagram of another embodiment of the storage unit provided in the embodiment of the present application.

[0098] like Figure 8 As shown, for example, taking the example that the top electrodes of the first MTJ and the second MTJ are connected through the first metal wire, the reference layer and the free layer in the first MTJ have opposite magnetic field directions, and the first MTJ is in a high resistance state. The reference layer and the free layer in the second MTJ have opposite magnetic field directions, and the second MTJ is in a high resistance state.

[0099] In the embodiments of the present application, the flip current is the current intensity that can change the direction of the magnetic field of the free layer in the MTJ when the current direction is different from the direction of the magnetic field of the free layer. The flip current may be different when the parallel state is switched to the antiparallel state, and when the antiparallel state is switched to the parallel state. The parallel state means that the magnetic field directions of the free layer and the reference layer are the same, and the antiparallel state means that the magnetic field directions of the free layer and the reference layer are opposite. When the current value provided by the outside world is greater than the flip current, the magnetization direction in the free layer will change, and thus, the resistance state of the MTJ will change. The above embodiments describe four types of resistance states, and the mutual switching between the resistance state types will be described in detail below.

[0100] In the embodiment of the present application, the resistance state 1 is taken as an example for explanation, the current IA 1 or IA 2 Flowing into the first MTJ and the second MTJ in series, IA 1 The current flows from the bottom electrode of the first MTJ into the memory cell, flows through the first metal line, and is then derived from the bottom electrode of the second MTJ. The direction of the current is Fig. 9 Direction from 1 to 2. 2 The current flows from the bottom electrode of the second MTJ into the memory cell, flows through the first metal line, and is derived from the bottom electrode of the first MTJ. The direction of the current is Fig. 9 2 to 1 direction. 1 with IA 2 The flip current of the first MTJ is named I 1 , the flip current of the second MTJ is named I 2 .

[0101] Fig. 9 It is a schematic diagram of another embodiment of the storage unit provided in the embodiment of the present application.

[0102] For example, Fig. 9 The resistance state of the memory cell shown is resistance state 2, such as Fig. 9 The current in the direction shown flows into the first MTJ from the bottom electrode of the first MTJ, flows through the second MTJ via the first metal line, and then is output from the bottom electrode of the second MTJ to other modules.

[0103] If IA 1 <I 1 <I 2 , then IA 1 After flowing into the first MTJ and the second MTJ, the magnetic field of the free layer of the first MTJ will not be reversed, nor will the magnetic field of the free layer of the second MTJ be reversed, and the resistance state of the memory cell will not change.

[0104] If I 1 <IA 1<I 2 , then IA 1 After flowing into the first MTJ and the second MTJ, since the magnetic field direction of the first MTJ is the same as the current direction, the magnetic field of the free layer of the first MTJ will not be reversed. 1 Less than the flip current I of the second MTJ 2 Therefore, the magnetic field of the free layer of the second MTJ will not be flipped, and the resistance state of the memory cell will not change.

[0105] If I 1 <I 2 <IA 1 , then IA 1 After flowing into the first MTJ and the second MTJ, although IA 1 Greater than the flip current I of the first MTJ 1 Since the direction of the magnetic field of the first MTJ is the same as the direction of the current, the magnetic field of the free layer of the first MTJ will not be reversed. 1 Greater than the flip current I of the second MTJ 2 , and the magnetic field direction of the second MTJ is opposite to the current direction, which will cause the magnetic field of the free layer of the second MTJ to flip. The resistance state of the memory cell is switched from the first MTJ low resistance state + the second MTJ low resistance state to the first MTJ low resistance state + the second MTJ high resistance state, and the resistance state of the memory cell is switched from resistance state 1 to resistance state 3.

[0106] In the embodiment of the present application, when the memory cell is in resistance state 1, the current IA 2 After flowing into the second MTJ from the bottom electrode of the second MTJ, it flows through the first MTJ through the first metal line, and then outputs from the bottom electrode of the first MTJ to other modules. Under this condition, different sizes of IA 2 The switching of the resistance state of the memory cell after the input to the memory cell is similar to the principle described in the above embodiment, and the details are not repeated here.

[0107] In the embodiment of the present application, the resistance state 2 is taken as an example for explanation, the current IA 1 The flip current flowing into the first MTJ and the second MTJ in series is named I 1 , the flip current of the second MTJ is named I 2 .

[0108] Fig.10 It is a schematic diagram of another embodiment of the storage unit provided in the embodiment of the present application.

[0109] For example, Fig.10 The resistance state of the memory cell shown is resistance state 2, such as Fig.10 The current IA in the direction shown 1After flowing into the first MTJ from the bottom electrode of the first MTJ, it flows through the second MTJ via the first metal line, and then is output from the bottom electrode of the second MTJ to other modules.

[0110] If IA 1 <I 1 <I 2 , then IA 1 After flowing into the first MTJ and the second MTJ, the magnetic field of the free layer of the first MTJ will not be reversed, nor will the magnetic field of the free layer of the second MTJ be reversed, and the resistance state of the memory cell will not change.

[0111] If I 1 <IA 1 <I 2 , then IA 1 After flowing into the first MTJ and the second MTJ, IA 1 Greater than the flip current I of the first MTJ 1 , and the magnetic field direction of the first MTJ is consistent with the current IA 1 The opposite direction will cause the magnetic field of the free layer of the first MTJ to flip. 1 Less than the flip current I of the second MTJ 2 , although the magnetic field direction of the second MTJ is consistent with the current IA 1 The direction is opposite, and the magnetic field of the free layer of the second MTJ will not be flipped. The resistance state of the memory cell is switched from the first MTJ high resistance state + the second MTJ low resistance state to the first MTJ low resistance state + the second MTJ low resistance state, and the resistance state of the memory cell is switched from resistance state 2 to resistance state 1.

[0112] If I 1 <I 2 <IA 1 , then IA 1 After flowing into the first MTJ and the second MTJ, IA 1 Greater than the flip current I of the first MTJ 1 , and IA 1 The direction of IA is opposite to that of the free layer in the first MTJ, thus causing the magnetic field of the free layer of the first MTJ to flip. 1 Greater than the flip current I of the second MTJ 2 , and IA 1 The direction is opposite to that of the free layer in the second MTJ, thus causing the magnetic field of the free layer of the second MTJ to flip. The resistance state of the memory cell switches from the first MTJ high resistance state + the second MTJ low resistance state to the first MTJ low resistance state + the second MTJ high resistance state, and the resistance state of the memory cell switches from resistance state 2 to resistance state 3.

[0113] In the embodiment of the present application, when the memory cell is in resistance state 2, the current IA 2 After flowing into the second MTJ from the bottom electrode of the second MTJ, it flows through the first MTJ through the first metal line, and then outputs from the bottom electrode of the first MTJ to other modules. Under this condition, since the directions of the free layer magnetic fields of the first MTJ and the second MTJ are the same as IA 2 Same direction, different size of IA 2 After the input to the memory cell, the resistance state of the memory cell does not switch.

[0114] In the embodiment of the present application, if the storage unit is in the blocking state 3, it receives IA signals of different sizes in different directions. 1 IA 2 The process of switching the resistance state is similar to the process of switching the resistance state when the storage unit is in the resistance state 2 in the above embodiment, and will not be described in detail here.

[0115] In the embodiment of the present application, if the storage unit is in the blocking state 4, it receives IA signals of different sizes in different directions. 1 IA 2 The process of switching the resistance state is similar to the process of switching the resistance state when the storage unit is in the resistance state 1 in the above embodiment, and will not be described in detail here.

[0116] In the embodiment of the present application, the switching of the resistance state can also be understood from the perspective of data writing.

[0117] (1) Obtain resistance state 1

[0118] In the embodiment of the present application, first, a medium voltage is applied to the memory cell at the bottom electrode of the second MTJ. Figure 5 IA in the 2 to 1 direction shown 2 , and satisfies I 1 <I 2 <IA 2 At this time, the magnetic field directions between the free layer and the reference layer of the first MTJ in the storage unit are opposite, and the first MTJ is in a high resistance state. The magnetic field directions between the free layer and the reference layer of the second MTJ are the same, and the second MTJ is in a low resistance state. Then, a medium voltage is applied to the storage unit at the bottom electrode of the first MTJ. Figure 5 IA from 1 to 2 as shown 1 , and satisfies I 1 <IA 1 <I 2 , at this time, the magnetic field directions between the free layer and the reference layer of the first MTJ in the storage unit are the same, and the first MTJ is in a low resistance state. The magnetic field directions between the free layer and the reference layer of the second MTJ are the same, and the second MTJ is in a low resistance state. The storage unit is in resistance state 1.

[0119] (2) Obtaining resistance state 2

[0120] In the embodiment of the present application, a medium such as Figure 6 IA2 in the 2 to 1 direction shown, and satisfies I 1 <I 2 <IA 2 , at this time, the magnetic field directions between the free layer and the reference layer of the first MTJ in the storage unit are opposite, and the first MTJ is in a high resistance state. The magnetic field directions between the free layer and the reference layer of the second MTJ are the same, and the second MTJ is in a low resistance state. The storage unit is in resistance state 2.

[0121] (3) Obtain resistance state 3

[0122] In the embodiment of the present application, a medium such as Figure 7 IA1 from 1 to 2 as shown, and satisfies I 1 <I 2 <IA 1 , at this time, the magnetic field directions between the free layer and the reference layer of the first MTJ in the storage unit are the same, and the first MTJ is in a low resistance state. The magnetic field directions between the free layer and the reference layer of the second MTJ are opposite, and the second MTJ is in a high resistance state. The storage unit is in resistance state 3.

[0123] (4) Obtaining resistance state 4

[0124] In the embodiment of the present application, first, a medium voltage is applied to the memory cell at the bottom electrode of the first MTJ. Figure 8 IA from 1 to 2 as shown 1 , and satisfies I 1 <I 2 <IA 1 At this time, the magnetic field directions between the free layer and the reference layer of the first MTJ in the storage unit are the same, and the first MTJ is in a low resistance state. The magnetic field directions between the free layer and the reference layer of the second MTJ are opposite, and the second MTJ is in a high resistance state. Then, a medium voltage is applied to the storage element at the bottom electrode of the second MTJ. Figure 8 IA in the 2 to 1 direction shown 2 , and satisfies I 1 <IA 2 2 , at this time, the magnetic field directions between the free layer and the reference layer of the first MTJ in the storage unit are opposite, and the first MTJ is in a high resistance state. The magnetic field directions between the free layer and the reference layer of the second MTJ are opposite, and the second MTJ is in a high resistance state. The storage unit is in resistance state 4.

[0125] In the embodiment of the present application, Figure 5 , Figure 6 , Figure 7 ,​ Figure 8 , Fig. 9 as well as Fig.10 The first MTJ shown to be smaller than the second MTJ is only for illustration. In actual application, the first MTJ may be smaller than the second MTJ, or the second MTJ may be smaller than the first MTJ. The specific details are not limited here.

[0126] Fig.11 It is a schematic diagram of another embodiment of the storage unit provided in the embodiment of the present application.

[0127] like Fig.11 As shown, in the embodiment of the present application, the storage unit includes a first metal connector, a second metal connector and a switch element.

[0128] The second electrode of the first MTJ is electrically connected to the first end of the switch element through the first metal connector;

[0129] The second electrode of the second MTJ is electrically connected to a bit line through a second metal connection member;

[0130] The second end of the switch element is electrically connected to a source line;

[0131] The control terminal of the switch element is electrically connected to a word line.

[0132] In one embodiment, if the switching element is a transistor, the word line is electrically connected to the gate of the transistor, the source line is electrically connected to the source of the transistor, and the second metal connector is electrically connected to the drain of the transistor. If the switching element is other elements, there may be other connection methods, which are not specifically limited here.

[0133] The switch element inputs currents of different magnitudes into the first MTJ and the second MTJ through the first metal connector, or the bit line inputs currents of different magnitudes into the first MTJ and the second MTJ through the second metal connector, thereby changing the resistance state of the first MTJ and / or the second MTJ.

[0134] In an embodiment of the present application, the second electrode of the first MTJ is electrically connected to the switching element through a first metal connector. Optionally, the switching element may be a transistor, the switching element may be a gate tube, or the switching element may be other electronic components with control functions, which are not specifically limited here. Optionally, the second electrode of the first MTJ is electrically connected to the switching element through a first metal connector, and the second electrode of the first MTJ and the first metal connector may also include many other metal connectors for achieving electrical connection, which are not specifically limited here. Similarly, it can be seen that, optionally, the second electrode of the second MTJ is electrically connected to the bit line through a second metal connector, and the second electrode of the second MTJ and the second metal connector may also include many other metal connectors for achieving electrical connection, which are not specifically limited here. Optionally, the second electrodes of the first MTJ and the second MTJ may be top electrodes, and the second electrodes of the first MTJ and the second MTJ may be bottom electrodes, which are not specifically limited here.

[0135] In an embodiment of the present application, the signal module is used to input an electrical signal to a storage unit. In a possible implementation, the memory receives a data recording instruction from an electronic device, the word line and the bit line can select the location in the storage unit where data needs to be input, and the electronic device controls the switch element through the source line to open and input current to the first MTJ and the second MTJ, or the electronic device inputs current to the second MTJ and the first MTJ through the bit line, thereby changing the resistance state of the first MTJ and the second MTJ. The first MTJ and the second MTJ are combined into different resistance states to achieve data storage.

[0136] In the embodiment of the present application, the switch element can input currents of different directions and magnitudes into the first MTJ and the second MTJ through the first metal connector to change the resistance state of the first MTJ and / or the second MTJ. The way in which the switch element changes the resistance state through current is similar to that in the above embodiment. Figures 5 to 10 The method described is similar and will not be described in detail here.

[0137] In the embodiment of the present application, the memory cell may further include a third MTJ, a first metal line, a second metal line, a first metal connector, a second metal connector, and a switch element;

[0138] The second electrode of the first MTJ is electrically connected to the first end of the switch element through the first metal connector;

[0139] The second MTJ and the third MTJ are connected in series via a second metal line;

[0140] The first end of the second metal connection line is electrically connected to the second electrode of the second MTJ, the second end of the second metal connection line is electrically connected to the first electrode of the third MTJ, and the second electrode of the second MTJ and the first electrode of the third MTJ are both top electrodes or bottom electrodes;

[0141] A second electrode of the third MTJ is electrically connected to the bit line through a second metal connection member;

[0142] The second end of the switch element is electrically connected to the source line;

[0143] The control terminal of the switch element is electrically connected to the word line.

[0144] The switch element inputs currents of different directions and magnitudes into the first MTJ, the second MTJ and the third MTJ through the first metal connector, which changes the resistance state of the first MTJ, the second MTJ and / or the third MTJ.

[0145] In the embodiment of the present application, the functions of the various components in the connection module and the signal module are as follows: Fig.11 The functions in the described embodiments are similar and will not be described in detail here.

[0146] In the embodiment of the present application, Fig.11 The first MTJ shown to be larger than the second MTJ is only for illustrative purposes. In actual applications, the first MTJ may be smaller than the second MTJ, or the second MTJ may be smaller than the first MTJ. The specific details are not limited here.

[0147] Fig.12 It is a schematic diagram of another embodiment of the storage unit provided in the embodiment of the present application.

[0148] In the present application embodiment, Fig.12 As shown, the first MTJ, the second MTJ and the third MTJ are all electrodes of the same layer. After a film structure is formed on the wafer by a thin film deposition, the first MTJ, the second MTJ and the third MTJ are etched at different positions on the film structure, and the sizes of the first MTJ, the second MTJ and the third MTJ are different. The first MTJ, the second MTJ and the third MTJ are connected in series in an end-to-end manner. Exemplarily, if the top electrode of the first MTJ is connected in series with the top electrode of the second MTJ through a first metal wire, the bottom electrode of the second MTJ is connected in series with the bottom electrode of the third MTJ through a second metal wire. If the bottom electrodes of the first MTJ and the second MTJ are connected in series through a first metal wire, the top electrode of the second MTJ is connected in series with the top electrode of the third MTJ through a second metal wire.

[0149] In the embodiment of the present application, the switch element inputs currents of different directions and magnitudes into the first MTJ, the second MTJ and the third MTJ through the first metal connector, which changes the resistance state of the first MTJ, the second MTJ and / or the third MTJ. 3 resistance state, with N MTJs there will be 2 N The way in which the switch element changes its resistance state through current is similar to that in the above-mentioned embodiment. Figures 5 to 10 The method described is similar and will not be described in detail here.

[0150] In the embodiments of the present application, the first MTJ, the second MTJ and the third MTJ have a variety of reasonable arrangements, and the specific arrangements will be described in the following embodiments.

[0151] Fig.13 It is a schematic diagram of another embodiment of the storage unit provided in the embodiment of the present application.

[0152] 1. The angle between the first metal line and the second metal line is an acute angle, and the lines connecting the center of the first MTJ, the center of the second MTJ, and the center of the third MTJ form an acute triangle.

[0153] See also Fig.13 In the embodiment of the present application, the first MTJ, the second MTJ and the third MTJ can be arranged in a triangle, thereby reducing the space occupied by the three MTJs and further reducing the size of the memory.

[0154] 2. The first metal line is parallel to the second metal line, and a line connecting the center of the first MTJ, the center of the second MTJ, and the center of the third MTJ forms a straight line.

[0155] Fig.14 It is a schematic diagram of another embodiment of the storage unit provided in the embodiment of the present application.

[0156] See also Fig.14 In the embodiment of the present application, the first MTJ, the second MTJ and the third MTJ can be arranged in a straight line. In addition, the space occupied by the three MTJs can be reduced, further reducing the volume of the memory. Since the first MTJ, the second MTJ and the third MTJ are connected in series, the current flowing through the first MTJ, the first metal line and the second MTJ is the same as the current flowing through the second MTJ, the second metal line and the third MTJ.

[0157] In the embodiment of the present application, it is characterized in that the storage unit further includes a third MTJ, a first metal line, a second metal line, a first metal connection member, a second metal connection member and a switch element;

[0158] The second electrode of the first MTJ is electrically connected to the first end of the switching element through the first metal connector;

[0159] The second MTJ and the third MTJ are connected in series via the second metal line;

[0160] The first end of the second metal connection line is electrically connected to the second electrode of the second MTJ, the second end of the second metal connection line is electrically connected to the first electrode of the third MTJ, and the second electrode of the second MTJ and the first electrode of the third MTJ are both top electrodes or bottom electrodes;

[0161] The second electrode of the third MTJ is electrically connected to the bit line through the second metal connection member;

[0162] The second end of the switch element is electrically connected to the source line;

[0163] The control end of the switch element is electrically connected to the word line.

[0164] Among them, the switching element inputs currents of different directions and sizes into the first MTJ, the second MTJ, the third MTJ and the fourth MTJ through the first metal connector, or the bit line inputs currents of different directions and sizes into the fourth MTJ, the third MTJ, the second MTJ and the first MTJ through the second metal connector, which will change the resistance state of the first MTJ, the second MTJ, the third MTJ and / or the fourth MTJ.

[0165] In the embodiment of the present application, the functions of the various components in the connection module and the signal module are as follows: Fig.11 The functions in the described embodiments are similar and will not be described in detail here.

[0166] In the embodiment of the present application, the switch element inputs currents of different directions and magnitudes into the first MTJ, the second MTJ and the third MTJ through the first metal connector, which changes the resistance state of the first MTJ, the second MTJ and / or the third MTJ. 3 resistance state, with N MTJs there will be 2 N The way in which the switch element changes its resistance state through current is similar to that in the above-mentioned embodiment. Figures 5 to 10 The method described is similar and will not be described in detail here.

[0167] In the embodiment of the present application, Fig.12 , Fig.13 as well as Fig.14The size relationship among the first MTJ, the second MTJ, and the third MTJ shown in FIG. 1 is only for illustration, and the specific size relationship is not limited here.

[0168] In the embodiments of the present application, the first MTJ, the second MTJ, the third MTJ and the fourth MTJ have a variety of reasonable arrangements, and the specific arrangements will be described in the following embodiments.

[0169] Fig.15 It is a schematic diagram of another embodiment of the storage unit provided in the embodiment of the present application.

[0170] 1. The lines connecting the center of the first MTJ, the center of the second MTJ, the center of the third MTJ, and the center of the fourth MTJ form a quadrilateral.

[0171] See also Fig.15 In the embodiment of the present application, the first MTJ, the second MTJ, the third MTJ and the fourth MTJ can be arranged in a quadrilateral manner, thereby reducing the space occupied by the four MTJs when arranged, and further reducing the size of the memory.

[0172] 2. The first metal line is parallel to the second metal line, and the lines connecting the center of the first MTJ, the center of the second MTJ, the center of the third MTJ, and the center of the fourth MTJ form a straight line.

[0173] Fig.16 It is a schematic diagram of another embodiment of the storage unit provided in the embodiment of the present application.

[0174] See also Fig.16 In the embodiment of the present application, the first MTJ, the second MTJ, the third MTJ and the fourth MTJ can be arranged in a straight line, thereby reducing the space occupied by the four MTJs when arranged, and further reducing the size of the memory.

[0175] In the embodiments of the present application, the bit lines, word lines and source lines have a variety of reasonable arrangements, and the specific arrangements will be described in the following embodiments.

[0176] 1. The bit line is parallel to the first metal line, the bit line is perpendicular to the word line, and the bit line is perpendicular to the source line.

[0177] In the embodiment of the present application, the solution including two MTJs in the storage unit is taken as an example for description. Fig.11In the embodiment, the bitline is parallel to the first metal line, the bit line is perpendicular to the word line, and the bit line is perpendicular to the source line. This can reduce the space occupied by the bit line, word line, and source line after arrangement, and further reduce the size of the memory.

[0178] In the embodiment of the present application, Fig.15 , Fig.16 The size relationship among the first MTJ, the second MTJ, the third MTJ and the fourth MTJ shown in FIG. 1 is only for illustration, and the specific size relationship is not limited here.

[0179] Fig.17 It is a schematic diagram of another embodiment of the storage unit provided in the embodiment of the present application.

[0180] 2. The bit line is perpendicular to the first metal line, the bit line is perpendicular to the word line, and the bit line is parallel to the source line.

[0181] In the embodiment of the present application, the solution including two MTJs in the storage unit is taken as an example for description. Fig.17 In the embodiment, the bitline is perpendicular to the first metal line, the bit line is perpendicular to the word line, and the bit line is parallel to the source line, which can reduce the space occupied by the bit line, word line and source line after arrangement, and further reduce the size of the memory.

[0182] In the embodiment of the present application, Fig.17 The first MTJ shown to be larger than the second MTJ is only for illustrative purposes. In actual applications, the first MTJ may be smaller than the second MTJ, or the second MTJ may be smaller than the first MTJ. The specific details are not limited here.

[0183] In the embodiment of the present application, the memory array includes a word line, a bit line, a source line and at least one memory cell. Optionally, a memory cell may include two MTJs, three MTJs, or N MTJs, and the series connection method of the N MTJs is similar to the series connection method described in the above embodiment, and is not specifically limited here.

[0184] The embodiment of the present application provides a memory cell, wherein the first electrode of the first MTJ included in the memory cell is connected in series with the first electrode of the second MTJ through a first metal wire, and the first electrode of the first MTJ and the first electrode of the second MTJ are electrodes of the same layer. That is, the first electrode of the first MTJ and the second electrode of the second MTJ are both top electrodes or bottom electrodes. After currents of different directions and sizes flow through the first MTJ and the second MTJ, the resistance state of the first MTJ and / or the second MTJ will be changed. Since the first MTJ and the second MTJ are connected to the same-layer electrodes, with the direction from the bottom electrode to the top electrode of the first MTJ and the second MTJ as the reference direction, the currents in the first MTJ and the second MTJ are equal in magnitude and opposite in direction, and the currents have opposite effects on the magnetic field directions of the free layers of the first MTJ and the second MTJ. Furthermore, polymorphic storage can be achieved by combining different resistance values ​​of the first MTJ and the second MTJ, thereby improving the storage efficiency of the memory.

[0185] The storage unit and memory provided in the embodiments of the present application are described in detail above. The principles and implementation methods of the present application are described in detail using specific examples herein. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for those skilled in the art, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as limiting the present application.

Claims

1. A storage unit, It is characterized in that The memory cell includes: a first magnetic tunnel junction MTJ, a second MTJ and a first metal line, and the first MTJ and the second MTJ have different sizes; The first MTJ and the second MTJ are connected in series via the first metal line; The first end of the first metal line is electrically connected to the first electrode of the first MTJ, the second end of the first metal line is electrically connected to the first electrode of the second MTJ, and the first electrode of the first MTJ and the first electrode of the second MTJ are both top electrodes or bottom electrodes; The first MTJ and the second MTJ are used for allowing currents of different directions and magnitudes to flow through them, so as to change the resistance state of the first MTJ and / or the second MTJ.

2. The storage unit according to claim 1, It is characterized in that The first MTJ and the second MTJ are located in the same layer of the stacked structure and are formed by one thin film deposition.

3. The storage unit according to claim 1 or 2, It is characterized in that The storage unit further includes a first metal connector, a second metal connector and a switch element; The second electrode of the first MTJ is electrically connected to the first end of the switching element through the first metal connector; The second electrode of the second MTJ is electrically connected to the bit line through the second metal connection member; The second end of the switch element is electrically connected to the source line; The control end of the switch element is electrically connected to the word line.

4. The storage unit according to claim 1 or 2, It is characterized in that The memory cell further includes a third MTJ, a first metal line, a second metal line, a first metal connection, a second metal connection, and a switch element; The second electrode of the first MTJ is electrically connected to the first end of the switching element through the first metal connector; The second MTJ and the third MTJ are connected in series via the second metal line; The first end of the second metal connection line is electrically connected to the second electrode of the second MTJ, the second end of the second metal connection line is electrically connected to the first electrode of the third MTJ, and the second electrode of the second MTJ and the first electrode of the third MTJ are both top electrodes or bottom electrodes; The second electrode of the third MTJ is electrically connected to the bit line through the second metal connection member; The second end of the switch element is electrically connected to the source line; The control end of the switch element is electrically connected to the word line.

5. The storage unit according to claim 4, It is characterized in that The angle between the first metal line and the second metal line is an acute angle, and the lines connecting the center of the first MTJ, the center of the second MTJ, and the center of the third MTJ form an acute triangle.

6. The storage unit according to claim 4, It is characterized in that The first metal line is parallel to the second metal line, and a connection line between the first MTJ, the second MTJ and the third MTJ forms a straight line.

7. The storage unit according to claim 1 or 2, It is characterized in that The memory cell further includes a second metal line, a third metal line, a third MTJ, a fourth MTJ, a first metal connection, a second metal connection, and a switch element. The second electrode of the first MTJ is electrically connected to the first end of the switching element through the first metal connector; The second MTJ and the third MTJ are connected in series via the second metal line; The first end of the second metal connection line is electrically connected to the second electrode of the second MTJ, the second end of the second metal connection line is electrically connected to the first electrode of the third MTJ, and the second electrode of the second MTJ and the first electrode of the third MTJ are both top electrodes or bottom electrodes; The third MTJ and the fourth MTJ are connected in series via the third metal line; The first end of the third metal connection line is electrically connected to the second electrode of the third MTJ, the second end of the third metal connection line is electrically connected to the first electrode of the fourth MTJ, and the second electrode of the third MTJ and the first electrode of the fourth MTJ are both top electrodes or bottom electrodes; The second end of the switch element is electrically connected to the source line; The control end of the switch element is electrically connected to the word line.

8. The storage unit according to claim 7, It is characterized in that Lines connecting the center of the first MTJ, the center of the second MTJ, the center of the third MTJ, and the center of the fourth MTJ form a quadrilateral.

9. The storage unit according to claim 7, It is characterized in that Lines connecting the center of the first MTJ, the center of the second MTJ, the center of the third MTJ, and the center of the fourth MTJ constitute a straight line.

10. The storage unit according to claim 4, It is characterized in that The bit line is parallel to the first metal line, the bit line is perpendicular to the word line, and the bit line is perpendicular to the source line.

11. The storage unit according to claim 4, It is characterized in that The bit line is perpendicular to the first metal line, the bit line is perpendicular to the word line, and the bit line is parallel to the source line.

12. A storage array, It is characterized in that include: word lines, bit lines, source lines and at least one memory cell; The storage unit is the storage unit according to any one of claims 1 to 11.

13. A memory, It is characterized in that include: Storage unit and controller; The storage unit stores data under the control of the controller, and the storage unit is the storage unit according to any one of claims 1 to 11.

14. A storage device, It is characterized in that include: Storage unit and controller; The storage unit stores data and / or calculates data under the control of the controller, and the storage unit is the storage unit according to any one of claims 1 to 11.

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