Display device

Abstract

A display device is provided. The display device includes a plurality of pixels arranged in a display area, wherein: each of the plurality of pixels includes: a first electrode and a second electrode separated from each other in a first direction; and at least one light emitting diode disposed between the first electrode and the second electrode and electrically connected to the first electrode and the second electrode; and a distance in the first direction between one end of the light emitting diode and one end of the second electrode is greater than a distance in the first direction between the other end of the light emitting diode and the one end of the first electrode.

Description

Technical Field

[0001] This disclosure relates to a display device. Background Technology

[0002] With increasing interest in information display and growing demand for portable information media, the need for and commercialization of display devices has become a focus. Summary of the Invention

[0003] Technical issues

[0004] The objective of this disclosure is to provide a display device capable of bias alignment and center alignment of light-emitting elements using a single alignment signal (or alignment voltage).

[0005] The purposes are not limited to those described above, and those skilled in the art will clearly understand other technical purposes not described in the following description.

[0006] Technical solution

[0007] According to embodiments of the present disclosure, in order to achieve the above objective, a display device includes a plurality of pixels disposed in a display area, each of the plurality of pixels including: a first electrode and a second electrode, spaced apart from each other in a first direction; and at least one light-emitting element disposed between the first electrode and the second electrode and electrically connected to the first electrode and the second electrode, wherein the distance between one end of the light-emitting element and one end of the second electrode in the first direction is greater than the distance between the other end of the light-emitting element and one end of the first electrode in the first direction.

[0008] The width of the second electrode in the first direction may be greater than the width of the first electrode in the first direction.

[0009] The light-emitting element may include: a first semiconductor layer; a second semiconductor layer; and an active layer disposed between the first semiconductor layer and the second semiconductor layer. The first semiconductor layer may be electrically connected to a second electrode, and the second semiconductor layer may be electrically connected to a first electrode.

[0010] The first semiconductor layer may be stacked with the second electrode, and the second semiconductor layer may be stacked with the first electrode.

[0011] The area where the second electrode and the first semiconductor layer are stacked can be larger than the area where the first electrode and the second semiconductor layer are stacked.

[0012] The distance between the active layer and one end of the first electrode in the first direction can be substantially the same as the distance between the active layer and one end of the second electrode in the first direction.

[0013] The plurality of pixels may further include: a first dam pattern disposed below and superimposed on the first electrode; and a second dam pattern disposed below and superimposed on the second electrode.

[0014] The distance between one end of the second electrode and one end of the second embankment pattern in the first direction can be greater than the distance between one end of the first electrode and one end of the first embankment pattern in the first direction.

[0015] The distance between one end of the light-emitting element and one end of the second embankment pattern in the first direction can be substantially the same as the distance between the other end of the light-emitting element and one end of the first embankment pattern in the first direction.

[0016] The light-emitting element may include: a first semiconductor layer; a second semiconductor layer; and an active layer disposed between the first semiconductor layer and the second semiconductor layer, wherein the distance between one end of the second embankment pattern and the active layer in a first direction may be greater than the distance between one end of the first embankment pattern and the active layer in the first direction.

[0017] According to another embodiment of this disclosure, in order to achieve the above objective, the display device may include a plurality of pixels disposed in a display area, each of the plurality of pixels may include: a first electrode and a second electrode, separated from each other in a first direction; at least one intermediate electrode, disposed between the first electrode and the second electrode; a first light-emitting element, disposed between the intermediate electrode and the first electrode; and a second light-emitting element, disposed between the intermediate electrode and the second electrode, wherein the area of ​​the intermediate electrode and the first light-emitting element overlapping may be greater than the area of ​​the intermediate electrode and the second light-emitting element overlapping.

[0018] Each of the first light-emitting element and the second light-emitting element may include: a first semiconductor layer; a second semiconductor layer; and an active layer disposed between the first semiconductor layer and the second semiconductor layer.

[0019] The intermediate electrode can be stacked with the first semiconductor layer of the first light-emitting element.

[0020] The intermediate electrode can be stacked with the second semiconductor layer of the second light-emitting element.

[0021] The distance in the first direction between one end of the intermediate electrode and one end of the first semiconductor layer of the first light-emitting element can be greater than the distance in the first direction between the other end of the intermediate electrode and one end of the second semiconductor layer of the second light-emitting element.

[0022] The distance between one end of the intermediate electrode and the active layer of the first light-emitting element in the first direction can be substantially the same as the distance between the other end of the intermediate electrode and the active layer of the second light-emitting element in the first direction.

[0023] Multiple pixels may also include a dam pattern set below the central electrode.

[0024] The distance between one end of the intermediate electrode and one end of the embankment pattern in the first direction can be greater than the distance between the other end of the intermediate electrode and the other end of the embankment pattern in the first direction.

[0025] The distance between one end of the embankment pattern and one end of the first light-emitting element in the first direction can be substantially the same as the distance between the other end of the embankment pattern and one end of the second light-emitting element in the first direction.

[0026] Each of the first light-emitting element and the second light-emitting element may include: a first semiconductor layer; a second semiconductor layer; and an active layer disposed between the first semiconductor layer and the second semiconductor layer, wherein the distance between the active layer of the first light-emitting element and one end of the embankment pattern in a first direction may be greater than the distance between the active layer of the second light-emitting element and the other end of the embankment pattern in the first direction.

[0027] Details of other embodiments are included in the detailed description and accompanying drawings.

[0028] Beneficial effects

[0029] According to an embodiment, by asymmetrically designing the alignment electrodes, a single alignment signal can be used to center-align the light-emitting element. That is, since a separate center alignment signal can be omitted, the alignment signal can be simplified, and the contact area between the light-emitting element and the contact electrode can be reliably ensured through center alignment.

[0030] The effects of the embodiments are not limited to the above-described examples, and many more different effects are included in this specification. Attached Figure Description

[0031] Figures 1 to 6 These are perspective and cross-sectional views of the light-emitting element according to an embodiment.

[0032] Figure 7 This is a plan view of a display device according to an embodiment.

[0033] Figures 8 to 11 These are circuit diagrams illustrating pixels according to an embodiment.

[0034] Figure 12 This is a plan view showing pixels according to an embodiment.

[0035] Figure 13 and Figure 14 It is along Figure 12 A sectional view taken by line A-A'.

[0036] Figure 15 yes Figure 13 An enlarged sectional view of region A.

[0037] Figure 16 This is a plan view of pixels according to another embodiment.

[0038] Figure 17 and Figure 18 It is along Figure 16 The sectional view taken by line B-B'.

[0039] Figure 19 This is a plan view of pixels according to yet another embodiment.

[0040] Figure 20 and Figure 21 It is along Figure 19 A sectional view taken by line C-C'.

[0041] Figure 22 This is a plan view of pixels according to another embodiment.

[0042] Figure 23 and Figure 24 It is along Figure 22 A sectional view taken by line D-D'. Detailed Implementation

[0043] See below and appendix Figure 1 The embodiments, advantages, features, and methods of implementing them described in detail will become apparent. However, this disclosure is not limited to the embodiments disclosed below and can be implemented in a variety of different forms. This disclosure is provided so that it is thorough and complete, and that those skilled in the art to which this disclosure pertains will fully understand its scope. This disclosure is limited only by the scope of the claims.

[0044] The use of the term "on" another element or layer to refer to an element or layer includes cases where the element or layer is disposed directly on said other element or layer, or where another layer or element is disposed between these elements or layers. Throughout this specification, the same reference numerals refer to the same reference components.

[0045] Although terms such as "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, within the spirit of the art, the first component described below can be the second component. Unless the context clearly specifies otherwise, singular expressions include plural expressions.

[0046] In the following description, embodiments are illustrated with reference to the accompanying drawings. The same or similar reference numerals are used for the same components in the drawings.

[0047] Figures 1 to 6These are perspective and cross-sectional views of the light-emitting element according to an embodiment.

[0048] Figures 1 to 6 A cylindrical rod-shaped light-emitting element (LD) is shown, but the type and / or shape of the light-emitting element (LD) is not limited to this.

[0049] First, refer to Figure 1 and Figure 2 According to an embodiment, the light-emitting element LD includes a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 disposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, the light-emitting element LD may include a first semiconductor layer 11, an active layer 12, and a second semiconductor layer 13 stacked sequentially along a length L direction.

[0050] According to an embodiment, the light-emitting element LD can be configured as a rod shape extending along one direction. When the extending direction of the light-emitting element LD is referred to as the length L direction, the light-emitting element LD can have one end and another end along the length L direction.

[0051] According to an embodiment, one of the first semiconductor layer 11 and the second semiconductor layer 13 may be disposed at one end of the light-emitting element LD. Alternatively, the other of the first semiconductor layer 11 and the second semiconductor layer 13 may be disposed at the other end of the light-emitting element LD.

[0052] According to an embodiment, the light-emitting element LD can be a rod-shaped light-emitting diode manufactured in a rod shape. In this specification, the term "rod-shaped" includes rod-shaped or strip-shaped (such as cylindrical or polygonal prisms) shapes that are long (i.e., have an aspect ratio greater than 1) in the length L direction, and the shape of its cross-section is not particularly limited. For example, the length L of the light-emitting element LD can be greater than its diameter D (or the width of its cross-section).

[0053] According to embodiments, the light-emitting element (LD) can have dimensions ranging from nanometer to micrometer (nanometer to micrometer). For example, the LD can have a diameter D and / or a length L ranging from nanometer to micrometer. However, in this disclosure, the size of the LD is not limited to this. For example, the size of the LD can vary depending on the design conditions of various devices (e.g., display devices) that use the LD as a light source.

[0054] The first semiconductor layer 11 may include, for example, at least one N-type semiconductor layer. For instance, the first semiconductor layer 11 may include any one of the semiconductor materials InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include an N-type semiconductor layer doped with a first dopant such as Si, Ge, or Sn. However, the materials used to construct the first semiconductor layer 11 are not limited to these; various other materials may be used to construct the first semiconductor layer 11.

[0055] The active layer 12 can be disposed on the first semiconductor layer 11 and can be formed in a single quantum well or multiple quantum well (MQW) structure. In embodiments, a capping layer (not shown) doped with a conductive dopant can be formed on and / or under the active layer 12. For example, the capping layer can be formed of an AlGaN layer or an InAlGaN layer. According to embodiments, materials such as AlGaN and InAlGaN can be used to form the active layer 12, and various other materials can be used to construct the active layer 12.

[0056] When a voltage equal to or greater than the threshold voltage is applied across the light-emitting element (LD), the LD emits light while electron-hole pairs combine in the active layer 12. By controlling the emission of the LD using this principle, the LD can be used as a light source for various light-emitting devices, including pixels in display devices.

[0057] The second semiconductor layer 13 may be disposed on the active layer 12 and may include a semiconductor layer of a different type than the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one P-type semiconductor layer. For example, the second semiconductor layer 13 may include at least one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a P-type semiconductor layer doped with a second dopant such as Mg. However, the materials used to construct the second semiconductor layer 13 are not limited to these, and various other materials may be used to construct the second semiconductor layer 13.

[0058] The thicknesses of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 can be different from each other. Here, the thicknesses of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 can refer to their thicknesses in the length L direction. In an embodiment, the thickness of the first semiconductor layer 11 can be greater than the thickness of the second semiconductor layer 13. Due to the thickness difference between the first semiconductor layer 11 and the second semiconductor layer 13, the active layer 12 may not be disposed at the center of the light-emitting element LD. Therefore, when aligning the light-emitting element LD using the permanent dipole of the active layer 12, the center alignment of the light-emitting element LD may not occur smoothly due to the eccentricity of the active layer 12. Therefore, the display device according to the embodiment can take into account the eccentricity of the active layer 12 in the light-emitting element LD by asymmetrically designing the alignment electrodes to use a single alignment signal to center-align the light-emitting element LD. Refer to later. Figures 12 to 15 Describe it in detail.

[0059] The light-emitting element (LD) may further include an insulating layer INF disposed on its surface. The insulating layer INF may be formed on the surface of the LD to at least surround the outer circumferential surface of at least the active layer 12, and may also surround a region of the first semiconductor layer 11 and the second semiconductor layer 13. However, the insulating layer INF may expose the two ends of the LD that have different polarities. For example, the insulating layer INF may not cover and may expose one end of each of the first semiconductor layer 11 and the second semiconductor layer 13 located at both ends of the LD in the length L direction, for example, the two bottom surfaces of a cylinder (…). Figure 1 and Figure 2 (The upper and lower surfaces of the light-emitting element LD in the image). In some other embodiments, the insulating layer INF may expose the two ends of the light-emitting element LD with different polarities and the sides of the semiconductor layers 11 and 13 adjacent to the two ends.

[0060] According to an embodiment, the insulating layer INF may include silicon nitride (SiN). x ), silicon dioxide (SiO) x ), aluminum oxide (AlO) x ) and titanium dioxide (TiO) x The insulating layer INF may be any one of the following insulating materials, but is not limited thereto. That is, there are no particular restrictions on the material in which the insulating layer INF is constructed, and the insulating layer INF may be formed from various currently known insulating materials.

[0061] In embodiments, in addition to the first semiconductor layer 11, active layer 12, second semiconductor layer 13, and / or insulating layer INF, the light-emitting element LD may also include additional components. For example, the light-emitting element LD may additionally include one or more phosphor layers, active layers, semiconductor layers, and / or electrode layers disposed on one end side of the first semiconductor layer 11, active layer 12, and / or second semiconductor layer 13.

[0062] For example, such as Figure 3 and Figure 4 As shown, the light-emitting element LD may further include at least one additional electrode 14 disposed on one end side of the second semiconductor layer 13. Additionally, according to an embodiment, as... Figure 5 and Figure 6 As shown, the light-emitting element LD may further include at least one additional electrode 15 disposed on one end side of the first semiconductor layer 11. Figure 3 and Figure 5 For ease of description, a portion of the insulating layer INF has been omitted.

[0063] Each of the additional electrodes 14 and 15 may be an ohmic contact electrode, but is not limited thereto. According to an embodiment, the additional electrodes 14 and 15 may be Schottky electrodes. Additionally, each of the additional electrodes 14 and 15 may comprise a metal or a metal oxide. For example, each of the additional electrodes 14 and 15 may be formed individually or in combination using chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), their oxides or alloys, transparent electrode materials (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium tin zinc oxide (ITZO)). Furthermore, according to an embodiment, the additional electrodes 14 and 15 may be substantially transparent or translucent. Therefore, light generated from the light-emitting element LD can pass through the additional electrodes 14 and 15 and can be emitted to the outside of the light-emitting element LD.

[0064] According to an embodiment, the insulating layer INF may or may not at least partially surround the outer circumferential surfaces of the additional electrodes 14 and 15. That is, the insulating layer INF may be selectively formed on the surfaces of the additional electrodes 14 and 15. Additionally, the insulating layer INF may be formed to expose the two ends of the light-emitting element LD with different polarities; for example, the insulating layer INF may expose at least one region of the additional electrodes 14 and 15. According to an embodiment, the insulating layer INF may have a curved shape in the corner region adjacent to the additional electrodes 14 and 15. The curved surface can be formed by etching when manufacturing the light-emitting element LD. In another embodiment, the insulating layer INF may not be provided.

[0065] When the insulating layer INF is disposed on the surface of the light-emitting element LD (specifically, the surface of the active layer 12), short circuits between the active layer 12 and at least one electrode (not shown) (e.g., at least one of the contact electrodes connected to both ends of the light-emitting element LD) can be prevented. Therefore, the electrical stability of the light-emitting element LD can be ensured. In describing each embodiment, the term "connection (or access)" can refer generally to physical and / or electrical connection (or access). Furthermore, this can refer generally to direct and / or indirect connection (or access) and integral or non-integral connection (or access).

[0066] Furthermore, since the insulating layer INF is formed on the surface of the light-emitting element (LD), surface defects of the LD can be minimized, thus improving lifespan and efficiency. Additionally, when the insulating layer INF is formed on the surface of each LD, unwanted short circuits between the LDs can be prevented even when multiple LDs are placed close to each other.

[0067] Additionally, in this embodiment, the light-emitting element (LD) can be manufactured using a surface treatment process. For example, a surface treatment can be performed on each LD such that when multiple LDs are mixed in a fluid solution (or solvent) and supplied to each emission region (e.g., the emission region of each pixel), the LDs can be uniformly dispersed in the solution without uneven aggregation.

[0068] As a related non-limiting embodiment, the insulating layer INF itself can be formed as a hydrophobic layer using a hydrophobic material, or a hydrophobic layer formed of a hydrophobic material can be additionally formed on the insulating layer INF. According to embodiments, the hydrophobic material can be a material containing fluorine to exhibit hydrophobicity. Additionally, according to embodiments, the hydrophobic material can be applied to the light-emitting element LD in the form of a self-assembled monolayer (SAM). In this case, the hydrophobic material can include octadecyltrichlorosilane, fluoroalkyltrichlorosilane, perfluoroalkyltriethoxysilane, etc. Alternatively, the hydrophobic material can be a commercially available fluorinated material (such as Teflon). TM ) or Cytop TM (or its corresponding materials.)

[0069] Light-emitting devices including the aforementioned light-emitting elements (LDs) can be used in various types of devices requiring a light source, including display devices. For example, at least one ultra-small light-emitting element (LD) (e.g., multiple ultra-small light-emitting elements (LDs) each having a size ranging from nanometers to micrometers) can be disposed in each pixel area of ​​a display panel, and the ultra-small light-emitting elements (LDs) can be used to construct the light source (or light source unit) for each pixel. However, in this disclosure, the application of light-emitting elements (LDs) is not limited to display devices. For example, light-emitting elements (LDs) can be used in other types of devices requiring a light source (such as lighting devices).

[0070] Figure 7 This is a plan view of a display device according to an embodiment.

[0071] According to an embodiment, Figure 7 A display device (specifically, a display panel PNL included in the display device) is shown as a device that can be used. Figures 1 to 6 The light-emitting element (LD) described herein is an example of a device that serves as a light source. For example, each of the pixels PXL in a display panel PNL may include at least one light-emitting element (LD).

[0072] For convenience, Figure 7 The structure of the display panel PNL is briefly shown based on the display area DA. However, according to an embodiment, at least one driving circuit unit (e.g., at least one of a scan driver and a data driver) and / or multiple lines, not shown, may also be provided in the display panel PNL.

[0073] Reference Figure 7 According to an embodiment, the display panel PNL may include a substrate layer BSL and a plurality of pixels PXL disposed on the substrate layer BSL. Specifically, the display panel PNL and the substrate layer BSL for forming the display panel PNL may include a display area DA for displaying an image and a non-display area NDA other than the display area DA. In addition, the pixels PXL may be disposed on the substrate layer BSL in the display area DA.

[0074] According to an embodiment, the display area DA can be located in the central area of ​​the display panel PNL, and the non-display area NDA can be located in the edge area of ​​the display panel PNL to surround the display area DA. However, the positions of the display area DA and the non-display area NDA are not limited to this, and the positions of the display area DA and the non-display area NDA can be changed. The display area DA can be configured as a screen on which an image is displayed.

[0075] The substrate layer (BSL) can constitute the substrate component of the display panel (PNL). According to embodiments, the substrate layer (BSL) can be a rigid or flexible substrate or film, and its material or properties are not particularly limited. For example, the substrate layer (BSL) can be a rigid substrate formed of glass or tempered glass, a flexible substrate (or film) of plastic or metallic material, or at least an insulating layer, and its material and / or physical properties are not particularly limited.

[0076] In addition, the substrate layer (BSL) can be transparent, but is not limited to this. For example, the substrate layer (BSL) can be a transparent, translucent, opaque, or reflective substrate component.

[0077] A region on the substrate layer BSL can be defined as a display region DA and can house pixels PXL, while the remaining region can be defined as a non-display region NDA. For example, the substrate layer BSL may include a display region DA and a non-display region NDA. The display region DA includes multiple pixel regions in which each pixel PXL is formed, and the non-display region NDA is located outside the display region DA. Various lines and / or built-in circuit units connected to the pixels PXL in the display region DA can be located in the non-display region NDA.

[0078] According to an embodiment, pixels PXL can be disposed in each pixel region of the display area DA. In an embodiment, pixels PXL can be arranged in the display area DA in a stripe or penTile arrangement structure, but are not limited thereto. For example, pixels PXL can be arranged in the display area DA in various currently known arrangement structures.

[0079] Each pixel PXL may include at least one light source driven by a predetermined control signal (e.g., scan signal and data signal) and / or a predetermined power supply (e.g., a first power supply and a second power supply). For example, each pixel PXL may include according to... Figures 1 to 6 The light-emitting element (LD) in any of the embodiments is, for example, at least one ultra-miniature rod-shaped light-emitting element (LD) having dimensions from the nanometer to the micrometer scale. However, in the embodiments, the type of light-emitting element (LD) that can be used as the light source for the pixel PXL is not limited thereto. For example, in another embodiment, each pixel PXL may include a core-shell structured light-emitting element manufactured by a growth method. In the embodiments, the core-shell structured light-emitting element may be an ultra-miniature core-shell structured light-emitting element having dimensions from the nanometer to the micrometer scale, but the size of the core-shell structured light-emitting element is not limited.

[0080] In this embodiment, each pixel PXL can be configured as an active pixel. However, there are no specific limitations on the type, structure, and / or driving method of the pixel PXL that can be applied to the display device. For example, each pixel PXL can be configured as a pixel of a passive or active light-emitting display device with various currently known structures and / or driving methods.

[0081] Figures 8 to 11 These are circuit diagrams illustrating pixels according to an embodiment.

[0082] For example, Figures 8 to 11 Different embodiments of the pixel PXL that can be applied to an active display device are shown. However, the types of pixels PXL and display devices to which these embodiments can be applied are not limited to these. According to the embodiments, Figures 8 to 11 Each pixel PXL shown can be included in Figure 7Any one of the pixels PXL in the display panel PNL, and the pixels PXL can have substantially the same or similar structure to each other.

[0083] First refer to Figure 8 According to an embodiment, pixel PXL includes a light source unit LSU for generating light with a brightness corresponding to a data signal. Additionally, pixel PXL may optionally include pixel circuitry PXC for driving the light source unit LSU.

[0084] According to an embodiment, the light source unit (LSU) may include a plurality of light-emitting elements (LDs) connected between a first power supply (VDD) and a second power supply (VSS). For example, the LSU may include a first electrode ET1 connected to the first power supply (VDD) via a pixel circuit (PXC) and a first power line (PL1), a second electrode ET2 connected to the second power supply (VSS) via a second power line (PL2), and a plurality of light-emitting elements (LDs) connected in parallel in the same direction between the first electrode ET1 and the second electrode ET2. In this embodiment, the first electrode ET1 may be an anode electrode, and the second electrode ET2 may be a cathode electrode.

[0085] According to an embodiment, each of the light-emitting elements (LDs) may include a P-type terminal connected to a first power supply VDD via a first electrode ET1 and an N-type terminal connected to a second power supply VSS via a second electrode ET2. That is, the light-emitting elements (LDs) may be connected in parallel in the forward direction between the first electrode ET1 and the second electrode ET2. As described above, each light-emitting element (LD) connected in the forward direction between the first power supply VDD and the second power supply VSS can constitute each effective light source, and these effective light sources can be aggregated to construct the light source unit (LSU) of pixel PXL.

[0086] According to an embodiment, the first power supply VDD and the second power supply VSS can have different potentials, causing the light-emitting element LD to emit light. For example, the first power supply VDD can be set to a high potential power supply, and the second power supply VSS can be set to a low potential power supply. In this case, during at least the emission period of pixel PXL, the potential difference between the first power supply VDD and the second power supply VSS can be set to be greater than or equal to the threshold voltage of the light-emitting element LD.

[0087] According to an embodiment, the P-type terminal of the light-emitting element LD that constitutes each light source unit LSU can be connected to the pixel circuit PXC through one electrode of the light source unit LSU (e.g., the first electrode ET1 of each pixel PXL) (also referred to as the "first pixel electrode" or "first alignment electrode"), and can be connected to the first power supply VDD through the pixel circuit PXC and the first power line PL1. Additionally, the N-type terminal of the light-emitting element LD can be connected to the second power supply VSS through another electrode of the light source unit LSU (e.g., the second electrode ET2 of each pixel PXL) (also referred to as the "second pixel electrode" or "second alignment electrode") and the second power line PL2.

[0088] The light-emitting elements (LDs) of the light source unit (LSU) can emit light with a brightness corresponding to the drive current supplied through the corresponding pixel circuit (PXC). For example, during each frame period, the pixel circuit (PXC) can supply a drive current corresponding to the grayscale value of the corresponding frame data to the light source unit (LSU). The drive current supplied to the light source unit (LSU) can be divided and can flow through the light-emitting elements (LDs) connected in the forward direction. Therefore, the light source unit (LSU) can emit light with a brightness corresponding to the drive current, while each light-emitting element (LD) emits light with a brightness corresponding to the current flowing through it.

[0089] The pixel circuit PXC can be connected to the scan line Si and data line Dj of the corresponding pixel PXL. For example, assuming that pixel PXL is located in the i-th (i is a positive integer) row and j-th (j is a positive integer) column of display area DA, then the pixel circuit PXC of pixel PXL can be connected to the i-th scan line Si and the j-th data line Dj of display area DA. According to an embodiment, the pixel circuit PXC may include a first transistor T1, a second transistor T2, and a storage capacitor Cst.

[0090] The first transistor T1 (also called the "driving transistor") is connected between the first power supply VDD and the light source unit LSU. Additionally, the gate electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 controls the driving current supplied to the light source unit LSU in response to the voltage at the first node N1.

[0091] A second transistor T2 (also called a "switching transistor") is connected between the data line Dj and the first node N1. Additionally, the gate electrode of the second transistor T2 is connected to the scan line Si. When a scan signal with a gate turn-on voltage (e.g., a low-level voltage) is supplied from the scan line Si, the second transistor T2 turns on, electrically connecting the data line Dj and the first node N1.

[0092] In each frame cycle, the data signal of the corresponding frame is supplied to the data line Dj, and the data signal is transmitted to the first node N1 via the second transistor T2. Therefore, the voltage corresponding to the data signal charges the storage capacitor Cst.

[0093] One electrode of the storage capacitor Cst is connected to the first power supply VDD, and the other electrode is connected to the first node N1. During each frame period, the storage capacitor Cst is charged with a voltage corresponding to the data signal supplied to the first node N1.

[0094] At the same time, Figure 8 In the pixel circuit PXC, all transistors (e.g., first transistor T1 and second transistor T2) are P-type transistors, but this disclosure is not limited thereto. That is, at least one of the first transistor T1 and the second transistor T2 can be changed to an N-type transistor.

[0095] For example, such as Figure 9 As shown, both the first transistor T1 and the second transistor T2 can be N-type transistors. In this case, the gate turn-on voltage for writing the data signal supplied to the data line Dj to the scan signal of pixel PXL in each frame cycle can be a high-level voltage (also referred to as "gate high voltage"). Similarly, the voltage of the data signal used to turn on the first transistor T1 can be... Figure 8 The voltage level is opposite to the level of the embodiment. For example, in Figure 9 In one embodiment, when the grayscale value to be expressed increases, a higher voltage data signal can be supplied.

[0096] In this embodiment, the interconnection positions of the pixel circuit PXC and the light source unit LSU can be changed. For example, as... Figure 9 As shown, when all of the first transistor T1 and the second transistor T2 in the pixel circuit PXC are N-type transistors, the pixel circuit PXC can be connected between the light source unit LSU and the second power supply VSS, and the storage capacitor Cst can be connected between the first node N1 and the second power supply VSS. However, this disclosure is not limited thereto. For example, in another embodiment, even if the pixel circuit PXC is constructed of N-type transistors, the pixel circuit PXC can still be connected between the first power supply VDD and the light source unit LSU, and the storage capacitor Cst can also be connected between the first node N1 and the first power supply VDD.

[0097] Aside from the fact that the connection positions of some circuit elements and the voltage levels of control signals (e.g., scan signals and data signals) change depending on the type of transistor, Figure 9 The construction and operation of pixel PXL shown are similar to Figure 8 The construction and operation of the pixel PXL are basically similar. Therefore, omit... Figure 9 Detailed description of the pixel PXL.

[0098] Meanwhile, the structure of the pixel circuit PXC is not limited to Figure 8 and Figure 9 The embodiment shown illustrates this. That is, the pixel circuit PXC can be constructed using various currently known pixel circuit structures and / or driving methods. For example, the pixel circuit PXC can be as follows: Figure 10 It is constructed as shown in the embodiment.

[0099] Reference Figure 10 In addition to the corresponding horizontal scan line Si, the pixel circuit PXC can also be connected to at least one other scan line (or control line). For example, the pixel circuit PXC of pixel PXL located in the i-th row of display area DA can also be connected to the (i-1)-th scan line Si-1 and / or the (i+1)-th scan line Si+1. Furthermore, according to an embodiment, in addition to the first power supply VDD and the second power supply VSS, the pixel circuit PXC can also be connected to a third power supply. For example, the pixel circuit PXC can also be connected to the initialization power supply Vint. According to an embodiment, the pixel circuit PXC may include first transistors T1 to seventh transistors T7 and a storage capacitor Cst.

[0100] The first transistor T1 is connected between the first power supply VDD and the light source unit LSU. For example, one electrode of the first transistor T1 (e.g., the source electrode) can be connected to the first power supply VDD via the fifth transistor T5 and the first power line PL1, and the other electrode of the first transistor T1 (e.g., the drain electrode) can be connected to an electrode of the light source unit LSU (e.g., the first pixel electrode and / or the first contact electrode of the corresponding pixel PXL) via the sixth transistor T6. Additionally, the gate electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 controls the drive current supplied to the light source unit LSU in response to the voltage of the first node N1.

[0101] A second transistor T2 is connected between the data line Dj and one electrode of the first transistor T1. Furthermore, the gate electrode of the second transistor T2 is connected to the corresponding scan line Si. When a scan signal with a gate-on voltage is supplied from the scan line Si, the second transistor T2 is turned on to electrically connect the data line Dj to the first electrode of the first transistor T1. Therefore, when the second transistor T2 is turned on, the data signal supplied from the data line Dj is transmitted to the first transistor T1.

[0102] The third transistor T3 is connected between the other electrode of the first transistor T1 and the first node N1. Furthermore, the gate electrode of the third transistor T3 is connected to the corresponding scan line Si. When a scan signal supplying a gate-on voltage is received from the scan line Si, the third transistor T3 is turned on, thereby connecting to the first transistor T1 in a diode-like manner.

[0103] A fourth transistor T4 is connected between the first node N1 and the initialization power supply Vint. Additionally, the gate electrode of the fourth transistor T4 is connected to the previous scan line (e.g., the (i-1)th scan line Si-1). When a scan signal with a gate-on voltage is supplied to the (i-1)th scan line Si-1, the fourth transistor T4 is turned on to transmit the voltage of the initialization power supply Vint to the first node N1. According to an embodiment, when the first transistor T1 is a P-type transistor, the voltage of the initialization power supply Vint used to initialize the gate voltage of the first transistor T1 can be less than or equal to the minimum voltage of the data signal.

[0104] The fifth transistor T5 is connected between the first power supply VDD and the first transistor T1. Additionally, the gate electrode of the fifth transistor T5 is connected to the corresponding emitter control line (e.g., the i-th emitter control line Ei). The fifth transistor T5 is turned off when an emitter control signal with a gate cutoff voltage (e.g., a high-level voltage) is supplied to the emitter control line Ei, and is turned on under other conditions.

[0105] The sixth transistor T6 is connected between the first transistor T1 and the light source unit LSU. Additionally, the gate electrode of the sixth transistor T6 is connected to the corresponding emission control line (e.g., the i-th emission control line Ei). The sixth transistor T6 is turned off when the emission control signal with the gate cutoff voltage is supplied to the emission control line Ei, and is turned on under other conditions.

[0106] A seventh transistor T7 is connected between an electrode of the light source unit LSU (e.g., the first pixel electrode ET1 of the corresponding pixel PXL) and the initialization power supply Vint. Additionally, the gate electrode of the seventh transistor T7 is connected to any of the scan lines of the next level (the next horizontal pixel column) (e.g., the (i+1)th scan line Si+1). When a scan signal with a gate-on voltage is supplied to the (i+1)th scan line Si+1, the seventh transistor T7 is turned on to supply the voltage of the initialization power supply Vint to an electrode of the light source unit LSU. Therefore, during each initialization period in which the voltage of the initialization power supply Vint is transmitted to the light source unit LSU, the voltage of an electrode of the light source unit LSU is initialized. Simultaneously, the control signal used to control the operation of the seventh transistor T7 can be varied. For example, in another embodiment, the gate electrode of the seventh transistor T7 can be connected to the scan line of the corresponding horizontal line (i.e., the i-th scan line Si). In this case, when a scan signal with a gate-on voltage is supplied to the i-th scan line Si, the seventh transistor T7 can be turned on to supply the voltage of the initialization power supply Vint to an electrode of the light source unit LSU.

[0107] The storage capacitor Cst is connected between the first power supply VDD and the first node N1. In each frame period, the storage capacitor Cst stores the data signal supplied to the first node N1 and the voltage corresponding to the threshold voltage of the first transistor T1.

[0108] At the same time, Figure 10 In the pixel circuit PXC, all transistors (e.g., first transistor T1 to seventh transistor T7) are P-type transistors, but this disclosure is not limited thereto. For example, at least one of the first transistor T1 to seventh transistor T7 may be changed to an N-type transistor.

[0109] in addition, Figures 8 to 10 An embodiment in which all effective light sources (i.e., light-emitting elements LD) constructing each light source unit (LSU) are connected in parallel is shown, but this disclosure is not limited thereto. For example, in another embodiment, such as Figure 11 As shown, the light source unit (LSU) of each pixel PXL can be constructed to include a series connection structure. In the description... Figure 11 In the embodiments, the following are omitted: Figures 8 to 10 A detailed description of embodiments with similar or identical constructions (e.g., pixel circuits PXC).

[0110] Reference Figure 11A light source unit (LSU) may include at least two light-emitting elements connected in series with each other. For example, a light source unit (LSU) may include a first light-emitting element LD1, a second light-emitting element LD2, and a third light-emitting element LD3 connected in series in the forward direction between a first power supply VDD and a second power supply VSS to construct each effective light source. In the following text, when referring to a specific light-emitting element among the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3, the corresponding light-emitting element is referred to as "first light-emitting element LD1," "second light-emitting element LD2," or "third light-emitting element LD3." Furthermore, when referring to at least one of the first light-emitting elements LD1, the second light-emitting element LD2, and the third light-emitting element LD3, or referring to the first light-emitting elements LD1, the second light-emitting element LD2, and the third light-emitting element LD3 in general, the at least one of the first light-emitting elements LD1, the second light-emitting element LD2, and the third light-emitting element LD3, or the first light-emitting elements LD1, the second light-emitting element LD2, and the third light-emitting element LD3, is referred to as "light-emitting element LD" or "multiple light-emitting elements LD."

[0111] The P-type terminal of the first light-emitting element LD1 can be connected to the first power supply VDD through the first electrode ET1 of the light source unit LSU, and the N-type terminal of the first light-emitting element LD1 can be connected to the P-type terminal of the second light-emitting element LD2 through the first intermediate electrode IET1. The P-type terminal of the second light-emitting element LD2 can be connected to the N-type terminal of the first light-emitting element LD1, and the N-type terminal of the second light-emitting element LD2 can be connected to the P-type terminal of the third light-emitting element LD3 through the second intermediate electrode IET2. The P-type terminal of the third light-emitting element LD3 can be connected to the N-type terminal of the second light-emitting element LD2, and the N-type terminal of the third light-emitting element LD3 can be connected to the second power supply VSS through the second electrode ET2 of the light source unit LSU and the second power supply line PL2. In the described method, the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can be sequentially connected in series between the first electrode ET1 and the second electrode ET2 of the light source unit LSU.

[0112] At the same time, Figure 11 The illustration shows an embodiment in which the light-emitting elements (LDs) are connected in a three-stage series structure, but this disclosure is not limited thereto. For example, in another embodiment, two light-emitting elements (LDs) may be connected in a two-stage series structure, or four or more light-emitting elements (LDs) may be connected in a four-stage or more series structure.

[0113] Assuming that light-emitting elements (LDs) with identical conditions (e.g., identical size and / or number) represent the same brightness, in a light source unit (LSU) with LDs connected in series, the voltage applied between the first electrode ET1 and the second electrode ET2 can be increased, and the magnitude of the drive current flowing through the light source unit (LSU) can be decreased, compared to a light source unit (LSU) with LDs connected in parallel. Therefore, when constructing the light source unit (LSU) for each pixel PXL using a series connection structure of LDs, the panel current flowing through the display panel (PNL) can be reduced when the display device is driven. Thus, efficiency can be improved by reducing power loss, and power consumption can be reduced. Furthermore, when the magnitude of the drive current supplied to the light source unit (LSU) to represent each grayscale is reduced, the size of the driving transistor (e.g., the first transistor T1) and / or the output buffer (e.g., the amplifier circuit for each channel) of the pixel PXL can be reduced.

[0114] Furthermore, in a light source unit LSU in which the light-emitting elements (LDs) are connected in parallel only, when a short-circuit defect occurs in at least one of the LDs, the driving current may not flow smoothly through the remaining LDs because the driving current will flow through the defective LD. Therefore, dark spot defects may occur. On the other hand, in a light source unit LSU in which the LDs are connected in a series structure of at least two stages, even if a short-circuit defect occurs in some of the series stages, the remaining LDs can still emit light when the driving current flows through them.

[0115] As in the embodiments described above, the pixel PXL may include pixel circuits PXC and / or light source units LSU of various structures. However, the structure of the pixel PXL applicable to this disclosure is not limited to... Figures 8 to 11 The embodiments shown are illustrated, and each pixel PXL can have various currently known structures. For example, the pixel circuit PXC included in each pixel PXL can be constructed using pixel circuits with various currently known structures and / or driving methods. Alternatively, in another embodiment, each pixel PXL can be constructed internally in a passive light-emitting display device, etc. In this case, the pixel circuit PXC can be omitted, and each of the first electrode ET1 and the second electrode ET2 of the light source unit LSU can be directly connected to the scan line Si, data line Dj, power line, and / or control line, etc.

[0116] Figure 12 This is a plan view showing pixels according to an embodiment.

[0117] Figure 12 Each pixel PXL shown can be Figures 8 to 11Any of the pixels PXL shown. In the embodiment, it is set to... Figure 7 The pixels PXL in the display area DA can have essentially the same or similar structures to each other.

[0118] exist Figure 12 The image shows the structure of the pixel PXL based on the light source unit LSU. However, the pixel PXL may also include circuitry for constructing each pixel (e.g., Figures 8 to 11 The circuit elements are pixel circuits (PXC). According to an embodiment, the circuit elements can be disposed on a different layer than the light source unit (LSU). For example, the circuit elements can be disposed on a surface of the substrate layer (BSL) in the circuit element layer (or also referred to as the "pixel circuit layer"), and the light source unit (LSU) can be disposed in a display element layer positioned on the circuit element layer.

[0119] Additionally, according to the embodiments, in Figure 12 The present invention illustrates an embodiment in which each light source unit LSU is connected to a predetermined power line (e.g., a first power line PL1 and / or a second power line PL2), circuit elements (e.g., at least one circuit element constituting a pixel circuit PXC), and / or signal lines (e.g., scan lines Si and / or data lines Dj) via a first contact hole CH1 and a second contact hole CH2, but the present disclosure is not limited thereto. For example, in another embodiment, at least one of the first electrode ET1 and the second electrode ET2 of each pixel PXL may be directly connected to the predetermined power line and / or signal line, without through contact holes and / or intermediate lines, etc.

[0120] First, refer to Figure 12 According to an embodiment, the pixel PXL may include a first electrode ET1 and a second electrode ET2 separated from each other, and a plurality of light-emitting elements LD disposed between the first electrode ET1 and the second electrode ET2 to be electrically connected to the first electrode ET1 and the second electrode ET2.

[0121] According to an embodiment, the first electrode ET1 and the second electrode ET2 can be spaced apart from each other and arranged alternately along a first direction (X-axis direction). Furthermore, each of the first electrode ET1 and the second electrode ET2 can extend in a second direction (Y-axis direction) intersecting the first direction. However, the shape, arrangement direction, and / or mutual arrangement structure of the electrodes constituting the light source unit LSU are not limited to this and can be varied. For example, at least one of the first electrode ET1 and the second electrode ET2 can have a structure that is bent or folded in one region.

[0122] According to an embodiment, the width WET2 of the second electrode ET2 in the first direction (X-axis direction) can be greater than the width WET1 of the first electrode ET1 in the first direction (X-axis direction). Therefore, even if the active layer 12 is not positioned at the center of the light-emitting element LD due to the thickness difference (length difference in the first direction (X-axis direction)) between the first semiconductor layer 11 and the second semiconductor layer 13, the light-emitting element LD can be centrally aligned by designing a large width WET2 of the second electrode ET2, which is stacked with the first semiconductor layer 11, in the first direction (X-axis direction). See below. Figure 15 Describe it in detail.

[0123] According to an embodiment, the first electrode ET1 can be electrically connected to the first electrode line ETL1 (also referred to as the "first alignment line" or "first connection line"), and can be electrically connected to the pixel circuit PXC and / or the first power supply VDD via the first electrode line ETL1. According to an embodiment, the first electrode ET1 and the first electrode line ETL1 can be connected integrally or non-integrally. When the first electrode ET1 and the first electrode line ETL1 are integrally connected, the first electrode ET1 and the first electrode line ETL1 can be considered as a single electrode, a line, or different regions of a pattern.

[0124] According to an embodiment, the second electrode ET2 can be electrically connected to the second electrode line ETL2 (also referred to as the "second alignment line" or "second connection line"), and can be electrically connected to the second power supply VSS via the second electrode line ETL2. According to an embodiment, the second electrode ET2 and the second electrode line ETL2 can be connected integrally or non-integrally. When the second electrode ET2 and the second electrode line ETL2 are integrally connected, the second electrode ET2 and the second electrode line ETL2 can be considered as a single electrode, a line, or different regions of a pattern.

[0125] In an embodiment, each of the first electrode line ETL1 and the second electrode line ETL2 may extend in a direction intersecting the first electrode ET1 and the second electrode ET2. For example, each of the first electrode line ETL1 and the second electrode line ETL2 may extend in a first direction (X-axis direction) and may be arranged parallel to each other, with the corresponding light source unit LSU's electrode located between the first electrode line ETL1 and the second electrode line ETL2.

[0126] The first electrode line ETL1 can be connected between the first power line PL1 and the first electrode ET1. During the period in which the display device is driven, the first electrode line ETL1 can receive a first power supply VDD (or a first drive signal such as a scan signal, data signal, or predetermined other control signal) supplied from the first power line PL1 and can transmit it to the first electrode ET1. In an embodiment, the first electrode line ETL1 can be electrically connected to a first contact hole CH1, a predetermined circuit element (e.g., at least one transistor constituting a pixel circuit PXC), a power line (e.g., the first power line PL1), and / or a signal line (e.g., a scan line Si, a data line Dj, or a predetermined control line). For example, the first electrode line ETL1 can be electrically connected to a predetermined circuit element disposed beneath it through the first contact hole CH1, and can be connected to the first power line PL1 through the circuit element. For example, each pixel PXL can also include a pixel circuit PXC connected between the first electrode line ETL1 and the first power supply VDD. According to an embodiment, the pixel circuit PXC can be disposed beneath each light source unit LSU and electrically connected to the first electrode line ETL1 of the light source unit LSU through the first contact hole CH1. In another embodiment, the first electrode line ETL1 can be connected via a first contact hole CH1 or the like to a signal line to which a predetermined first drive signal is supplied. In yet another embodiment, the first electrode line ETL1 can be directly connected to the first power supply line PL1 or the predetermined signal line without passing through the first contact hole CH1 and / or circuit elements. In this case, the first electrode line ETL1 can be integrally or non-integrally connected to the first power supply line PL1 or the predetermined signal line.

[0127] In an embodiment, the first electrode line ETL1 connected to the first electrode ET1 of each of the pixels PXL may initially be formed in a manner that is commonly connected to the plurality of pixels PXL, so as to receive a predetermined first alignment signal (or first alignment voltage) in the step of aligning the light-emitting element LD.

[0128] The second electrode line ETL2 can be connected between the second power line PL2 and the second electrode ET2. During the period when the display device is driven, the second electrode line ETL2 can receive the second power supply VSS (or a second drive signal such as a scan signal, data signal, or a predetermined other control signal) and transmit it to the second electrode ET2. In an embodiment, the second electrode line ETL2 can be electrically connected to the second contact hole CH2, a predetermined circuit element (e.g., at least one transistor constituting the pixel circuit PXC), a power line (e.g., the second power line PL2), and / or a signal line (e.g., a scan line Si, a data line Dj, or a predetermined control line). For example, the second electrode line ETL2 can be connected to the second power line PL2 disposed below it through the second contact hole CH2. In another embodiment, the second electrode line ETL2 can be directly connected to the second power line PL2 or a predetermined signal line without passing through the second contact hole CH2 and / or circuit elements, etc. In this case, the second electrode line ETL2 can be integrally or non-integrally connected to the second power line PL2 or the predetermined signal line.

[0129] During the step of aligning the light-emitting element LD, the second electrode line ETL2 can receive a predetermined second alignment signal (or a second alignment voltage). Simultaneously, during the period in which the display device is actually driven, the second electrode line ETL2 can receive a second power supply VSS or a predetermined second drive signal.

[0130] For example, the first electrode line ETL1 and the second electrode line ETL2 can be alignment lines. These alignment lines receive a predetermined alignment signal applied to each light source unit LSU during the step of aligning the light-emitting elements LD within each pixel PXL to manufacture the display device, and are positioned along the path of the alignment current corresponding to the alignment signal. Alternatively, the first electrode line ETL1 and the second electrode line ETL2 can be connecting lines. These connecting lines receive a predetermined driving voltage applied to each light source unit LSU during the driving step of the display device (e.g., in practical applications), and are positioned along the path of the driving current of each pixel PXL.

[0131] The aforementioned first alignment signal (or first alignment voltage) and second alignment signal (or second alignment voltage) can be signals having a voltage difference and / or a phase difference, under which the light-emitting element (LD) can be aligned. At least one of the first alignment signal (or first alignment voltage) and second alignment signal (or second alignment voltage) can be an AC signal, but is not necessarily limited to this.

[0132] At least one light-emitting element (LD) can be disposed between the first electrode ET1 and the second electrode ET2 to be electrically connected to the first electrode ET1 and the second electrode ET2.

[0133] In embodiments, each light-emitting element (LD) can be an ultra-miniature light-emitting element (e.g., from nanometer to micrometer scale) using a material with an inorganic crystal structure. For example, such as Figures 1 to 6 As shown, each light-emitting element (LD) can be an ultra-miniature rod-shaped light-emitting element with dimensions ranging from nanometers to micrometers. However, the size, type, shape, etc., of the light-emitting element (LD) can vary. For example, in another embodiment, each light-emitting element (LD) can be a core-shell structured light-emitting element manufactured by a growth method. The core-shell structured light-emitting element can be an ultra-miniature light-emitting element with dimensions ranging from nanometers to micrometers, but is not limited to this.

[0134] According to an embodiment, the light-emitting element (LD) can be prepared in a dispersed form in a predetermined solution and supplied to each pixel region (each emitting region surrounded by a dike (also called a "pixel defining layer") disposed between adjacent pixels PXL) using inkjet printing or other methods. In an embodiment, the LD can be supplied to each pixel region by inkjet printing, slot coating, or various other methods. For example, the LD can be mixed with a volatile solvent and supplied to the emitting region of each pixel PXL. At this time, when a predetermined alignment signal (or alignment voltage) is applied to the first electrode ET1 and the second electrode ET2, an electric field is formed between adjacent electrodes, so the LD is aligned between the electrodes by the permanent dipole of the active layer 12. After aligning the LD, the solvent can be evaporated or removed by another method to stably dispose the LD within each pixel PXL.

[0135] Pixel PXL may also include a plurality of embankment patterns PW superimposed on a region of each of the electrodes of the light source unit LSU. Each of the embankment patterns PW may be arranged to be spaced apart from each other along a first direction (X-axis direction). Additionally, each of the embankment patterns PW may extend along a second direction (Y-axis direction). However, the shape, arrangement direction, and / or arrangement structure of the embankment patterns PW are not limited thereto and can be varied. The embankment patterns PW may include a first embankment pattern PW1 and a third embankment pattern PW3 superimposed on a first electrode ET1, and a second embankment pattern PW2 and a fourth embankment pattern PW4 superimposed on a second electrode ET2. The aforementioned first light-emitting element LD1 may be disposed between the first embankment pattern PW1 and the second embankment pattern PW2, the second light-emitting element LD2 may be disposed between the second embankment pattern PW2 and the third embankment pattern PW3, and the third light-emitting element LD3 may be disposed between the third embankment pattern PW3 and the fourth embankment pattern PW4.

[0136] Additionally, the pixel PXL may also include a plurality of contact electrodes CE superimposed on a region of each of the electrodes constituting the light source unit LSU. Each of the contact electrodes CE may be arranged to be spaced apart from each other along a first direction (X-axis direction). Furthermore, each of the contact electrodes CE may extend along a second direction (Y-axis direction). However, the shape, arrangement direction, and / or arrangement structure of the contact electrodes CE are not limited thereto and can be varied. The contact electrodes CE may include a first contact electrode CE1 and a third contact electrode CE3 superimposed on a first electrode ET1, and a second contact electrode CE2 and a fourth contact electrode CE4 superimposed on a second electrode ET2. The first contact electrode CE1 may be superimposed on one end of the first light-emitting element LD1, the second contact electrode CE2 may be superimposed on the other end of the first light-emitting element LD1 and one end of the second light-emitting element LD2, the third contact electrode CE3 may be superimposed on the other end of the second light-emitting element LD2 and one end of the third light-emitting element LD3, and the fourth contact electrode CE4 may be superimposed on the other end of the third light-emitting element LD3.

[0137] Figure 13 and Figure 14 It is along Figure 12 A sectional view taken by line A-A'. Figure 15 yes Figure 13 An enlarged sectional view of region A.

[0138] Figure 13 and Figure 14 Different embodiments of a cross-section of pixel PXL according to an example are shown.

[0139] First, refer to Figure 13 According to the embodiments, the pixel PXL and the display device including the pixel PXL may include a circuit element layer PCL and a display element layer DPL sequentially disposed on one surface of the substrate layer BSL.

[0140] The circuit element layer (PCL) may include at least one circuit element electrically connected to the light-emitting element (LD) of each pixel PXL. For example, the PCL may include multiple transistors (T) and storage capacitors (Cst) that construct each pixel circuit PXC. Additionally, the PCL may also include at least one power line and / or signal line connected to each pixel circuit PXC and / or light source unit (LSU).

[0141] For ease of description, Figure 13 The diagram typically shows only one transistor T among the circuit elements and lines disposed in the circuit element layer. However, according to embodiments, the planar / sectional structure of the circuit element layer PCL can be varied, and the position and cross-sectional structure of each transistor T can be varied.

[0142] Additionally, the circuit element layer PCL may include multiple insulating layers. For example, the circuit element layer PCL may include a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, and / or a passivation layer PSV sequentially stacked on one surface of the substrate layer BSL. Furthermore, according to an embodiment, the circuit element layer PCL may also include at least one light-blocking pattern (not shown) disposed beneath at least some of the transistors T.

[0143] The buffer layer BFL prevents impurities from diffusing into each circuit element. The buffer layer BFL can be constructed as a single layer, or as a multilayer structure with two or more layers. When the buffer layer BFL is multilayered, each layer can be formed of the same material or different materials. Various circuit elements, such as transistors T and storage capacitors Cst, as well as various lines connected to the circuit elements, can be disposed on the buffer layer BFL. Alternatively, according to an embodiment, the buffer layer BFL can be omitted, and in this case, at least one circuit element and / or line can be directly disposed on one surface of the substrate layer BSL.

[0144] Each transistor T includes a semiconductor layer SCL (also referred to as a "semiconductor pattern" or "active layer"), a gate electrode GE, and a first transistor electrode TE1 and a second transistor electrode TE2. Meanwhile, according to an embodiment, in... Figure 13 The present invention illustrates an embodiment in which each transistor T includes a first transistor electrode TE1 and a second transistor electrode TE2 formed separately from the semiconductor layer SCL, but the present disclosure is not limited thereto. For example, in another embodiment of the present disclosure, the first transistor electrode TE1 and / or the second transistor electrode TE2 disposed in at least one transistor T may be integral with each semiconductor layer SCL to be constructed.

[0145] The semiconductor layer SCL can be disposed on the buffer layer BFL. For example, the semiconductor layer SCL can be disposed between the substrate layer BSL on which the buffer layer BFL is formed and the gate insulating layer GI. The semiconductor layer SCL may include a first region contacting each first transistor electrode TE1, a second region contacting each second transistor electrode TE2, and a channel region located between the first region and the second region. According to an embodiment, one of the first region and the second region may be a source region, and the other may be a drain region.

[0146] According to an embodiment, the semiconductor layer SCL can be a semiconductor pattern formed from polycrystalline silicon, amorphous silicon, oxide semiconductor, etc. Furthermore, the channel region of the semiconductor layer SCL can be an intrinsic semiconductor pattern that is an undoped semiconductor pattern, and each of the first and second regions of the semiconductor layer SCL can be a semiconductor pattern doped with a predetermined impurity.

[0147] In one embodiment, the semiconductor layer SCL of the transistor T that constitutes each pixel circuit PXC can be formed of substantially the same or similar materials. For example, the semiconductor layer SCL of the transistor T can be formed of any one of polycrystalline silicon, amorphous silicon, and oxide semiconductor. In another embodiment, a portion and the remainder of the transistor T may include semiconductor layers SCL formed of different materials. For example, the semiconductor layer SCL of a portion of the transistor T can be formed of polycrystalline silicon or amorphous silicon, and the semiconductor layer SCL of another portion of the transistor T can be formed of oxide semiconductor.

[0148] The gate insulating layer GI can be disposed on the semiconductor layer SCL. For example, the gate insulating layer GI can be disposed between the semiconductor layer SCL and the gate electrode GE. The gate insulating layer GI can be constructed as a single layer or multiple layers, and can include at least one inorganic insulating material and / or an organic insulating material.

[0149] The gate electrode GE can be disposed on the gate insulating layer GI. For example, the gate electrode GE can be stacked with the semiconductor layer SCL, and the gate insulating layer GI can be disposed between the gate electrode GE and the semiconductor layer SCL. Meanwhile, in Figure 13 The image shows a transistor T with a top-gate structure, but in another embodiment, transistor T may have a bottom-gate structure. In this case, the gate electrode GE may be disposed below the semiconductor layer SCL to be stacked with the semiconductor layer SCL.

[0150] An interlayer insulating layer (ILD) can be disposed on the gate electrode GE. For example, the ILD can be disposed between the gate electrode GE and the first transistor electrode TE1 and the second transistor electrode TE2. The ILD can be constructed as a single layer or multiple layers and can include at least one inorganic insulating material and / or an organic insulating material.

[0151] A first transistor electrode TE1 and a second transistor electrode TE2 may be disposed on each semiconductor layer SCL, and at least one interlayer insulating layer ILD is disposed between the first transistor electrode TE1 and the second transistor electrode TE2 and each semiconductor layer SCL. For example, the first transistor electrode TE1 and the second transistor electrode TE2 may be disposed at different ends of the semiconductor layer SCL, and a gate insulating layer GI and an interlayer insulating layer ILD are disposed between the first transistor electrode TE1 and the second transistor electrode TE2 and the different ends of the semiconductor layer SCL. The first transistor electrode TE1 and the second transistor electrode TE2 may be electrically connected to each semiconductor layer SCL. For example, the first transistor electrode TE1 and the second transistor electrode TE2 may be connected to a first region and a second region of the semiconductor layer SCL through corresponding contact holes passing through the gate insulating layer GI and the interlayer insulating layer ILD. According to an embodiment, one of the first transistor electrode TE1 and the second transistor electrode TE2 may be a source electrode, and the other may be a drain electrode.

[0152] A passivation layer PSV can be disposed on circuit elements and / or lines including transistors T. The passivation layer PSV can be constructed as a single layer or multiple layers and can include at least one inorganic insulating material and / or an organic insulating material. For example, the passivation layer PSV may include at least one organic insulating layer and can substantially planarize the surface of the circuit element layer PCL. A display element layer DPL can be disposed on the passivation layer PSV.

[0153] The Display Component Layer (DPL) can be set on the Circuit Component Layer (PCL).

[0154] The display element layer (DPL) may include a light source unit (LSU) for each of the pixels (PXL). For example, the display element layer (DPL) may include multiple electrodes that construct the light source unit (LSU) of each pixel (PXL) and multiple light-emitting elements (LDs) disposed between the electrodes. For example, the display element layer (DPL) may include a first electrode (ET1) and a second electrode (ET2) for each pixel (PXL), a first electrode line (ETL1) and a second electrode line (ETL2) respectively connected to the first electrode (ET1) and the second electrode (ET2), and multiple light-emitting elements (LDs) disposed between the first electrode (ET1) and the second electrode (ET2) for electrical connection to the first electrode (ET1) and the second electrode (ET2).

[0155] Additionally, the display element layer DPL may include a plurality of embankment patterns PW for protruding one region of each of the electrodes in a third direction (Z-axis direction) and a plurality of contact electrodes CE for more stable connection of the light-emitting elements LD between the electrodes. Furthermore, the display element layer DPL may also include at least one conductive layer and / or an insulating layer.

[0156] The embankment patterns PW can be configured to be spaced apart from each other in the emission region of each pixel PXL. These embankment patterns PW can protrude along a third direction (Z-axis direction) on a surface of the substrate layer BSL on which the circuit element layer PCL is formed. According to embodiments, the embankment patterns PW can have substantially the same height, but are not limited thereto.

[0157] According to an embodiment, each dam pattern PW can be disposed between each electrode (e.g., either the first electrode ET1 or the second electrode ET2) and the circuit element layer PCL. Additionally, each dam pattern PW can be disposed around at least one light-emitting element LD, facing one end or the other end of an adjacent at least one light-emitting element LD.

[0158] According to embodiments, the embankment pattern PW can have various shapes. In one embodiment, the embankment pattern PW can have a semi-circular or semi-elliptical cross-section in which the width narrows towards the top. In this case, each embankment pattern PW can have a curved surface on at least one side surface. Additionally, each electrode and / or insulating layer disposed on the embankment pattern PW can have a shape corresponding to the embankment pattern PW. For example, each electrode and / or insulating layer disposed on the embankment pattern PW can have an inclined surface or a curved surface in the region corresponding to the embankment pattern PW. However, in this disclosure, the shape of the embankment pattern PW is not particularly limited and can be varied.

[0159] The embankment pattern PW may include an insulating material comprising at least one inorganic and / or organic material. For example, the embankment pattern PW may include at least one inorganic layer comprising various currently known inorganic insulating materials, including silicon nitride (SiN). x ) or silicon dioxide (SiO) x Optionally, the embankment pattern PW may include at least one organic layer, which may comprise various types of currently known organic insulating materials and / or photoresist layers, or may be constructed as a single layer or multiple layers of insulator comprising organic / inorganic materials in combination. That is, in the embodiments, the construction materials of the embankment pattern PW may vary.

[0160] In an embodiment, the embankment pattern PW can be used as a reflective member. For example, the embankment pattern PW can be used together with the first electrode ET1 and the second electrode ET2 to guide the light emitted from each of the light-emitting elements LD in a desired direction to improve the light efficiency of the pixel PXL.

[0161] The first electrode ET1 and the second electrode ET2 of the light source unit LSU can be disposed on the embankment pattern PW. According to an embodiment, the electrodes can have a shape corresponding to each embankment pattern PW. For example, each electrode can protrude in a third direction (Z-axis direction) and have an inclined surface or a curved surface corresponding to each embankment pattern PW.

[0162] The first electrode ET1 and the second electrode ET2 may comprise at least one conductive material. For example, the first electrode ET1 and the second electrode ET2 may comprise at least one metal or alloy thereof selected from various metallic materials (including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), and copper (Cu)), conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc antimony oxide (AZO), indium tin zinc oxide (ITZO), or tin oxide (SnO2), and conductive polymers such as PEDOT, but are not limited thereto.

[0163] Furthermore, the first electrode ET1 and the second electrode ET2 can be constructed as a single layer or multiple layers. For example, the first electrode ET1 and the second electrode ET2 may include at least one reflective electrode layer. Additionally, the first electrode ET1 and the second electrode ET2 may optionally include at least one transparent electrode layer disposed on and / or below the reflective electrode layer, and at least one conductive capping layer covering the upper portion of the reflective electrode layer and / or the transparent electrode layer.

[0164] A first insulating layer INS1 may be disposed on a region of the first electrode ET1 and the second electrode ET2. For example, the first insulating layer INS1 may be formed to cover a region of the first electrode ET1 and the second electrode ET2 and may include openings to expose another region of the first electrode ET1 and the second electrode ET2. For example, the first insulating layer INS1 may expose a region of the first electrode ET1 and the second electrode ET2 on each embankment pattern PW. Meanwhile, according to an embodiment, the first insulating layer INS1 may be omitted.

[0165] In one embodiment, the first insulating layer INS1 can be formed to initially completely cover the first electrode ET1 and the second electrode ET2. After the light-emitting element LD is supplied and aligned on the first insulating layer INS1, the first insulating layer INS1 can be partially opened to expose the first electrode ET1 and the second electrode ET2 in a region on each embankment pattern PW. Alternatively, in another embodiment, after the supply and alignment of the light-emitting element LD are completed, the first insulating layer INS1 can be patterned as a separate pattern, which is only partially disposed under the light-emitting element LD. That is, the first insulating layer INS1 can be placed between the first electrode ET1 and the second electrode ET2 and the light-emitting element LD, and at least one region of each of the electrodes can be exposed. After the electrodes are formed, the first insulating layer INS1 can be formed to cover the electrodes, thereby preventing the electrodes from being damaged in subsequent processes. In addition, the first insulating layer INS1 can stably support each light-emitting element LD.

[0166] The first insulating layer INS1 can be constructed as a single layer or multiple layers, and can include at least one inorganic insulating material and / or an organic insulating material.

[0167] Multiple light-emitting elements (LDs) can be supplied and aligned in each pixel region (specifically, in the emission region of each pixel PXL) in which the first insulating layer INS1 is formed. For example, the multiple light-emitting elements (LDs) can be supplied to the emission region of each pixel PXL by inkjet printing, slot coating, various other methods, etc., and the light-emitting elements (LDs) can be directionally aligned by an alignment signal (or alignment voltage).

[0168] For a detailed description of the alignment of the light-emitting element (LD), please refer to... Figure 15 In the following text, for ease of description, the offset alignment and center alignment of the light-emitting element LD are described based on the first light-emitting element LD1.

[0169] Reference Figure 15 The alignment signal (or alignment voltage) can be used to align the first light-emitting element LD1 using the permanent dipole of the active layer 12. In this case, the active layer 12 can be disposed at the center of one end of the first electrode ET1 and one end of the second electrode ET2. That is, the distance E112 between the active layer 12 and the said end of the first electrode ET1 in the first direction (X-axis direction) can be substantially the same as the distance E212 between the active layer 12 and the said end of the second electrode ET2 in the first direction (X-axis direction).

[0170] The first light-emitting element LD1 can be directionally aligned between the first electrode ET1 and the second electrode ET2 by an alignment signal (or alignment voltage).

[0171] According to an embodiment, the first light-emitting element LD1 can be aligned along a first direction (X-axis direction) such that the first semiconductor layer 11 is adjacent to the second electrode ET2 and the second semiconductor layer 13 is adjacent to the first electrode ET1. That is, the first light-emitting element LD1 can be aligned along the first direction (X-axis direction) such that one end of the first semiconductor layer 11 is superimposed on the second electrode ET2 and one end of the second semiconductor layer 13 is superimposed on the first electrode ET1. As described above, when the light-emitting elements LD are biased and aligned, material efficiency can be improved compared to the case where the light-emitting elements LD are randomly arranged.

[0172] On the other hand, when the light-emitting element LD is biased and aligned, as described above, the center alignment of the light-emitting element LD may not be performed smoothly due to the eccentricity of the active layer 12 caused by the thickness difference (length difference in the first direction (X-axis direction)) between the first semiconductor layer 11 and the second semiconductor layer 13.

[0173] Therefore, the display device according to the embodiment can take into account the eccentricity of the active layer 12 by asymmetrically designing the first electrode ET1 and the second electrode ET2 to centrally align the light-emitting element LD without a separate center alignment signal.

[0174] That is, the distance E211 between one end 11E (N-type end) of the first light-emitting element LD1 and one end of the second electrode ET2 in the first direction (X-axis direction) can be designed to be greater than the distance E113 between the other end 13E (P-type end) of the first light-emitting element LD1 and one end of the first electrode ET1 in the first direction (X-axis direction). Therefore, the space in which the first semiconductor layer 11 is aligned can be ensured by the eccentricity of the active layer 12 in the first light-emitting element LD1.

[0175] According to an embodiment, the area where the first light-emitting element LD1 and the second electrode ET2 are stacked can be larger than the area where the first light-emitting element LD1 and the first electrode ET1 are stacked. Furthermore, the area where the first semiconductor layer 11 and the second electrode ET2 are stacked can be larger than the area where the second semiconductor layer 13 and the first electrode ET1 are stacked. Additionally, the distance P2E2 between one end of the second electrode ET2 and one end of the second embankment pattern PW2 in the first direction (X-axis direction) can be larger than the distance P1E1 between one end of the first electrode ET1 and one end of the first embankment pattern PW1 in the first direction (X-axis direction). That is, the second electrode ET2 can extend relative to one end of the second embankment pattern PW2 to ensure the alignment of the first semiconductor layer 11 within the space.

[0176] According to the above embodiment, even if the active layer 12 is not disposed at the center of the light-emitting element LD due to the thickness difference (length difference in the first direction (X-axis direction)) of the first semiconductor layer 11 and the second semiconductor layer 13, the light-emitting element LD can be centered between the embankment patterns PW using a single alignment signal (or alignment voltage). That is, since a separate center alignment signal can be omitted, the alignment signal (or alignment voltage) can be simplified.

[0177] Furthermore, since the light-emitting element LD is centrally aligned between the embankment pattern PW, sufficient space can be ensured between one end 11E and the other end 13E of the light-emitting element LD and the embankment pattern PW. That is, the contact area between one end 11E and the other end 13E of the light-emitting element LD and the contact electrode CE can be reliably ensured.

[0178] When the light-emitting elements LD are aligned centrally between the dike patterns PW, the distance P211 between one end 11E of the first light-emitting element LD1 and one end of the second dike pattern PW2 in the first direction (X-axis direction) can be substantially the same as the distance P113 between the other end 13E of the first light-emitting element LD1 and one end of the first dike pattern PW1 in the first direction (X-axis direction). Furthermore, the distance P112 between the active layer 12 and one end of the first dike pattern PW1 in the first direction (X-axis direction) can be different from the distance P212 between the active layer 12 and one end of the second dike pattern PW2 in the first direction (X-axis direction). For example, the distance P212 between the active layer 12 and one end of the second dike pattern PW2 in the first direction (X-axis direction) can be greater than the distance P112 between the active layer 12 and one end of the first dike pattern PW1 in the first direction (X-axis direction).

[0179] Refer again Figure 13 An insulating pattern INP can be disposed on a region of the light-emitting element LD. For example, the insulating pattern INP can be partially disposed on a region including the central region of each of the light-emitting elements LD while exposing one end and the other end of each of the light-emitting elements LD. The insulating pattern INP can be formed as an independent pattern in the emission region of each pixel PXL, but is not limited thereto. According to an embodiment, the insulating pattern INP can be omitted.

[0180] The insulating pattern INP can be constructed as a single layer or multiple layers and can include at least one inorganic insulating material and / or an organic insulating material.

[0181] When the insulating pattern INP is formed on the light-emitting element (LD) after alignment, it prevents the LD from deviating from its alignment position. Furthermore, when a separation space exists between the first insulating layer INS1 and the LD, this space can be filled with the insulating material introduced during the process of forming the insulating pattern INP. Therefore, the LD can be supported more stably.

[0182] One end of the light-emitting element LD that is not covered by the insulating pattern INP may be covered by the contact electrode CE. For example, one end of each of the adjacent contact electrodes CE may be provided with the insulating pattern INP placed therebetween, and may be configured to be separated at one end and the other end of at least one adjacent light-emitting element LD.

[0183] In an embodiment, such as Figure 13 As shown, the contact electrode CE can be formed simultaneously on one surface of the substrate layer BSL in the same layer. Therefore, the manufacturing process of the pixel PXL and the display device including the pixel PXL can be simplified.

[0184] In another embodiment, the contact electrode CE can be divided into multiple groups, and for each group, it can be sequentially formed in different layers on one surface of the substrate layer BSL. For example, as Figure 14 As shown, a pair of adjacent contact electrodes CE can be sequentially formed in different layers on one surface of the substrate layer BSL. In this case, a third insulating layer INS3 can be additionally disposed between the pair of contact electrodes CE. That is, the positions and mutual arrangement of the contact electrodes CE can be varied.

[0185] Additionally, the contact electrode CE can be disposed on the first electrode ET1 and the second electrode ET2 to cover the exposed areas of the first electrode ET1 and the second electrode ET2. For example, the contact electrode CE can be disposed on at least one area of ​​the first electrode ET1 and the second electrode ET2 to contact the first electrode ET1 and the second electrode ET2. Therefore, the first electrode ET1 and the second electrode ET2 can be electrically connected to the contact electrode CE disposed thereon, and can be electrically connected to one end and the other end of at least one light-emitting element LD disposed between the first electrode ET1 and the second electrode ET2 via the contact electrode CE.

[0186] According to an embodiment, the contact electrode CE can be formed of various transparent conductive materials. For example, the contact electrode CE may include at least one of various transparent conductive materials comprising ITO, IZO, and ITZO, and can be made substantially transparent or translucent to meet a predetermined light transmittance. Therefore, light emitted from one end and the other end of the light-emitting element LD can pass through the contact electrode CE to be emitted to the outside of the display device.

[0187] The second insulating layer INS2 can be disposed on the contact electrode CE. For example, the second insulating layer INS2 can be entirely formed and / or disposed in the display area DA of the substrate layer BSL on which the embankment pattern PW, the first electrode ET1 and the second electrode ET2, the light-emitting element LD, the insulating pattern INP and the contact electrode CE are formed, to cover the embankment pattern PW, the first electrode ET1 and the second electrode ET2, the light-emitting element LD, the insulating pattern INP and the contact electrode CE. The second insulating layer INS2 may include at least one inorganic layer and / or an organic layer.

[0188] In this embodiment, the second insulating layer INS2 may include, but is not limited to, a multilayer thin-film encapsulation layer. Additionally, according to this embodiment, at least one overcoat layer OC may be disposed on the second insulating layer INS2.

[0189] According to embodiments, each of the second insulating layer INS2 and the outer cladding layer OC can be constructed as a single layer or multiple layers, and can include at least one inorganic insulating material and / or an organic insulating material. For example, each of the second insulating layer INS2 and the outer cladding layer OC can include various types of currently known organic / inorganic insulating materials, including silicon nitride (SiN). x ), silicon dioxide (SiO) x )wait.

[0190] According to the above embodiments, by asymmetrically designing the first electrode ET1 and the second electrode ET2, a single alignment signal (or alignment voltage) can be used to center-align the light-emitting element LD. That is, since a separate center alignment signal can be omitted, the alignment signal (or alignment voltage) can be simplified, and the contact area between the light-emitting element LD and the contact electrode CE can be reliably ensured through center alignment.

[0191] Figure 16 This is a plan view of pixels according to another embodiment. Figure 17 and Figure 18 It is along Figure 16 The sectional view taken by line B-B'.

[0192] exist Figures 16 to 18 In the embodiments described above, the same reference numerals are used for constructions that are similar to or the same as those in the above embodiments, and their detailed descriptions are omitted.

[0193] According to the pixel PXL of this embodiment and Figures 1 to 15 The difference in the embodiment is that multiple dike patterns are omitted.

[0194] Specifically, the first electrode ET1 and the second electrode ET2 can be directly disposed on one surface of the uppermost surface of the circuit element layer PCL (e.g., the passivation layer PSV). The first electrode ET1 and the second electrode ET2 can be disposed flatly along the shape of one surface of the uppermost surface of the circuit element layer PCL (e.g., the passivation layer PSV).

[0195] The light-emitting element LD can be disposed on the first electrode ET1 and the second electrode ET2, and one end and the other end of the light-emitting element LD can be covered by the contact electrode CE. For example, one end of each of the adjacent contact electrodes CE can be provided with an insulating pattern INP placed therebetween, and can be configured to be separated on one end and the other end of at least one adjacent light-emitting element LD.

[0196] In an embodiment, such as Figure 17 As shown, the contact electrode CE can be formed simultaneously on one surface of the substrate layer BSL in the same layer. Therefore, the manufacturing process of the pixel PXL and the display device including the pixel PXL can be simplified.

[0197] In another embodiment, the contact electrode CE can be divided into multiple groups, and for each group, it can be sequentially formed in different layers on one surface of the substrate layer BSL. For example, as Figure 14 As shown, a pair of adjacent contact electrodes CE can be sequentially formed in different layers on one surface of the substrate layer BSL. In this case, a third insulating layer INS3 can be additionally disposed between the pair of contact electrodes CE. That is, the positions and mutual arrangement of the contact electrodes CE can be varied.

[0198] Additionally, the contact electrode CE can cover one surface of the first electrode ET1 and the second electrode ET2 that is exposed by the first insulating layer INS1. Therefore, one end of the light-emitting element LD can be electrically connected to the first electrode ET1 through the first contact electrode CE1, and the other end of the light-emitting element LD can be electrically connected to the second electrode ET2 through the second contact electrode CE2.

[0199] According to this embodiment, since multiple embankment patterns in pixel PXL can be omitted, the element density in pixel PXL can be improved.

[0200] Due to reference Figures 1 to 15 Other constructs are described, so repeated content has been omitted.

[0201] Figure 19 This is a plan view of pixels according to yet another embodiment. Figure 20 and Figure 21 It is along Figure 19 A sectional view taken by line C-C'.

[0202] exist Figures 19 to 21 In the embodiments described above, the same reference numerals are used for constructions that are similar to or the same as those in the above embodiments, and their detailed descriptions are omitted.

[0203] According to the pixel PXL of this embodiment and Figures 1 to 15 The difference in the embodiment is that the pixel PXL according to this embodiment also includes at least one intermediate electrode IET disposed between the first electrode ET1 and the second electrode ET2, and the light-emitting elements LD are connected in series.

[0204] Specifically, refer to Figure 19 The pixel PXL may include a first electrode ET1 and a second electrode ET2 separated from each other, at least one intermediate electrode IET disposed between the first electrode ET1 and the second electrode ET2, and a plurality of light-emitting elements LD connected between a pair of adjacent electrodes in the first electrode ET1, the second electrode ET2 and the at least one intermediate electrode IET.

[0205] The first electrode ET1, at least one intermediate electrode IET, and the second electrode ET2 can be connected in series sequentially via each light-emitting element LD to construct the electrodes of each series stage.

[0206] The first electrode ET1, the first intermediate electrode IET1, the second intermediate electrode IET2, and the second electrode ET2 can be separated from each other and arranged sequentially along a first direction (X-axis direction). The first electrode ET1 and the first intermediate electrode IET1 adjacent to each other can form a pair to construct a first series stage. Similarly, the first intermediate electrode IET1 and the second intermediate electrode IET2 adjacent to each other can form a pair to construct a second series stage, and the second intermediate electrode IET2 and the second electrode ET2 adjacent to each other can form a pair to construct a third series stage.

[0207] Each of the first electrode ET1, the first intermediate electrode IET1, the second intermediate electrode IET2, and the second electrode ET2 can extend along a second direction (Y-axis direction). For example, each of the first electrode ET1, the first intermediate electrode IET1, the second intermediate electrode IET2, and the second electrode ET2 can be arranged side by side with each other, having a strip shape extending along the second direction (Y-axis direction). However, the shape, arrangement direction, and / or mutual arrangement structure of the electrodes constituting the light source unit LSU are not limited to this and can be varied. For example, a pair of electrodes in each series stage of the light source unit LSU can be arranged to be separated from each other by a double helix structure or the like. In addition, at least one of the first electrode ET1, the first intermediate electrode IET1, the second intermediate electrode IET2, and the second electrode ET2 can have a structure that is bent or folded in one region.

[0208] According to an embodiment, the first electrode ET1 can be electrically connected to the first electrode line ETL1, and can be electrically connected to the pixel circuit PXC and / or the first power supply VDD through the first electrode line ETL1. The second electrode ET2 can be electrically connected to the second electrode line ETL2, and can be electrically connected to the second power supply VSS through the second electrode line ETL2.

[0209] In an embodiment, each of the first electrode line ETL1 and the second electrode line ETL2 may extend in a direction intersecting the first electrode ET1 and the second electrode ET2. For example, each of the first electrode line ETL1 and the second electrode line ETL2 may extend in a first direction (X-axis direction) and may be configured to be parallel to each other, with the corresponding light source unit LSU's electrode positioned between the first electrode line ETL1 and the second electrode line ETL2.

[0210] The first electrode line ETL1 can be connected between the first power line PL1 and the first electrode ET1. During the period in which the display device is driven, the first electrode line ETL1 can receive a first power supply VDD (or a first drive signal such as a scan signal, data signal, or predetermined other control signal) supplied from the first power line PL1 and can transmit it to the first electrode ET1. In an embodiment, the first electrode line ETL1 can be electrically connected to a first contact hole CH1, a predetermined circuit element (e.g., at least one transistor constituting a pixel circuit PXC), a power line (e.g., the first power line PL1), and / or a signal line (e.g., a scan line Si, a data line Dj, or a predetermined control line). For example, the first electrode line ETL1 can be electrically connected to a predetermined circuit element disposed beneath it through the first contact hole CH1, and can be connected to the first power line PL1 through the circuit element. For example, each pixel PXL can also include a pixel circuit PXC connected between the first electrode line ETL1 and the first power supply VDD. According to an embodiment, the pixel circuit PXC can be disposed beneath each light source unit LSU and electrically connected to the first electrode line ETL1 of the light source unit LSU through the first contact hole CH1. In another embodiment, the first electrode line ETL1 can be connected via a first contact hole CH1 or the like to a signal line to which a predetermined first drive signal is supplied. In yet another embodiment, the first electrode line ETL1 can be directly connected to the first power supply line PL1 or the predetermined signal line without passing through the first contact hole CH1 and / or circuit elements. In this case, the first electrode line ETL1 can be integrally or non-integrally connected to the first power supply line PL1 or the predetermined signal line.

[0211] In an embodiment, the first electrode line ETL1 connected to the first electrode ET1 of each pixel PXL can initially be formed in a manner that is commonly connected to multiple pixels PXL to receive a predetermined first alignment signal (or first alignment voltage) during the step of aligning the light-emitting element LD. Subsequently, by disconnecting the first electrode lines ETL1 between pixels PXL, pixels PXL can be manufactured in a manner that allows them to be driven individually. For example, the first electrode lines ETL1 of pixels PXL can be separated from each other between adjacent pixels PXL.

[0212] The second electrode line ETL2 can be connected between the second power line PL2 and the second electrode ET2. During the period when the display device is driven, the second electrode line ETL2 can receive the second power supply VSS (or a second drive signal such as a scan signal, data signal, or a predetermined other control signal) and transmit it to the second electrode ET2. In an embodiment, the second electrode line ETL2 can be electrically connected to the second contact hole CH2, a predetermined circuit element (e.g., at least one transistor constituting the pixel circuit PXC), a power line (e.g., the second power line PL2), and / or a signal line (e.g., a scan line Si, a data line Dj, or a predetermined control line). For example, the second electrode line ETL2 can be connected to the second power line PL2 disposed below it through the second contact hole CH2. In another embodiment, the second electrode line ETL2 can be directly connected to the second power line PL2 or a predetermined signal line without passing through the second contact hole CH2 and / or circuit elements, etc. In this case, the second electrode line ETL2 can be integrally or non-integrally connected to the second power line PL2 or the predetermined signal line.

[0213] During the step of aligning the light-emitting element LD, the second electrode line ETL2 can receive a predetermined second alignment signal (or a second alignment voltage). Simultaneously, during the period in which the display device is actually driven, the second electrode line ETL2 can receive a second power supply VSS or a predetermined second drive signal.

[0214] For example, the first electrode line ETL1 and the second electrode line ETL2 can be alignment lines. These alignment lines receive a predetermined alignment signal applied to each light source unit LSU during the step of aligning the light-emitting elements LD within each pixel PXL to manufacture the display device, and are positioned along the path of the alignment current corresponding to the alignment signal. Alternatively, the first electrode line ETL1 and the second electrode line ETL2 can be connecting lines. These connecting lines receive a predetermined driving voltage applied to each light source unit LSU during the driving step of the display device (e.g., in practical applications), and are positioned along the path of the driving current of each pixel PXL.

[0215] According to an embodiment, each intermediate electrode IET (e.g., a first intermediate electrode IET1 and a second intermediate electrode IET2) can initially be formed in the form of being connected to a first electrode line ETL1 or a second electrode line ETL2, so as to receive a predetermined first alignment signal or a second alignment signal during the step of aligning the light-emitting element LD. Furthermore, after the alignment of the light-emitting element LD is completed, the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can be connected in series by separating each intermediate electrode IET from the first electrode line ETL1 or the second electrode line ETL2.

[0216] At least one light-emitting element (LD) can be connected in the forward direction between a pair of adjacent electrodes. For example, at least one first light-emitting element (LD1) can be connected in the forward direction between the first electrode (ET1) and the first intermediate electrode (IET1), at least one second light-emitting element (LD2) can be connected in the forward direction between the first intermediate electrode (IET1) and the second intermediate electrode (IET2), and at least one third light-emitting element (LD3) can be connected in the forward direction between the second intermediate electrode (IET2) and the second electrode (ET2).

[0217] Pixel PXL may also include a plurality of embankment patterns PW disposed under a region of each of the electrodes in the light source unit LSU, and / or a plurality of contact electrodes CE disposed on each of the electrodes. For example, pixel PXL may include first embankment patterns to fourth embankment patterns PW1, PW2, PW3, and PW4 disposed under the first electrode ET1, the first intermediate electrode IET1, the second intermediate electrode IET2, and the second electrode ET2, respectively. Additionally, pixel PXL may include first contact electrodes to fourth contact electrodes CE1, CE2, CE3, and CE4 disposed on the first electrode ET1, the first intermediate electrode IET1, the second intermediate electrode IET2, and the second electrode ET2, respectively.

[0218] In the following text, for ease of description, the detailed structure of the circuit element layer PCL is omitted, and the cross-sectional structure of the pixel PXL is described based on the first light-emitting element LD1 and the second light-emitting element LD2.

[0219] Reference Figure 20 The first light-emitting element LD1 can be disposed between the first electrode ET1 and the first intermediate electrode IET1, and the second light-emitting element LD2 can be disposed between the first intermediate electrode IET1 and the second intermediate electrode IET2.

[0220] The first light-emitting element LD1 and the second light-emitting element LD2 can be aligned between electrodes using the permanent dipole of the active layer 12 via an alignment signal (or alignment voltage).

[0221] In this case, the distance E121 between the active layer 12 of the first light-emitting element LD1 and one end of the first intermediate electrode IET1 in the first direction (X-axis direction) can be substantially the same as the distance E122 between the active layer 12 of the second light-emitting element LD2 and the other end of the first intermediate electrode IET1 in the first direction (X-axis direction).

[0222] The first light-emitting element LD1 and the second light-emitting element LD2 can be directionally aligned between the electrodes using an alignment signal (or alignment voltage). The first light-emitting element LD1 and the second light-emitting element LD2 can be arranged in the same direction, but are not necessarily limited to this. For example, each of the first light-emitting element LD1 and the second light-emitting element LD2 can be aligned such that the first semiconductor layer 11 faces a first direction (X-axis direction), and the second semiconductor layer 13 faces a direction opposite to the first direction (X-axis direction). That is, the first light-emitting element LD1 can be aligned along the first direction (X-axis direction) such that the first semiconductor layer 11 is adjacent to the first intermediate electrode IET1, and the second semiconductor layer 13 is adjacent to the first electrode IET1. The second light-emitting element LD2 can be aligned along the first direction (X-axis direction) such that the first semiconductor layer 11 is adjacent to the second intermediate electrode IET2, and the second semiconductor layer 13 is adjacent to the first intermediate electrode IET1.

[0223] According to an embodiment, the first intermediate electrode IET1 may be stacked with the first semiconductor layer 11 of the first light-emitting element LD1 and with the second semiconductor layer 13 of the second light-emitting element LD2. As described above, when the light-emitting elements LD are biased and aligned, material efficiency can be improved compared to the case described above where the light-emitting elements LD are randomly arranged.

[0224] On the other hand, when the light-emitting element LD is biased and aligned, as described above, the center alignment of the light-emitting element LD may not be performed smoothly due to the eccentricity of the active layer 12 caused by the thickness difference (length difference in the first direction (X-axis direction)) between the first semiconductor layer 11 and the second semiconductor layer 13.

[0225] Therefore, the display device according to the embodiment can take into account the eccentricity of the active layer 12 by asymmetrically designing the first intermediate electrode IET1 to centrally align the light-emitting element LD without a separate center alignment signal.

[0226] That is, the area where the first intermediate electrode IET1 and the first semiconductor layer 11 of the first light-emitting element LD1 are stacked can be designed to be larger than the area where the first intermediate electrode IET1 and the second semiconductor layer 13 of the second light-emitting element LD2 are stacked. Therefore, the alignment space of the first semiconductor layer 11 can be ensured by the eccentricity of the active layer 12 in the light-emitting elements LD1 and LD2.

[0227] According to an embodiment, the distance E11 between one end of the first intermediate electrode IET1 and one end of the first semiconductor layer 11 of the first light-emitting element LD1 in the first direction (X-axis direction) can be greater than the distance E13 between the other end of the first intermediate electrode IET1 and one end of the second semiconductor layer 13 of the second light-emitting element LD2 in the first direction (X-axis direction). Additionally, the distance PE1 between one end of the first intermediate electrode IET1 and one end of the second embankment pattern PW2 in the first direction (X-axis direction) can be greater than the distance PE2 between the other end of the first intermediate electrode IET1 and the other end of the second embankment pattern PW2 in the first direction (X-axis direction).

[0228] According to this embodiment, even if the active layer 12 is not disposed at the center of the light-emitting element LD due to the thickness difference (length difference in the first direction (X-axis direction)) of the first semiconductor layer 11 and the second semiconductor layer 13, the light-emitting element LD can be centered between the embankment patterns PW using a single alignment signal (or alignment voltage). That is, as described above, since a separate center alignment signal can be omitted, the alignment signal (or alignment voltage) can be simplified.

[0229] Furthermore, since the light-emitting element (LD) is centrally aligned between the embankment pattern (PW), sufficient space can be ensured between one end of the LD and the embankment pattern (PW). That is, the contact area between one end of the LD and the contact electrode (CE) can be reliably ensured.

[0230] According to an embodiment, the distance P11 between one end of the first semiconductor layer 11 of the first light-emitting element LD1 and one end of the second embankment pattern PW2 in the first direction (X-axis direction) can be substantially the same as the distance P13 between one end of the second semiconductor layer 13 of the second light-emitting element LD2 and the other end of the second embankment pattern PW2 in the first direction (X-axis direction). Furthermore, the distance P121 between the active layer 12 of the first light-emitting element LD1 and one end of the second embankment pattern PW2 in the first direction (X-axis direction) can be different from the distance P122 between the active layer 12 of the second light-emitting element LD2 and the other end of the second embankment pattern PW2 in the first direction (X-axis direction). For example, the distance P121 between the active layer 12 of the first light-emitting element LD1 and one end of the second embankment pattern PW2 in the first direction (X-axis direction) can be greater than the distance P122 between the active layer 12 of the second light-emitting element LD2 and the other end of the second embankment pattern PW2 in the first direction (X-axis direction).

[0231] Due to reference Figures 1 to 15 Other constructs are described, so repeated content has been omitted.

[0232] Figure 22This is a plan view of pixels according to another embodiment. Figure 23 and Figure 24 It is along Figure 22 A sectional view taken by line D-D'.

[0233] exist Figures 22 to 24 In the embodiments described above, the same reference numerals are used for constructions that are similar to or the same as those in the above embodiments, and their detailed descriptions are omitted.

[0234] According to the pixel PXL of this embodiment and Figures 19 to 21 The difference in the embodiment is that multiple dike patterns are omitted.

[0235] Specifically, the first electrode ET1, the first intermediate electrode IET1, and the second intermediate electrode IET2 can be directly disposed on one surface of the uppermost surface of the circuit element layer PCL (e.g., the passivation layer PSV). The first electrode ET1, the first intermediate electrode IET1, and the second intermediate electrode IET2 can be disposed flatly along the shape of one surface of the uppermost surface of the circuit element layer PCL (e.g., the passivation layer PSV).

[0236] The light-emitting element LD can be disposed on the first electrode ET1, the first intermediate electrode IET1, the second intermediate electrode IET2, and the second electrode ET2, and one end and the other end of the light-emitting element LD can be covered by the contact electrode CE. For example, one end of each of the adjacent contact electrodes CE can be provided with an insulating pattern INP placed therebetween, and can be configured to be separated on one end and the other end of at least one adjacent light-emitting element LD.

[0237] In an embodiment, such as Figure 23 As shown, the contact electrode CE can be formed simultaneously on one surface of the substrate layer BSL in the same layer. Therefore, the manufacturing process of the pixel PXL and the display device including the pixel PXL can be simplified.

[0238] In another embodiment, the contact electrode CE can be divided into multiple groups, and for each group, it can be sequentially formed in different layers on one surface of the substrate layer BSL. For example, as Figure 24 As shown, a pair of adjacent contact electrodes CE can be sequentially formed in different layers on one surface of the substrate layer BSL. In this case, a third insulating layer INS3 can be additionally disposed between the pair of contact electrodes CE. That is, the positions and mutual arrangement of the contact electrodes CE can be varied.

[0239] In addition, the contact electrode CE can cover one surface of the first electrode ET1, the first intermediate electrode IET1, the second intermediate electrode IET2, and the second electrode ET2 that is exposed by the first insulating layer INS1.

[0240] According to this embodiment, as described above, since multiple embankment patterns in pixel PXL can be omitted, the element density in pixel PXL can be improved.

[0241] Due to reference Figures 19 to 21 Other constructs are described, so repeated content has been omitted.

[0242] Although embodiments have been described above with reference to the accompanying drawings, those skilled in the art to which this disclosure pertains will understand that this disclosure may be implemented in other specific forms without altering its technical spirit or essential characteristics. Therefore, it should be understood that the above embodiments are illustrative in all respects and not restrictive.

Claims

1. A display device, the display device comprising: Multiple pixels, set in the display area. Each of the plurality of pixels includes: a first electrode and a second electrode, spaced apart from each other in a first direction; and at least one light-emitting element disposed between the first electrode and the second electrode and electrically connected to the first electrode and the second electrode. Wherein, the distance between one end of the light-emitting element and one end of the second electrode in the first direction is greater than the distance between the other end of the light-emitting element and one end of the first electrode in the first direction. The light-emitting element includes: a first semiconductor layer; a second semiconductor layer; and an active layer disposed between the first semiconductor layer and the second semiconductor layer. Wherein, the thickness of the first semiconductor layer in the first direction is greater than the thickness of the second semiconductor layer in the first direction, and the active layer is not disposed at the center of the light-emitting element, and The first electrode and the second electrode are used for alignment.

2. The display device according to claim 1, wherein, The width of the second electrode in the first direction is greater than the width of the first electrode in the first direction.

3. The display device according to claim 1, wherein, The first semiconductor layer is electrically connected to the second electrode, and the second semiconductor layer is electrically connected to the first electrode.

4. The display device according to claim 3, wherein, The first semiconductor layer is stacked with the second electrode, and the second semiconductor layer is stacked with the first electrode.

5. The display device according to claim 4, wherein, The area of ​​the second electrode stacked with the first semiconductor layer is larger than the area of ​​the first electrode stacked with the second semiconductor layer.

6. The display device according to claim 3, wherein, The distance in the first direction between the active layer and one end of the first electrode is the same as the distance in the first direction between the active layer and one end of the second electrode.

7. The display device according to claim 1, wherein, The plurality of pixels also includes: A first embankment pattern is disposed below and superimposed on the first electrode; and The second embankment pattern is disposed below the second electrode and superimposed on the second electrode.

8. The display device according to claim 7, wherein, The distance in the first direction between one end of the second electrode and one end of the second embankment pattern is greater than the distance in the first direction between one end of the first electrode and one end of the first embankment pattern.

9. The display device according to claim 7, wherein, The distance in the first direction between one end of the light-emitting element and one end of the second dike pattern is the same as the distance in the first direction between the other end of the light-emitting element and one end of the first dike pattern.

10. The display device according to claim 7, wherein, The distance between one end of the second embankment pattern and the active layer in the first direction is greater than the distance between one end of the first embankment pattern and the active layer in the first direction.

11. A display device, the display device comprising: Multiple pixels, set in the display area. Each of the plurality of pixels includes: a first electrode and a second electrode, spaced apart from each other in a first direction; at least one intermediate electrode; disposed between the first electrode and the second electrode; a first light-emitting element disposed between the intermediate electrode and the first electrode; and a second light-emitting element disposed between the intermediate electrode and the second electrode. Wherein, the area where the intermediate electrode and the first light-emitting element are stacked is larger than the area where the intermediate electrode and the second light-emitting element are stacked. Each of the first light-emitting element and the second light-emitting element includes: a first semiconductor layer; a second semiconductor layer; and an active layer disposed between the first semiconductor layer and the second semiconductor layer. Wherein, the thickness of the first semiconductor layer in the first direction is greater than the thickness of the second semiconductor layer in the first direction, and the active layer is not disposed at the center of each of the first and second light-emitting elements. The first electrode, the second electrode, and the intermediate electrode are used for alignment.

12. The display device according to claim 11, wherein, The intermediate electrode is stacked with the first semiconductor layer of the first light-emitting element.

13. The display device according to claim 11, wherein, The intermediate electrode is stacked with the second semiconductor layer of the second light-emitting element.

14. The display device according to claim 11, wherein, The distance in the first direction between one end of the intermediate electrode and one end of the first semiconductor layer of the first light-emitting element is greater than the distance in the first direction between the other end of the intermediate electrode and one end of the second semiconductor layer of the second light-emitting element.

15. The display device according to claim 11, wherein, The distance in the first direction between one end of the intermediate electrode and the active layer of the first light-emitting element is the same as the distance in the first direction between the other end of the intermediate electrode and the active layer of the second light-emitting element.

16. The display device according to claim 11, wherein, The plurality of pixels also includes a dam pattern disposed below the intermediate electrode.

17. The display device according to claim 16, wherein, The distance in the first direction between one end of the intermediate electrode and one end of the embankment pattern is greater than the distance in the first direction between the other end of the intermediate electrode and the other end of the embankment pattern.

18. The display device according to claim 16, wherein, The distance in the first direction between one end of the embankment pattern and one end of the first light-emitting element is the same as the distance in the first direction between the other end of the embankment pattern and one end of the second light-emitting element.

19. The display device according to claim 16, wherein, The distance in the first direction between the active layer of the first light-emitting element and one end of the embankment pattern is greater than the distance in the first direction between the active layer of the second light-emitting element and the other end of the embankment pattern.

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