Pixel and display device including the same

Abstract

A pixel and a display device including the pixel are disclosed. The pixel may include: a light emitting device; and a pixel circuit connected to first to third gate control lines and the light emitting device, the pixel circuit including first to fourth nodes. The pixel circuit may include: a driving transistor connected to the first to third nodes; a first transistor connected to the first gate control line and the first and second nodes; a second transistor connected to the second gate control line, the second node and the first driving voltage line; a third transistor connected to the first gate control line, the third and fourth nodes; a fourth transistor connected to the first gate control line, the fourth node and the initialization voltage line; a fifth transistor connected to the third gate control line, the third node and the data line; and a storage capacitor disposed between the first and fourth nodes. Therefore, by sharing the gate control signal in adjacent horizontal rows, a narrow frame can be achieved and power consumption can be reduced.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2021-0101890, filed on August 3, 2021, which is hereby incorporated by reference as if fully set forth herein. Technical Field

[0003] The present disclosure relates to a pixel and a display device including the pixel. Background Art

[0004] With the advancement of information technology, the market for display devices as a connection medium between users and information is increasing. In addition to the information transmission based on letters between users, various types of communications are also active. As the type of information changes, the performance of display devices in displaying information is improving. Therefore, the use of various types of display devices such as organic light emitting display devices, liquid crystal display (LCD) devices, micro light emitting diode (LED) display devices and quantum dot (QD) display devices is increasing.

[0005] In a light-emitting display device, pixels including a light-emitting device and a driving transistor are arranged in a matrix type, and the brightness of an image displayed by the pixel is adjusted based on the grayscale of image data. The driving transistor controls a driving current flowing in the light-emitting device based on a voltage applied between its gate electrode and source electrode. The amount of light emitted from the light-emitting device is determined based on the driving current, and the brightness of the image is determined based on the amount of light emitted from the light-emitting device.

[0006] For example, in a light emitting display device, when a gate signal and a data signal are supplied to a sub-pixel, a light emitting device of a selected sub-pixel may emit light, and thus an image may be displayed. The light emitting device may be implemented based on an organic material or an inorganic material.

[0007] A light-emitting display device displays an image based on light emitted from a light-emitting device of a sub-pixel, and thus has various advantages, but it is necessary to improve the accuracy of a pixel driving circuit that controls the light emission of the sub-pixel, thereby improving image quality. For example, the accuracy of the pixel driving circuit can be improved by compensating for a threshold voltage of a driving transistor included in the pixel driving circuit.

[0008] The pixel driving circuit may further include a compensation circuit including a plurality of switching transistors and capacitors, in addition to a driving transistor and a switching transistor for supplying a data voltage, and may provide a plurality of scan signals for driving the compensation circuit.

[0009] The above background is what the inventor of the present application has in order to derive the present disclosure, or the above background is technical information obtained when deriving the present disclosure. The above background is not necessarily a known technology disclosed to the public before applying the present disclosure. Summary of the invention

[0010] As the resolution and power consumption of light-emitting display devices increase, driving technology for reducing the power consumption of light-emitting display devices is being developed. To reduce power consumption, pixels may be driven at a low frequency by reducing a frame rate during a specific period.

[0011] However, in order to improve the image quality characteristics of low-frequency driving, it is necessary to increase the number of gate control signals used to drive the pixel compensation circuit, thereby increasing the design area of ​​the gate driving circuit that generates and provides the gate control signal, making it difficult to achieve a narrow frame.

[0012] Furthermore, due to the switching of clocks for generating a plurality of gate control signals in the gate driving circuit in the low-frequency driving, there is a problem that the effect of reducing power consumption is reduced.

[0013] One aspect of the present disclosure is to provide a pixel and a display device including the pixel, wherein the number of gate control signals required for a pixel driving circuit is reduced by sharing gate control signals in adjacent horizontal lines, thereby achieving a narrow frame and reducing power consumption.

[0014] Other advantages and features of the present disclosure will be described in part in the following description and will become apparent to those of ordinary skill in the art when viewing the following or may be learned from the practice of the present disclosure. The purposes and other advantages of the present disclosure can be realized and obtained through the structures specifically pointed out in the written description and claims and the drawings.

[0015] To achieve these and other advantages and in accordance with the purposes of the present disclosure, as embodied and broadly described herein, there is provided a pixel comprising: a light emitting device; and a pixel circuit connected to a first gate control line, a second gate control line, and a third gate control line and the light emitting device, the pixel circuit comprising a first node, a second node, a third node, and a fourth node, wherein the pixel circuit comprises: a driving transistor connected to the first node to the third node; a first transistor connected to the first gate control line and the first node and the second node; a second transistor connected to the second gate control line, the second node, and a first driving voltage line; a third transistor connected to the first gate control line, the third node, and the fourth node; a fourth transistor connected to the first gate control line, the fourth node, and an initialization voltage line; a fifth transistor connected to the third gate control line, the third node, and a data line; and a storage capacitor disposed between the first node and the fourth node.

[0016] In another aspect of the present disclosure, a display device is provided, comprising: a display panel, the display panel comprising a display area and a non-display area arranged near the display area, wherein a plurality of pixels are arranged in a first direction and a second direction intersecting the first direction; and a gate driver, the gate driver being arranged in the non-display area to provide a scanning signal, a first light-emitting control signal, and a second light-emitting control signal to each of the plurality of pixels, wherein two pixels adjacent to each other in the second direction among the plurality of pixels share one or more of the first light-emitting control signal and the second light-emitting control signal.

[0017] In another aspect of the present disclosure, a display device is provided, comprising: a display panel, the display panel comprising a display area and a first non-display area and a second non-display area parallel to each other with the display area therebetween, wherein an nth pixel and an n+1th pixel vertically adjacent to each other are arranged in the display area, where n is an odd number of 1 or greater; a first gate driver, the first gate driver providing a first light-emitting control signal to the nth pixel and the n+1th pixel in the first non-display area; and a second gate driver, the second gate driver providing a second light-emitting control signal to the nth pixel and the n+1th pixel in the second non-display area, wherein each of the nth pixel and the n+1th pixel emits light based on the first light-emitting control signal and the second light-emitting control signal.

[0018] It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are used to provide a further understanding of the present disclosure and are incorporated into and constitute a part of the present application. These drawings illustrate embodiments of the present disclosure and together with the description are used to explain the principles of the present disclosure. In the drawings:

[0020] Figure 1 is a block diagram of a display device according to an embodiment of the present disclosure;

[0021] Figure 2 is a circuit diagram of a pixel circuit and a light emitting device according to an embodiment of the present disclosure;

[0022] Figure 3 is a waveform diagram of a voltage of a specific node and a gate signal input to a pixel circuit according to an embodiment of the present disclosure;

[0023] Figures 4 to 8 is a diagram for describing a driving method of a pixel circuit according to an embodiment of the present disclosure;

[0024] Fig. 9 is a block diagram illustrating a portion of a gate drive circuit according to an embodiment of the present disclosure; and

[0025] Fig.10 1 is a waveform diagram of a voltage of a specific node and a gate signal φ(V) input to a pixel circuit of each vertically adjacent pixel according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] The advantages and features of the present disclosure and its implementation methods will be more clearly understood through the following embodiments described in conjunction with the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided to make the present disclosure thorough and complete and to fully convey the scope of the present disclosure to those skilled in the art. In addition, the present disclosure is limited only by the scope of the claims.

[0027] The shapes, sizes, proportions, angles, and quantities disclosed in the drawings used to describe the embodiments of the present disclosure are examples only, and therefore, the present disclosure is not limited to the details shown. Throughout the application, the same reference numerals refer to the same elements. In the following description, when the detailed description of the relevant known functions or configurations is determined to be unnecessary to obscure the focus of the present disclosure, the detailed description will be omitted.

[0028] In the case where “including,” “having,” and “comprising” described in the present application are used, another part may be added unless “only to” is used. Terms in the singular form may include plural forms unless otherwise specified.

[0029] In interpreting an element, the element is interpreted as including a range of error even though it is not explicitly described.

[0030] When describing a positional relationship, for example, when the positional relationship is described as "on," "over," "under," and "beside," unless "just" or "directly" is used, another one or more parts may be arranged between the two parts.

[0031] When describing a time relationship, for example, when a time sequence is described as "after," "subsequently," "next," and "before," discontinuous cases may be included unless "just" or "directly" is used.

[0032] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to separate one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present disclosure.

[0033] The terms “first horizontal axis direction”, “second horizontal axis direction” and “vertical axis direction” should not be interpreted solely based on the geometric relationship that the directions are perpendicular to each other, and may refer to directions with wider directivity within the range in which the components of the present disclosure can functionally operate.

[0034] The term "at least one" should be understood to include any and all combinations of one or more of the related listed items. For example, the meaning of "at least one of the first, second, and third items" means a combination of two or more of the first, second, and third items and all items proposed by the first, second, or third items.

[0035] The features of the various embodiments of the present disclosure may be coupled or combined with each other in part or in whole, and may interoperate with each other in various ways and be technically driven as can be fully understood by those skilled in the art. The embodiments of the present disclosure may be implemented independently of each other or may be implemented together in an interdependent relationship.

[0036] Here, the pixel circuit and gate drive circuit provided on the substrate of the display panel may be implemented with an N-type or P-type transistor. For example, the transistor may be implemented as a transistor having an N-type or P-type metal oxide semiconductor field effect transistor (MOSFET) structure. The transistor may be a three-electrode element including a gate electrode, a source electrode, and a drain electrode. The source electrode and the drain electrode of the transistor may not be fixed and may be switched between them based on the applied voltage.

[0037] The gate signal of the transistor used as a switching element may swing between a gate-on voltage and a gate-off voltage. The gate-on voltage may be set to a voltage for turning on the transistor, and the gate-off voltage may be set to a voltage for turning off the transistor. In an N-type transistor, the gate-on voltage may be a gate high voltage (VGH) having a first voltage level, and the gate-off voltage may be a gate low voltage (VGL) having a second voltage level lower than the gate high voltage (VGH). In a P-type transistor, the gate-on voltage may be a gate low voltage (VGL) having a second voltage level, and the gate-off voltage may be a gate high voltage (VGH) having a first voltage level.

[0038] At least a first gate control line, a second gate control line, and a third gate control line may be provided between the gate driving circuit and the pixel circuit. The signal provided to the first gate control line may be referred to as a first signal, a first gate signal, a first gate control signal, or a first light-emitting control signal. In addition, the signal provided to the second gate control line may be referred to as a second signal, a second gate signal, a second gate control signal, or a second light-emitting control signal. In addition, the signal provided to the third gate control line may be referred to as a third signal, a third gate signal, a third gate control signal, or a third light-emitting control signal. In the following description, the signal provided to the first gate control line may be referred to as a "first light-emitting control signal", the signal provided to the second gate control line may be referred to as a "second light-emitting control signal", and the signal provided to the third gate control line may be referred to as a "scanning signal".

[0039] Hereinafter, preferred embodiments of a pixel and a display device including the pixel according to the present disclosure will be described in detail with reference to the accompanying drawings. Where possible, the same reference numerals will be used throughout the accompanying drawings to refer to the same or similar parts. Since the proportions of each element shown in the accompanying drawings are different from the actual proportions for ease of description, the present disclosure is not limited to the proportions shown.

[0040] Figure 1 is a block diagram of a display device 100 according to an embodiment of the present disclosure.

[0041] Reference Figure 1According to an embodiment of the present disclosure, a display device 100 may include a display panel 110 and a plurality of driving circuits for providing driving signals to the display panel 110, in which a plurality of data lines DL and a plurality of gate lines GL are arranged and a plurality of pixels PX connected to the plurality of data lines DL and the plurality of gate lines GL are arranged.

[0042] It is illustrated that the plurality of pixels PX are arranged in a matrix type to configure a pixel array, but the embodiments of the present disclosure are not limited thereto, and the plurality of pixels PX may be arranged in various types.

[0043] The driving circuit may include a data driving circuit 120 providing data signals to the plurality of data lines DL, a gate driving circuit GD providing gate signals to the plurality of gate lines GL, and a controller 130 controlling the data driving circuit 120 and the gate driving circuit GD.

[0044] The display panel 110 may include a display area DA displaying an image and a non-display area NDA disposed near the display area DA. A plurality of pixels PX, data lines DL transmitting data signals to the plurality of pixels PX, and gate lines GL transmitting gate signals to the plurality of pixels PX may be arranged in the display area DA.

[0045] A plurality of gate lines GL disposed in the display area DA may extend to the non-display area NDA and may be electrically connected to the gate drive circuit GD. The gate lines GL may electrically connect the gate drive circuit GD to a plurality of pixels PX arranged in a first direction (or row direction). In addition, gate drive-related lines required for generating various gate signals or driving a plurality of pixels PX by using the gate drive circuit GD may be arranged in the non-display area NDA. For example, the gate drive-related lines may include one or more high-level gate voltage lines for transmitting a high-level gate voltage to the gate drive circuit GD, one or more low-level gate voltage lines for transmitting a low-level gate voltage to the gate drive circuit GD, a plurality of clock lines for transmitting a plurality of clock signals to the gate drive circuit GD, and one or more start lines for transmitting one or more start signals to the gate drive circuit GD.

[0046] The plurality of data lines DL disposed in the display area DA may extend to the non-display area NDA and may be electrically connected to the data driving circuit 120. The data lines DL may electrically connect the data driving circuit 120 to the plurality of pixels PX arranged in a second direction (or a column direction) crossing the first direction and may be implemented as a single line or may be implemented by connecting a plurality of lines via contact holes using connection lines.

[0047] In the display panel 110, a plurality of data lines DL and a plurality of gate lines GL may be arranged together with a pixel array. As described above, a plurality of data lines DL and a plurality of gate lines GL may be arranged in rows or columns, and for convenience of description, it may be assumed that a plurality of data lines DL are arranged in columns and a plurality of gate lines GL are arranged in rows. However, the embodiments of the present disclosure are not limited thereto.

[0048] The controller 130 may start data signal scanning based on a timing implemented in each frame, convert input video data input from the outside to output converted image data based on a data signal format used in the data driving circuit 120, and control the data driving circuit 120 at an appropriate time based on the scanning.

[0049] The controller 130 may receive timing signals including a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, and a clock signal from the outside together with the input video data. The timing controller 130 may receive the timing signals to generate and output control signals for controlling the data driving circuit 120 and the gate driving circuit GD.

[0050] For example, the controller 130 may output various data control signals including a source start pulse, a source sampling clock, and a source output enable signal for controlling the data driving circuit 120. The source start pulse may control the data sampling start timing of one or more data signal generating circuits constituting the data driving circuit 120. The source sampling clock may be a clock signal that controls the sampling timing of data in each data signal generating circuit. The source output enable signal may control the output timing of the data driving circuit 120.

[0051] In addition, the controller 130 may output a gate control signal for controlling the gate drive circuit GD including a gate start pulse, a gate shift clock, and a gate output enable signal. The gate start pulse may control the operation start timing of one or more gate signal generating circuits constituting the gate drive circuit GD. The gate shift clock may be a clock signal commonly input to one or more gate signal generating circuits and may control the shift timing of the scan signal. The gate output enable signal may specify timing information about one or more gate signal generating circuits.

[0052] The controller 130 may be a timing controller used in a general display device technology, or may be a control device that performs another control function in addition to the timing controller.

[0053] The controller 130 may be implemented as a separate element from the data driving circuit 120, or the controller 130 and the data driving circuit 120 may be integrated and implemented as one integrated circuit (IC).

[0054] The data driving circuit 120 may be implemented to include one or more data signal generating circuits. The data signal generating circuit may include a shift register, a latch circuit, a digital-to-analog converter, and an output buffer. Depending on the situation, the data signal generating circuit may also include an analog-to-digital converter.

[0055] The data signal generating circuit may be connected to a bonding pad of the display panel 110 by using a tape automated bonding (TAB) type, a chip on glass (COG) type, or a chip on panel (COP) type, or may be directly disposed in the display panel 110 and may be integrated and disposed in the display panel 110. In addition, a plurality of data signal generating circuits may be implemented as a chip on film (COF) type in which the data signal generating circuit is mounted on a source circuit film connected to the display panel 110.

[0056] The gate driving circuit GD may sequentially provide gate signals to the plurality of gate lines GL to drive the plurality of pixels PX connected to the plurality of gate lines GL. The gate driving circuit GD may include a shift register and a level converter.

[0057] The gate driving circuit GD may be connected to a bonding pad of the display panel 110 by using a TAB type, a COG type, or a COP type, or may be implemented as a gate-in-panel (GIP) type and may be directly disposed in the display panel 110. In addition, a plurality of gate signal generating circuits may be implemented as a COF type in which the gate signal generating circuits are mounted on a gate circuit film connected to the display panel 110. The gate driving circuit GD may include a plurality of gate signal generating circuits, and the plurality of gate signal generating circuits may be implemented as a GIP type and may be disposed in the non-display area NDA of the display panel 110.

[0058] The gate driving circuit GD may sequentially provide a plurality of gate lines GL with gate signals having a gate high voltage VGH of a first voltage level for turning on / off the transistor or a gate low voltage VGL of a second voltage level for turning on / off the transistor based on the control of the controller 130. When a signal is provided to a specific gate line through the gate driving circuit GD, the data driving circuit 120 may convert image data received from the controller 130 into an analog data signal, and may provide the analog data signal to the plurality of data lines DL.

[0059] The data driving circuit 120 may be disposed on one side of the display panel 110. For example, the data driving circuit 120 may be disposed on the upper side, the lower side, the left side, or the right side of the display panel 110. In addition, the data driving circuit 120 may be disposed on both sides of the display panel 110 based on a driving type or a panel design type. For example, the data driving circuit 120 may be disposed on the upper side and the lower side, or the left side and the right side of the display panel 110.

[0060] The gate driving circuit GD may be disposed on one side of the display panel 110. For example, the gate driving circuit GD may be disposed on the upper side, the lower side, the left side, or the right side of the display panel 110. In addition, the gate driving circuit GD may be disposed on both sides of the display panel 110 based on the driving type or the panel design type. For example, the gate driving circuit GD may be disposed on the upper side and the lower side, or the left side and the right side of the display panel 110. The gate driving circuit GD may be formed in the left and / or right non-display areas NDA of the substrate together with the process of manufacturing the thin film transistor (TFT) of the pixel PX, and may be operated based on a single feed type to provide a gate signal to each of the plurality of gate lines GL. Alternatively, the gate driving circuit GD may be formed in each of the left and right non-display areas NDA of the substrate, and may be operated based on a dual feed type to provide a gate signal to each of the plurality of gate lines GL. Alternatively, the gate driving circuit GD may be formed in each of the left and right non-display areas NDA of the substrate, and may be operated based on an interlaced type to provide a gate signal to each of the plurality of gate lines GL.

[0061] An example is described in which a plurality of gate lines GL are arranged in a first direction (or row direction) and a plurality of pixels PX are arranged in a second direction (or column direction) intersecting the first direction in a display panel 110, and thus the present disclosure is described assuming that a data driving circuit 120 is disposed on the upper side of the display panel 110 and a gate driving circuit GD is disposed on the left and right sides of the display panel 110.

[0062] The plurality of gate lines GL provided in the display panel 110 may include a plurality of first gate control lines, a plurality of second gate control lines, and a plurality of third gate control lines. The first gate control line, the second gate control line, and the third gate control line may be lines for transmitting different kinds of gate signals to the gates of different transistors. For example, the first gate control line may be a line for transmitting a first light emission control signal, the second gate control line may be a line for transmitting a second light emission control signal, and the third gate control line may be a line for transmitting a scan signal.

[0063] Therefore, the gate driving circuit GD may include multiple first light-emitting control driving circuits that output first light-emitting control signals to the first gate control line of the gate line GL, multiple second light-emitting control driving circuits that output second light-emitting control signals to the second gate control line, and multiple scan driving circuits that output scan signals to the third gate control line.

[0064] The period in which all pixels PX arranged in the second direction (or column direction) in the display area DA are scanned by gate signals including the first and second light-emitting control signals and the scanning signal and the data signal is applied once each may be referred to as one frame period. One frame period may be divided into a scanning period, in which the data of the input image is applied to the pixel PX through the gate line GL connected to the pixel PX, and a light-emitting period after the scanning period, in which the pixel PX emits light based on the first and second light-emitting control signals. The scanning period may include an initialization period and a sampling period. In addition, the sampling period may include a programming period. During the scanning period, the nodes included in the pixel circuit may be initialized, the threshold voltage of the driving transistor may be compensated, and the data voltage may be charged; during the light-emitting period, the light-emitting operation may be performed. The scanning period may be only about several horizontal scanning periods, and most of one frame period may be occupied by the light-emitting period.

[0065] Figure 2 is a circuit diagram of a pixel circuit and a light emitting device according to an embodiment of the present disclosure. Figure 2 The pixel circuit and light emitting device shown in FIG. Figure 1 , and the pixels arranged in the n-th horizontal row will be described below.

[0066] Reference Figure 2 , a pixel circuit for transmitting a driving current to the light emitting device ED may include a plurality of transistors and capacitors, and may be electrically connected to a first driving voltage VDD line, a second driving voltage VSS line, an initialization voltage VINI line, a first gate control line GL1, a second gate control line GL2, a third gate control line GL3, and a data line DL. The pixel circuit according to an embodiment of the present disclosure may be an internal compensation circuit for compensating for a threshold voltage of a driving transistor DT.

[0067] The light emitting device ED may be disposed between a first electrode (or anode electrode) connected to the pixel circuit and a second electrode (or cathode electrode) connected to the second driving voltage VSS line. The light emitting device ED according to the embodiment may include an organic light emitting unit, a quantum dot light emitting unit, or an inorganic light emitting unit, or may include a micro light emitting diode device. The light emitting device ED may emit light using a data voltage provided from the pixel circuit.

[0068] The pixel circuit may include a driving transistor DT, five switching transistors T1 to T5, and a storage capacitor C. The pixel circuit may be provided with a first driving voltage VDD as a high level voltage, a second driving voltage VSS as a low level voltage, an initialization voltage VINI as a source voltage, the pixel circuit may be provided with a gate signal as a first light emitting control signal EM1(n), a second light emitting control signal EM2(n), and a scan signal Scan(n) through a gate driving circuit GD, and the pixel circuit may be provided with a data voltage Vdata through a data driving circuit 120. The first light emitting control signal EM1(n), the second light emitting control signal EM2(n), and the scan signal Scan(n) may be gate signals applied to pixels arranged in an n-th horizontal row.

[0069] The driving transistor DT may be a driving element that regulates a current flowing in the light emitting device ED based on its gate-source voltage Vgs, and may include a first node N1 connected to one side of the capacitor C, a second node N2 connected to the first transistor T1 and the second transistor T2, and a third node N3 connected to the third transistor T3 and the fifth transistor T5. The driving transistor DT may include a gate electrode connected to the first node N1, a drain electrode connected to the second node N2, and a source electrode connected to the third node N3.

[0070] When the first transistor T1 and the second transistor T2 are turned on, the driving transistor DT may store the first driving voltage VDD in the first node N1 as the gate electrode thereof. In addition, when the data voltage Vdata is provided in the state where the first transistor T1 is turned on, the data voltage Vdata may be applied to the first node N1 through the diode connection. In addition, the driving transistor DT may provide a driving current to the light emitting device ED based on the first light emitting control signal EM1(n) and the second light emitting control signal EM2(n), thereby adjusting the brightness of the light emitting device ED based on the amount of current.

[0071] The first transistor T1 may be connected to the first gate control line GL1, the first node N1, and the second node N2 and may be turned on or off by the first light emission control signal EM1(n) via the first gate control line GL1. For example, the first transistor T1 may be a TFT having a first conductivity type (or N-type), and when the first light emission control signal EM1(n) is a gate high voltage VGH having a first voltage level, the first transistor T1 may be turned on. In addition, when the first light emission control signal EM1(n) is a gate low voltage VGL having a second voltage level, the first transistor T1 may be turned off.

[0072] Therefore, when the first light emitting control signal EM1(n) is the gate high voltage VGH, the first transistor Tl can be turned on and the sampling voltage of the driving transistor DT or the first driving voltage VDD as the high level voltage of the second node N2 can be transmitted to the first node N1, thereby initializing the data voltage Vdata applied to the light emitting device ED or applying the data voltage Vdata to sample the threshold voltage Vth of the driving transistor DT.

[0073] The second transistor T2 may be connected to the second gate control line GL2, the second node N2, and the first driving voltage VDD line, and may be turned on or off by the second light emission control signal EM2(n) via the second gate control line GL2. For example, the second transistor T2 may be a TFT having a second conductivity type (or P-type), and when the second light emission control signal EM2(n) is a gate low voltage VGL having a second voltage level, the second transistor T2 may be turned on. In addition, when the second light emission control signal EM2(n) is a gate high voltage VGH having a first voltage level, the second transistor T2 may be turned off.

[0074] Therefore, when the second light emitting control signal EM2(n) is the gate low voltage VGL, the second transistor T2 may be turned on and may electrically connect the first driving voltage VDD line to the second node N2, so that the first driving voltage VDD may be provided to the second node N2. Therefore, the second transistor T2 may adjust the current amount of the light emitting device ED based on the data voltage Vdata.

[0075] The third transistor T3 may be connected to the first gate control line GL1, the third node N3, and the fourth node N4 connected to the anode electrode of the light emitting device ED, and may be turned on or off by the first light emission control signal EM1(n) via the first gate control line GL1. For example, the third transistor T3 may be a TFT having a second conductivity type (or P-type), and when the first light emission control signal EM1(n) is a gate low voltage VGL having a second voltage level, the third transistor T3 may be turned on. In addition, when the first light emission control signal EM1(n) is a gate high voltage VGH having a first voltage level, the third transistor T3 may be turned off.

[0076] Therefore, when the first light emission control signal EM1(n) is the gate low voltage VGL, the third transistor T3 may be turned on and the third node N3 may be electrically connected to the fourth node N4, and thus the voltage of the third node N3 may be supplied to the fourth node N4. Therefore, when the third transistor T3, the driving transistor DT, and the second transistor T2 are turned on, the first driving voltage VDD may be supplied to the driving transistor DT and the driving current may be supplied to the light emitting device ED, and thus the light emitting device ED may emit light.

[0077] The fourth transistor T4 may be connected to the first gate control line GL1, the fourth node N4, and the initialization voltage VINI line, and may be turned on or off by the first light emission control signal EM1(n) via the first gate control line GL1. For example, the fourth transistor T4 may be a TFT having a first conductivity type (or N-type), and when the first light emission control signal EM1(n) is a gate high voltage VGH having a first voltage level, the fourth transistor T4 may be turned on. In addition, when the first light emission control signal EM1(n) is a gate low voltage VGL having a second voltage level lower than the first voltage level, the fourth transistor T4 may be turned off.

[0078] Therefore, when the first light emitting control signal EM1(n) is the gate high voltage VGH, the fourth transistor T4 can be turned on and can electrically connect the initialization voltage VINI line to the fourth node N4, thereby transmitting the initialization voltage VINI to the fourth node N4 to initialize the data voltage Vdata applied to the light emitting device ED.

[0079] The fifth transistor T5 may be connected to the third gate control line GL3, the third node N3, and the data line DL, and may be turned on or off by the scan signal Scan(n) via the third gate control line GL3. For example, the fifth transistor T5 may be a TFT having a second conductivity type (or P-type), and when the scan signal Scan(n) is a gate low voltage VGL having a second voltage level, the fifth transistor T5 may be turned on. In addition, when the scan signal Scan(n) is a gate high voltage VGH having a first voltage level, the fifth transistor T5 may be turned off.

[0080] Therefore, when the scan signal Scan(n) is the gate low voltage VGL, the fifth transistor T5 may be turned on and may electrically connect the data line DL to the third node N3 , and thus the data voltage Vdata may be provided to the third node N3 .

[0081] The capacitor C may be a storage capacitor C that stores a voltage applied to a first node N1 connected to a gate electrode of the driving transistor DT, and may be disposed between the second node N1 and a fourth node N4 connected to an anode electrode of the light emitting device ED. The capacitor C may be connected to the first node N1 and the fourth node N4, and may store a voltage difference between a voltage at the gate electrode of the driving transistor DT and a voltage supplied to the anode electrode of the light emitting device ED.

[0082] The pixel circuit according to an embodiment of the present disclosure may be configured with a plurality of types of transistors in which semiconductor layers included in the driving transistor DT and the first to fifth transistors T1 to T5 include different materials.

[0083] For example, in a pixel circuit including multiple types of transistors, a TFT including a semiconductor layer of crystalline silicon may include a low-temperature polycrystalline silicon (LTPS) TFT including LTPS, and a TFT including a semiconductor layer of oxide may include an oxide semiconductor TFT including a low-temperature polycrystalline oxide (LTPO).

[0084] In the pixel circuit according to the embodiment of the present disclosure, the driving transistor DT and the driving transistor DT, the first transistor T1 and the fourth transistor T4 among the first transistor T1 to the fifth transistor T5 may be configured as a TFT having a first conductivity type (or N-type), and the second transistor T2, the third transistor T3 and the fifth transistor T5 may be configured as a TFT having a second conductivity type (or P-type). For example, the driving transistor DT may be configured as an oxide semiconductor TFT having a first conductivity type (or N-type), the first transistor T1 and the fourth transistor T4 may be configured as an LTPS TFT or an oxide semiconductor TFT having a first conductivity type (or N-type), and the second transistor T2, the third transistor T3 and the fifth transistor T5 may be configured as an LTPS TFT having a second conductivity type (or P-type).

[0085] Polycrystalline silicon semiconductor materials can have a high electron mobility (100cm 2 / Vs or higher), thus having low power consumption and excellent reliability. The oxide semiconductor material may have a lower cut-off current, thus having a short on-time and maintaining a longer cut-off time. Therefore, in the pixel circuit according to the embodiment of the present disclosure, the driving transistor DT that needs to accurately control the current and needs a low leakage current in the low-frequency drive for low-power drive, and the first transistor T1 and the fourth transistor T4 may each be implemented as an oxide semiconductor TFT having a first conductivity type (or N-type), and the second transistor T2, the third transistor T3, and the fifth transistor T5 that are arranged in the supply path of the current and need fast and stable driving characteristics may each be implemented as an LTPS TFT having a second conductivity type (or P-type). In addition, the first transistor T1 and the fourth transistor T4 connected to the same first gate control line GL1 may each be implemented as a TFT having a first conductivity type (or N-type), and the third transistor T3 may be implemented as a TFT having a second conductivity type (or P-type), thereby minimizing the structure of the gate drive circuit and the gate line.

[0086] Therefore, in a display device according to an embodiment of the present disclosure, TFTs having characteristics suitable for the performance required of transistors for constructing pixel circuits can be arranged to share gate control signals, so that low-frequency driving for low-power driving can be performed, and the construction of the gate driving circuit and the gate line can be minimized, thereby achieving a narrow border and improving power consumption.

[0087] Figure 3 is a waveform diagram of a voltage of a specific node and a gate signal input to a pixel circuit according to an embodiment of the present disclosure, Figures 4 to 8 is a diagram for describing a driving method of a pixel circuit according to an embodiment of the present disclosure. Figure 3 The waveforms shown in Figure 2 , and is used to describe the pixels arranged in the n-th horizontal line.

[0088] Reference Figure 3 as well as Figures 4 to 8 , the pixel circuit according to the embodiment of the present disclosure may be separately driven in the first interval ①, the second interval ②, the third interval ③, the fourth interval ④, and the fifth interval ⑤. For example, each pixel arranged in the nth horizontal row may be provided with a data voltage Vdata through the first to fifth intervals ①, ②, ③, ④, and ⑤ and may emit light. According to the embodiment, the time of each of the first to fifth intervals ①, ②, ③, ④, and ⑤ may be changed differently.

[0089] The gate signals input to the pixel circuit may include a first emission control signal EM1(n) applied via the first gate control line GL1, a second emission control signal EM2(n) applied via the second gate control line GL2, and a scan signal Scan(n) applied via the third gate control line GL3.

[0090] The first light emission control signal EM1(n) may have a gate high voltage VGH of a first voltage level in the first to third intervals ①, ②, and ③, and may have a gate low voltage VGL of a second voltage level different from the first voltage level in the fourth and fifth intervals ④ and ⑤.

[0091] The second light emitting control signal EM2(n) may have the same period as the first light emitting control signal EM1(n), have a phase overlapping with the phase of the first light emitting control signal EM1(n), have a gate high voltage VGH of a first voltage level in the second to fourth intervals ②, ③ and ④, and have a gate low voltage VGL of a second voltage level in the first interval ① and the fifth interval ⑤.

[0092] The scan signal Scan(n) may have a gate high voltage VGH of a first voltage level in the first interval ① and the third to fifth intervals ③, ④, and ⑤, and may have a gate low voltage VGL of a second voltage level in the second interval ②. In an interval where the phase of the first light emitting control signal EM1(n) overlaps with the phase of the second light emitting control signal EM2(n), a pulse of the scan signal Scan(n) having the gate low voltage VGL may have a period of one horizontal period 1H in one frame. According to embodiments, the pulse period of the scan signal Scan(n) may be variously changed.

[0093] In the following, reference will be made to Figures 4 to 8 The operation of the pixel circuit in each driving period is described.

[0094] First, at the time when the first interval ① starts, the first light emitting control signal EM1(n) may rise and may have a gate high voltage VGH, the second light emitting control signal EM2(n) may maintain a gate low voltage VGL, and the scan signal Scan(n) may maintain a gate high voltage VGH. Figure 4 As shown in the figure, during the first interval ①, based on the gate high voltage VGH of the first light emitting control signal EM1(n), the first transistor T1 and the fourth transistor T4 can be turned on and the third transistor T3 can be turned off; based on the gate low voltage VGL of the second light emitting control signal EM2(n), the second transistor T2 can be turned on; and based on the gate high voltage VGH of the scan signal Scan(n), the fifth transistor T5 can be turned off.

[0095] Therefore, the initialization voltage VINI may be supplied to the fourth node N4 through the fourth transistor T4, and the first driving voltage VDD applied to the second node N2 through the second transistor T2 may be supplied to the first node N1 through the first transistor T1. That is, when the initialization voltage VINI is supplied to the fourth node N4 connected to the anode electrode of the light emitting device ED, the data voltage Vdata applied to the light emitting device ED may be initialized, and the first driving voltage VDD may be supplied to the first node N1 connected to the gate electrode of the driving transistor DT.

[0096] At the time when the second interval ② starts, the scan signal Scan(n) may drop and may have a gate low voltage VGL, the first light emitting control signal EM1(n) may maintain a gate high voltage VGH, and the second light emitting control signal EM2(n) may rise to a gate high voltage VGH and may maintain a gate high voltage VGH. At this time, the second light emitting control signal EM2(n) may first rise to a gate high voltage VGH before the second interval ② starts, so the second light emitting control signal EM2(n) and the scan signal Scan(n) may not be mixed. The period when the second light emitting control signal EM2(n) first rises may be approximately one horizontal period 1H, but the embodiments of the present disclosure are not limited thereto. Figure 5 As shown in, during the second interval ②, based on the gate high voltage VGH of the first light emitting control signal EM1(n), the first transistor T1 and the fourth transistor T4 can be turned on and the third transistor T3 can be turned off; based on the gate high voltage VGH of the second light emitting control signal EM2(n), the second transistor T2 can be turned off; and based on the gate low voltage VGL of the scan signal Scan(n), the fifth transistor T5 can be turned on.

[0097] Therefore, the data voltage Vdata may be provided to the third node N3 through the fifth transistor T5. In addition, when the second transistor T2 is turned off and the first transistor T1 is turned on, the first node N1 and the second node N2 of the driving transistor DT may be connected to each other, and thus the gate-source voltage Vgs of the driving transistor DT may be sampled as the threshold voltage Vth of the driving transistor DT through the diode connection. In addition, as the fourth transistor T4 is turned on, the initialization voltage VINI may be provided to the fourth node N4, and the voltage difference "Vdata+Vth-VINI" between the sum of the data voltage Vdata and the threshold voltage Vth of the driving transistor DT and the initialization voltage VINI may be stored in the capacitor C. Therefore, during the second interval ②, the voltage of each of the first node N1 and the second node N2 may converge to a voltage that is the sum of the data voltage Vdata and the threshold voltage Vth of the driving transistor DT, the voltage of the third node N3 may be the data voltage Vdata, and the voltage of the fourth node N4 may be the initialization voltage VINI.

[0098] At the start time of the third interval ③, the scan signal Scan(n) may rise and may have a gate high voltage VGH, the first light emitting control signal EM1(n) may maintain the gate high voltage VGH, and the second light emitting control signal EM2(n) may maintain the gate high voltage VGH. Figure 6 As shown in, during the third interval ③, based on the gate high voltage VGH of the first light emitting control signal EM1(n), the first transistor T1 and the fourth transistor T4 can be turned on and the third transistor T3 can be turned off; based on the gate high voltage VGH of the second light emitting control signal EM2(n), the second transistor T2 can be turned off; and based on the gate high voltage VGH of the scan signal Scan(n), the fifth transistor T5 can be turned off.

[0099] Therefore, when the second transistor T2, the third transistor T3 and the fifth transistor T5 are turned off, each of the first node N1, the second node N2, the third node N3 and the fourth node N4 to which the voltage is sampled or applied can float in the second interval ②, and the voltage of each node can be maintained.

[0100] At the start time of the fourth interval ④, the first light emitting control signal EM1(n) may fall and may have a gate low voltage VGL, the second light emitting control signal EM2(n) may maintain a gate high voltage VGH, and the scan signal Scan(n) may maintain a gate high voltage VGH. Figure 7As shown in , during the fourth period ④, only the third transistor T3 may be turned on, and the first, second, fourth and fifth transistors T1, T2, T4 and T5 may be turned off. Therefore, the third transistor T3 may be turned on and may be connected to the third node N3 and the fourth node N4, and the data voltage Vdata maintained by the third node N3 may be provided to the fourth node N4.

[0101] At the time when the fifth interval ⑤ starts, the second light emitting control signal EM2(n) may fall and may have a gate low voltage VGL, the first light emitting control signal EM1(n) may maintain the gate low voltage VGL, and the scan signal Scan(n) may maintain the gate high voltage VGH. Figure 8 As shown in , during the fifth interval ⑤, the first, fourth and fifth transistors T1, T4 and T5 may be turned off, and the second transistor T2 and the third transistor T3 may be turned on. In addition, the driving transistor DT may be turned on by the sum of the threshold voltage Vth of the driving transistor DT and the voltage of the data voltage Vdata stored in the first node N1, thereby forming a path for the driving current to flow from the first driving voltage VDD line to the light emitting device ED. That is, the driving current may flow to the light emitting device ED through the driving transistor DT, the second transistor T2 and the third transistor T3 turned on during the fifth interval ⑤. In addition, in the fifth interval ⑤, the gate-source voltage Vgs of the driving transistor DT may be referred to as the data voltage Vdata, and the threshold voltage Vth of the driving transistor DT may be compensated, so that the level of the driving current may be adjusted based on the level of the data voltage Vdata of the driving transistor DT, and the light emitting device ED may emit light using the driving current, thereby increasing the brightness.

[0102] Fig. 9 is a block diagram illustrating a portion of a gate driving circuit according to an embodiment of the present disclosure. Fig. 9 The gate drive circuit shown in Figure 1 1 and is used to describe a stage of the gate driving circuit corresponding to pixels arranged in nth to n+3th horizontal rows among the pixels arranged in the display panel 110.

[0103] Combination Figure 1 For reference Fig. 9According to an embodiment of the present disclosure, the gate driving circuit GD may include a plurality of gate signal generating circuits including stages ST corresponding to the pixels PX arranged in each horizontal row. For example, the gate driving circuit GD may include a plurality of first light emitting control driving circuits EM1 ST(n / n+1) and EM1 ST(n+2 / n+3) outputting a plurality of first light emitting control signals EM1, a plurality of second light emitting control driving circuits EM2 ST(n / n+1) and EM2 ST(n+2 / n+3) outputting a plurality of second light emitting control signals EM2, and a plurality of scan driving circuits Scan ST(n), Scan ST(n+1), Scan ST(n+2), and Scan ST(n+3) outputting a plurality of scan signals Scan.

[0104] like Fig. 9 As shown in , the gate driving circuit GD may be separately disposed in the left non-display area NDA and the right non-display area NDA divided based on the display area DA of the display panel 110. For example, the gate driving circuit GD may include a first gate driving circuit GD_R disposed in the left non-display area NDA and a second gate driving circuit GD_L disposed in the right non-display area NDA.

[0105] The first gate driving circuit GD_R and the second gate driving circuit GD_L may be configured to output gate signals having different timings, and may be circuits having the same structure or may be different circuits outputting different gate signals.

[0106] Each of the first gate drive circuit GD_R and the second gate drive circuit GD_L may include a plurality of first light-emitting control drive circuits EM1 ST (n / n+1) and EM1 ST (n+2 / n+3), a plurality of second light-emitting control drive circuits EM2 ST (n / n+1) and EM2 ST (n+2 / n+3), and a plurality of scan drive circuits Scan ST (n), Scan ST (n+1), Scan ST (n+2), and Scan ST (n+3). For example, the first gate drive circuit GD_R may include the second light-emitting control drive circuits EM2 ST (n / n+1) and EM2 ST (n+2 / n+3) and some scan drive circuits Scan ST (n) and Scan ST (n+2), and the second gate drive circuit GD_L may include the first light-emitting control drive circuits EM1 ST (n / n+1) and EM1 ST (n+2 / n+3) and some scan drive circuits Scan ST (n+1) and Scan ST (n+3).

[0107] The first light emitting control driving circuit EM1 ST (n / n+1) and EM1 ST (n+2 / n+3) may be disposed in the right non-display area and may have a subordinate connection structure, and furthermore, each of the first light emitting control driving circuit EM1 ST (n / n+1) and EM1 ST (n+2 / n+3) may receive an output signal of at least one previous stage or a next stage as an input signal. The first light emitting control driving circuit EM1 ST (n / n+1) and EM1 ST (n+2 / n+3) may share clock signals EM1 CLK1 and EM1 CLK2 and driving voltages VGH and VGL, and a start signal EM1 VST may be applied to the first light emitting control driving circuit EM1 ST (n / n+1) of the previous stage. Each of the first light emitting control driving circuit EM1 ST (n / n+1) and EM1 ST (n+2 / n+3) may provide a first light emitting control signal shared by pixels arranged in horizontal rows vertically adjacent to each other. For example, the first light emission control driving circuit EM1 ST(n / n+1) may provide the first light emission control signal to the pixel Line(n)PX arranged in the nth horizontal line and the pixel Line(n+1)PX arranged in the n+1th horizontal line, and another first light emission control driving circuit EM1 ST(n+2 / n+3) may provide the first light emission control signal to the pixel Line(n+2)PX arranged in the n+2th horizontal line and the pixel Line(n+3)PX arranged in the n+3th horizontal line. That is, each of the first light emission control driving circuits EM1 ST(n / n+1) and EM1 ST(n+2 / n+3) may be configured to provide the first light emission control signal shared by the pixels arranged in two adjacent horizontal lines, and thus may be designed to have a structure in which the width of each circuit level in the horizontal direction is smaller than the width of each circuit level in the vertical direction, thereby reducing the border area of ​​the display panel.

[0108] The second light emitting control driving circuit EM2 ST (n / n+1) and EM2 ST (n+2 / n+3) may be arranged in the left non-display area and may have a subordinate connection structure. In addition, each of the second light emitting control driving circuit EM2 ST (n / n+1) and EM2 ST (n+2 / n+3) may receive an output signal of at least one previous stage or a next stage as an input signal. The second light emitting control driving circuit EM2 ST (n / n+1) and EM2 ST (n+2 / n+3) may share clock signals EM2 CLK1 and EM2 CLK2 and driving voltages VGH and VGL, and the start signal EM2 VST may be applied to the second light emitting control driving circuit EM2 ST (n / n+1) of the previous stage. Each of the second light emitting control driving circuit EM2 ST (n / n+1) and EM2 ST (n+2 / n+3) may provide a second light emitting control signal shared by pixels arranged in horizontal rows vertically adjacent to each other. For example, the second light emitting control driving circuit EM2 ST(n / n+1) can provide the second light emitting control signal to the pixels Line(n)PX arranged in the nth horizontal row and the pixels Line(n+1)PX arranged in the n+1th horizontal row, and another second light emitting control driving circuit EM2 ST(n+2 / n+3) can provide the second light emitting control signal to the pixels Line(n+2)PX arranged in the n+2th horizontal row and the pixels Line(n+3)PX arranged in the n+3th horizontal row. That is, each of the second light emitting control driving circuits EM2 ST(n / n+1) and EM2 ST(n+2 / n+3) can be configured to provide the first light emitting control signal shared by the pixels arranged in two adjacent horizontal rows, and thus can be designed to be a structure in which the width of each circuit level in the horizontal direction is smaller than the width of each circuit level in the vertical direction, thereby reducing the border area of ​​the display panel.

[0109] The scan drive circuits Scan ST(n), Scan ST(n+1), Scan ST(n+2) and Scan ST(n+3) may be separately arranged in the left non-display area and the right non-display area, and may have a subordinate connection structure in each area, and each scan drive circuit may receive an output signal of at least the previous stage or the next stage as an input signal. The scan drive circuits Scan ST(n), Scan ST(n+1), Scan ST(n+2) and Scan ST(n+3) may share clock signals Scan CLK1 and Scan CLK2 and drive voltages VGH and VGL, and the start signal Scan VST may be applied to the scan drive circuit Scan ST(n) of the previous stage. The scan drive circuits Scan ST(n), Scan ST(n+1), Scan ST(n+2) and Scan ST(n+3) may sequentially provide scan signals to pixels arranged in each horizontal row. The scan drive circuits Scan ST(n), Scan ST(n+1), Scan ST(n+2) and Scan ST(n+3) may be alternately arranged in the left non-display area and the right non-display area. For example, the scan drive circuit Scan ST(n) corresponding to the pixel Line(n) PX arranged in the nth horizontal line may be arranged in the left non-display area, the scan drive circuit Scan ST(n+1) corresponding to the pixel Line(n+1) PX arranged in the n+1th horizontal line may be arranged in the right non-display area, the scan drive circuit Scan ST(n+2) corresponding to the pixel Line(n+2) PX arranged in the n+2th horizontal line may be arranged in the left non-display area, and the scan drive circuit Scan ST(n+3) corresponding to the pixel Line(n+3) PX arranged in the n+3th horizontal line may be arranged in the right non-display area. That is to say, the scan driving circuits Scan ST(n), Scan ST(n+1), Scan ST(n+2) and Scan ST(n+3) can be separately arranged in the left non-display area and the left non-display area, and thus can be designed into a structure in which the width of each circuit level in the horizontal direction is smaller than the width of each circuit level in the vertical direction, thereby reducing the border area of ​​the display panel.

[0110] Fig.10 is a waveform diagram of a voltage of a specific node and a gate signal input to a pixel circuit of each of vertically adjacent pixels according to an embodiment of the present disclosure. Fig.10 The waveform diagram shown in relates to pixels vertically adjacent to each other, and is used to describe pixels arranged in an n-th horizontal line and pixels arranged in an (n+1)-th horizontal line.

[0111] Reference Fig.10, the pixel circuit of each of the vertically adjacent pixels according to the embodiment of the present disclosure may be driven separately in the first interval ①, the second interval ②' and ②", the third interval ③' and ③", the fourth interval ④, and the fifth interval ⑤. For example, each pixel arranged in the nth horizontal row may be provided with a data voltage Vdata through the first to fifth intervals ①, ②', ③', ④, and ⑤ and may emit light, and each pixel arranged in the n+1th horizontal row may be provided with a data voltage Vdata through the first to fifth intervals ①, ②", ③", ④, and ⑤ and may emit light. Here, each pixel arranged in the nth horizontal row may be referred to as the nth pixel, and each pixel arranged in the n+1th horizontal row may be referred to as the n+1th pixel. Each of the nth pixel and the n+1th pixel may be driven identically in the first interval ①, the second interval ②' and ②", the third interval ③' and ③", the fourth interval ④, and the fifth interval ⑤, and may be driven differently in the second interval ②' and ②" and the third interval ③' and ③". For example, the second interval ②" and the third interval ③" of the n+1th pixel may be driven in the opposite order as compared to the second interval ②' and the third interval ③' of the nth pixel. That is, the nth pixel may be first driven in the second interval ②' and then may be driven in the third interval ③', and the n+1th pixel may be first driven in the third interval ③" and then may be driven in the second interval ②". According to an embodiment, the times of the first to fifth intervals ①, ②', ③', ④ and ⑤ of the nth pixel and the first to fifth intervals ①, ②", ③", ④ and ⑤ of the n+1th pixel may be changed differently.

[0112] The gate signals input to the pixel circuits of the nth pixel and the n+1th pixel vertically adjacent to each other may include a first light emitting control signal EM1(n / n+1) applied via the first gate control line GL1, a light emitting control signal EM2(n / n+1) applied via the second gate control line GL2, and scan signals Scan(n) and Scan(n+1) applied via the third gate control line GL3.

[0113] The first light emitting control signal EM1 (n / n+1) may be shared and applied by the nth pixel and the n+1th pixel, and for the driving interval of the nth pixel, the first light emitting control signal EM1 (n / n+1) may have a gate high voltage VGH of a first voltage level in the first to third intervals ①, ②' and ③', and may have a gate low voltage VGL of a second voltage level different from the first voltage level in the fourth interval ④ and the fifth interval ⑤. In addition, for the driving interval of the n+1th pixel, the first light emitting control signal EM1 (n / n+1) may have a gate high voltage VGH of a first voltage level in the first, third and second intervals ①, ③" and ②", and may have a gate low voltage VGL of a second voltage level different from the first voltage level in the fourth interval ④ and the fifth interval ⑤.

[0114] The second light emitting control signal EM2(n / n+1) may be shared and applied by the nth pixel and the n+1th pixel, and may have the same period as the first light emitting control signal EM1(n / n+1) and a phase overlapping with the phase of the first light emitting control signal EM1(n / n+1). In addition, for the driving interval of the nth pixel, the second light emitting control signal EM2(n / n+1) may have a gate high voltage VGH of a first voltage level in the second to fourth intervals ②', ③', and ④, and may have a gate low voltage VGL of a second voltage level in the first interval ① and the fifth interval ⑤. In addition, for the driving interval of the n+1th pixel, the second light emitting control signal EM2(n / n+1) may have a gate high voltage VGH of a first voltage level in the third, second, and fourth intervals ③", ②", and ④, and may have a gate low voltage VGL of a second voltage level in the first interval ① and the fifth interval ⑤.

[0115] The scan signals Scan(n) and Scan(n+1) may include an nth scan signal Scan(n) corresponding to an nth pixel and an n+1th scan signal Scan(n+1) corresponding to an n+1th pixel. In the interval in which the first light emitting control signal EM1(n / n+1) and the second light emitting control signal EM2(n / n+1) overlap each other in the gate high voltage VGH, the nth scan signal Scan(n) and the n+1th scan signal Scan(n+1) may not overlap each other. The nth scan signal Scan(n) may have a gate high voltage VGH of a first voltage level in the first interval ① and the third to fifth intervals ③', ④ and ⑤ of the nth pixel, and may have a gate low voltage VGL of a second voltage level in the second interval ②'. In addition, the n+1th scan signal Scan(n+1) may have a gate high voltage VGH of a first voltage level in the first interval ① and the third to fifth intervals ③", ④ and ⑤ of the n+1th pixel, and may have a gate low voltage VGL of a second voltage level in the second interval ②".

[0116] Therefore, in an interval in which the first light emitting control signal EM1(n / n+1) and the second light emitting control signal EM2(n / n+1) overlap each other in the gate high voltage VGH having the first voltage level, the second interval ②' and ②" and the third interval ③' and ③" of each of the nth pixel and the n+1th pixel may overlap. In addition, the second interval ②' and ②" of each of the nth pixel and the n+1th pixel may be an interval in which each of the scan signals Scan(n) and Scan(n+1) has the gate low voltage VGL of the second voltage level in an interval in which the first light emitting control signal EM1(n / n+1) and the second light emitting control signal EM2(n / n+1) overlap with each other in the gate high voltage VGH having the first voltage level, and the third interval ③' and ③" of each of the nth pixel and the n+1th pixel may be an interval other than the second interval ②' and ②" in an interval in which the first light emitting control signal EM1(n / n+1) and the second light emitting control signal EM2(n / n+1) overlap with each other in the gate high voltage VGH having the first voltage level.

[0117] In the following, reference will be made to Figures 4 to 8 The operation of the pixel circuit in each of the driving intervals of the nth pixel and the n+1th pixel is described. The operation of the pixel circuit of the nth pixel can be described with reference to the above Figure 3 The descriptions given are the same, and thus only the operation of the pixel circuit of the (n+1)th pixel will be described below and repeated descriptions will be omitted.

[0118] First, at the time when the first interval ① of the n+1th pixel starts, the first light emitting control signal EM1(n / n+1) may rise and may have a gate high voltage VGH, the second light emitting control signal EM2(n / n+1) may maintain a gate low voltage VGL, and the scan signal Scan(n+1) may maintain a gate high voltage VGH. Figure 4 As shown in, during the first interval ①, based on the gate high voltage VGH of the first light emitting control signal EM1(n / n+1), the first transistor T1 and the fourth transistor T4 can be turned on and the third transistor T3 can be turned off; based on the gate low voltage VGL of the second light emitting control signal EM2(n / n+1), the second transistor T2 can be turned on; based on the gate high voltage VGH of the scan signal Scan(n)+1, the fifth transistor T5 can be turned off.

[0119] Therefore, the initialization voltage VINI may be supplied to the fourth node N4 through the fourth transistor T4, and the first driving voltage VDD applied to the second node N2 through the second transistor T2 may be supplied to the first node N1 through the first transistor T1. That is, when the initialization voltage VINI is supplied to the fourth node N4 connected to the anode electrode of the light emitting device ED, the data voltage Vdata applied to the light emitting device ED may be initialized, and the first driving voltage VDD may be supplied to the first node N1 connected to the gate electrode of the driving transistor DT.

[0120] Unlike the nth pixel, in the n+1th pixel, the third interval ③" may be performed first, and the second interval ②" may be performed subsequently. During the third interval ③" of the n+1th pixel, the scan signal Scan(n+1) may maintain the gate high voltage VGH, the first light emitting control signal EM1(n / n+1) may maintain the gate high voltage VGH, and the second light emitting control signal EM2(n / n+1) may rise to the gate high voltage VGH and may maintain the gate high voltage VGH. Figure 6 As shown in the figure, during the third interval ③", based on the gate high voltage VGH of the first light emitting control signal EM1(n / n+1), the first transistor T1 and the fourth transistor T4 may be turned on and the third transistor T3 may be turned off; based on the gate high voltage VGH of the second light emitting control signal EM2(n / n+1), the second transistor T2 may be turned off; and based on the gate high voltage VGH of the scan signal Scan(n+1), the fifth transistor T5 may be turned off.

[0121] Therefore, the second transistor T2, the third transistor T3, and the fifth transistor T5 may be turned off, and thus the voltages of the first node N1, the second node N2, the third node N3, and the fourth node N4 initialized in the first interval ① may be maintained.

[0122] At the time when the second interval ②" of the n+1th pixel starts, the scan signal Scan(n+1) may fall and may have a gate low voltage VGL, the first light emitting control signal EM1(n / +1) may maintain a gate high voltage VGH, and the second light emitting control signal EM2(n / n+1) may maintain a gate high voltage VGH. At this time, the time of the scan signal Scan(n+1) of the n+1th pixel may have a specific interval after the time when the scan signal Scan(n) of the nth pixel rises again, so the scan signals Scan(n) and Scan(n+1) may not be mixed. The interval between the scan signals Scan(n) and Scan(n+1) may be within about one horizontal period 1H, but the embodiments of the present disclosure are not limited thereto. Figure 5As shown in the figure, during the second interval ②", based on the gate high voltage VGH of the first light emitting control signal EM1(n / n+1), the first transistor T1 and the fourth transistor T4 can be turned on and the third transistor T3 can be turned off; based on the gate high voltage VGH of the second light emitting control signal EM2(n / n+1), the second transistor T2 can be turned off; based on the gate low voltage VGL of the scan signal Scan(n+1), the fifth transistor T5 can be turned on.

[0123] Therefore, the data voltage Vdata may be provided to the third node N3 through the fifth transistor T5. In addition, when the second transistor T2 is turned off and the first transistor T1 is turned on, the first node N1 and the second node N2 of the driving transistor DT may be connected to each other, and thus the gate-source voltage Vgs of the driving transistor DT may be sampled as the threshold voltage Vth of the driving transistor DT through the diode connection. In addition, as the fourth transistor T4 is turned on, the initialization voltage VINI may be provided to the fourth node N4, and the voltage difference "Vdata+Vth-VINI" between the sum of the data voltage Vdata and the threshold voltage Vth of the driving transistor DT and the initialization voltage VINI may be stored in the capacitor C. Therefore, during the second interval ②", the voltage of each of the first node N1 and the second node N2 may converge to a voltage that is the sum of the data voltage Vdata and the threshold voltage Vth of the driving transistor DT, the voltage of the third node N3 may be the data voltage Vdata, and the voltage of the fourth node N4 may be the initialization voltage VINI.

[0124] At the time when the fourth interval ④ of the n+1th pixel starts, the scan signal Scan(n+1) may rise and may have a gate high voltage VGH, the first light emitting control signal EM1(n / n+1) may fall and may have a gate low voltage VGL, and the second light emitting control signal EM2(n / n+1) may maintain the gate high voltage VGH. Figure 7 As shown in , during the fourth period ④, only the third transistor T3 may be turned on, and the first, second, fourth and fifth transistors T1, T2, T4 and T5 may be turned off. Therefore, the third transistor T3 may be turned on and may be connected to the third node N3 and the fourth node N4, and the data voltage Vdata maintained by the third node N3 may be provided to the fourth node N4.

[0125] At the time when the fifth interval ⑤ starts, the second light emitting control signal EM1(n / n+1) may fall and may have a gate low voltage VGL, the first light emitting control signal EM1(n / n+1) may maintain the gate low voltage VGL, and the scan signal Scan(n+1) may maintain the gate high voltage VGH. Figure 8As shown in , during the fifth interval ⑤, the first, fourth and fifth transistors T1, T4 and T5 may be turned off, and the second transistor T2 and the third transistor T3 may be turned on. In addition, the driving transistor DT may be turned on by the sum of the threshold voltage Vth of the driving transistor DT and the voltage of the data voltage Vdata stored in the first node N1, thereby forming a path for the driving current to flow from the first driving voltage VDD line to the light emitting device ED. That is, the driving current may flow to the light emitting device ED through the driving transistor DT, the second transistor T2 and the third transistor T3 turned on during the fifth interval ⑤. In addition, in the fifth interval ⑤, the gate-source voltage Vgs of the driving transistor DT may be referred to as the data voltage Vdata, and the threshold voltage Vth of the driving transistor DT may be compensated, so that the level of the driving current may be adjusted based on the level of the data voltage Vdata of the driving transistor DT, and the light emitting device ED may emit light using the driving current, thereby increasing the brightness.

[0126] Therefore, in the display device according to the embodiment of the present disclosure, TFTs having characteristics suitable for the performance required by transistors constituting pixel circuits can be arranged, so that pixels arranged in vertically adjacent horizontal rows can share the first light emission control signal and the second light emission control signal. Therefore, low-frequency driving for low-power driving can be performed, and the construction of the gate driving circuit and the gate line can be minimized, thereby achieving a narrow frame and improving power consumption.

[0127] A pixel and a display device including the pixel according to an embodiment of the present disclosure may be described as follows.

[0128] According to an embodiment of the present disclosure, a pixel may include: a light-emitting device; and a pixel circuit, the pixel circuit is connected to a first gate control line, a second gate control line, a third gate control line and the light-emitting device, the pixel circuit includes a first node, a second node, a third node and a fourth node, wherein the pixel circuit includes: a driving transistor, the driving transistor is connected to the first node to the third node; a first transistor, the first transistor is connected to the first gate control line and the first node and the second node; a second transistor, the second transistor is connected to the second gate control line, the second node and a first driving voltage line; a third transistor, the third transistor is connected to the first gate control line, the third node and the fourth node; a fourth transistor, the fourth transistor is connected to the first gate control line, the fourth node and an initialization voltage line; a fifth transistor, the fifth transistor is connected to the third gate control line, the third node and a data line; and a storage capacitor, the storage capacitor is arranged between the first node and the fourth node.

[0129] In the pixel according to the embodiment of the present disclosure, some of the driving transistor and the first to fifth transistors may have a first conductivity type, and the other transistors may have a second conductivity type different from the first conductivity type.

[0130] In the pixel according to the embodiment of the present disclosure, the driving transistor and the first and fourth transistors may have the first conductivity type, and the second, third and fifth transistors may have the second conductivity type.

[0131] In the pixel according to the embodiment of the present disclosure, some of the driving transistor and the first to fifth transistors may include an oxide semiconductor layer including oxide, and the other transistors may include a silicon semiconductor layer including crystalline silicon.

[0132] In the pixel according to the embodiment of the present disclosure, the driving transistor may include an oxide semiconductor layer having the first conductivity type.

[0133] In the pixel according to the embodiment of the present disclosure, the first transistor and the fourth transistor may include an oxide semiconductor layer having the first conductivity type.

[0134] In the pixel according to the embodiment of the present disclosure, the second transistor, the third transistor, and the fifth transistor may include a silicon semiconductor layer having the second conductivity type.

[0135] In a pixel according to an embodiment of the present disclosure, the pixel circuit can be driven in a first interval, a second interval, a third interval, a fourth interval and a fifth interval, the signal of the first gate control line can have a first voltage level in the first interval to the third interval and can have a second voltage level different from the first voltage level in the fourth interval and the fifth interval, the signal of the second gate control line can have the first voltage level in the second interval to the fourth interval and can have the second voltage level in the first interval and the fifth interval, and the signal of the third gate control line can have the first voltage level in the first interval and the third interval to the fifth interval, and can have the second voltage level in the second interval.

[0136] In a pixel according to an embodiment of the present disclosure, the first transistor may be turned on only in the first interval to the third interval among the first interval to the fifth interval, the second transistor may be turned on only in the first interval and the fifth interval among the first interval to the fifth interval, the third transistor may be turned on only in the fourth interval and the fifth interval among the first interval to the fifth interval, the fourth transistor may be turned on only in the first interval to the third interval among the first interval to the fifth interval, and the fifth transistor may be turned on only in the second interval among the first interval to the fifth interval.

[0137] In the pixel according to the embodiment of the present disclosure, the first conductivity type is an N type, and the second conductivity type is a P type.

[0138] A display device according to an embodiment of the present disclosure may include: a display panel, the display panel including a display area and a non-display area arranged near the display area, wherein a plurality of pixels are arranged in a first direction and a second direction intersecting the first direction in the display area; and a gate driver, the gate driver being arranged in the non-display area to provide a scanning signal, a first light-emitting control signal, and a second light-emitting control signal to each of the plurality of pixels, wherein two pixels adjacent to each other in the second direction among the plurality of pixels share one or more of the first light-emitting control signal and the second light-emitting control signal.

[0139] In a display device according to an embodiment of the present disclosure, each of the multiple pixels may include a pixel circuit, which includes a light-emitting device, a driving transistor, a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor and a storage capacitor, and the driving transistor and some of the first to fifth transistors may have a first conductivity type, and other transistors may have a second conductivity type different from the first conductivity type.

[0140] In the display device according to the embodiment of the present disclosure, some of the driving transistor and the first to fifth transistors may include an oxide semiconductor layer including oxide, and the other transistors may include a silicon semiconductor layer including crystalline silicon.

[0141] In a display device according to an embodiment of the present disclosure, the driving transistor and the driving transistor among the first to fifth transistors may include an oxide semiconductor layer having the first conductivity type, the first transistor and the fourth transistor may include an oxide semiconductor layer or a silicon semiconductor layer having the first conductivity type, and the second transistor, the third transistor and the fifth transistor may include a silicon semiconductor layer having the second conductivity type.

[0142] In a display device according to an embodiment of the present disclosure, the gate driver may provide a first light-emitting control signal, a second light-emitting control signal, and a scanning signal having a first voltage level and a second voltage level different from the first voltage level to each of the plurality of pixels, may provide a shared first light-emitting control signal and a second light-emitting control signal to two pixels adjacent to each other in the second direction, and may provide different scanning signals to the two pixels.

[0143] In the display device according to an embodiment of the present disclosure, the first light emitting control signal and the second light emitting control signal may partially overlap in the interval having the first voltage level, and the scanning signals provided to the two pixels may not overlap in the interval having the second voltage level.

[0144] In a display device according to an embodiment of the present disclosure, the pixel circuit of each of the multiple pixels can be driven in the first interval, the second interval, the third interval, the fourth interval and the fifth interval, and the pixel circuit of each of the two pixels can be driven identically in the first interval, the fourth interval and the fifth interval among the first interval to the fifth interval, and can be driven differently in the second interval and the third interval.

[0145] In a display device according to an embodiment of the present disclosure, the second interval and the third interval of each of the two pixels may overlap with an interval in which the first light emitting control signal and the second light emitting control signal have the first voltage level, the second interval of each of the two pixels may be an interval in which each scanning signal has the second voltage level in the interval in which the first light emitting control signal and the second light emitting control signal have the first voltage level, and the third interval of each of the two pixels may be an interval in which the first light emitting control signal and the second light emitting control signal have the first voltage level except the second interval.

[0146] In the display device according to the embodiment of the present disclosure, the first conductivity type is an N type, and the second conductivity type is a P type.

[0147] A display device according to an embodiment of the present disclosure may include: a display panel, the display panel including a display area and a first non-display area and a second non-display area parallel to each other with the display area therebetween, wherein an nth pixel and an n+1th pixel vertically adjacent to each other are arranged in the display area, where n is an odd number of 1 or more; a first gate driver, the first gate driver providing a first light-emitting control signal to the nth pixel and the n+1th pixel in the first non-display area; and a second gate driver, the second gate driver providing a second light-emitting control signal to the nth pixel and the n+1th pixel in the second non-display area, wherein each of the nth pixel and the n+1th pixel emits light based on the first light-emitting control signal and the second light-emitting control signal.

[0148] In a display device according to an embodiment of the present disclosure, the first gate driver may include a first light-emitting control driving circuit and an nth scanning driving circuit, the first light-emitting control driving circuit providing the first light-emitting control signal shared by the nth pixel and the n+1th pixel, and the nth scanning driving circuit providing the nth scanning signal to the nth pixel, and the second gate driver may include a second light-emitting control driving circuit and an n+1th scanning driving circuit, the second light-emitting control driving circuit providing the second light-emitting control signal shared by the nth pixel and the n+1th pixel, and the n+1th scanning driving circuit providing the n+1th scanning signal to the n+1th pixel.

[0149] In a display device according to an embodiment of the present disclosure, the first light-emitting control signal, the second light-emitting control signal, the nth scan signal and the n+1th scan signal may have a first voltage level and a second voltage level different from the first voltage level, the first light-emitting control signal and the second light-emitting control signal may partially overlap in an interval having the first voltage level, and in an interval in which the first light-emitting control signal and the second light-emitting control signal overlap in the first voltage level, the nth scan signal and the n+1th scan signal may have the second voltage level that does not overlap.

[0150] In a pixel and a display device including the pixel according to the present disclosure, the number of gate control signals required for a pixel driving circuit can be reduced by sharing gate control signals in adjacent horizontal lines, and thus a narrow frame can be achieved and power consumption can be reduced.

[0151] It will be apparent to those skilled in the art that the above disclosure is not limited to the above embodiments and drawings, and that various substitutions, modifications and variations may be made in the disclosure without departing from the spirit and scope of the disclosure. Therefore, the scope of the disclosure is defined by the appended claims, and all changes or modifications derived from the meaning, scope and equivalent concepts of the claims are intended to fall within the scope of the disclosure.

Claims

1. A pixel comprising: Light emitting device; and a pixel circuit connected to the first gate control line, the second gate control line, the third gate control line and the light emitting device, the pixel circuit comprising a first node, a second node, a third node and a fourth node, The pixel circuit comprises: a driving transistor connected to the first node to the third node; a first transistor connected to the first gate control line and the first node and the second node; a second transistor connected to the second gate control line, the second node and a first driving voltage line; a third transistor connected to the first gate control line, the third node and the fourth node; a fourth transistor connected to the first gate control line, the fourth node and an initialization voltage line; a fifth transistor connected to the third gate control line, the third node, and a data line; and a storage capacitor disposed between the first node and the fourth node, wherein the pixel circuit is driven in a first interval, a second interval, a third interval, a fourth interval and a fifth interval, The signal of the first gate control line has a first voltage level in the first to third intervals and has a second voltage level different from the first voltage level in the fourth and fifth intervals, The signal of the second gate control line has the first voltage level in the second interval to the fourth interval and has the second voltage level in the first interval and the fifth interval, and The signal of the third gate control line has the first voltage level in the first interval and the third to fifth intervals, and has the second voltage level in the second interval. 2 . The pixel according to claim 1 , wherein some of the driving transistor and the first to fifth transistors have a first conductivity type, and the other transistors have a second conductivity type different from the first conductivity type.

3. The pixel according to claim 2, wherein the driving transistor and the first and fourth transistors have the first conductivity type, and The second transistor, the third transistor, and the fifth transistor have the second conductivity type. 4 . The pixel according to claim 2 , wherein some of the driving transistor and the first to fifth transistors include an oxide semiconductor layer including oxide, and the other transistors include a silicon semiconductor layer including crystalline silicon. 5 . The pixel according to claim 4 , wherein the driving transistor includes an oxide semiconductor layer having the first conductivity type. 6 . The pixel according to claim 5 , wherein the first transistor and the fourth transistor include an oxide semiconductor layer having the first conductivity type. 7 . The pixel according to claim 4 , wherein the second transistor, the third transistor, and the fifth transistor include a silicon semiconductor layer having the second conductivity type.

8. The pixel according to claim 1, wherein the first transistor is turned on only in the first to third intervals among the first to fifth intervals, The second transistor is turned on only in the first section and the fifth section among the first section to the fifth section, The third transistor is turned on only in the fourth section and the fifth section among the first section to the fifth section, The fourth transistor is turned on only in the first to third sections among the first to fifth sections, and The fifth transistor is turned on only in the second section among the first section to the fifth section. 9 . The pixel according to claim 2 , wherein the first conductivity type is an N type, and the second conductivity type is a P type.

10. A display device, comprising: A display panel, the display panel comprising a display area and a non-display area arranged near the display area, wherein a plurality of pixels are arranged in a first direction and a second direction intersecting the first direction in the display area; as well as a gate driver disposed in the non-display area to provide a scan signal, a first light emission control signal, and a second light emission control signal to each of the plurality of pixels, wherein two pixels adjacent to each other in the second direction among the plurality of pixels share one or more of the first light emission control signal and the second light emission control signal, and Each of the plurality of pixels is a pixel according to any one of claims 1 to 9.

11. The display device according to claim 10, wherein the gate driver providing a first light emitting control signal, a second light emitting control signal, and a scanning signal having a first voltage level and a second voltage level different from the first voltage level to each of the plurality of pixels, providing the first light emission control signal and the second light emission control signal shared by two pixels adjacent to each other in the second direction, and Different scanning signals are provided to the two pixels.

12. The display device according to claim 11, wherein the first light emission control signal and the second light emission control signal partially overlap in a section having the first voltage level, and The scanning signals supplied to the two pixels do not overlap in a section having the second voltage level.

13. The display device according to claim 12, wherein the pixel circuit of each of the two pixels is driven identically in the first interval, the fourth interval, and the fifth interval among the first interval to the fifth interval, and is driven differently in the second interval and the third interval.

14. The display device according to claim 13, wherein the second interval and the third interval of each of the two pixels overlap with an interval in which the first light emission control signal and the second light emission control signal have the first voltage level, The second interval of each of the two pixels is an interval in which each scanning signal has the second voltage level in an interval in which the first light emission control signal and the second light emission control signal have the first voltage level, and The third interval of each of the two pixels is an interval other than the second interval among intervals in which the first light emission control signal and the second light emission control signal have the first voltage level.

15. A display device comprising: A display panel comprising a display area and a first non-display area and a second non-display area parallel to each other with the display area therebetween, wherein an nth pixel and an n+1th pixel vertically adjacent to each other are arranged in the display area, where n is an odd number of 1 or more; a first gate driver providing a first light emitting control signal to the nth pixel and the (n+1)th pixel in the first non-display area; as well as a second gate driver, the second gate driver providing a second light emitting control signal to the nth pixel and the (n+1)th pixel in the second non-display area; wherein each of the nth pixel and the n+1th pixel emits light based on the first light emission control signal and the second light emission control signal, and Each of the nth pixel and the (n+1)th pixel is a pixel according to any one of claims 1 to 9.

16. The display device according to claim 15, wherein the first gate driver comprises a first light emission control driving circuit and an nth scanning driving circuit, the first light emission control driving circuit provides the first light emission control signal shared by the nth pixel and the n+1th pixel, the nth scanning driving circuit provides the nth scanning signal to the nth pixel, and The second gate driver includes a second light-emitting control driving circuit and an n+1th scanning driving circuit, the second light-emitting control driving circuit provides the second light-emitting control signal shared by the nth pixel and the n+1th pixel, and the n+1th scanning driving circuit provides the n+1th scanning signal to the n+1th pixel.

17. The display device according to claim 16, wherein the first light emission control signal, the second light emission control signal, the nth scan signal, and the (n+1)th scan signal have a first voltage level and a second voltage level different from the first voltage level, The first light emission control signal and the second light emission control signal partially overlap in a section having the first voltage level, and In a section in which the first light emitting control signal and the second light emitting control signal overlap in the first voltage level, the nth scan signal and the (n+1)th scan signal have the second voltage level which does not overlap.

Images