Correction coefficient storage circuit and system

Abstract

The present invention discloses a correction coefficient storage circuit and system. The correction coefficient storage circuit is arranged in an LED light board, and includes: an address setting module, a memory, and a cascade module. The input end of the address setting module is connected to an address setting signal; the address setting module is used to set an address code according to the address setting signal; the address end of the memory is electrically connected to the output end of the address setting module, and the data end of the memory is connected to a data signal; the memory is used to store the correction coefficient information corresponding to the address information in the data signal when the address information of the LED light board in the data signal matches the address code; the input end of the cascade module is connected to the address setting signal, and the output end serves as the output end of the correction coefficient storage circuit; the output signal of the cascade module serves as the address setting signal of the correction coefficient storage circuit of the next level. The embodiments of the present invention can improve the flexibility of the correction coefficient storage system in the LED display screen and reduce its cost.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to a correction coefficient storage circuit and system. Background Art

[0002] Existing LED (Light Emitting Diode) display screens are usually composed of multiple LED boxes, each of which includes multiple LED light panels. Due to the inherent semiconductor properties of LEDs (especially full-color LEDs), different LED pixels have different luminous and attenuation characteristics, and the chromaticity and brightness are both discrete, which will cause uneven display of the LED light panel. Therefore, it is necessary to introduce brightness and chromaticity correction, and load a correction coefficient to each pixel to achieve uniform display of the LED display screen.

[0003] The correction coefficient storage system on a conventional LED display screen usually sets up a separate memory independent of each LED light board to store all correction coefficients. However, in this method, the correction coefficients pre-written into the memory must correspond one-to-one to the positions of each cascaded LED light board. Once an LED light board is added or replaced, all data in the memory must be erased and rewritten, and the system flexibility is poor. Alternatively, a memory is set in each LED light board to store the correction coefficient corresponding to the LED light board; however, each LED light board needs to be connected one-to-one with the input and output interface of the control system, which has poor applicability and high cost. Therefore, the correction coefficient storage system in the existing LED display screen has the problems of poor flexibility and high cost. Summary of the invention

[0004] The embodiments of the present invention provide a correction coefficient storage circuit and system to improve the flexibility of the correction coefficient storage system in an LED display screen and reduce its cost.

[0005] An embodiment of the present invention provides a correction coefficient storage circuit, which is arranged in an LED light board and includes:

[0006] An address setting module comprises an input terminal and an output terminal; the input terminal of the address setting module serves as an input terminal of the correction coefficient storage circuit and is connected to an address setting signal; the address setting module is used to set an address code according to the address setting signal;

[0007] A memory, comprising an address terminal and a data terminal; the address terminal of the memory is electrically connected to the output terminal of the address setting module; the data terminal of the memory serves as the data terminal of the correction coefficient storage circuit, and is connected to the data signal; the memory is used to store the correction coefficient information corresponding to the address information in the data signal when the address information of the LED light board in the data signal matches the address code;

[0008] The cascade module comprises an input end and an output end; the input end of the cascade module is connected to the address setting signal; the output end of the cascade module serves as the output end of the correction coefficient storage circuit; the output signal of the cascade module serves as the address setting signal of the next-level correction coefficient storage circuit.

[0009] Optionally, the cascade module includes: a first voltage-stabilizing diode; a first electrode of the first voltage-stabilizing diode is connected to the address setting signal; and a second electrode of the first voltage-stabilizing diode serves as an output end of the cascade module.

[0010] Optionally, the address end of the memory includes: at least two address interfaces;

[0011] The address setting module includes: at least two address setting units, and the number of the address setting units is less than or equal to the number of the address interfaces;

[0012] The address setting unit comprises an input end and an output end; the input end of the address setting unit constitutes the input end of the address setting module, and the output ends of different address setting units are electrically connected to different address interfaces.

[0013] Optionally, the address end of the memory includes three address interfaces, namely: a first address interface, a second address interface and a third address interface; the address setting module includes two address setting units, namely: a first address setting unit and a second address setting unit;

[0014] The output end of the first address setting unit is electrically connected to the first address interface; the output end of the second address setting unit is electrically connected to the second address interface; and the third address interface is grounded.

[0015] Optionally, the first address setting unit includes: a second voltage stabilizing diode, a first resistor, a second resistor, a third resistor and a first transistor;

[0016] The first electrode of the second voltage-stabilizing diode is connected to the address setting signal, and the second electrode of the second voltage-stabilizing diode is electrically connected to the first end of the first resistor and the first end of the second resistor respectively; the second end of the first resistor is grounded; the second end of the second resistor is electrically connected to the control electrode of the first transistor; the first electrode of the first transistor is grounded; the second electrode of the first transistor is electrically connected to the second end of the third resistor and serves as the output end of the first address setting unit; the first end of the third resistor is connected to the power supply signal;

[0017] The second address setting unit includes: a fourth resistor, a fifth resistor and a second transistor;

[0018] The first end of the fourth resistor is connected to the address setting signal, and the second end of the fourth resistor is electrically connected to the control electrode of the second transistor; the first electrode of the second transistor is grounded; the second electrode of the second transistor is electrically connected to the second end of the fifth resistor and serves as the output end of the second address setting unit; the first end of the fifth resistor is connected to the power supply signal.

[0019] Optionally, the memory is an electrically erasable programmable read-only memory.

[0020] An embodiment of the present invention further provides a correction coefficient storage system, comprising: a control module and a correction coefficient storage circuit as provided in any embodiment of the present invention;

[0021] The control module includes an output terminal and a data terminal; the control module is used to perform brightness and chromaticity correction on the LED light board, and output the address setting signal through the output terminal, and output the data signal through the data terminal;

[0022] The input end of the correction coefficient storage circuit of the first stage is electrically connected to the output end of the control module; the data end of the correction coefficient storage circuit is electrically connected to the data end of the control module through a data bus.

[0023] Optionally, the control module is further used to verify the correspondence between the correction coefficient information in the memory and the LED light board where the memory is located.

[0024] Optionally, the control module is also used to: when the correction coefficient information in the memory does not correspond to the LED light board where the memory is located, control the LED light board to go black, and re-transmit the address setting signal and the data signal to the correction coefficient storage circuit in the LED light board.

[0025] Optionally, the correction coefficient storage system further includes: a switching board connected between the control module and the first-stage correction coefficient storage circuit.

[0026] In the correction coefficient storage circuit provided in the embodiment of the present invention, an address setting module, a memory and a cascade module are provided. The cascade module can realize the cascade of the correction coefficient storage circuits in different LED light boards, thereby effectively saving the number of connection ports required by the control module to reduce the cost. The address setting module can set the address code for each LED light board in the cascade structure; in a cascade structure, different LED light boards correspond to different address codes to ensure that the memory can correctly store the correction coefficient information of the LED light board where it is located. In addition, since the address setting module can indicate the position of the LED light board, if the correction information is wrong, or there is a situation of adding or reducing the LED light board, the control module can adjust the correction coefficient information stored in its internal memory according to the position of the LED light board. Therefore, the correction coefficient storage circuit enables the LED display screen to be assembled and used without the need for each LED light board to be arranged according to the position and order when the correction coefficient is stored, which effectively improves the flexibility of the system. Therefore, compared with the prior art, the embodiment of the present invention can improve the flexibility of the correction coefficient storage system in the LED display screen and reduce its cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a structural schematic diagram of a correction coefficient storage system in the prior art;

[0028] Figure 2 is a structural schematic diagram of a correction coefficient storage circuit provided by an embodiment of the present invention;

[0029] Figure 3 is a schematic structural diagram of another correction coefficient storage circuit provided by an embodiment of the present invention;

[0030] Figure 4 It is a structural schematic diagram of a correction coefficient storage system provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0031] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0032] Figure 1 It is a structural diagram of a correction coefficient storage system in the prior art. Figure 1As described in the background technology, the chromaticity and brightness of each LED pixel in the full-color LED display are discrete, which will cause the LED light board 300 to display unevenly. Therefore, the current LED light board 300 production needs to be calibrated in the factory, that is, the brightness and chromaticity information of all pixels is obtained through camera sampling, and the correction unit in the control module 100 loads a correction coefficient to each pixel to make the display brightness and chromaticity consistent. Figure 1 As shown, taking each LED lamp board 300 including a memory, usually a Flash memory 301 as an example, the existing correction coefficient storage system is described.

[0033] Since the correction coefficients of each pixel in each LED light board 300 are different, the correction data of all pixels in the LED light board 300 need to be stored in the Flash memory 301 on the LED light board 300. The control module 100 is connected to the LED light board 300 through the input / output interface 200. Among them, the Flash memory 301 requires 4 interfaces to transmit signals, and the signals to be transmitted are: data input signal MOSI, clock signal CLK, chip select signal CS and data output signal MISO. Due to too many signal lines, it is necessary to increase the interface pins, resulting in the LED light board 300 cannot use a light board of general specifications, and the cost of raw materials increases. In addition, the cascade between LED light boards 300 and LED light boards 300 cannot be realized in this correction system, and a single set of data cannot be continuously transmitted to multiple LED light boards 300; resulting in the control module 100 requiring multiple input / output interfaces 200 to connect different LED light boards 300, which increases the material cost.

[0034] In summary, the existing correction coefficient storage system has the problems of complex wiring, poor flexibility and high cost.

[0035] Based on the above research, an embodiment of the present invention provides a correction coefficient storage circuit. The correction coefficient storage circuit is arranged in each LED light board in a one-to-one correspondence. Figure 2 is a schematic diagram of the structure of a correction coefficient storage circuit provided by an embodiment of the present invention. Figure 2 The correction coefficient storage circuit 10 includes: an address setting module 110 , a memory 120 and a cascade module 130 .

[0036] Among them, the address setting module 110 includes an input end and an output end; the input end of the address setting module 110 is used as the input end of the correction coefficient storage circuit 10, and is connected to the address setting signal ADD_IN; the address setting module 110 is used to set the address code according to the address setting signal ADD_IN. The memory 120 includes an address end and a data end; the address end of the memory 120 is electrically connected to the output end of the address setting module 110; the data end of the memory 120 is used as the data end of the correction coefficient storage circuit 10, and is connected to the data signal DATA; the memory 120 is used to store the correction coefficient information corresponding to the address information in the data signal DATA when the address information of the LED light board in the data signal DATA matches the address code. The cascade module 130 includes an input end and an output end; the input end of the cascade module 130 is connected to the address setting signal ADD_IN; the output end of the cascade module 130 is used as the output end of the correction coefficient storage circuit 10; the output signal ADD_OUT of the cascade module 130 is used as the address setting signal of the correction coefficient storage circuit 10 of the next stage.

[0037] Exemplarily, the address setting module 110 sets the address code in the form of binary code; when the LED light board is placed at different positions of the display screen, or when the LED light board is at different levels of the cascade structure, the address setting module 110 generates different address codes according to the address setting signal it receives. That is to say, the address code essentially indicates the position of the LED light board in the cascade structure, and does not refer to a specific light board. In the actual brightness and chromaticity correction process, since the position of each LED light board is determined and remains unchanged. Therefore, in the brightness and chromaticity correction process, each address code refers to a uniquely determined LED light board, and the address information in the data signal DATA keeps a one-to-one correspondence with each LED light board in the cascade structure, and there will be no storage error caused by information mismatch. After the storage in the memory 120 is completed, when the LED light board is used to assemble the LED light box, the position of the LED light board in the cascade structure does not need to be arranged in the order of correction. After the assembly is completed, each address code still refers to a uniquely determined LED light board, and the control module can adjust the correction coefficient information stored in the memory 120 in the LED light board according to the address code. However, during the brightness and chromaticity calibration process and the assembly process, the same address code can correspond to different LED light boards.

[0038] For example, the cascade structure includes two LED light boards, which are denoted as light board 1 and light board 2; the address setting module 110 sets the address code in the form of two-bit binary code. In the brightness and chromaticity correction process, the first-level LED light board is light board 1, and the second-level LED light board is light board 2; the address code 00 represents light board 1, and the address code 01 represents light board 2; then, in the data signal DATA, the address information corresponding to the address code 00 is followed by the correction coefficient information of light board 1, and the address information corresponding to the address code 01 is followed by the correction coefficient information of light board 2. In the assembly process, the first-level LED light board can be light board 2, and the second-level LED light board can be light board 1; then, the address code 00 represents light board 2, and the address code 01 represents light board 1; accordingly, in the data signal DATA, the address information corresponding to the address code 00 is followed by the correction coefficient information of light board 2, and the address information corresponding to the address code 01 is followed by the correction coefficient information of light board 1, so as to ensure the correspondence between the correction coefficient information and the LED light board.

[0039] The cascade module 130 converts the address setting signal ADD_IN to form an output signal ADD_OUT, and transmits it to the next stage correction coefficient storage circuit 10. Exemplarily, the cascade module 130 can change the size of the address setting signal ADD_IN through a voltage regulator diode or a voltage regulator chip. By cascading multiple LED light panels through the cascade module 130, the number of connection lines between the entire LED light panel and the external circuit, such as the control module, can be reduced.

[0040] In the correction coefficient storage circuit provided in the embodiment of the present invention, an address setting module 110, a memory 120 and a cascade module 130 are provided. The cascade module 130 can realize the cascade of the correction coefficient storage circuits 10 in different LED light boards, thereby effectively saving the number of connection ports required by the control module to reduce costs. The address setting module 110 can set an address code for each LED light board in the cascade structure; in a cascade structure, different LED light boards correspond to different address codes to ensure that the memory 120 can correctly store the correction coefficient information of the LED light board where it is located. In addition, since the address setting module 110 can indicate the position of the LED light board, if the correction information is wrong, or there is a situation of adding or reducing the LED light board, the control module can adjust the correction coefficient information stored in the memory 120 according to the position of the LED light board. Therefore, the correction coefficient storage circuit 10 enables the LED display screen to be assembled and used, and each LED light board does not need to be arranged according to the position and order when the correction coefficient is stored, which effectively improves the flexibility of the system. Therefore, the embodiment of the present invention can improve the flexibility of the correction coefficient storage system in the LED display screen and reduce its cost.

[0041] On the basis of the above-mentioned embodiments, the memory 120 is optionally an electrically erasable programmable read-only memory (EEPROM). This embodiment uses IIC (Inter-Integrated Circuit) signals for data transmission; the electrically erasable programmable read-only memory is connected to the clock bus and the data bus when in use, and both the clock signal and the data signal can be transmitted bidirectionally. Using a single set of IIC signals (including the address setting signal ADD_IN, the data signal DATA and the clock signal) can realize the access of the correction coefficient information of multiple LED light boards. The electrically erasable programmable read-only memory only requires two interfaces. Even if the interface of the cascade module 130 to access the address setting signal ADD_IN is added, the correction coefficient storage circuit 10 provided in this embodiment only requires three external interfaces. Compared with the Flash memory in the prior art, this embodiment requires one less input and output signal, which can reduce the number of external interfaces of the correction coefficient storage circuit 10 and reduce the cost of using electronic materials; and enable the entire system to use industry-standard materials, further reducing costs; it can also reduce the wiring space occupied by setting the memory 120 on the LED lamp board.

[0042] On the basis of the above embodiments, optionally, the address end of the memory 120 includes: at least two address interfaces. The address setting module 110 includes: at least two address setting units, and the number of address setting units is less than or equal to the number of address interfaces. Among them, the address setting unit includes an input end and an output end; the input end of the address setting unit constitutes the input end of the address setting module 110, and the output ends of different address setting units are electrically connected to different address interfaces. Exemplarily, the data received by each address interface represents a bit of address data in the address code.

[0043] Figure 3 Schematic diagram of another correction coefficient storage circuit provided by an embodiment of the present invention. Figure 3 As an example, the structure of the correction coefficient storage circuit 10 is specifically described, but it is not intended to limit the present invention.

[0044] See also Figure 3In one embodiment, optionally, the memory 120 is composed of an EEPROM memory U1. The EEPROM memory U1 includes a power interface VCC, which is connected to a power signal VDD; a write protection interface WP, which is connected to a power signal VDD; a clock interface SCL, which is connected to a clock signal CK and is connected to the power terminal through a pull-up resistor R6; a data interface SDA, which is connected to a data signal DATA and is connected to the power terminal through a pull-up resistor R7; a ground interface GND is directly grounded; and an address terminal, including three address interfaces, namely: a first address interface A0, a second address interface A1, and a third address interface A2.

[0045] The address setting module 110 includes two address setting units, namely: a first address setting unit 111 and a second address setting unit 112. The output end of the first address setting unit 111 is electrically connected to the first address interface A0, and is used to set the first bit of address data in the address code according to the address setting signal ADD_IN; the output end of the second address setting unit 112 is electrically connected to the second address interface A1, and is used to set the second bit of address data in the address code according to the address setting signal ADD_IN; the third address interface A2 is grounded, which is equivalent to setting the third bit of address data in the address code to 0. Exemplarily, using binary coding, up to four address codes can be set through two address setting units, that is, the setting capacity of the two address setting units allows up to four LED light panels to be cascaded, and the actual number of cascades can be selected according to actual needs and the specific structure of the address setting unit.

[0046] Continue to see Figure 3 In a specific implementation, optionally, the first address setting unit 111 includes: a second voltage-stabilizing diode D2, a first resistor R1, a second resistor R2, a third resistor R3 and a first transistor Q1. The first electrode of the second voltage-stabilizing diode D2 is connected to the address setting signal ADD_IN, and the second electrode of the second voltage-stabilizing diode D2 is electrically connected to the first end of the first resistor R1 and the first end of the second resistor R2 respectively; the second end of the first resistor R1 is grounded; the second end of the second resistor R2 is electrically connected to the control electrode of the first transistor Q1; the first electrode of the first transistor Q1 is grounded; the second electrode of the first transistor Q1 is electrically connected to the second end of the third resistor R3 and serves as the output end of the first address setting unit 111; the first end of the third resistor R3 is connected to the power supply signal VDD.

[0047] The second address setting unit 112 includes: a fourth resistor R4, a fifth resistor R5 and a second transistor Q2. The first end of the fourth resistor R4 is connected to the address setting signal ADD_IN, and the second end of the fourth resistor R4 is electrically connected to the control electrode of the second transistor Q2; the first electrode of the second transistor Q2 is grounded; the second electrode of the second transistor Q2 is electrically connected to the second end of the fifth resistor R5 and serves as the output end of the second address setting unit 112; the first end of the fifth resistor R5 is connected to the power supply signal VDD.

[0048] The second resistor R2 and the fourth resistor R4 are used as control electrode resistors and can be set to 10 kΩ; the first resistor R1 can be set to 1 kΩ.

[0049] According to the voltage of the address setting signal ADD_IN, the address setting module 110 can generate three different address codes. For example, taking the first transistor Q1 and the second transistor Q2 as NPN transistors, V1 represents the sum of the conduction threshold voltages of the second voltage stabilizing diode D2 and the first transistor Q1, and V2 represents the conduction threshold voltage of the second transistor Q2 (for example, 0.7V), the working process of the address setting module 110 includes:

[0050] When the level of the address setting signal ADD_IN is greater than V1, the voltage transmitted to the control electrode of the first transistor Q1 is greater than the conduction threshold voltage of the first transistor Q1, the first transistor Q1 is controlled to be turned on, and the ground signal is output through the first transistor Q1. The voltage transmitted to the control electrode of the second transistor Q2 is greater than the conduction threshold voltage of the second transistor Q2, the second transistor Q2 is controlled to be turned on, and the ground signal is output through the second transistor Q2. That is, the first address setting unit 111 outputs a low level, the second address setting unit 112 outputs a low level, and the address code (A2A1A0) is set to 000.

[0051] When the level of the address setting signal ADD_IN is greater than V2 and less than V1, the voltage transmitted to the control electrode of the first transistor Q1 is less than the conduction threshold voltage of the first transistor Q1, the first transistor Q1 is controlled to be turned off, and the power supply signal VDD is output after passing through the third resistor R3. The voltage transmitted to the control electrode of the second transistor Q2 is greater than the conduction threshold voltage of the second transistor Q2, the second transistor Q2 is controlled to be turned on, and the ground signal is output through the second transistor Q2. That is, the first address setting unit 111 outputs a high level, the second address setting unit 112 outputs a low level, and the address code (A2A1A0) is set to 001.

[0052] When the level of the address setting signal ADD_IN is less than V2, the voltage transmitted to the control electrode of the first transistor Q1 is less than the conduction threshold voltage of the first transistor Q1, the first transistor Q1 is controlled to be cut off, and the power signal VDD is output after passing through the third resistor R3. The voltage transmitted to the control electrode of the second transistor Q2 is less than the conduction threshold voltage of the second transistor Q2, the second transistor Q2 is controlled to be cut off, and the power signal VDD is output after passing through the fifth resistor R5. That is, the first address setting unit 111 outputs a high level, the second address setting unit 112 outputs a high level, and the address code (A2A1A0) is set to 011.

[0053] In this embodiment, the address setting signal ADD_IN is transmitted to the base (control electrode) of the transistor. The level on the base of the transistor is used to control the switch state between the emitter and the collector of the transistor to achieve the NOT gate effect of the digital circuit. And through the setting of the second voltage stabilizing diode D2, the voltage transmitted to the control electrode of the first transistor Q1 can be controlled to be different from the voltage transmitted to the control electrode of the second transistor Q2, so that the first address setting unit 111 and the second address setting unit 112 can output different level values ​​to increase the number of cascaded LED light boards.

[0054] Continue to see Figure 3 In one embodiment, optionally, the cascade module 130 includes: a first zener diode D1. The first pole of the first zener diode D1 is connected to the address setting signal ADD_IN; the second pole serves as the output end of the cascade module 130. By setting the first zener diode D1, the address setting signal in the cascade structure can be gradually reduced. By reasonably setting the voltage of the first address setting signal ADD_IN and the first zener diode D1, different levels of address setting modules 110 can output different address codes. In summary, the structure of the cascade module 130 is simple and easy to implement.

[0055] An embodiment of the present invention further provides a correction coefficient storage system, including a correction coefficient storage circuit as provided in any embodiment of the present invention, which has corresponding beneficial effects. Figure 4 Schematic diagram of a correction coefficient storage system provided by an embodiment of the present invention. Figure 4 The correction coefficient storage system includes: a control module 20 and a plurality of correction coefficient storage circuits connected in cascade. Figure 4 The cascade structure is exemplarily shown to include a single correction coefficient storage circuit, which is respectively arranged in three LED light boards.

[0056] Among them, the control module 20 includes an output terminal and a data terminal; the first-level correction coefficient storage circuit 10-1 includes a first-level memory 120-1, which is arranged in the first-level LED light board 1-1, and its input terminal is electrically connected to the output terminal of the control module 20; the second-level correction coefficient storage circuit 10-2 includes a second-level memory 120-2, which is arranged in the second-level LED light board 1-2, and its input terminal is electrically connected to the output terminal of the first-level correction coefficient storage circuit 10-1; the third-level correction coefficient storage circuit 10-3 includes a third-level memory 120-3, which is arranged in the third-level LED light board 1-3, and its input terminal is electrically connected to the output terminal of the second-level correction coefficient storage circuit 10-2. The data terminal of the correction coefficient storage circuit is electrically connected to the data terminal of the control module 20 through the data bus W1. Optionally, the control module 20 also includes a clock terminal, and the correction coefficient storage circuit also includes a clock terminal; the clock terminal of the correction coefficient storage circuit is electrically connected to the clock terminal of the control module 20 through the clock bus W2. The control module 20 is used to perform brightness and chromaticity correction on the LED light board, and output an address setting signal ADD_IN1 through an output terminal, and output a data signal DATA through a data terminal.

[0057] Continue to see Figure 4 On the basis of the above-mentioned embodiments, optionally, the correction coefficient storage system further includes: an adapter board 21, which serves as an external interface of the control module 20, and the adapter board 21 is connected between the control module 20 and the first-stage correction coefficient storage circuit 10-1.

[0058] Exemplarily, the working process of the correction coefficient storage system includes:

[0059] The control module 20 performs brightness and chromaticity correction on multiple LED light boards connected in cascade, and outputs an address setting signal ADD_IN1, a clock signal CK and a data signal DATA. The data signal DATA includes address information of all LED light boards and correction coefficient information corresponding to the address information; for example, the data signal DATA includes multiple pieces of data information, the first few bits of each piece of data information represent address information, and the remaining bits represent correction coefficient information. The clock signal CK is used to control whether each memory enters a read state.

[0060] Multiple correction coefficient storage circuits receive the clock signal CK and the data signal DATA, and receive the address setting signal in sequence, and the memory stores the correction coefficient information corresponding to the LED light board in sequence. Specifically, taking the cascade of three LED light boards as an example, the first-stage correction coefficient storage circuit 10-1 receives the address setting signal ADD_IN1; the output signal ADD_OUT1 of the first-stage correction coefficient storage circuit 10-1 is used as the address setting signal ADD_IN2 of the second-stage correction coefficient storage circuit 10-2; the output signal ADD_OUT2 of the second-stage correction coefficient storage circuit 10-1 is used as the address setting signal ADD_IN3 of the third-stage correction coefficient storage circuit 10-3. Exemplarily, in combination Figure 3 and Figure 4 The address setting signals of the LED light boards at each level and the logical values ​​of the address codes formed therefrom are shown in Table 1.

[0061] Table 1

[0062]

[0063] In Table 1, V1 represents the sum of the conduction threshold voltages of the second voltage-stabilizing diode D2 and the first transistor Q1, and V2 represents the conduction threshold voltage of the second transistor Q2 (for example, 0.7V). By properly setting the address setting signal ADD_IN1 and the voltage value of the second voltage-stabilizing diode D2, different LED panels can have different addresses, so that the memory can identify and access the correction coefficient information.

[0064] On the basis of the above-mentioned embodiments, optionally, the control module 20 is also used to: verify the correspondence between the correction coefficient information in the memory and the LED light board where the memory is located. And when the correction coefficient information in the memory does not correspond to the LED light board where the memory is located, the LED light board is controlled to be black, and the address setting signal and the data signal are retransmitted to the correction coefficient storage circuit in the LED light board. Especially when the connection sequence of the LED light board is disrupted during assembly, after the LED display screen is powered on, the control module 20 self-checks the storage status of the correction coefficient information in the LED light board. If the correction coefficient information stored in the memory does not correspond to the LED light board, the control module 20 performs data supplementation processing, which can effectively ensure the uniformity of the display.

[0065] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A correction coefficient storage circuit, characterized in that: Set in the LED light board, including: An address setting module comprises an input terminal and an output terminal; the input terminal of the address setting module serves as an input terminal of the correction coefficient storage circuit and is connected to an address setting signal; the address setting module is used to set an address code according to the address setting signal; A memory, comprising an address terminal and a data terminal; the address terminal of the memory is electrically connected to the output terminal of the address setting module; the data terminal of the memory serves as the data terminal of the correction coefficient storage circuit, and is connected to the data signal; the memory is used to store the correction coefficient information corresponding to the address information in the data signal when the address information of the LED light board in the data signal matches the address code; A cascade module, comprising an input end and an output end; the input end of the cascade module is connected to the address setting signal; the output end of the cascade module serves as the output end of the correction coefficient storage circuit; the output signal of the cascade module serves as the address setting signal of the next-stage correction coefficient storage circuit; The address end of the memory includes three address interfaces, namely: a first address interface, a second address interface and a third address interface; the address setting module includes two address setting units, namely: a first address setting unit and a second address setting unit; The first address setting unit includes: a second voltage stabilizing diode, a first resistor, a second resistor, a third resistor and a first transistor; The first electrode of the second voltage-stabilizing diode is connected to the address setting signal, and the second electrode of the second voltage-stabilizing diode is electrically connected to the first end of the first resistor and the first end of the second resistor respectively; the second end of the first resistor is grounded; the second end of the second resistor is electrically connected to the control electrode of the first transistor; the first electrode of the first transistor is grounded; the second electrode of the first transistor is electrically connected to the second end of the third resistor and serves as the output end of the first address setting unit; the first end of the third resistor is connected to the power supply signal; The second address setting unit includes: a fourth resistor, a fifth resistor and a second transistor; The first end of the fourth resistor is connected to the address setting signal, and the second end of the fourth resistor is electrically connected to the control electrode of the second transistor; the first electrode of the second transistor is grounded; the second electrode of the second transistor is electrically connected to the second end of the fifth resistor and serves as the output end of the second address setting unit; the first end of the fifth resistor is connected to the power supply signal.

2. The correction coefficient storage circuit according to claim 1, characterized in that: The cascade module includes: a first voltage-stabilizing diode; a first pole of the first voltage-stabilizing diode is connected to the address setting signal; and a second pole of the first voltage-stabilizing diode serves as an output end of the cascade module.

3. The correction coefficient storage circuit according to claim 1, characterized in that: The address end of the memory includes: at least two address interfaces; The address setting module includes: at least two address setting units, and the number of the address setting units is less than or equal to the number of the address interfaces; The address setting unit comprises an input end and an output end; the input end of the address setting unit constitutes the input end of the address setting module, and the output ends of different address setting units are electrically connected to different address interfaces.

4. The correction coefficient storage circuit according to claim 3, characterized in that: The output end of the first address setting unit is electrically connected to the first address interface; the output end of the second address setting unit is electrically connected to the second address interface; and the third address interface is grounded.

5. The correction coefficient storage circuit according to claim 1, characterized in that: The memory is an electrically erasable programmable read-only memory.

6. A correction coefficient storage system, characterized in that: include: A control module and a plurality of correction coefficient storage circuits as described in any one of claims 1 to 5 connected in cascade; The control module includes an output terminal and a data terminal; the control module is used to perform brightness and chromaticity correction on the LED light board, and output the address setting signal through the output terminal, and output the data signal through the data terminal; The input end of the correction coefficient storage circuit of the first stage is electrically connected to the output end of the control module; the data end of the correction coefficient storage circuit is electrically connected to the data end of the control module through a data bus.

7. The correction coefficient storage system according to claim 6, characterized in that: The control module is also used to verify the correspondence between the correction coefficient information in the memory and the LED light board where the memory is located.

8. The correction coefficient storage system according to claim 7, characterized in that: The control module is also used to: when the correction coefficient information in the memory does not correspond to the LED light board where the memory is located, control the LED light board to go black, and re-transmit the address setting signal and the data signal to the correction coefficient storage circuit in the LED light board.

9. The correction coefficient storage system according to claim 6, characterized in that: Also includes: A switching board, wherein the switching board is connected between the control module and the first-stage correction coefficient storage circuit.

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