Modular memory architecture with gating subarray operation

Abstract

Various embodiments of the present invention relate to a modular memory architecture with gating subarray operation. A memory circuit includes a memory cell array arranged with first word lines connected to a first subarray of stored less significant bits and second word lines connected to a second subarray of stored more significant bits. A row decoder circuit coupled to the first and second word lines generates word line signals. A word line gating circuit is configured to selectively gating the transmission of word line signals to the second word lines of the second subarray in response to an assertion of a maximum value signal. A data modification circuit performs a mathematical operation on data read from the memory cell array and asserts a maximum value signal if the mathematical operation performed on the less significant bits of the data from the first subarray produces a maximum data value.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Patent Application No. 63 / 231,856, filed August 11, 2021, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention generally relates to a static random access memory (SRAM) circuit, and more specifically, to a modular memory architecture for an SRAM circuit, wherein subarrays of the memory are selected depending on the data content stored in the memory. Background Technology

[0004] right Figure 1 For reference, Figure 1 A block diagram of a static random access memory (SRAM) 10 is shown. The memory 10 includes a memory core 12 formed by a plurality of SRAM cells (C) (e.g., 6T or 8T types well known in the art). The cells C are arranged in an array comprising j rows and k columns. Cells C in each row of the memory core 12 are coupled to a corresponding word line (WL), and cells in each column are coupled to at least one corresponding bit line (BL). In an implementation using a 6T type SRAM circuit, there is a pair of complementary bit lines used for situations related to writing data to and reading data from memory cells in the column. In an implementation using an 8T type SRAM circuit, there is a pair of complementary write bit lines and a single read bit line, the write bit line used for situations related to writing data to memory cells, and the read bit line used for situations related to reading data from memory cells.

[0005] The memory 10 also includes a row decoder circuit 14 configured to receive memory addresses (addresses). The row decoder circuit 14 decodes the received memory address and selectively actuates a word line (WL) corresponding to the decoded memory address in the memory core 12. Details of the circuitry for the row decoder circuit 14 are not provided because such circuitry is well known to those skilled in the art.

[0006] The data input / output (I / O) circuitry system 16 for memory 10 includes I / O circuitry 18 for each column of memory core 12. Each I / O circuit 18 includes a sense amplifier circuit SA and a precharge circuit PCH connected to the bit line BL of the corresponding column. The precharge circuit PCH is used to precharge the bit line BL to a specific voltage level (e.g., Vdd) before a read or write operation. When the sense amplifier circuit SA is actuated during a read operation by an assertion of the sense amplifier enable (SAEN) signal, it drives the amplifier output signal to a power rail (e.g., Vdd or ground) based on the logic state of the data bit in the memory cell C of the row selected by the actuation of the word line WL. The logic state of the data bit output by the sense amplifier circuit SA is latched by a bit latch circuit. In conjunction with a data read operation, the output from each latch circuit is coupled to the data output lines Q(0), ..., Q(k-1) of the corresponding bit for the data output port via a multiplexing circuitry system MUX. In conjunction with the SRAM 12 data write operation, the multiplexing circuit system MUX couples the corresponding data input lines D(0), ..., D(k-1) of the data input port to the bit line BL to write the data into the memory cell C.

[0007] The control (CTRL) circuitry 20 for memory 10 generates a set of control signals 22, which are applied to the I / O circuitry system 16 to control its operation. The control signals 22 include, for example, a precharge control signal for the precharge circuitry PCH, a multiplexer control signal for the multiplexing circuitry system MUX, and a sense amplifier enable (SAEN) signal for the sense amplifier circuitry SA. Details of the circuitry system for control circuitry 20 are not provided because such circuitry is well known to those skilled in the art.

[0008] Further Figure 2 For reference, it shows an SRAM 10 configured to store data. Figure 1 A block diagram of circuit 30. In a particular application, the stored data is histogram data, where each data word location (dw loc) in memory core 12 of memory 10 stores a count value (count). For example, for Figure 1The memory 10 has k memory cells C in each row at a given memory address location forming a bin, which stores a data word corresponding to the count value (count) of the histogram. The bit stored in the memory cell C of column 0 is the least significant bit (LSB) of the count value, while the bit stored in the memory cell C of column (k-1) is the most significant bit (MSB) of the count value. As part of the operation of the circuit 30 used to construct the histogram, the count value is modified in some way (e.g., incremented by one) each time a data word location is accessed. This operation typically involves three steps: step 1) reading the k bits of the current count value from a specific data word location accessed in response to an m-bit memory address (address); step 2) mathematically modifying the current count value (e.g., incrementing by one); and step 3) writing the modified count value back to the SRAM 12 at the accessed data word location. The step 2) operation for mathematically modifying the count value is performed here by a data modification circuit 32 located outside (and separate from) the memory 10. The data modification circuit 32 is coupled to the data output (Q) port and input (D) port of the data memory 10 via one or more n-bit data bus circuits. As an example, the data modification circuit 32 may include an n-bit adder circuit that operates on the current count value read from the memory at the data output (Q) to increment by one and outputs the modified count value to be written back to the memory at the data input (D).

[0009] Now to Figure 3Referring to the diagram shown, a timing diagram of the operation of circuit 30 is illustrated. At time t1, the chip select signal (CSN) is asserted as logic low to select SRAM 10, and the write enable signal (WEN) is deasserted as logic high to put SRAM 10 into data read mode. At time t2, the memory address (address) is applied, and the clock signal CLK pulses for the first time to initiate a read operation. The address is decoded by SRAM 10, and the word line (WL) coupled to the data word location (dwloc) corresponding to the decoded address is asserted as logic high at time t3. The count value (count) is then read (step 1) from the addressed data word location in memory core 12 and output through the data output (Q) port of SRAM 10 at time t4. The chip select signal (CSN) is then deasserted as logic high at time t5 to deselect SRAM 10, so that SRAM 10 does not perform the operation in response to the next pulse of the clock signal CLK. At time t6, the second pulse of the clock signal CLK causes the data modification circuit 32 to perform a mathematical modification operation (step 2) at time t7, which in this example is an increment (+1) operation. Then, at time t8, the modified count value (count + 1) is applied to the data input (D) port of SRAM 10 via the data modification circuit 32. At time t9, the write enable signal (WEN) is asserted as logic low to put SRAM 10 into write mode. Then, at time t10, the chip select signal (CSN) is asserted as logic low to select SRAM 10. At time t11, the memory address (address) is applied (e.g., maintaining the application from the read start) and the third pulse of the clock signal CLK initiates the data write operation. The address is decoded by SRAM 10, and the word line (WL) coupled to the data word location (dw loc) is asserted as logic high at time t12. Then, at time t13, the modified count value (count + 1) is written from the data input port of SRAM 10 (step 3) to the addressable data word location.

[0010] Figure 2 Circuit 30 and its in Figure 3 The operation detailed in the text has several problems. The circuit operation is multi-cycle because it requires three clock cycles and two separate word line assertions to complete. Due to this multi-cycle operation, there is significant high power consumption in circuit 30 (particularly within memory 10) due to data signal switching. The power consumption problem is further amplified by the fact that the mathematical modification part of the operation (step 2) occurs outside SRAM 10, thus requiring data switching at both the data output (Q) port and the data input (D) port.

[0011] Therefore, there is a need in the art to address the power consumption problem and provide a more efficient implementation of read-modify-write operations. Summary of the Invention

[0012] In one embodiment, a circuit includes a memory circuit comprising: a memory core formed by an array of memory cells storing data words in rows, wherein each row is connected to a word line, and wherein the array is arranged to include a first subarray and a second subarray, the first subarray storing the less significant bits of the data words and the second subarray storing the more significant bits of the data words; and a row decoder circuit configured to receive an address, decode the received address, and generate a word line signal applied to a selected word line in the word line for a specific data location based on the decoded address. The circuit also includes a data modification circuit configured to perform a mathematical operation on a data word read from the specific data location in the memory cell array corresponding to the selected word line in the word line to produce a modified data word to be written back to that specific data location in the memory cell array. The row decoder also includes a word line gating circuit configured to selectively gating a passage of the word line signal to a memory cell in the second subarray in response to an assertion of a maximum value signal. The detection circuit is configured to generate a maximum data value for the lower significant bits of the data word in response to a mathematical operation performed on the lower significant bits of the data word from the first subarray, thereby asserting the maximum value signal.

[0013] In one embodiment, a circuit includes a memory circuit comprising: a memory cell array arranged to include a first subarray and a second subarray, the first subarray storing less significant bits of data and the second subarray storing more significant bits of data; a first plurality of word lines for the first subarray; a second plurality of word lines for the first subarray; and a row decoder circuit coupled to the first and second plurality of word lines, wherein the row decoder generates word line signals and includes a word line gating circuit configured to selectively gating the word line signals to channels of the second plurality of word lines for the second subarray in response to an assertion of a maximum value signal. A data modification circuit is configured to perform a mathematical operation on data read from the memory cell array. A detection circuit is configured to assert the maximum value signal in response to a maximum data value generated by a mathematical operation performed on the less significant bits of data from the first subarray.

[0014] One embodiment also relates to a method for operating a memory circuit including an array of memory cells arranged in a modular architecture having a first subarray and a second subarray, the first subarray being configured to store less significant bits of data and the second subarray being configured to store more significant bits of data. The method includes: reading data from the memory circuit; performing a mathematical operation on the data read from the memory circuit to generate modified data; and writing the modified data back to the memory circuit; wherein reading the data and writing the modified data include: asserting a word line signal to select a data location in the memory for reading the data and writing the modified data. The method further includes: preventing the word line signal from being applied to the second subarray; wherein performing the mathematical operation includes performing a mathematical operation on the less significant bits of the data read from the data location; asserting a maximum value signal if the mathematical operation performed on the less significant bits of the read data produces a maximum data value; and thereafter, in response to the asserted maximum value signal, allowing the word line signal to be applied to the second subarray for at least the data location. Attached Figure Description

[0015] To better understand the embodiments, reference will now be made to the accompanying drawings by way of example only, wherein:

[0016] Figure 1 A block diagram of a static random access memory (SRAM) circuit is shown;

[0017] Figure 2 A block diagram is shown of a circuit configured to perform a read-modify-write operation on a count value stored in SRAM using an external modification circuit.

[0018] Figure 3 It shows Figure 2 The operating timing diagram of the circuit;

[0019] Figure 4 , Figure 7 , Figure 10 and Figure 11 Block diagrams of circuits are shown, each configured to perform read-modify-write operations using an SRAM circuit with a modular memory architecture including subarrays that are gated for operation depending on the data content stored in the memory.

[0020] Figure 5 Is Figure 4 A circuit diagram of an example embodiment of the carry detection circuit used in the circuit;

[0021] Figure 6A This is when a data modification operation produces the maximum count value of the lowest (LESS) significant data bits. Figure 4 The operating timing diagram of the circuit;

[0022] Figure 6B yes Figure 4 The timing diagram of the data modification operation of the circuit after the maximum count value of the lower valid data bits has been reached;

[0023] Figure 8 A block diagram for logic circuits is shown;

[0024] Figure 9A This is when a data modification operation produces the maximum count value of the lowest significant data bits. Figure 7 The operating timing diagram of the circuit;

[0025] Figure 9B yes Figure 7 The timing diagram of the data modification operation of the circuit after the maximum count value of the lower valid data bits has been reached;

[0026] Figure 12A This is when a data modification operation produces the maximum count value of the lowest significant data bits. Figure 11 The operating timing diagram of the circuit;

[0027] Figure 12B yes Figure 11 The timing diagram of the data modification operation after the maximum count value of the lower valid data bits has been reached; and

[0028] Figure 13 It was taken advantage of Figure 4 , Figure 7 , Figure 10 or Figure 11 A schematic representation of a device with memory, such as an image sensor. Detailed Implementation

[0029] right Figure 4 Reference is made to the diagram illustrating a block diagram of circuitry 130 including an SRAM 110 configured to store data. The memory 110 includes a memory core 112 formed by a plurality of SRAM cells (C) (e.g., of the 6T or 8T type well known in the art). An overall array for the core 112 is arranged comprising j rows and k columns, and this overall array is divided into a modular architecture, wherein a first subarray 112L comprises j rows and x columns, and a second subarray 112M comprises j rows and kx columns. The column division between the first and second subarrays 112L and 112M need not be equal. Furthermore, the description of the two subarrays is by way of example only, and it should be understood that the invention described herein can be applied to memory cores 112 comprising three or more subarrays.

[0030] In certain applications, the data stored in memory 110 is histogram data, where each data word location in memory core 112 stores a count value (count). For example, for Figure 4 The memory 110 has k memory cells C in each row at a given memory address location forming a bin that stores a data word corresponding to a count value (count) in a histogram. The bits stored in the memory cells of column 0 are the least significant bits (LSB) of the count value, while the bits stored in the memory cells of column (k-1) are the most significant bits (MSB) of the count value. Therefore, it should be understood that a first subarray 112L comprising memory cells C storing bits 0 to x-1 of the count value forms a lower significant subarray of core 112 (where the "L" indicator is used to indicate the portion of memory 110 associated with the lower significant bits of the count value). A second subarray 112M comprising memory cells C storing bits x to k-1 of the count value forms a higher (MORE) significant subarray of core 112 (where the "M" indicator is used to indicate the portion of memory 110 associated with the higher significant bits of the count value).

[0031] In memory core 12, each row of cells C is coupled to a corresponding word line (WL), and each column of cells is coupled to at least one corresponding bit line (BL). In an implementation using a 6T SRAM circuit, a pair of complementary bit lines are used for situations related to writing data to and reading data from a column of memory cells. In an implementation using an 8T SRAM circuit, a pair of complementary write bit lines and a single read bit line are used; the write bit line is used for situations related to writing data to a memory cell, and the read bit line is used for situations related to reading data from a memory cell.

[0032] The memory 110 also includes a row decoder circuit 114 configured to receive memory addresses (addresses). The row decoder circuit 114 decodes the received memory address and selectively actuates a word line (WL) corresponding to the decoded memory address in the memory core 112. Details of the circuitry for the row decoder circuit 114 are not provided because such circuitry is well known to those skilled in the art. The row decoder includes word line (WL) driver circuitry enabled for operation in response to an assertion of a first row decoder control signal (RowDecL).

[0033] Given the modular architecture of core 112 divided into a first subarray 112L and a second subarray 112M, the row decoder circuit 114 also includes a word line signal gating circuit 115, which operates to selectively pass (or gating) word line signals generated by the WL driver circuit to word lines WL connected to memory cells C in the second subarray 112M. The word line signal gating circuit 115 may, for example, include logic circuitry (formed using AND gating) that logically combines the word line signals and the second row decoder control signal (RowDecM). The output of the word line signal gating circuit 115 is coupled to the word lines for the second subarray 112M. When the second row decoder control signal (RowDecM) is de-asserted, the logic circuitry of the word line signal gating circuit 115 prevents the word line signal generated by the WL driver circuit from being applied to the word line of the memory cell C in the second subarray 112M. In this configuration, only the word line signal from the WL driver circuit is applied to the memory cell C in the first subarray 112L by the row decoder 114. Conversely, when the second row decoder control signal (RowDecM) is asserted, the logic circuitry of the word line signal gating circuit 115 passes the word line signal to the word line of the memory cell C in the second subarray 112M. In this configuration, the word line signal is applied to the memory cell C in both the first and second subarrays 112L and 112M by the row decoder 114.

[0034] The data input / output (I / O) circuitry system 116 for memory 10 includes I / O circuitry 118 for each column of memory core 112. The I / O circuitry system 116 is divided according to the modular architecture of memory core 12 into a first I / O circuitry system (I / OL) 116L connected to the bit lines of a first subarray 112L for lower active bits and a second I / O circuitry system (I / OM) 116M connected to the bit lines of a second subarray 112M for higher active bits. Each I / O circuit 118 includes a sense amplifier circuit SA and a precharge circuit PCH connected to the bit line BL of the corresponding column. The precharge circuit PCH is used to precharge the bit line BL to a specific voltage level (e.g., Vdd) before a read or write operation. When the sense amplifier circuit SA is actuated during a read operation by an assertion of the sense amplifier enable (SAEN) signal, it drives the amplifier output signal to a power rail (e.g., Vdd or ground) according to the logic state of the data bits stored in the memory cell C of the row selected by the actuation of word line WL. The logic state of the data bits output by the sense amplifier SA circuit is latched by the bit latch circuit. In conjunction with data read operations, the output from each latch circuit is coupled to the corresponding bit's data output lines Q(0), ..., Q(k-1) of the data output port via a multiplexing circuit system MUX. In conjunction with SRAM 112 data write operations, the multiplexing circuit system MUX couples the corresponding bit's data input lines D(0), ..., D(k-1) of the data input port to the bit line BL to write data into the memory cell C.

[0035] The control (CTRL) circuitry 120 for memory 110 generates a set of control signals 122, which are applied to the I / O circuitry system 116 to control its operation. The control signals 122 include, for example, a precharge control signal for the precharge circuitry PCH, a multiplexer control signal for the multiplexing circuitry system MUX, and a sense amplifier enable signal for the sense amplifier circuitry SA. Details of the circuitry system for control circuitry 120 are not provided because such circuitry is well known to those skilled in the art.

[0036] The core 112 is divided into first and second subarrays 112L and 112M, respectively, and the I / O circuit system 116 is divided into first and second I / O circuit systems 116L and 116M, respectively, in a modular architecture. The control circuit 120 also includes a first clock generator circuit (clock generator.lower) and a second clock generator circuit (clock generator.higher (More)). The first clock generator circuit generates a control signal 122 to be applied to the lower significant bit of the first I / O circuit system (I / OL) 116L, and the second clock generator circuit generates a control signal 122 to be applied to the higher significant bit of the second I / O circuit system (I / OL) 116M. The first clock generator circuit (clock generator.lower) also generates a first row decoder control signal (RowDecL), which enables the operation of the WL driver circuit. The second clock generator circuit (clock generator.higher) receives a strobe control signal (Max) and outputs a second row decoder control signal (RowDecM) to control the operation of the word line signal strobe circuit 115.

[0037] The second clock generator circuit (clock generator, higher) operates to selectively pass (or gating) control signal 122 to the precharge circuit PCH, multiplexing circuit system MUX, and sense amplifier circuit SA of I / O circuit 118 in the second I / O circuit system 112M in response to the gating control signal (Max). Furthermore, the second clock generator circuit (clock generator, higher) asserts the second row decoder control signal (RowDecM) in response to the gating control signal (Max). The second clock generator circuit (clock generator, higher) may, for example, include logic circuitry (formed using logical AND gating) that logically combines the various control signals 122 and the gating control signal (Max). When the strobe control signal (Max) is deasserted, the logic circuitry of the second clock generator circuit (clock generator, higher) prevents the control signal 122 from being applied to the precharge circuit PCH, multiplexing circuit system MUX, and sense amplifier circuit SA of the I / O circuit 118 in the second I / O circuit system 112M. In this configuration, the control signal is applied only to the first I / O circuit system 112L by the control circuit 120. Furthermore, the second row decoder control signal (RowDecM) is deasserted by the second clock generator circuit (clock generator, higher), and the word line signal strobe circuit 115 responds by preventing word line signals from being applied to the word lines in the second subarray 112M. Conversely, when the strobe control signal (Max) is asserted, the logic circuitry of the second clock generator circuit (clock generator, higher) transmits control signal 122 to the precharge circuit PCH, multiplexing circuit system MUX, and sense amplifier circuit SA in the I / O circuit 118 of the second I / O circuit system 112M. In this configuration, the control signal is applied by control circuitry 120 to both the first and second I / O circuit systems 112L and 112M. Furthermore, the second row decoder control signal (RowDecM) is asserted by the second clock generator circuit (clock generator, higher), and the word line signal gating circuit 115 responds by transmitting word line signals to the word lines in the second subarray 112M.

[0038] As previously noted, SRAM 110 stores data in the form of a histogram of count values ​​(counts). As part of the operation of circuitry 130 used to construct the histogram, the count value is modified in some way (e.g., incremented by one) each time a data word location is accessed. This operation typically involves three steps: step 1) reading the n-bit current count value from a specific data word location accessed in response to an m-bit memory address (address); step 2) mathematically modifying the current count value (e.g., incrementing (e.g., incrementing by one), decrementing, multiplying); and step 3) writing the modified count value back to the SRAM core 112 at the accessed data word location. The step 2) operation for mathematically modifying the count value is performed here by data modification circuitry 132, which is external to (and separate from) memory 110. Data modification circuitry 132 is coupled to the data output (Q) port and input (D) port of data memory 110. As an example, the data modification circuit 132 may include an n-bit adder circuit that operates on the current count value read from memory at the data output (Q) to increment by one and outputs the modified count value to be written back to memory at the data input (D).

[0039] The data modification circuit 132 includes a maximum count detection (or test) circuit 135 configured to determine whether a data modification operation performed by the data modification circuit 132 on the less significant bits 0 to x-1 produces a maximum count value. The assertion of the strobe control signal (Max) depends on this determination. Specifically, the strobe control signal (Max) is de-asserted as long as the data modification operation generates an output that is not in the less significant bits 0 to x-1 of the maximum count value. As an example, consider a data modification operation incremented by one, where the less significant data bits (0 to x-1) received from the data output (Q) are <0,1,1,1> (for x=4) and the result of the incremented operation produces less significant data bits (0 to x-1) <1,0,0,0> for application at the data input (D). In this case, the count value <1,0,0,0> is not the maximum possible count value for the less significant data bits (0 to x-1), and the strobe control signal (Max) is de-asserted by the maximum count detection circuit 135. Conversely, consider the same data modification operation incremented by one, where the lower significant data bits (0 to x-1) received from the data output (Q) are <1,1,1,0>, and the result of the incremented operation is to produce lower significant data bits (0 to x-1) <1,1,1,1> for application at the data input (D). In this case, the maximum possible count value produced by the incremented operation is <1,1,1,1>, and in response, the strobe control signal (Max) is asserted by the maximum count detection circuit 135.

[0040] Now to Figure 5Referring to the circuit diagram shown is a circuit diagram of an example embodiment of a maximum count detection circuit 135. The maximum count detection circuit 135 includes a set-reset (SR) latch with a valid low control configuration. The set input of the SR latch is configured to receive a memory reset signal. When the memory reset signal is asserted (logic low), along with resetting all count values ​​to zero, the latch output is set to logic high. A logic inverter circuit inverts the latch output to generate a logic low deassertion of the memory strobe signal (Max). The reset input of the SR latch is configured to receive an output from detection logic circuitry including an AND gate configured to perform a logical AND operation on all lower valid data bits (0 to x-1) of a given count value. When all lower valid data bits are logic high, indicating that the maximum count value has been reached, the output of the AND gate is also logic high, and the logic inverter circuit inverts this output to generate a logic low assertion at the reset input. In response, the latch output is changed (reset) to logic low. Then, the logic inverter circuit inverts the latch output to generate a logic high assertion for the memory strobe signal (Max).

[0041] The overall operation of circuit 130 will be better understood by considering the following: Initialization of memory 110 is performed to reset all count values ​​and deprecate the assertion strobe control signal (Max). With the strobe signal (Max) deprecated, word line signal strobe circuit 115 prevents word line signals from being applied to word line WL connected to memory cell C in the second subarray 112M, and the logic circuitry of control circuit CTRL prevents control signal 122 from being applied to the precharge circuit PCH, multiplexing circuit system MUX, and sense amplifier circuit SA of I / O circuit 118 in the second I / O circuit system 112M. In this operational configuration for memory 110, the second subarray 112M and the second I / O circuit system 112M are effectively disabled to support a lower power operation mode. For the lower significant bits (0 to x-1), counting, data modification, and histogram generation are performed only for the first subarray 112L and the first I / O circuit system 112L. In response to the received memory address, the line decoder 114 performs a decoding operation and selects a word line WL to be asserted. The count value (count) in the less significant bits (0 to x-1) is then read from the addressed data word location in memory core 112 and output through the data output (Q) port of SRAM 110. The data modification circuit 132 then performs a mathematical modification operation, in this example, incrementing by one (+1), and the modified count value (count + 1) is applied to the data input (D) port of SRAM 110 to be written back to the addressed data word location. This process is repeated for each applied memory address to construct a histogram with incrementing count values, and the strobe control signal (Max) remains in a state of canceled assertion as long as the maximum count value is not reached during the data modification operation.

[0042] However, the operational configuration of memory 110 changes in response to a mathematical modification operation generating a maximum count value for the less significant bits (0 to x-1). Let's assume, as an example, that the less significant bits (0 to x-1) at a specific data word location in memory 110 currently store a count value <1,1,1,0>. In response to the received memory address (address) for that specific data word location, line decoder 114 performs a decoding operation and selects the corresponding word line WL to be asserted. The count value (count) <1,1,1,0> in the less significant bits (0 to x-1) is then read from the addressed data word location in memory core 112 and output through the data output (Q) port of SRAM 110. Data modification circuitry 132 then performs a mathematical modification operation, in this example, an increment (+1) operation, and the modified count value (count +1) <1,1,1,1> is generated. The maximum count value for the lower significant bits (0 to x-1) is detected by the maximum count detection circuit 135, and in response, the strobe control signal (Max) is asserted. The operating configuration of memory 110 is then changed to a configuration where both the first subarray 112L and the second I / O circuit system 112M are enabled. For any subsequent operating cycle, the strobe circuit 115 will allow the word line signal to the word line of memory cell C in the second subarray 112M, and the logic circuitry of the control circuit CTRL will allow the control signal 122 to the channels of the precharge circuit PCH, the multiplexing circuit system MUX, and the sense amplifier circuit SA of the I / O circuit 118 in the second I / O circuit system 112M. Therefore, read and write operations to the addressed locations in the memory are performed using the lower significant bits (0 to x-1) and higher significant bits (x to k-1) of the first and second subarrays 112L and 112M, respectively.

[0043] Now to Figure 6A For reference, it shows the maximum count value when a data modification operation produces lower significant data bits (0 to x-1). Figure 4The timing diagram of the circuit operation is shown below. A pulse of the system clock (Clk) is asserted at time t1 to initiate data operation. In response to the pulse of the system clock Clk, the internal clock (CKintL) of the first clock generator circuit (clock generator.low) of control circuit 120, in conjunction with enabling the first clock generator circuit (clock generator.low), generates a pulse at time t2 to apply control signal 122 to I / O circuit 118 of the first I / O circuit system 116L. Furthermore, at time t3, the first clock generator circuit (clock generator.low) asserts the first row decoder control signal (RowDecL) to enable the row decoder's WL driver circuit. The row decoder then decodes the applied memory address and asserts at time t4 one of the word line signals applied to the first subarray 112L (referred to as WLL).

[0044] Because the memory strobe control signal (Max) is not asserted, indicating the fact that there is no prior instance of the maximum count value being reached for the lower significant data bits (0 to x-1), the internal clock (CKintM) of the second clock generator circuit (clock generator.higher) of control circuit 120 remains deasserted. Therefore, the second clock generator circuit (clock generator.higher) is not enabled to apply control signal 122 to I / O circuit 118 of the second I / O circuit system 116M, and the second row decoder control signal (RowDecM) is deasserted to prevent the row decoder gate circuit 115 from applying word line signals to the word lines (referred to as WLM) of the second subarray 112M.

[0045] At time t5, the control circuit CTRL applies control signal 122 to I / O circuit 118 of the first I / O circuit system 116L. Specifically, this indicates, for example, that the sense amplifier in the first I / O circuit system 116L is actuated by asserting the sense amplifier enable signal (SEANL) to read the lower significant data bits (0 to x-1) of the count value from the addressed location. In this case, the read count value is <1,1,1,0>. It should be noted that because the second clock generator circuit (clock generator, higher) of the control circuit 120 is deasserted, the control circuit CTRL does not apply control signal 122 to I / O circuit 118 of the second I / O circuit system 116M. This specifically indicates, for example, that the sense amplifier enable signal (SEANM) for the sense amplifier in the second I / O circuit system 116M is continuously deasserted.

[0046] At time t6, the incrementing circuit 132 performs an increment operation, and the count value is modified to <1,1,1,1>. The count value <1,1,1,1> for the lower significant data bits (0 to x-1) is the maximum possible count value. The maximum count detection circuit 135 detects this condition and asserts the memory strobe control signal (Max) at time t7. It should be noted that this assertion of the memory strobe control signal (Max) is a latched state (see [link to relevant documentation]). Figure 5 The reset input of the SR latch in the memory remains in place until a memory reset occurs via a memory reset signal (see [link]). Figure 5 (Setting input for the SR latch in the middle).

[0047] At time t8, the control circuit CTRL applies another control signal from control signal 122 to the I / O circuit 118 of the first I / O circuit system 116L to initiate writing an incrementing count value of the lower significant data bits (0 to x-1) with values ​​<1,1,1,1,> back to the addressed memory location in the first subarray 112L. This specifically indicates, for example, an assertion using the write enable signal (WRL) of the first I / O circuit system 116L. Again, because the second clock generator circuit (clock generator, higher) of the control circuit 120 is de-asserted, it should be noted that the control circuit CTRL does not apply control signal 122 to the I / O circuit 118 of the second I / O circuit system 116M, and therefore the write enable signal (WRM) for the I / O circuit 118 of the second I / O circuit system 116M remains de-asserted.

[0048] After a write operation is detected as complete, the control circuit reset signal (Rst) is asserted as logic low at time t9. The assertion of the control circuit reset signal (Rst) at time t9 triggers a series of events between times t10 and t15 to reset the various clocks and signals of the circuit (CKintL, RowDecL, WLL, SAENL, WRL, and Rst) in the expected next cycle.

[0049] Now to Figure 6B For reference, it shows Figure 4The timing diagram shows the operation of the data modification operation after the maximum count value of the lower significant data bits (0 to x-1) has been reached. It should be noted that the memory strobe control signal (Max) is latched into an assertion state because the maximum count value of the lower significant data bits (0 to x-1) was reached in a previous cycle. A pulse of the system clock (Clk) is asserted at time t1 to initiate the data operation. In response to the pulse of the system clock Clk and the assertion state of the memory strobe signal (Max), the internal clocks (CKintL and CKintM) of the first and second clock generator circuits (clock generator.low and clock generator.high) of the control circuit 120 generate pulses at time t2 in conjunction with enabling the first and second clock generator circuits (clock generator.low and clock generator.high) to apply control signal 122 to the I / O circuits 118 of the first and second I / O circuit systems 116L and 116M. Furthermore, at time t3, the first clock generator circuit (clock generator.lower) asserts the first row decoder control signal (RowDecL) to enable the row decoder's WL driver circuit, and the second clock generator circuit (clock generator.higher) asserts the second row decoder control signal (RowDecM) to enable the gating circuit 115. The row decoder then decodes the applied memory address and at time t4 asserts one of the word line signals applied to the first and second subarrays 112L and 112M (referred to as WLL and WLM).

[0050] At time t5, the control circuit CTRL applies control signal 122 to the I / O circuit 118 of the first and second I / O circuit systems 116L and 116M. Specifically, this instructs, for example, to actuate the sense amplifier in the first I / O circuit system 116L using an assertion of the sense amplifier enable signal (SEANL) to read the lower significant data bits (0 to x-1) of the count value from the addressed location, and to actuate the sense amplifier in the second I / O circuit system 116M using an assertion of the sense amplifier enable signal (SEANM) to read the higher significant data bits (x to k-1) of the count value from the addressed location. In this case, the read count value is <0,0,0,0,1,1,1,1>, where <0,0,0,0> is the value of the higher significant data bits (x to k-1), and <1,1,1,1> is the value of the lower significant data bits (0 to x-1).

[0051] At time t6, the increment circuit 132 performs an increment operation, and the count value is modified from <0,0,0,0,1,1,1,1> to <0,0,0,1,0,0,0,0>, where <0,0,0,1> are the higher significant data bits (x to k-1), and <0,0,0,0> are the lower significant data bits (0 to x-1). It should be noted that although the lower significant data bits (0 to x-1) no longer indicate the maximum count value, the assertion of the memory strobe control signal (Max) remains latched.

[0052] At time t7, the control circuit CTRL applies another control signal from control signal 122 to the I / O circuit 118 of the first and second I / O circuit systems 116L and 116M to initiate writing the incrementing count value <0,0,0,1,0,0,0,0> back to the addressed memory location in the first and second subarrays 112L and 112M. This specifically indicates, for example, an assertion using the write enable signal (WRL) of the first I / O circuit system 116L and the write enable signal (WRM) of the second I / O circuit system 116M.

[0053] After the write operation is detected as complete, the control circuit reset signal (Rst) is asserted as logic low at time t8. The assertion of the control circuit reset signal (Rst) at time t8 triggers a series of events between times t9 and t14 to reset the various clocks and signals of the circuit (CKintL, CKintM, RowDecL, RowDecM, WLL, WLM, SAENL, SAENM, WRL, WRM, and Rst) in the expected next cycle.

[0054] exist Figure 4 In the illustrated architecture, the strobe control signal (Max) is a unit signal. Therefore, all memory cells C in all rows of the second subarray 112M are either disabled (when the strobe control signal (Max) is de-asserted) or enabled (when the strobe signal (Max) is asserted). However, it should be recognized that a higher degree of granularity can be applied to the strobe control of memory word lines.

[0055] Figure 7 and Figure 8An embodiment providing this higher degree of granularity for word line gating control is shown. Word line signal gating circuit 115 includes an AND gate 146 for each row. The first input of AND gate 146 receives the word line signal for that row from the WL driver circuit. The second input of AND gate 146 receives a gating control signal output from a latch circuit (Lt), which operates to selectively latch the assertion logic state of the maximum count control signal (Cntmax) on a row-by-row basis. Each latch circuit Lt includes a D-type latch 140 with an effective high control configuration. The reset (R) input of latch 140 is configured to receive a memory reset signal. When the memory reset signal is asserted (logic high), along with resetting all count values ​​to zero, the latch output is reset to logic low. In this configuration, AND gate 146 blocks the path of the word line signal for that row from the WL driver circuit to the word lines of the second subarray 112M. The clock (C) input of latch 140 is configured to receive a latch timing control signal. The data (D) input of latch 140 is configured to receive a maximum count control signal (Cntmax) generated by an AND gate configured to perform a logical AND operation on all lower significant data bits (0 to x-1) of a given count value. When all lower significant data bits are logic high, it indicates that the maximum count value has been reached, and the output of the AND gate is also logic high. In response to the assertion of the maximum count control signal (Cntmax) and the latch timing control signal, the latch output becomes logic high. In this configuration, AND gate 146 passes the word line signal for that row from the WL driver circuitry to the word line of the second subarray 112M. The latch timing control signal is generated by AND gate 142 having a first input configured to receive a word line selection signal, which the row decoder 114 asserts as logic high when the associated word line is selected in response to address decoding. The second input of AND gate 142 receives the logic inversion of the internal clock signal CKint, generated by the control circuit CTRL and associated with the enable operation of the WL driver circuit of the row decoder. Therefore, the latch timing control signal is asserted only when the word line select signal is asserted and the internal clock signal CKint is deasserted. This timing condition occurs only at the end of the operating cycle (as will be described in more detail below) and is used to ensure that latch 140 is set when it is impossible to apply word line signals to the word lines of the second subarray 112M (i.e., when the internal clock signal CKint has disabled the WL driver circuit). In the next cycle at the same address, the maximum count control signal (Cntmax) will be logic low because the lower significant bit will no longer have a maximum count value. In response to the subsequent assertion of the timing signal from AND gate 142, latch 140 will be cleared (i.e., deasserted), and the corresponding row of memory cell C in the second subarray 112M will return to the disabled state via the gating of the word line signal provided by AND gate 146.

[0056] The control circuit CTRL includes a gating circuit 123 (shown herein as a logic AND circuit) that selectively passes the control signal 122 to the I / O circuit 118 in the second I / O circuit system 112M in response to the logic state of the gate control signal (Gcont). The gate control signal (Gcont) is asserted as logic high by the row decoder in response to an assertion of the word line signal by the WL driver circuit and the latch circuit 140 that is set thereto (e.g., logic AND). In other words, the gate control signal (Gcont) is asserted in response to a logical OR operation of the signal generated by performing a logical AND operation on the latch output and the word line selection signal associated therewith. See also Figure 8 .

[0057] The overall operation of circuit 130 will be better understood by considering the following: Initialization of memory 110 is performed to reset all count values, and a memory reset signal is used to further reset all latch circuits 140. With latches 140 in the reset state, word line signal gating circuit 115 prevents word line signals from being applied to word lines WL connected to memory cells C in the second subarray 112M, and logic circuit 123 of control circuit CTRL prevents control signal 122 from being applied to the precharge circuit PCH, multiplexing circuit system MUX, and sense amplifier circuit SA of I / O circuit 118 in the second I / O circuit system 112M. In this operational configuration for memory 110, the second subarray 112M and the second I / O circuit system 112M are effectively disabled to support a lower power consumption operating mode. For the lower significant bits (0 to x-1), counting, data modification, and histogram generation are performed only for the first subarray 112L and the first I / O circuit system 112L. In response to the received memory address, the line decoder 114 performs a decoding operation and selects a word line WL to be asserted. The count value (count) in the less significant bits (0 to x-1) is then read from the addressed data word location in memory core 112 and output through the data output (Q) port of SRAM 110. The data modification circuit 132 then performs a mathematical modification operation, in this example, incrementing by one (+1), and the modified count value (count + 1) is applied to the data input (D) port of SRAM 110 to be written back to the addressed data word location. This process is repeated for each applied memory address to construct a histogram with the incrementing count value, and the strobe control signal (Max) maintains the assertion cancellation.

[0058] However, the operational configuration of memory 110 changes in response to a mathematical modification operation that generates the maximum count value of the less significant bits (0 to x-1). Let's assume, as an example, that the less significant bits (0 to x-1) at a specific data word location in memory 110 currently store a count value <1,1,1,0>. In response to the received memory address (address) for that specific data word location, line decoder 114 performs a decoding operation and selects the corresponding word line WL to be asserted. The count value (count) <1,1,1,0> in the less significant bits (0 to x-1) is then read from the addressed data word location in memory core 112 and output through the data output (Q) port of SRAM 110. Data modification circuitry 132 then performs a mathematical modification operation, in this example, an increment (+1) operation, and the modified count value (count +1) <1,1,1,1> is generated. The maximum count value for the lower significant bits (0 to x-1) is detected by a logic AND gate, and the maximum count control signal (Cntmax) is asserted. At the end of the operation of writing the modified count value back to the addressed data word location, the latch timing control signal is asserted, and the latch circuit 140 responds to the assertion (Cntmax) of both the latch timing control signal and the maximum count control signal by setting the latch Lt output to logic high. The operation configuration for memory 110 is then such that the first subarray 112L is enabled, and the memory cell C on the word line (i.e., row) of the second subarray 112M, where the associated latch Lt has been set, is also enabled. For the next operating cycle with the same address, the strobe circuit 115 will allow the word line signal to the path of the word line of the memory cell C in the second subarray 112M where the associated latch Lt has been set. With at least one latch circuit 140 in a set state, the assertion gate control signal (Gcont) can be performed during subsequent memory accesses (i.e., when a word line signal corresponding to any set latch Lt is applied), and the logic circuit 123 of the control circuit CTRL will allow the control signal 122 to the channels of the precharge circuit PCH, the multiplexing circuit system MUX, and the sense amplifier circuit SA of the I / O circuit 118 in the second I / O circuit system 112M. Therefore, read and write operations to the addressed locations in the memory are performed using the lower significant bits (0 to x-1) and higher significant bits (x to k-1) of the first and second subarrays 112L and 112M, respectively.

[0059] Now to Figure 9A For reference, it shows the maximum count value when a data modification operation produces lower significant data bits (0 to x-1). Figure 7The timing diagram of the circuit operation is shown below. A pulse of the system clock (Clk) is asserted at time t1 to initiate data operation. In response to the pulse of the system clock Clk, the internal clock (CKint) of the control circuit 120 is pulsed at time t2 in conjunction with the generation of the enable control signal 122 and applied to the I / O circuit 118 of the first I / O circuit system 116L. Furthermore, this internal clock (CKint) is applied to the row decoder to enable the WL driver circuit. The row decoder then decodes the applied memory address and asserts one word line signal among the word line signals applied to the first subarray 112L (referred to as WLL) at time t3.

[0060] Because latch circuit 140 has not yet been configured, indicating the fact that there is no prior instance of the maximum count value being reached for the lower significant data bits (0 to x-1), circuit 115 will prevent word line signals from being applied to the word lines of the second subarray 112M (referred to as WLM). Additionally, the strobe signal (Gcont) remains canceled, and strobe circuit 123 will prevent control signal 122 from being applied to I / O circuit 118 of the second I / O circuit system 116M.

[0061] At time t4, the control circuit CTRL applies control signal 122 to I / O circuit 118 of the first I / O circuit system 116L. Specifically, this indicates, for example, that the sense amplifier in the first I / O circuit system 116L is actuated by asserting the sense amplifier enable signal (SEANL) to read the lower significant data bits (0 to x-1) of the count value from the addressed location. In this case, the read count value is <1,1,1,0>. It should be noted that because the gate control signal (Gcont) remains de-asserted, the control circuit CTRL does not apply control signal 122 to I / O circuit 118 of the second I / O circuit system 116M. This specifically indicates, for example, that the sense amplifier enable signal (SEANM) for the sense amplifier in the second I / O circuit system 116M is continuously de-asserted.

[0062] At time t5, the incrementing circuit 132 performs an increment operation and the count value is modified to <1,1,1,1>. The count value <1,1,1,1> of the lower significant data bits (0 to x-1) is the maximum possible count value, and this data condition is detected by an AND logic gate, and the maximum count control signal (Cntmax) is asserted at time t6.

[0063] At time t7, the control circuit CTRL applies another control signal from control signal 122 to the I / O circuit 118 of the first I / O circuit system 116L to initiate writing an incrementing count value of the lower valid data bits (0 to x-1) back to the addressed memory location in the first subarray 112L. This specifically indicates, for example, an assertion using the write enable signal (WRL) of the first I / O circuit system 116L. Again, because the gate control signal (Gcont) remains canceled, it should be noted that the control circuit CTRL does not apply control signal 122 to the I / O circuit 118 of the second I / O circuit system 116M, and therefore the write enable signal (WRM) for the I / O circuit 118 of the second I / O circuit system 116M remains canceled.

[0064] After a write operation is detected as complete, the control circuit reset signal (Rst) is asserted as logic low at time t8. This assertion of the control circuit reset signal (Rst) at time t8 triggers a series of events at times t9, t10, and t12-t14 to reset various clocks and signals of the circuit (CKintL, RowDecL, WLL, SAENL, WRL, and Rst) in the expected next cycle. Furthermore, when the internal clock CKint is reset to logic low at time t9, and the word line WLL remains asserted, the latch clock input timing signal is asserted by AND gate 142 around time t10. When both the data input and clock input (i.e., the maximum count control signal (Cntmax)) of the latch circuit 140 are asserted simultaneously, the output of the latch circuit 140 (i.e., the latch set signal) associated with the row where the maximum possible count value is detected changes to the set state at time t11.

[0065] Now to Figure 9B For reference, it shows Figure 7 The timing diagram shows the operation of the circuit after setting the latch in response to the maximum count value of the lower valid data bits (0 to x-1). It should be noted that this is related to the operation of the circuit used in... Figure 9A The latch circuit 140 corresponding to the word line of the memory location associated with the memory address used in the process shown is latched in a set state, as indicated by the logic high state of the latch set signal. A pulse of the system clock (Clk) is asserted at time t1 to begin data operation. In response to the pulse of the system clock Clk, the internal clock (CKint) of the control circuit 120 pulses at time t2 in conjunction with the generation of the enable control signal 122 and its application to the I / O circuit 118 of the first I / O circuit system 116L. Furthermore, this internal clock (CKint) is applied to the line decoder to enable the WL driver circuitry. Here it will be assumed that for this operating cycle, the memory address and the word line of the memory location associated with the latch set signal are latched in a set state, as indicated by the logic high state of the latch set signal. A pulse of the system clock (Clk) is asserted at time t1 to begin data operation. Figure 9AThe memory address applied in the process shown is the same. The row decoder decodes the applied memory address and asserts the same word line signal in the word line signals. Because the latch circuit 140 associated with the selected word line is set, the corresponding AND gate 146 is enabled, and therefore at time t3, the asserted word line signal is applied to both the first subarray 112L (referred to as WLL) and the second subarray 112M (referred to as WLM) at the corresponding row.

[0066] In response to the setting of latch circuit 140 and the assertion of the corresponding word line signal WLL by the line decoder, the gate control signal (Gcont) is also asserted at time t3 to enable the operation of AND gate 123 of control circuit CTRL.

[0067] At time t4, the control circuit CTRL applies control signal 122 to the I / O circuit 118 of the first and second I / O circuit systems 116L and 116M. Specifically, this instructs, for example, to actuate the sense amplifier in the first I / O circuit system 116L using an assertion of the sense amplifier enable signal (SEANL) to read the lower significant data bits (0 to x-1) of the count value from the addressed location, and to actuate the sense amplifier in the second I / O circuit system 116M using an assertion of the sense amplifier enable signal (SEANM) to read the higher significant data bits (x to k-1) of the count value from the addressed location. In this case, the count value is read as <0,0,0,0,1,1,1,1>, where <0,0,0,0> are the higher significant data bits (x to k-1) and <1,1,1,1> are the lower significant data bits (0 to x-1).

[0068] At time t5, the incrementing circuit 132 performs an increment operation and the count value is modified from <0,0,0,0,1,1,1,1> to <0,0,0,1,0,0,0,0>, where <0,0,0,1> are the higher significant data bits (x to k-1) and <0,0,0,0> are the lower significant data bits (0 to x-1).

[0069] At time t6, the control circuit CTRL applies another control signal from control signal 122 to the I / O circuit 118 of the first and second I / O circuit systems 116L and 116M to initiate the writing of the incrementing count value <0,0,0,1,0,0,0,0> back to the addressed memory location in the first and second subarrays 112L and 112M. This specifically indicates, for example, the assertion using the write enable signal (WRL) of the first I / O circuit system 116L and the write enable signal (WRM) of the second I / O circuit system 116M. It should be noted here that since the lower significant bit of the count value is <0,0,0,0>, it cancels the assertion of the maximum count control signal (Cntmax) as logic low.

[0070] After a write operation is detected as complete, the control circuit reset signal (Rst) is asserted as logic low at time t7. This assertion of the control circuit reset signal (Rst) at time t7 triggers a series of events at times t8, t9, and t11-t13 to reset various clocks and signals of the circuit (CKintL, CKintM, RowDecL, RowDecM, WLL, WLM, SAENL, SAENM, WRL, WRM, and Rst) in the predicted next cycle. Furthermore, when the internal clock CKint is reset to logic low at time t8 and the word line WLL remains asserted, the latch clock input timing signal is asserted by AND gate 142 at time t19. When the data input (maximum count control signal (Cntmax)) of latch circuit 140 is deasserted and the clock input is asserted, the output of the row-associated latch circuit 140 (i.e., the latch set signal) changes back to a logic low setting state at time t10.

[0071] Figure 10 Another embodiment providing this higher degree of granularity for word line gating control is shown. In this embodiment, the address storage circuit 150 in the row decoder 114 stores the memory address (address) of each data storage location (i.e., row), where a gating signal (Max) has been asserted due to the detection that the count value of the lower significant bits (0 to x-1) has reached the maximum count value. The address storage circuit 150 decodes the stored address and asserts a gating signal 152, which is applied to the second input of a logic AND gate 146 corresponding to the row of the decoded address. The first input of the logic AND gate 146 receives the word line signal for that row from the WL driver circuitry. After a reset, no address is stored in the address storage circuit 150, and the second subarray 112M is disabled by blocking the word line signal through the AND gate 146. However, for each instance of asserting the strobe signal (Max) during histogram construction, the address storage circuit 150 stores the memory address currently being applied, and this address is decoded in the row decoder 114 to assert the corresponding strobe signal 152 for selectively enabling rows of memory cells in the second subarray 112M, thereby receiving word line signals through the strobe provided by the AND gate 146.

[0072] The strobe circuit 123 of the control circuit CTRL selectively strobes the control signal 122 applied to the I / O circuit 118 of the second I / O circuit system 116M in response to the strobe control signal Gcont. The strobe control signal Gcont is asserted each time the address storage circuit 150 asserts one of the strobe signals 152.

[0073] By using Figure 10 The address storage circuit 150 in the memory provides further advantages by storing addresses that have been asserted by the strobe control signal (Max) due to mathematical modification operations on the lower significant bits that have reached the maximum count value. The memory locations corresponding to these stored memory addresses will obviously store higher-value counts. In most histogram operations, higher counts are the most important or of greater interest. Knowing the memory locations storing these higher counts, the system can use the addresses stored in the address storage circuit 150 in conjunction with selectively reading histogram data from memory 110. Because this read operation is limited to those addresses stored in the address storage circuit 150, it can be performed in a more power-efficient and time-efficient manner.

[0074] As another improvement, only a limited number of addresses are stored in address storage circuit 150, where those addresses represent memory locations where the highest count value is stored. Tests can be performed by address storage circuit 150 to track the number of times a specific address is received for a memory location where a strobe control signal (Max) has been asserted, and only the maximum number of assertions (or more than a certain threshold) is saved. Knowing the memory location storing the highest count value, the system can use the addresses stored in address storage circuit 150 in conjunction with selectively reading histogram data from memory 110. Because this read operation is limited to only a few selected addresses stored in address storage circuit 150, it can be performed in a more power-efficient and time-saving manner.

[0075] As a further improvement, the address storage circuit 150 can also be configured to store an identifier (e.g., by using a flag) of an individual memory address associated with a single highest count value. Knowing this information, the system can use the flagged address stored in the address storage circuit 150 in conjunction with performing a read operation that specifically reads histogram data from memory 110 for the highest count value. Because this read operation is limited to a single address stored in the address storage circuit 150, it can be performed with greater efficiency in terms of power and time.

[0076] like Figure 4 , Figure 7 and Figure 10 The circuit 130 shown utilizes an external data modification circuit 132 coupled to the data output (Q) port and data input (D) port of the memory 110. In an alternative embodiment, such as Figure 11As shown, step 2) for mathematically modifying the count value is performed internally within the SRAM 110. This is an advantageous solution for further reducing power consumption because it eliminates the need to switch data signals at the SRAM 110's data output (Q) port and data input (D) port or external power supply circuitry in conjunction with implementing the increment operation. In addition to the following, Figure 11 The configuration of circuit 130 in the middle is similar to Figure 4 The configuration of circuit 130 in the middle.

[0077] The memory includes an internal data modification circuit 132' that operates to perform data modification on bits of a count value latched from the read amplifier SA by a latching circuit. The data modification circuit 132' includes an n-bit adder circuit that operates on the latched data word (which is the current count value stored in the memory) to increment and output the modified data word (i.e., count + 1).

[0078] The n-bit adder for the internal data modification circuit 132' is formed by a plurality of half-adder (ADD) circuits, each of which can be implemented as a component of each I / O circuit 118. Each ADD circuit includes a first input and a second input, the first input being coupled to receive a latched data bit from a latch circuit of its corresponding I / O circuit 118, and the second input being coupled to the carry output of the preceding ADD circuit (except for the first ADD circuit associated with the least significant bit column of the logic high-voltage power supply node (Vdd) coupled to the second input). Each ADD circuit also includes a sum output (S) coupled to a MUX circuit and a carry output (C) coupled to the second input of the following ADD circuit. The plurality of ADD circuits in the data input / output (I / O) circuit system 116 are used to perform an increment-by-one operation on the data word provided by the bit latched by the latch circuit.

[0079] The maximum count detection circuit 135 within the memory is coupled to the sum output (S) of the ADD circuit for the less significant bits 0 to x-1. The maximum count detection circuit 135 operates to determine whether the data modification operation performed by the internal data modification circuit 132' on the less significant bits 0 to x-1 produces a maximum count value. The assertion of the strobe control signal (Max) depends on this determination.

[0080] Whenever a data modification operation performed by the ADD circuit generates an output using the least significant bits 0 to x-1 that do not have a maximum value, the strobe control signal (Max) is de-asserted. As an example, consider the following scenario where the least significant data bits (0 to x-1) stored in the latch circuit of I / O circuit 116L are <1,1,0,1> (for x=4), and the result of an increment by one performed by the ADD circuit produces the least significant data bits (0 to x-1) <1,1,1,0> to be applied to the MUX circuit. In this case, the strobe control signal (Max) is de-asserted. Conversely, consider the following scenario where the least significant data bits (0 to x-1) in the latch circuit of I / O circuit 116L are <1,1,1,0>, and the result of an increment by one performed by the AND circuit produces the least significant data bits (0 to x-1) <1,1,1,1> to be applied to the MUX circuit. In this case, the strobe control signal (Max) is asserted.

[0081] The overall operation of circuit 130 will be better understood by considering the following: Initialization of memory 110 is performed to reset all count values ​​and deprecate the assertion strobe control signal (Max). With the strobe signal (Max) deprecated, word line signal strobe circuit 115 prevents word line signals from being applied to word line WL connected to memory cell C in the second subarray 112M, and the logic circuitry of control circuit CTRL prevents control signal 122 from being applied to the precharge circuit PCH, multiplexing circuit system MUX, and sense amplifier circuit SA of I / O circuit 118 in the second I / O circuit system 112M. In this operational configuration for memory 110, the second subarray 112M and the second I / O circuit system 112M are effectively disabled to support a lower power consumption operating mode. For the less significant bits (0 to x-1), counting, data modification, and histogram generation are performed only for the first subarray 112L and the first I / O circuit system 112L. In response to the received memory address, line decoder 114 performs a decoding operation and selects a word line WL to be asserted. The count value (count) in the less significant bits (0 to x-1) is then read from the addressed data word location in memory core 112 and latched into the memory's I / O circuitry. The internal data modification circuit 132' then performs a mathematical modification operation, incrementing by one (+1) in this example, and the modified count value (count + 1) is written back to the addressed data word location via the MUX circuit. This process is repeated for each applied memory address to construct a histogram with the incrementing count value, and the strobe control signal (Max) maintains the assertion cancellation.

[0082] However, the operational configuration of memory 110 changes in response to a mathematical modification operation generating a maximum count value for the less significant bits (0 to x-1). Let's assume, as an example, that the less significant bits (0 to x-1) at a specific data word location in memory 110 currently store a count value <1,1,1,0>. In response to the received memory address (address) for that specific data word location, line decoder 114 performs a decoding operation and selects the corresponding word line WL to be asserted. The count value (count) <1,1,1,0> in the less significant bits (0 to x-1) is then read from the addressed data word location in memory core 112 and latched in the memory's I / O circuitry. The internal data modification circuit 132' then performs a mathematical modification operation, in this example, incrementing by one (+1), and the modified count value (count + 1) <1,1,1,1> is generated and written back to the addressed data word location via the MUX circuitry. The maximum count value for the lower significant bits (0 to x-1) is detected by the maximum count detection circuit 135, and in response, the strobe control signal (Max) is asserted. The operating configuration for memory 110 is then changed to a configuration where both the first subarray 112L and the second I / O circuit system 112M are enabled. For any subsequent operating cycle, the strobe circuit 115 will allow the word line signal to the word line of memory cell C in the second subarray 112M, and the logic circuitry of the control circuit CTRL will allow the control signal 122 to the channels of the precharge circuit PCH, the multiplexing circuit system MUX, and the sense amplifier circuit SA of the I / O circuit 118 in the second I / O circuit system 112M. Therefore, read and write operations to the addressed locations in the memory are performed using the lower significant bits (0 to x-1) and higher significant bits (x to k-1) of the first and second subarrays 112L and 112M, respectively.

[0083] Now to Figure 12A For reference, it shows the maximum count value when a data modification operation produces lower significant data bits (0 to x-1). Figure 11The timing diagram of the circuit operation is shown below. A pulse of the system clock (Clk) is asserted at time t1 to initiate data operation. In response to the pulse of the system clock Clk, the internal clock (CKintL) of the first clock generator circuit (clock generator.low) of control circuit 120, in conjunction with enabling the first clock generator circuit (clock generator.low), generates a pulse at time t2 to apply control signal 122 to I / O circuit 118 of the first I / O circuit system 116L. Furthermore, at time t3, the first clock generator circuit (clock generator.low) asserts the first row decoder control signal (RowDecL) to enable the row decoder's WL driver circuit. The row decoder then decodes the applied memory address and asserts one word line signal among the word line signals applied to the first subarray 112L (referred to as WLL) at time t4.

[0084] Because the memory strobe control signal (Max) is not asserted, indicating the fact that there is no prior instance of the maximum count value being reached for the lower significant data bits (0 to x-1), the internal clock (CKintM) of the second clock generator circuit (clock generator.higher) of control circuit 120 remains deasserted. Therefore, the second clock generator circuit (clock generator.higher) is not enabled to apply control signal 122 to I / O circuit 118 of the second I / O circuit system 116M, and the second row decoder control signal (RowDecM) is deasserted to prevent the row decoder gate circuit 115 from applying word line signals to the word lines (referred to as WLM) of the second subarray 112M.

[0085] At time t5, the control circuit CTRL applies control signal 122 to the I / O circuit 118 of the first I / O circuit system 116L. Specifically, this indicates, for example, that the sense amplifier in the first I / O circuit system 116L is actuated by asserting the sense amplifier enable signal (SEANL) to read the lower significant data bits (0 to x-1) of the count value from the addressed location. In this case, the read count value is <1,1,1,0>, which is latched by the latch circuit associated with the lower significant data bits (0 to x-1). It should be noted that because the second clock generator circuit (clock generator, higher) of the control circuit 120 is deasserted, the control circuit CTRL does not apply control signal 122 to the I / O circuit 118 of the second I / O circuit system 116M. This specifically indicates, for example, that the continuous deassertion of the sense amplifier enable signal (SEANM) for the sense amplifier in the second I / O circuit system 116M is utilized.

[0086] At time t6, the internal increment circuit 132' performs an increment operation, and the adder outputs a count value <1,1,1,1>. This count value <1,1,1,1> for the lower significant data bits (0 to x-1) at the adder output is the maximum possible count value. The maximum count detection circuit 135 detects this condition and asserts the memory strobe control signal (Max) at time t7. It should be noted that this assertion of the memory strobe control signal (Max) is a latched state (see...). Figure 5 The reset input of the SR latch remains in place until a memory reset occurs via a memory reset signal (see [reference]). Figure 5 (Setting input for the SR latch in the middle).

[0087] At time t8, the control circuit CTRL applies another control signal from control signal 122 to the I / O circuit 118 of the first I / O circuit system 116L to initiate writing the incrementing count value of the lower valid data bits (0 to x-1) back to the addressed memory location in the first subarray 112L via the MUX circuit. This specifically indicates, for example, the assertion using the write enable signal (WRL) of the first I / O circuit system 116L. Again, because the second clock generator circuit (clock generator. higher) of the control circuit 120 is de-asserted, it should be noted that the control circuit CTRL does not apply control signal 122 to the I / O circuit 118 of the second clock I / O circuit system 116M, and therefore the write enable signal (WRM) for the I / O circuit 118 of the second I / O circuit system 116M remains de-asserted.

[0088] After a write operation is detected as complete, the control circuit reset signal (Rst) is asserted as logic low at time t9. The assertion of the control circuit reset signal (Rst) at time t9 triggers a series of events between times t10 and t15 to reset the various clocks and signals of the circuit (CKintL, RowDecL, WLL, SAENL, WRL, and Rst) in the expected next cycle.

[0089] Now to Figure 12B For reference, it shows Figure 11The timing diagram shows the operation of the data modification operation after the maximum count value of the lower significant data bits (0 to x-1) has been reached. It should be noted that the memory strobe control signal (Max) is latched into an assertion state because the maximum count value of the lower significant data bits (0 to x-1) was reached in a previous cycle. A pulse of the system clock (Clk) is asserted at time t1 to initiate the data operation. In response to the pulse of the system clock Clk and the assertion state of the memory strobe signal (Max), the internal clocks (CKintL and CKintM) of the first and second clock generator circuits (clock generator.low and clock generator.high) of the control circuit 120 generate pulses at time t2 in conjunction with enabling the first and second clock generator circuits (clock generator.low and clock generator.high) to apply control signal 122 to the I / O circuits 118 of the first and second I / O circuit systems 116L and 116M. Furthermore, at time t3, the first clock generator circuit (clock generator.lower) asserts the first row decoder control signal (RowDecL) to enable the row decoder's WL driver circuit, and the second clock generator circuit (clock generator.higher) asserts the second row decoder control signal (RowDecM) to enable the gating circuit 115. The row decoder then decodes the applied memory address and at time t4 asserts one of the word line signals applied to the first and second subarrays 112L and 112M (referred to as WLL and WLM).

[0090] At time t5, the control circuit CTRL applies control signal 122 to the I / O circuit 118 of the first and second I / O circuit systems 116L and 116M. Specifically, this instructs, for example, to actuate the sense amplifier in the first I / O circuit system 116L using an assertion of the sense amplifier enable signal (SEANL) to read the lower significant data bits (0 to x-1) of the count value from the addressed location, and to actuate the sense amplifier in the second I / O circuit system 116M using an assertion of the sense amplifier enable signal (SEANM) to read the higher significant data bits (x to k-1) of the count value from the addressed location. In this case, the count value is read as <0,0,0,0,1,1,1,1> latched by the latch circuit, where <0,0,0,0> is the latched higher significant data bit (x to k-1), and <1,1,1,1> is the latched lower significant data bit (0 to x-1).

[0091] At time t6, the increment circuit 132 performs an increment operation, and the count value is modified from <0,0,0,0,1,1,1,1> to <0,0,0,1,0,0,0,0>, where <0,0,0,1> are the higher significant data bits (x to k-1) generated by the adder circuit, and <0,0,0,0> are the lower significant data bits (0 to x-1) generated by the adder circuit. It should be noted that although the lower significant data bits (0 to x-1) no longer indicate the maximum count value, the assertion of the memory strobe control signal (Max) remains latched.

[0092] At time t7, the control circuit CTRL applies another control signal from control signal 122 to the I / O circuit 118 of the first and second I / O circuit systems 116L and 116M to initiate writing the incrementing count value <0,0,0,1,0,0,0,0> back to the addressed memory location in the first and second subarrays 112L and 112M. This specifically indicates, for example, an assertion using the write enable signal (WRL) of the first I / O circuit system 116L and the write enable signal (WRM) of the second I / O circuit system 116M.

[0093] After the write operation is detected as complete, the control circuit reset signal (Rst) is asserted as logic low at time t8. The assertion of the control circuit reset signal (Rst) at time t8 triggers a series of events between times t9 and t14 to reset the various clocks and signals of the circuit (CKintL, CKintM, RowDecL, RowDecM, WLL, WLM, SAENL, SAENM, WRL, WRM, and Rst) in the expected next cycle.

[0094] exist Figure 11 The implementation of the word line signal gating circuit 115 and the control signal gating circuit 123 shown corresponds to Figure 4 The implementation of this. However, it should be understood that, as Figure 7 The implementation of the word line signal gating circuit 115 and control signal gating circuit 123 shown in 10 is shown as using an external data modification circuit 132, which can be replaced by using, for example Figure 11 The internal data modification circuit 132' shown is used together.

[0095] Now to Figure 13 For reference, a schematic representation of device 300 is shown, which utilizes Figure 4 , Figure 7 , Figure 10 and Figure 11The device 300 may include, for example, an image sensor in the form of a system-on-a-chip (SoC) comprising a photosensitive circuit 302 having outputs processed by a central processing unit 304. The circuit 110 may include, for example, memory coupled to or embedded in the central processing unit 304. In a particular related example, the image sensor may include a time-of-flight (ToF) sensor known in the art. Such a sensor includes a transmitter circuit 306 configured to emit a light pulse that is reflected back to the photosensitive circuit 302 by a target. In response to the detection of the reflected light pulse, the CPU 304 accesses the circuit 110 at a memory address associated with a timing measurement. Each access causes a mathematical modification (e.g., increment by one) to a stored count value, which provides histogram data over time for identifying targets and distances to those targets.

[0096] While the invention has been detailed and described in the accompanying drawings and foregoing description, such description is to be considered illustrative or exemplary rather than restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments will be understood and implemented by those skilled in the art in practicing the claimed invention upon studying the drawings, the disclosure, and the appended claims.

Claims

1. A circuit comprising: The memory circuit includes: A memory core is formed by an array of memory cells storing data words in rows, wherein each row is connected to a word line, and wherein the array is arranged to include a first subarray and a second subarray, the first subarray storing the less significant bits of the data words and the second subarray storing the more significant bits of the data words; and A line decoder circuit is configured to receive an address, decode the received address, and generate a word line signal, which is applied to a selected word line for a specific data location based on the decoded address. A data modification circuit is configured to perform a mathematical operation on a data word read from a specific data location in the memory cell array corresponding to a selected word line in the word lines, so as to produce a modified data word that is written back to the specific data location in the memory cell array; The row decoder further includes a word line gating circuit configured to selectively gating the word line signal to a channel of memory cell in the second subarray in response to an assertion of a maximum value signal; and A detection circuit is configured to assert the maximum value signal by generating a maximum data value for the lower significant bit of the data word in response to determining the mathematical operation performed on the lower significant bit of the data word from the first subarray.

2. The circuit according to claim 1, wherein the data modification circuit is external to the memory circuit.

3. The circuit according to claim 1, wherein the data modification circuit is internal to the memory circuit.

4. The circuit according to claim 1, wherein the mathematical operation includes one of an increment operation, a decrement operation, or a multiplication operation.

5. The circuit of claim 1, wherein the word line gating circuit includes an AND gate for each word line, the AND gate including a first input configured to receive the word line signal, a second input configured to receive a gating control signal derived from the maximum value signal, and an output coupled to the word line for the memory cell of the second subarray.

6. The circuit of claim 1, wherein the word line gating circuit comprises: A logic AND gate for each word line, the logic AND gate including a first input configured to receive the word line signal, a second input configured to receive a strobe control signal, and an output coupled to the word line for the memory cell of the second subarray; as well as A latching circuit is configured to selectively latch the gating control signal in response to an assertion of the maximum value signal.

7. The circuit of claim 6, wherein the latching circuit comprises: A set-reset latch has a set input and a clock input configured to receive the maximum value signal; as well as Another logic AND gate includes a first input configured to receive a word line select signal, a second input configured to receive a clock signal, and an output coupled to the clock input of the set-reset latch.

8. The circuit of claim 1, wherein the word line gating circuit comprises: A logic AND gate for each word line, the logic AND gate including a first input configured to receive the word line signal, a second input configured to receive a strobe control signal, and an output coupled to the word line for the memory cell of the second subarray; as well as A maximum address circuit is configured to store an address associated with a data location in response to an assertion of the maximum value signal, wherein the mathematical operation is performed on the less significant bit of the data word from the first subarray at the data location to produce the maximum data value, and the maximum address circuit is further configured to output the strobe control signal when the memory is addressed at one of the stored addresses.

9. The circuit of claim 8, wherein the memory further comprises: An input / output circuitry system coupled to the memory core, wherein the input / output circuitry system is configured to read the data word for output only from the data location corresponding to the stored address.

10. The circuit of claim 9, wherein the maximum value address circuit is further configured to mark a stored address in which the data word has the highest value, and wherein the input / output circuit system is configured to read the data word for output only from the data location of the marked stored address.

11. The circuit of claim 1, wherein the memory further comprises: The first input / output circuit system is coupled to the first subarray; The second input / output circuitry system is coupled to the second subarray; as well as A control circuit is configured to generate a control signal for controlling the operation of circuits within the first input / output circuit system and the second input / output circuit system. The control circuitry includes a control signal gating circuit configured to selectively gating the control signal to a channel of the second input / output circuitry system in response to an assertion of the maximum value signal.

12. The circuit of claim 1, wherein the data modification circuit comprises a plurality of adder circuits connected in series, the plurality of adder circuits being configured to perform the mathematical operation, and wherein the detection circuit is configured to assert the maximum value signal if the outputs from all the adder circuits are in the same logic state.

13. The circuit of claim 1, wherein, in response to an assertion of the maximum value signal, the word line gating circuit allows access to all rows of the second subarray storing the higher significant bits of the data word.

14. The circuit of claim 1, wherein the word line gating circuit allows access only to a plurality of specific rows of the second subarray, the plurality of specific rows storing the higher significant bits of the data word for a data location, where the maximum data value is generated by performing the mathematical operation on the lower significant bits from the first subarray, the maximum value signal being asserted by the detection circuit.

15. The circuit of claim 1, wherein the memory circuit is further configured to operate in a data read operation mode to retrieve a data word, and wherein the word line strobing circuit is further configured to strobe a channel of the word line signal in the data read operation mode to access the memory cells of the second subarray.

16. A circuit comprising: The memory circuit includes: A memory cell array is arranged to include a first subarray and a second subarray, wherein the first subarray stores the less significant bits of a data word and the second subarray stores the more significant bits of a data word. The first multiple word lines are used for the first subarray; The second multiple word lines are used for the second subarray; and A line decoder circuit coupled to the first plurality of word lines and the second plurality of word lines, wherein the line decoder generates word line signals and includes a word line gating circuit configured to selectively gating the word line signals to channels for the second plurality of word lines for the second subarray in response to an assertion of a maximum value signal; The data modification circuit is configured to perform mathematical operations on data read from the memory cell array; and The detection circuit is configured to assert the maximum value signal by generating a maximum data value in response to the mathematical operation performed on the lower significant bits of the data from the first subarray.

17. The circuit of claim 16, wherein the data modification circuit and the detection circuit are external to the memory circuit.

18. The circuit of claim 16, wherein the data modification circuit and the detection circuit are internal to the memory circuit.

19. The circuit according to claim 16, wherein the mathematical operation is an incrementing operation of one.

20. The circuit of claim 16, wherein the word line gating circuit includes an AND gate for each of the second plurality of word lines, the AND gate including a first input configured to receive the word line signal, a second input configured to receive a gating control signal derived from the maximum value signal, and an output coupled to the word line of the second plurality of word lines.

21. The circuit of claim 16, wherein the word line gating circuit comprises: A logic AND gate for each of the second plurality of word lines, the logic AND gate including a first input configured to receive the word line signal, a second input configured to receive a strobe control signal, and an output coupled to the word line of the second plurality of word lines; as well as A latching circuit is configured to selectively latch the gating control signal in response to an assertion of the maximum value signal.

22. The circuit of claim 21, wherein the latching circuit comprises: A set-reset latch has a set input configured to receive the maximum value signal; as well as Another logic AND gate includes a first input configured to receive a word line select signal, a second input configured to receive a clock signal, and an output coupled to a clock setting input of the set-reset latch.

23. The circuit of claim 16, wherein the word line gating circuit comprises: A logic AND gate for each of the second plurality of word lines, the logic AND gate including a first input configured to receive the word line signal, a second input configured to receive a strobe control signal, and an output coupled to the word line of the second plurality of word lines; as well as A maximum address circuit is configured to store an address associated with a data location in response to an assertion of the maximum value signal, wherein the mathematical operation is performed on the less significant bit of the data word from the first subarray at the data location to produce the maximum data value, and the maximum address circuit is further configured to output the strobe control signal when the memory is addressed at one of the stored addresses.

24. The circuit of claim 23, wherein the memory further comprises: An input / output circuitry system coupled to the memory core, wherein the input / output circuitry system is configured to read the data word for output only from the data location corresponding to the stored address.

25. The circuit of claim 24, wherein the maximum value address circuit is further configured to mark a stored address in which the data word has the highest value, and wherein the input / output circuit system is configured to read the data word for output only from the data location of the marked stored address.

26. The circuit of claim 16, wherein the memory further comprises: The first input / output circuit system is coupled to the first subarray; The second input / output circuitry system is coupled to the second subarray; A control circuit is configured to generate a control signal for controlling the operation of circuits within the first input / output circuit system and the second input / output circuit system. The control circuitry includes a control signal gating circuit configured to selectively gating the control signal to a channel of the second input / output circuitry system in response to an assertion of the maximum value.

27. The circuit of claim 16, wherein the memory circuit is further configured to operate in a data read operation mode to retrieve a data word, and wherein the word line strobing circuit is further configured to strobe a channel of the word line signal in the data read operation mode to access the memory cells of the second subarray.

28. A method for operating a memory circuit, the memory circuit comprising an array of memory cells arranged in a modular architecture having a first subarray and a second subarray, the first subarray being configured to store the less significant bits of a data word, and the second subarray being configured to store the more significant bits of a data word, the method comprising: Read data from the memory circuit; Perform mathematical operations on the data read from the memory circuitry to generate modified data; as well as Write the modified data back to the memory circuit; Reading and writing the modified data includes assertion word line signals to select the data location in the memory for reading and writing the modified data; The method further includes: Prevent the word line signal from being applied to the second subarray; Performing the mathematical operation includes performing the mathematical operation on the less significant bit of the data read from the data position; If the mathematical operation performed on the less significant bits of the read data produces the maximum data value, then the maximum value signal is asserted; and Subsequently, in response to the asserted maximum value signal, the word line signal is allowed to be applied to the second subarray for at least the data location.

29. The method of claim 28, wherein the mathematical operation is an incrementing operation of one.

30. The method of claim 28, wherein blocking and subsequent enabling are performed by selectively strobing the word line signal.

31. The method of claim 28, further comprising: The maximum value signal is logically combined with the word line selection signal used for the data position to generate a gating control signal; as well as The word line signal is selectively selected in response to the logic state of the strobe control signal.

32. The method of claim 28, further comprising: If the maximum value signal is asserted by a mathematical operation performed on the less significant bit of the data read at the data location, then the address applied to the memory is stored to select the data location.

33. The method of claim 32, further comprising: The stored address is used to selectively control the application of the word line signal to the second subarray for the data location associated with the stored address.

34. The method of claim 32, further comprising: The modified data is selectively read from the memory using the stored address.

35. The method of claim 32, further comprising: If the modified data at the data location associated with the stored address has the highest value, then the stored address is marked.

36. The method of claim 35, further comprising: The modified data with the highest value is selectively read from the memory using the tagged stored address.

37. The method of claim 28, wherein the memory further comprises a first input / output circuitry system and a second input / output circuitry system, the first input / output circuitry system being associated with the first subarray and the second input / output circuitry system being associated with the second subarray, the method further comprising: In response to the cancellation assertion of the maximum value signal, the input / output control signal is applied to the first input / output circuitry system instead of the second input / output circuitry system; as well as In response to an assertion of the maximum value signal, input / output control signals are applied to both the first input / output circuit system and the second input / output circuit system.

38. The method of claim 28, wherein the memory circuitry is further configured to operate in a data read operation mode to retrieve a data word, the method comprising: In the data read operation mode, the strobe word line signal is applied to access the memory cells of the second subarray.

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