High voltage transistor structure and method of manufacturing the same

Abstract

A high voltage transistor structure and a method of fabricating the same are disclosed. The high voltage transistor structure includes a substrate, a first drift region, a second drift region, a first cap layer, a second cap layer, a gate structure, a first source / drain region, and a second source / drain region. The first drift region and the second drift region are disposed in the substrate. The first cap layer and the second cap layer are disposed on the first drift region and the second drift region, respectively. The gate structure is disposed on the substrate and above at least a portion of the first drift region and at least a portion of the second drift region. The first source / drain region and the second source / drain region are disposed in the first drift region and the second drift region, respectively, and are located on two sides of the gate structure. The size of the first drift region is asymmetric to the size of the second drift region.

Description

Technical Field

[0001] This invention relates to a semiconductor structure and its manufacturing method, and more particularly to a high-voltage transistor structure and its manufacturing method. Background Technology

[0002] Currently, high-voltage transistors are widely used in various electronic products. With technological advancements, the size of electronic components continues to shrink, making it increasingly difficult to improve the breakdown voltage of high-voltage transistors. Therefore, increasing the breakdown voltage of high-voltage transistors remains a continuous goal. Summary of the Invention

[0003] This invention provides a high-voltage transistor structure and its manufacturing method, which can improve the breakdown voltage of high-voltage transistor components.

[0004] This invention proposes a high-voltage transistor structure, including a substrate, a first drift region, a second drift region, a first capping layer, a second capping layer, a gate structure, a first source / drain region, and a second source / drain region. The first and second drift regions are disposed within the substrate. The first and second capping layers are respectively disposed on the first and second drift regions. The gate structure is disposed on the substrate and located above at least a portion of the first and second drift regions. The first and second source / drain regions are respectively disposed within the first and second drift regions and located on opposite sides of the gate structure. The dimensions of the first and second drift regions are asymmetrical.

[0005] According to an embodiment of the present invention, in the above-described high-voltage transistor structure, the materials of the first drift region and the second drift region can be epitaxial materials, respectively.

[0006] According to one embodiment of the present invention, in the above-described high-voltage transistor structure, the size of the second drift region may be larger than the size of the first drift region.

[0007] According to one embodiment of the present invention, in the above-described high-voltage transistor structure, the depth of the second drift region may be greater than the depth of the first drift region.

[0008] According to an embodiment of the present invention, in the above-described high-voltage transistor structure, the width of the second drift region may be greater than the width of the first drift region.

[0009] According to an embodiment of the present invention, in the above-described high-voltage transistor structure, the first drift region and the second drift region each may include a first epitaxial layer and a second epitaxial layer. The second epitaxial layer is located within the first epitaxial layer. The doping concentration of the second epitaxial layer may be greater than the doping concentration of the first epitaxial layer. The doping concentrations of the first source / drain region and the second source / drain region may be greater than the doping concentration of the second epitaxial layer.

[0010] According to an embodiment of the present invention, in the above-described high-voltage transistor structure, the first drift region and the second drift region may each further include a third epitaxial layer. The first epitaxial layer is located within the third epitaxial layer. The third epitaxial layer may be an undoped epitaxial layer.

[0011] According to an embodiment of the present invention, in the above-described high-voltage transistor structure, the first capping layer may be located between the gate structure and the first drift region, and the second capping layer may be located between the gate structure and the second drift region.

[0012] According to an embodiment of the present invention, in the above-described high-voltage transistor structure, the materials of the first capping layer and the second capping layer can be undoped epitaxial materials, respectively.

[0013] According to one embodiment of the present invention, in the above-described high-voltage transistor structure, the gate structure may include a gate and a gate dielectric layer. The gate is disposed on a substrate. The gate dielectric layer is located between the gate and the substrate.

[0014] According to one embodiment of the present invention, in the above-described high-voltage transistor structure, the gate structure may further include a spacer wall. The spacer wall is disposed on the sidewall of the gate.

[0015] This invention proposes a method for manufacturing a high-voltage transistor structure, comprising the following steps: Providing a substrate. Forming a first drift region and a second drift region in the substrate. Forming a first capping layer and a second capping layer on the first drift region and the second drift region, respectively. Forming a gate structure on the substrate. The gate structure is located above at least a portion of the first drift region and at least a portion of the second drift region. Forming a first source / drain region and a second source / drain region in the first drift region and the second drift region, respectively. The first source / drain region and the second source / drain region are located on opposite sides of the gate structure. The dimensions of the first drift region and the second drift region are asymmetrical.

[0016] According to an embodiment of the present invention, in the manufacturing method of the above-described high-voltage transistor structure, the method for forming the first drift region and the second drift region may include the following steps: forming a first recess and a second recess in a substrate; and forming the first drift region and the second drift region in the first recess and the second recess, respectively.

[0017] According to an embodiment of the present invention, in the above-described method for manufacturing a high-voltage transistor structure, the materials of the first drift region and the second drift region can be epitaxial materials, respectively.

[0018] According to an embodiment of the present invention, in the above-described method for manufacturing a high-voltage transistor structure, the size of the second drift region may be larger than the size of the first drift region.

[0019] According to an embodiment of the present invention, in the above-described method for manufacturing a high-voltage transistor structure, the depth of the second drift region may be greater than the depth of the first drift region.

[0020] According to an embodiment of the present invention, in the above-described method for manufacturing a high-voltage transistor structure, the width of the second drift region may be greater than the width of the first drift region.

[0021] According to an embodiment of the present invention, in the manufacturing method of the above-described high-voltage transistor structure, the first drift region and the second drift region may each include a first epitaxial layer and a second epitaxial layer. The second epitaxial layer is located within the first epitaxial layer. The doping concentration of the second epitaxial layer may be greater than the doping concentration of the first epitaxial layer. The doping concentrations of the first source / drain region and the second source / drain region may be greater than the doping concentration of the second epitaxial layer.

[0022] According to an embodiment of the present invention, in the manufacturing method of the above-described high-voltage transistor structure, the first drift region and the second drift region may each further include a third epitaxial layer. The first epitaxial layer is located within the third epitaxial layer. The third epitaxial layer may be an undoped epitaxial layer.

[0023] According to an embodiment of the present invention, in the manufacturing method of the above-described high-voltage transistor structure, the first capping layer may be located between the gate structure and the first drift region, and the second capping layer may be located between the gate structure and the second drift region.

[0024] Based on the above, in the high-voltage transistor structure and manufacturing method proposed in this invention, the breakdown voltage of the high-voltage transistor element can be increased because the dimensions of the first drift region and the second drift region are asymmetrical. Furthermore, the breakdown voltage of the high-voltage transistor element can be flexibly adjusted by adjusting the dimensions of the first drift region and / or the second drift region. Additionally, the breakdown voltage of the high-voltage transistor element can be flexibly adjusted by adjusting the thickness of the first capping layer and / or the thickness of the second capping layer.

[0025] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0026] Figures 1A-1E This is a cross-sectional view showing the manufacturing process of a high-voltage transistor structure according to an embodiment of the present invention.

[0027] Symbol Explanation

[0028] 10: High-voltage transistor structure

[0029] 100: Base

[0030] 102: Hard mask material layer

[0031] 102a: Hard mask layer

[0032] 104: Patterned photoresist layer

[0033] 106a, 106b: Drift Zones

[0034] 108a, 108b, 110a, 110b, 112a, 112b: Epitaxial layers

[0035] 114a, 114b: Cap layer

[0036] 116: Gate Structure

[0037] 118: Gate

[0038] 120: Gate dielectric layer

[0039] 122: Interstitial wall

[0040] 124a, 124b: Source / Drain Regions

[0041] D1~D4: Depth

[0042] W1~W4: Width Detailed Implementation

[0043] Figures 1A-1E This is a cross-sectional view showing the manufacturing process of a high-voltage transistor structure according to an embodiment of the present invention.

[0044] Please refer to Figure 1A A substrate 100 is provided. The substrate 100 may be a semiconductor substrate, such as a silicon substrate. Next, a hard mask material layer 102 may be formed on the substrate 100. The material of the hard mask material layer 102 may be, for example, silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbide nitride (SiCN). The hard mask material layer 102 may be formed by, for example, chemical vapor deposition.

[0045] Please refer to Figure 1B A patterned photoresist layer 104 can be formed on the hard mask material layer 102. The patterned photoresist layer 104 can be formed by photolithography.

[0046] Please refer to Figure 1CA patterned photoresist layer 104 can be used as a mask to remove part of the hard mask material layer 102, thereby forming a hard mask layer 102a. The method for removing part of the hard mask material layer 102 is, for example, dry etching.

[0047] Next, a portion of the substrate 100 can be removed using a patterned photoresist layer 104 as a mask. This forms recesses R1 and R2 in the substrate 100. The dimensions of recess R2 and recess R1 may be asymmetrical. In some embodiments, the dimension of recess R2 may be larger than the dimension of recess R1. In this embodiment, "dimension" may refer to the depth or width of a component. Furthermore, in this embodiment, "depth" refers to "maximum depth," and "width" refers to "maximum width." In some embodiments, the depth D2 of recess R2 may be greater than the depth D1 of recess R1. In some embodiments, the width W2 of recess R2 may be greater than the width W1 of recess R1. The method for removing a portion of the substrate 100 is, for example, dry etching. Furthermore, the shapes of recess R1 and recess R2 are not limited to... Figure 1C The shape in the middle.

[0048] The patterned photoresist layer 104 can then be removed. The removal method for the patterned photoresist layer 104 is, for example, dry stripping or wet stripping. In some embodiments, a cleaning process may be performed after the patterned photoresist layer 104 is removed.

[0049] Please refer to Figure 1D Drift regions 106a and 106b can be formed in recesses R1 and R2, respectively. Thus, drift regions 106a and 106b are formed in the substrate 100. The materials of drift regions 106a and 106b can be epitaxial materials, thereby increasing the turn-on current (Ion). For example, when the high-voltage semiconductor structure 10(…) to be fabricated… Figure 1E When the transistor is a P-type metal oxide semiconductor (PMOS), the materials of drift region 106a and drift region 106b can be silicon-germanium (SiGe), respectively. When the high-voltage semiconductor structure 10( Figure 1E When the transistor is an N-type metal oxide semiconductor (NMOS) transistor, the materials of the drift region 106a and the drift region 106b can be silicon phosphide (SiP), respectively.

[0050] The dimensions of drift region 106a and drift region 106b are asymmetrical, thereby increasing the breakdown voltage of the high-voltage transistor element. Furthermore, the breakdown voltage of the high-voltage transistor element can be flexibly adjusted by adjusting the dimensions of drift region 106a and / or drift region 106b. In some embodiments, the size of drift region 106b may be larger than the size of drift region 106a. In some embodiments, the depth D4 of drift region 106b may be greater than the depth D3 of drift region 106a. In some embodiments, the width W4 of drift region 106b may be greater than the width W3 of drift region 106a. Moreover, the shapes of drift region 106a and drift region 106b are not limited to these dimensions. Figure 1D The shape in the middle.

[0051] The drift region 106a may include epitaxial layers 108a and 110a. Epitaxial layer 110a is located within epitaxial layer 108a. In some embodiments, epitaxial layers 108a and 110a may be epitaxial layers doped with a P-type dopant (e.g., boron) or an N-type dopant (e.g., phosphorus). The doping concentration of epitaxial layer 110a may be greater than that of epitaxial layer 108a, thereby allowing the drift region 106a to have a gradient doping concentration. Furthermore, the drift region 106a may also include epitaxial layer 112a. Epitaxial layer 108a is located within epitaxial layer 112a. That is, epitaxial layer 112a may be located between epitaxial layer 108a and substrate 100. Epitaxial layer 112a may be an undoped epitaxial layer. In some embodiments, the breakdown voltage of the high-voltage transistor device can be flexibly adjusted by adjusting the thickness of epitaxial layer 112a.

[0052] Furthermore, when the high-voltage semiconductor structure to be fabricated is 10 ( Figure 1E When the transistor is a PMOS transistor, epitaxial layers 108a and 110a can be P-type conductive, and the materials of epitaxial layers 108a, 110a, and 112a can be silicon-germanium (SiGe), respectively. When the high-voltage semiconductor structure 10( Figure 1E When the transistor is an NMOS transistor, epitaxial layers 108a and 110a can be N-type conductive, and the materials of epitaxial layers 108a, 110a, and 112a can all be silicon phosphide (SiP). The drift region 106a can be formed, for example, by metal-organic chemical vapor deposition (MOCVD) sequentially forming epitaxial layers 112a, 108a, and 110a in the recess R1. Therefore, epitaxial layers 112a, 108a, and 110a can be formed continuously on the same process equipment, thereby reducing process complexity.

[0053] The drift region 106b may include epitaxial layers 108b and 110b. Epitaxial layer 110b is located within epitaxial layer 108b. In some embodiments, epitaxial layers 108b and 110b may be epitaxial layers doped with a P-type dopant (e.g., boron) or an N-type dopant (e.g., phosphorus). The doping concentration of epitaxial layer 110b may be greater than that of epitaxial layer 108b, thereby allowing the drift region 106b to have a gradient doping concentration. Furthermore, the drift region 106b may also include epitaxial layer 112b. Epitaxial layer 108b is located within epitaxial layer 112b. That is, epitaxial layer 112b may be located between epitaxial layer 108b and substrate 100. Epitaxial layer 112b may be an undoped epitaxial layer. In some embodiments, the breakdown voltage of the high-voltage transistor device can be flexibly adjusted by adjusting the thickness of epitaxial layer 112b.

[0054] Furthermore, when the high-voltage semiconductor structure to be fabricated is 10 ( Figure 1E When the transistor is a PMOS transistor, epitaxial layers 108b and 110b can be P-type conductive, and the materials of epitaxial layers 108b, 110b, and 112b can be silicon-germanium (SiGe), respectively. When the high-voltage semiconductor structure 10( Figure 1E When the transistor is an NMOS transistor, the materials of epitaxial layer 108b and epitaxial layer 110b can be N-type conductive, and the materials of epitaxial layer 108b, epitaxial layer 110b, and epitaxial layer 112b can all be silicon phosphide (SiP). The drift region 106b is formed, for example, by sequentially forming epitaxial layer 112b, epitaxial layer 108b, and epitaxial layer 110b in the recess R2 using metal-organic chemical vapor deposition. Therefore, epitaxial layer 112b, epitaxial layer 108b, and epitaxial layer 110b can be formed continuously on the same process equipment, thereby reducing process complexity.

[0055] In some embodiments, drift regions 106a and 106b can be formed simultaneously using the same process, thereby reducing process complexity. That is, epitaxial layers 112a and 112b can be formed simultaneously using the same process, as can epitaxial layers 108a and 108b, and epitaxial layers 110a and 110b. In some embodiments, the dimensions (e.g., depth and / or width) of epitaxial layer 108b can be larger than the dimensions (e.g., depth and / or width) of epitaxial layer 108a. In some embodiments, the dimensions (e.g., depth and / or width) of epitaxial layer 110b can be larger than the dimensions (e.g., depth and / or width) of epitaxial layer 110a. In some embodiments, the dimensions (e.g., depth and / or width) of epitaxial layer 112b can be larger than the dimensions (e.g., depth and / or width) of epitaxial layer 112a.

[0056] Next, capping layers 114a and 114b are formed on drift regions 106a and 106b, respectively.

[0057] In some embodiments, the breakdown voltage of the high-voltage transistor element can be flexibly adjusted by adjusting the thickness of capping layer 114a and / or the thickness of capping layer 114b. The materials of capping layer 114a and capping layer 114b can each be undoped epitaxial materials. In some embodiments, the materials of capping layer 114a and capping layer 114b can each be undoped epitaxial silicon. In some embodiments, when the high-voltage semiconductor structure 10 to be fabricated ( Figure 1E When the transistor is a PMOS transistor, the materials of the capping layer 114a and the capping layer 114b can be silicon-germanium (SiGe), respectively. When the high-voltage semiconductor structure 10 to be fabricated... Figure 1E When the transistor is an NMOS transistor, the materials of capping layer 114a and capping layer 114b can be silicon phosphide (SiP), respectively. The capping layers 114a and 114b can be formed, for example, by metal-organic chemical vapor deposition. In some embodiments, capping layers 114a and 114b can be formed simultaneously using the same process. In some embodiments, drift region 106a, drift region 106b, capping layers 114a and 114b can be formed continuously using the same process equipment, thereby reducing process complexity.

[0058] Then, after forming capping layers 114a and 114b, the hard mask layer 102a can be removed. The hard mask layer 102a can be removed, for example, by wet etching. In some embodiments, a cleaning process can be performed after removing the hard mask layer 102a.

[0059] Please refer to Figure 1E A gate structure 116 is formed on the substrate 100. The gate structure 116 is located above at least a portion of the drift regions 106a and at least a portion of the drift regions 106b. In addition, a capping layer 114a may be located between the gate structure 116 and the drift region 106a, and a capping layer 114b may be located between the gate structure 116 and the drift region 106b.

[0060] The gate structure 116 may include a gate 118 and a gate dielectric layer 120. The gate 118 is disposed on the substrate 100. The material of the gate 118 is, for example, doped polysilicon, but the invention is not limited thereto. The gate dielectric layer 120 is located between the gate 118 and the substrate 100. The material of the gate dielectric layer 120 is, for example, silicon oxide. Additionally, the gate structure 116 may also include a spacer wall 122. The spacer wall 122 is disposed on the sidewall of the gate 118. The spacer wall 122 may be a single-layer structure or a multi-layer structure. The material of the spacer wall 122 may be silicon oxide, silicon nitride, or a combination thereof.

[0061] Next, source / drain regions 124a and 124b are formed in drift regions 106a and 106b, respectively. Source / drain regions 124a and 124b are located on opposite sides of the gate structure 116. Furthermore, portions of source / drain regions 124a and 124b may be located within capping layers 114a and 114b, respectively. The doping concentration of source / drain region 124a may be greater than the doping concentration of epitaxial layer 110a. The doping concentration of source / drain region 124b may be greater than the doping concentration of epitaxial layer 110b. When the high-voltage semiconductor structure 10 is a PMOS transistor, source / drain regions 124a and 124b may be P-type conductive. When the high-voltage semiconductor structure 10 is an NMOS transistor, the source / drain regions 124a and 124b can be N-type conductive. The source / drain regions 124a and 124b can be formed, for example, by ion implantation.

[0062] In some embodiments, since a high voltage (VDD) is applied to the source / drain region 124b, a drift region 106b with a larger size can be positioned adjacent to the source / drain region 124b. For example, when the high-voltage transistor structure 10 is a PMOS transistor, a high voltage (VDD) is applied to the source region (e.g., the source / drain region 124b), and a drift region 106b with a larger size can be positioned adjacent to the source / drain region 124b. When the high-voltage transistor structure 10 is an NMOS transistor, a high voltage (VDD) is applied to the drain region (e.g., the source / drain region 124b), and a drift region 106b with a larger size can be positioned adjacent to the source / drain region 124b.

[0063] The following is through Figure 1E The high-voltage transistor structure 10 of this embodiment will be explained below. Furthermore, although the method for forming the high-voltage transistor structure 10 is described using the method described above as an example, the present invention is not limited thereto.

[0064] Please refer to Figure 1EThe high-voltage transistor structure 10 includes a substrate 100, drift regions 106a and 106b, capping layers 114a and 114b, a gate structure 116, and source / drain regions 124a and 124b. In some embodiments, the high-voltage transistor structure 10 may be a double diffused drain metal-oxide semiconductor (DDDMOS). Drift regions 106a and 106b are disposed in the substrate 100. Capping layers 114a and 114b are respectively disposed on drift regions 106a and 106b. The gate structure 116 is disposed on the substrate 100 and is located above at least a portion of drift regions 106a and 106b. Source / drain regions 124a and 124b are respectively disposed in drift regions 106a and 106b and are located on both sides of the gate structure 116. The dimensions of drift region 106a and drift region 106b are asymmetrical. Furthermore, the materials, formation methods, and configuration relationships of the components in the high-voltage transistor structure 10 have been described in detail in the above embodiments and will not be repeated here.

[0065] As can be seen from the above embodiments, in the high-voltage transistor structure 10 and its manufacturing method, the breakdown voltage of the high-voltage transistor element can be increased because the dimensions of the drift region 106a and the drift region 106b are asymmetrical. Furthermore, the breakdown voltage of the high-voltage transistor element can be flexibly adjusted by adjusting the dimensions of the drift region 106a and / or the drift region 106b. Additionally, the breakdown voltage of the high-voltage transistor element can be flexibly adjusted by adjusting the thickness of the capping layer 114a and / or the thickness of the capping layer 114b.

[0066] In summary, the high-voltage transistor structure and manufacturing method of the above embodiments can improve the breakdown voltage of the high-voltage transistor element and flexibly adjust the breakdown voltage of the high-voltage transistor element.

[0067] Although the present invention has been disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A high-voltage transistor structure, comprising: Base; The first drift region and the second drift region are disposed in the substrate; The first capping layer and the second capping layer are respectively disposed on the first drift region and the second drift region; A gate structure is disposed on the substrate and located above at least a portion of the first drift region and at least a portion of the second drift region; as well as The first source / drain region and the second source / drain region are respectively disposed in the first drift region and the second drift region, and are located on both sides of the gate structure, wherein The size of the first drift region is asymmetrical with the size of the second drift region. The materials of the first capping layer and the second capping layer respectively include undoped epitaxial materials. A portion of the first source / drain region and a portion of the second source / drain region are located in the first capping layer and the second capping layer, respectively.

2. The high-voltage transistor structure as claimed in claim 1, wherein the material of the first drift region and the material of the second drift region respectively comprise epitaxial materials.

3. The high-voltage transistor structure as claimed in claim 1, wherein the size of the second drift region is larger than the size of the first drift region.

4. The high-voltage transistor structure of claim 1, wherein the depth of the second drift region is greater than the depth of the first drift region.

5. The high-voltage transistor structure of claim 1, wherein the width of the second drift region is greater than the width of the first drift region.

6. The high-voltage transistor structure of claim 1, wherein the first drift region and the second drift region each comprise: First epitaxial layer; as well as The second epitaxial layer is located within the first epitaxial layer, wherein The doping concentration of the second epitaxial layer is greater than that of the first epitaxial layer, and The doping concentrations of the first source / drain region and the second source / drain region are greater than the doping concentration of the second epitaxial layer.

7. The high-voltage transistor structure of claim 6, wherein the first drift region and the second drift region each further include: The third epitaxial layer, wherein the first epitaxial layer is located within the third epitaxial layer, and the third epitaxial layer is an undoped epitaxial layer.

8. The high-voltage transistor structure as described in claim 1, wherein... The first capping layer is located between the gate structure and the first drift region, and The second capping layer is located between the gate structure and the second drift region.

9. The high-voltage transistor structure of claim 1, wherein the gate structure comprises: A gate is disposed on the substrate; as well as A gate dielectric layer is located between the gate and the substrate.

10. The high-voltage transistor structure of claim 9, wherein the gate structure further comprises: A spacer wall is disposed on the sidewall of the gate.

11. A method for manufacturing a high-voltage transistor structure, comprising: Provide a base; A first drift region and a second drift region are formed in the substrate; A first capping layer and a second capping layer are formed on the first drift region and the second drift region, respectively; A gate structure is formed on the substrate, wherein the gate structure is located above at least a portion of the first drift region and at least a portion of the second drift region; as well as A first source / drain region and a second source / drain region are formed in the first drift region and the second drift region, respectively. The first source / drain region and the second source / drain region are located on opposite sides of the gate structure, and The size of the first drift region is asymmetrical with the size of the second drift region. The materials of the first capping layer and the second capping layer respectively include undoped epitaxial materials. A portion of the first source / drain region and a portion of the second source / drain region are located in the first capping layer and the second capping layer, respectively.

12. The method for manufacturing a high-voltage transistor structure as claimed in claim 11, wherein the method for forming the first drift region and the second drift region comprises: A first recess and a second recess are formed in the substrate; as well as The first drift region and the second drift region are formed in the first depression and the second depression, respectively.

13. The method for manufacturing a high-voltage transistor structure as claimed in claim 11, wherein the material of the first drift region and the material of the second drift region respectively comprise epitaxial materials.

14. The method for manufacturing a high-voltage transistor structure as claimed in claim 11, wherein the size of the second drift region is larger than the size of the first drift region.

15. The method for manufacturing a high-voltage transistor structure as claimed in claim 11, wherein the depth of the second drift region is greater than the depth of the first drift region.

16. The method for manufacturing a high-voltage transistor structure as claimed in claim 11, wherein the width of the second drift region is greater than the width of the first drift region.

17. The method for manufacturing a high-voltage transistor structure as claimed in claim 11, wherein the first drift region and the second drift region each comprise: First epitaxial layer; as well as The second epitaxial layer is located within the first epitaxial layer, wherein The doping concentration of the second epitaxial layer is greater than that of the first epitaxial layer, and The doping concentrations of the first source / drain region and the second source / drain region are greater than the doping concentration of the second epitaxial layer.

18. The method for manufacturing a high-voltage transistor structure as claimed in claim 17, wherein the first drift region and the second drift region each further include: The third epitaxial layer, wherein the first epitaxial layer is located within the third epitaxial layer, and the third epitaxial layer is an undoped epitaxial layer.

19. The method for manufacturing a high-voltage transistor structure as described in claim 11, wherein, The first capping layer is located between the gate structure and the first drift region, and The second capping layer is located between the gate structure and the second drift region.

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